clk: ti: dra7: Add set parent rate flag to dpll divider clocks

Fixes 67a4f85: ( CLK: TI: DRA7: initialize DSP DPLL ..)

When CLK_SET_RATE_PARENT flag is added to clock flags the rate
change propgates to one level up as well.
If this flag i sadded to a child clock then we dont need to set
the parent explicitly to get desired rate for the child.

If this flags is not found then the ti_divider_get_best_divider logic
rounds up the divider to get the closest possible rate without
changing the parent clock which may be way too off from what is
desired.

example:
when setting the dsp_dpll_m2_ck to 600MHz,
without this flag we will get 20MHz output.
With this flag the parent dpll rate is updated to get 600MHz
as desired.

with this chnage we can remove the unnecessary code to set dsp dpll
rate in clk-7xx.c

Update devicetree clock entries for a few divider-clock that needs
this flag be set.

XXX: This change is not exhaustive as all divider-clocks are not
updated.

Change-Id: Ib7e75aade4b42de75945700a94201ae68fd0c5b7
Signed-off-by: Ravikumar Kattekola <rk@ti.com>

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 34b2eac95f03b8de5042ca76389ee38fb37fc94c..5fb605b94ef44219ae14b62db7f388aa1459553c 100644 (file)
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -351,6 +351,7 @@
                reg = <0x0244>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
@@ -386,6 +387,7 @@
                reg = <0x01b0>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        iva_dclk: iva_dclk {
@@ -421,6 +423,7 @@
                reg = <0x02e8>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        dpll_core_m2_ck: dpll_core_m2_ck {
@@ -432,6 +435,7 @@
                reg = <0x0130>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        core_dpll_out_dclk_div: core_dpll_out_dclk_div {
@@ -466,6 +470,7 @@
                reg = <0x0220>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        dpll_gmac_byp_mux: dpll_gmac_byp_mux {
@@ -493,6 +498,7 @@
                reg = <0x02b8>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        video2_dclk_div: video2_dclk_div {
@@ -568,6 +574,7 @@
                reg = <0x0294>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        eve_dclk_div: eve_dclk_div {
@@ -665,6 +672,7 @@
                reg = <0x0248>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        dpll_gmac_x2_ck: dpll_gmac_x2_ck {
@@ -1344,6 +1352,7 @@
                reg = <0x0150>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        func_96m_aon_dclk_div: func_96m_aon_dclk_div {
@@ -1379,6 +1388,7 @@
                reg = <0x0190>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
@@ -1390,6 +1400,7 @@
                reg = <0x0210>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+               ti,set-rate-parent;
        };
 
        dpll_per_x2_ck: dpll_per_x2_ck {

diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index f43e1fe142645fc594a3d7c08b29d95f56a10c84..1278b39ac4c0f99bdec581c6983b2887b822d214 100644 (file)
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -18,7 +18,6 @@
 
 #define DRA7_DPLL_ABE_DEFFREQ                          180633600
 #define DRA7_DPLL_GMAC_DEFFREQ                         1000000000
-#define DRA7_DPLL_DSP_DEFFREQ                          600000000
 #define DRA7_DPLL_DSP_GFCLK_NOMFREQ                    600000000
 #define DRA7_DPLL_EVE_GCLK_NOMFREQ                     400000000
 
@@ -321,7 +320,7 @@ int __init dra7xx_dt_clk_init(void)
        int rc;
        struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck;
        struct clk *ipu1_gfclk, *ipu1_gfclk_parent;
-       struct clk *dsp_dpll, *dsp_m2_dpll, *dsp_m3x2_dpll;
+       struct clk *dsp_m2_dpll, *dsp_m3x2_dpll;
        struct clk *atl_fck, *atl_parent;
 
        ti_dt_clocks_register(dra7xx_clks);
@@ -359,23 +358,17 @@ int __init dra7xx_dt_clk_init(void)
        if (rc)
                pr_err("%s: failed to reparent ipu1_gfclk_mux\n", __func__);
 
-       dsp_dpll = clk_get_sys(NULL, "dpll_dsp_ck");
-       rc = clk_set_rate(dsp_dpll, DRA7_DPLL_DSP_DEFFREQ);
-       if (!rc) {
-               dsp_m2_dpll = clk_get_sys(NULL, "dpll_dsp_m2_ck");
-               rc = clk_set_rate(dsp_m2_dpll, DRA7_DPLL_DSP_GFCLK_NOMFREQ);
-               if (rc)
-                       pr_err("%s: failed to configure DSP DPLL m2 output!\n",
-                              __func__);
+       dsp_m2_dpll = clk_get_sys(NULL, "dpll_dsp_m2_ck");
+       rc = clk_set_rate(dsp_m2_dpll, DRA7_DPLL_DSP_GFCLK_NOMFREQ);
+       if (rc)
+               pr_err("%s: failed to configure DSP DPLL m2 output!\n",
+                      __func__);
 
-               dsp_m3x2_dpll = clk_get_sys(NULL, "dpll_dsp_m3x2_ck");
-               rc = clk_set_rate(dsp_m3x2_dpll, DRA7_DPLL_EVE_GCLK_NOMFREQ);
-               if (rc)
-                       pr_err("%s: failed to configure DSP DPLL m3x2 divider!\n",
-                              __func__);
-       } else {
-               pr_err("%s: failed to configure DSP DPLL!\n", __func__);
-       }
+       dsp_m3x2_dpll = clk_get_sys(NULL, "dpll_dsp_m3x2_ck");
+       rc = clk_set_rate(dsp_m3x2_dpll, DRA7_DPLL_EVE_GCLK_NOMFREQ);
+       if (rc)
+               pr_err("%s: failed to configure DSP DPLL m3x2 divider!\n",
+                      __func__);
 
        atl_fck = clk_get_sys(NULL, "atl_gfclk_mux");
        atl_parent = clk_get_sys(NULL, "dpll_abe_m2_ck");