]> Gitweb @ Texas Instruments - Open Source Git Repositories - git.TI.com/gitweb - android-sdk/kernel-video.git/commitdiff
OMAPDSS: Adapt DSS driver for display sharing use-case
authorRakesh Movva <r-movva@ti.com>
Wed, 16 Sep 2015 12:42:56 +0000 (07:42 -0500)
committerVishal Mahaveer <vishalm@ti.com>
Fri, 18 Sep 2015 20:24:34 +0000 (15:24 -0500)
This patch makes sure that the interrupts used by the
remote core are not reset inadvertently by the kernel.

Change-Id: I645e26f21c25755b447157d29390447a729d6031
Signed-off-by: Sundar Raman <sunds@ti.com>
Signed-off-by: Rakesh Movva <r-movva@ti.com>
arch/arm/mach-omap2/Kconfig
drivers/video/fbdev/omap2/dss/dispc-compat.c
drivers/video/fbdev/omap2/dss/dispc.c
drivers/video/fbdev/omap2/dss/overlay.c

index 9175110d12edcacd75aad46d2dac2f6569e31c9f..5fd0c88cefd0418264c6c334522f20fca6500097 100644 (file)
@@ -379,6 +379,7 @@ config OMAP4_ERRATA_I688
          In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
          IO barrier ensure that there is no synchronisation loss on initiators
          operating on both interconnect port simultaneously.
          In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
          IO barrier ensure that there is no synchronisation loss on initiators
          operating on both interconnect port simultaneously.
+
 endmenu
 
 endif
 endmenu
 
 endif
index bc638bfd61d6d238943e18d4f2d954dc53d5a05b..e09a1c73b4e01722120e2b1550533e8c944ae2ea 100644 (file)
@@ -288,6 +288,9 @@ static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
 
        print_irq_status(irqstatus);
 
 
        print_irq_status(irqstatus);
 
+       if (omapdss_display_share())
+               irqstatus &= ~DISPC_IRQ_VID3_END_WIN;
+
        /* Ack the interrupt. Do it here before clocks are possibly turned
         * off */
        dispc_clear_irqstatus(irqstatus);
        /* Ack the interrupt. Do it here before clocks are possibly turned
         * off */
        dispc_clear_irqstatus(irqstatus);
@@ -439,7 +442,11 @@ int dss_dispc_initialize_irq(void)
         * there's SYNC_LOST_DIGIT waiting after enabling the DSS,
         * so clear it
         */
         * there's SYNC_LOST_DIGIT waiting after enabling the DSS,
         * so clear it
         */
-       dispc_clear_irqstatus(dispc_read_irqstatus());
+       if (omapdss_display_share())
+               dispc_clear_irqstatus(dispc_read_irqstatus() &
+                          ~DISPC_IRQ_VID3_END_WIN);
+       else
+               dispc_clear_irqstatus(dispc_read_irqstatus());
 
        INIT_WORK(&dispc_compat.error_work, dispc_error_worker);
 
 
        INIT_WORK(&dispc_compat.error_work, dispc_error_worker);
 
index 6697b5e3e3ee3042d4e4829cfa70b4765bdceeca..532aaf120de54becfd8639d476c75065baf6de8d 100644 (file)
@@ -577,7 +577,13 @@ EXPORT_SYMBOL(dispc_mgr_go_busy);
 void dispc_mgr_go(enum omap_channel channel)
 {
        WARN_ON(dispc_mgr_is_enabled(channel) == false);
 void dispc_mgr_go(enum omap_channel channel)
 {
        WARN_ON(dispc_mgr_is_enabled(channel) == false);
-       WARN_ON(dispc_mgr_go_busy(channel));
+
+       if (omapdss_display_share())
+               /* In case of display share use case, the remote core
+                * will be setting GO bit independently. Hence we might see the
+                * channel as busy on kernel side. Ignore this and proceed
+                * further */
+               WARN_ON(dispc_mgr_go_busy(channel));
 
        DSSDBG("GO %s\n", mgr_desc[channel].name);
 
 
        DSSDBG("GO %s\n", mgr_desc[channel].name);
 
@@ -3736,7 +3742,12 @@ void dispc_write_irqenable(u32 mask)
        /* clear the irqstatus for newly enabled irqs */
        dispc_clear_irqstatus((mask ^ old_mask) & mask);
 
        /* clear the irqstatus for newly enabled irqs */
        dispc_clear_irqstatus((mask ^ old_mask) & mask);
 
-       dispc_write_reg(DISPC_IRQENABLE, mask);
+       if (omapdss_display_share())
+               /* Should not clear already enabled interrupts since remote
+               * core must be using it */
+               dispc_write_reg(DISPC_IRQENABLE, mask | old_mask);
+       else
+               dispc_write_reg(DISPC_IRQENABLE, mask);
 }
 EXPORT_SYMBOL(dispc_write_irqenable);
 
 }
 EXPORT_SYMBOL(dispc_write_irqenable);
 
index 2f7cee985cdddea5e75178da51ce875525f255ce..50569053032c5b0f79e9fa60a403bf808ad3927a 100644 (file)
@@ -133,9 +133,20 @@ int dss_ovl_simple_check(struct omap_overlay *ovl,
                return -EINVAL;
        }
 
                return -EINVAL;
        }
 
-       if (info->zorder >= omap_dss_get_num_overlays()) {
-               DSSERR("check_overlay: zorder %d too high\n", info->zorder);
-               return -EINVAL;
+       /* In this case since the display is shared, we reduce the number of
+       overlays by n and share them across cores but z-order can be higher */
+       if (omapdss_display_share()) {
+               if (info->zorder >= (omap_dss_get_num_overlays() + 1)) {
+                       DSSERR("check_overlay: zorder %d too high\n",
+                               info->zorder);
+                       return -EINVAL;
+               }
+       } else {
+               if (info->zorder >= omap_dss_get_num_overlays()) {
+                       DSSERR("check_overlay: zorder %d too high\n",
+                               info->zorder);
+                       return -EINVAL;
+               }
        }
 
        if (dss_feat_rotation_type_supported(info->rotation_type) == 0) {
        }
 
        if (dss_feat_rotation_type_supported(info->rotation_type) == 0) {