omapdss: DSS DPLLs: Ignore PLL_PWR_STATUS on DRA7

There is a Vayu bug(VAYU-BUG02893) which prevents the correct update of
PLL_PWR_STATUS when the power state of DPLL_VIDEO1/2 is changed. Currently, the
driver reports the error but still proceeds ahead. Modify the code such that we
don't read the buggy field at all and adds a small delay for the power state to
change.

Signed-off-by: Archit Taneja <archit@ti.com>

diff --git a/drivers/video/omap2/dss/dss_dpll.c b/drivers/video/omap2/dss/dss_dpll.c
index 7fd69c87df25f03d5d0a340e1d9c7633058f0340..121fe39d689b4955e5f858fad27a1521ce1e7a85 100644 (file)
--- a/drivers/video/omap2/dss/dss_dpll.c
+++ b/drivers/video/omap2/dss/dss_dpll.c
@@ -352,11 +352,21 @@ static int dpll_power(enum dss_dpll dpll, int state)
        /* PLL_PWR_CMD = enable both hsdiv and clkout*/
        REG_FLD_MOD(dpll, CLK_CTRL, state, 31, 30);
 
        /* PLL_PWR_CMD = enable both hsdiv and clkout*/
        REG_FLD_MOD(dpll, CLK_CTRL, state, 31, 30);
 

-       /* PLL_PWR_STATUS: (NOTE: apparently buggy) */
+       /*
+        * PLL_PWR_STATUS doesn't correctly reflect the power state set on
+        * DRA7xx. Ignore the reg field and add a small delay for the power
+        * state to change.
+        */
+       if (omapdss_get_version() == OMAPDSS_VER_DRA7xx) {
+               msleep(1);
+               return 0;
+       }
+
+       /* PLL_PWR_STATUS */

        while (FLD_GET(dpll_read_reg(dpll, CLK_CTRL), 29, 28) != state) {
                if (++t > 1000) {
                        DSSERR("Failed to set DPLL power mode to %d\n", state);
        while (FLD_GET(dpll_read_reg(dpll, CLK_CTRL), 29, 28) != state) {
                if (++t > 1000) {
                        DSSERR("Failed to set DPLL power mode to %d\n", state);

-                       /* return -ENODEV; */
+                       return -ENODEV;

                        return 0;
                }
                udelay(1);
                        return 0;
                }
                udelay(1);