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raw | patch | inline | side by side (parent: f8da37e)
raw | patch | inline | side by side (parent: f8da37e)
author | Ruchika Kharwar <ruchika@ti.com> | |
Sat, 11 May 2013 15:34:58 +0000 (17:34 +0200) | ||
committer | Praneeth Bajjuri <praneeth@ti.com> | |
Fri, 19 Jul 2013 18:04:46 +0000 (13:04 -0500) |
Another phy type on dra7xx inspired the addition of a OMAP_CTRL_DEV_TYPE3
type of omap_control_usb system.
This phy is different in 2 ways
- usb2 only
- the power on is in different register with bit definitions dissimilar to
dev_conf.
Change-Id: I39969ea675ff9916aa746b5168784ba99119a54f
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
type of omap_control_usb system.
This phy is different in 2 ways
- usb2 only
- the power on is in different register with bit definitions dissimilar to
dev_conf.
Change-Id: I39969ea675ff9916aa746b5168784ba99119a54f
Signed-off-by: Ruchika Kharwar <ruchika@ti.com>
Documentation/devicetree/bindings/usb/omap-usb.txt | patch | blob | history | |
drivers/usb/phy/omap-control-usb.c | patch | blob | history | |
include/linux/usb/omap_control_usb.h | patch | blob | history |
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt b/Documentation/devicetree/bindings/usb/omap-usb.txt
index d4769f343d6cfbdaeb5ba16880d450e339145d6b..b5770b49c8ee02313696ec873a87b59dedf5319e 100644 (file)
usb mailbox or usb3 phy power. omap4 has usb mailbox in control module to
notify events to the musb core and omap5 has usb3 phy power register to
power on usb3 phy. Should be "1" if it has mailbox and "2" if it has usb3
- phy power.
+ phy power (usb3 phy power indicates the presense of a usb2 and usb3 phy),
+ should be "3" is it has only usb2 phy power.
omap_control_usb: omap-control-usb@4a002300 {
compatible = "ti,omap-control-usb";
index 19db6aad6bd99fb741994b98612ca7cf22859a4a..af61a8f33478d00df5ca8dd01c8011a425ed6ffa 100644 (file)
u32 val;
struct omap_control_usb *control_usb = dev_get_drvdata(dev);
- val = readl(control_usb->dev_conf);
+ if (control_usb->type == OMAP_CTRL_DEV_TYPE2) {
+
+ val = readl(control_usb->dev_conf);
+ if (on)
+ val &= ~OMAP_CTRL_DEV_PHY_PD;
+ else
+ val |= OMAP_CTRL_DEV_PHY_PD;
- if (on)
- val &= ~OMAP_CTRL_DEV_PHY_PD;
- else
- val |= OMAP_CTRL_DEV_PHY_PD;
+ writel(val, control_usb->dev_conf);
+ } else {
- writel(val, control_usb->dev_conf);
+ val = readl(control_usb->ctrl_core_srcomp_north_side);
+ if (on)
+ val &= ~OMAP_CTRL_USB_SRCOMP_NORTH_SIDE_PD;
+ else
+ val |= OMAP_CTRL_USB_SRCOMP_NORTH_SIDE_PD;
+ writel(val, control_usb->ctrl_core_srcomp_north_side);
+
+ }
}
EXPORT_SYMBOL_GPL(omap_control_usb_phy_power);
control_usb->dev = &pdev->dev;
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "control_dev_conf");
- control_usb->dev_conf = devm_request_and_ioremap(&pdev->dev, res);
- if (!control_usb->dev_conf) {
- dev_err(&pdev->dev, "Failed to obtain io memory\n");
- return -EADDRNOTAVAIL;
- }
-
if (control_usb->type == OMAP_CTRL_DEV_TYPE1) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"otghs_control");
}
if (control_usb->type == OMAP_CTRL_DEV_TYPE2) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "control_dev_conf");
+ control_usb->dev_conf = devm_request_and_ioremap(&pdev->dev, res);
+ if (!control_usb->dev_conf) {
+ dev_err(&pdev->dev, "Failed to obtain io memory\n");
+ return -EADDRNOTAVAIL;
+ }
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
"phy_power_usb");
control_usb->phy_power = devm_request_and_ioremap(
dev_dbg(&pdev->dev, "Failed to obtain io memory\n");
return -EADDRNOTAVAIL;
}
+ }
+
+ if (control_usb->type == OMAP_CTRL_DEV_TYPE3) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "ctrl_core_srcomp_north_side");
+ control_usb->ctrl_core_srcomp_north_side =
+ devm_request_and_ioremap(&pdev->dev, res);
+ if (!control_usb->ctrl_core_srcomp_north_side) {
+ dev_err(&pdev->dev, "Failed to obtain io memory\n");
+ return -EADDRNOTAVAIL;
+ }
+ }
+
+ if ((control_usb->type == OMAP_CTRL_DEV_TYPE2) ||
+ (control_usb->type == OMAP_CTRL_DEV_TYPE3)) {
control_usb->sys_clk = devm_clk_get(control_usb->dev,
"sys_clkin");
index 27b5b8c931b0bd70d1e20d636b08beb6ebe3dc64..c223476012918d7454775340bf2b03739a5f6ae7 100644 (file)
u32 __iomem *dev_conf;
u32 __iomem *otghs_control;
u32 __iomem *phy_power;
+ u32 __iomem *ctrl_core_srcomp_north_side;
struct clk *sys_clk;
};
/* To differentiate ctrl module IP having either mailbox or USB3 PHY power */
-#define OMAP_CTRL_DEV_TYPE1 0x1
-#define OMAP_CTRL_DEV_TYPE2 0x2
+#define OMAP_CTRL_DEV_TYPE1 0x1 /* mailbox */
+#define OMAP_CTRL_DEV_TYPE2 0x2 /* has a usb2 and usb3 phy */
+#define OMAP_CTRL_DEV_TYPE3 0x3 /* has only a usb2 phy */
#define OMAP_CTRL_DEV_PHY_PD BIT(0)
#define OMAP_CTRL_USB3_PHY_TX_RX_POWERON 0x3
#define OMAP_CTRL_USB3_PHY_TX_RX_POWEROFF 0x0
+#define OMAP_CTRL_USB_SRCOMP_NORTH_SIDE_PD BIT(28)
+
#if IS_ENABLED(CONFIG_OMAP_CONTROL_USB)
extern struct device *omap_get_control_dev(void);
extern void omap_control_usb_phy_power(struct device *dev, int on);