Merge branch 'p-ti-linux-3.8.y-video' into p-ti-android-3.8.y-video
authorPraneeth Bajjuri <praneeth@ti.com>
Mon, 15 Jul 2013 06:20:43 +0000 (01:20 -0500)
committerPraneeth Bajjuri <praneeth@ti.com>
Mon, 15 Jul 2013 06:20:43 +0000 (01:20 -0500)
* p-ti-linux-3.8.y-video:
  ARM: OMAP: omap2plus_defconfig: Enable Kernel Preemption
  arm: dra: Add gpu interface clock
  arm: dra7xx: Add gpu hwmod
  arm/dts: dra7: Add gpu supply
  arm: dts: dra7xx: Add gpu data

Conflicts:
arch/arm/boot/dts/dra7-evm.dts

Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
arch/arm/boot/dts/dra7-evm.dts
arch/arm/boot/dts/dra7.dtsi
arch/arm/configs/omap2plus_defconfig
arch/arm/mach-omap2/cclock7xx_data.c
arch/arm/mach-omap2/omap_hwmod_7xx_data.c

index 435024659b366fadce9d1ffde56b3a5a5a76b44b..8f0495b049218f134ae748cdbe0e7bf0aa24f268 100755 (executable)
                /*15 MB*/
                ti,omap_ion_heap_nonsecure_tiler_size = <0xF00000>;
        };
+
+       ocp {
+               gpu: gpu@0x56000000 {
+                       gpu-supply = <&avs_gpu>;
+               };
+       };
+
 };
 
 &dra7_pmx_core {
index 659b3b766312822feae18f3c702418a4b5172151..7f92247a03fc2b9f0ad120249bf8d2a09c5f2f94 100644 (file)
                        compatible = "ti,omap-clock";
                };
 
+               dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
+               dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
+               dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
+               gpu_core_gclk_mux: gpu_core_gclk_mux {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
+               gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
                sdma: dma-controller@4a056000 {
                        compatible = "ti,omap4430-sdma";
                        reg = <0x4a056000 0x1000>;
                        ti,hwmods = "dmm";
                };
 
+               gpu: gpu@0x56000000 {
+                       compatible = "ti,omap4-gpu";
+                       reg = <0x56000000 0xffff>;
+                       interrupts = <0 21 0x4>;
+                       ti,hwmods = "gpu";
+                       operating-points = <
+                               /* kHz    uV */
+                               425600  1090000
+                               500000  1210000
+                               532000  1280000
+                               >;
+                       clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>,
+                                       <&dpll_gpu_m2_ck>, <&gpu_core_gclk_mux>,
+                                       <&gpu_hyd_gclk_mux>;
+                       clock-names = "core", "per", "gpu", "gpu_core", "gpu_hyd";
+               };
+
                bandgap {
                        reg = <0x4a0021e0 0xc
                                0x4a00232c 0xc
index ffa9c311d093c8cdcda666f6600b111231c3fdb5..e3514f7e7c0fc12bd941f7cd90e239015ed32855 100644 (file)
@@ -30,6 +30,7 @@ CONFIG_ARM_THUMBEE=y
 CONFIG_ARM_ERRATA_411920=y
 CONFIG_SMP=y
 CONFIG_NR_CPUS=2
+CONFIG_PREEMPT=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
index 87f9d563caf9535319c4209079178af47ccc0103..e77d58771c7c45a15f104887ba6df2358fabfe15 100644 (file)
@@ -1259,6 +1259,20 @@ static struct clk_hw_omap l3_iclk_div_hw = {
 DEFINE_STRUCT_CLK(l3_iclk_div, mpu_dpll_hs_clk_div_parents,
                  apll_pcie_clkvcoldo_ops);
 
+static const char *gpu_l3_iclk_parents[] = {
+       "l3_iclk_div",
+};
+
+static struct clk gpu_l3_iclk;
+
+static struct clk_hw_omap gpu_l3_iclk_hw = {
+       .hw = {
+               .clk = &gpu_l3_iclk,
+       },
+};
+
+DEFINE_STRUCT_CLK(gpu_l3_iclk, gpu_l3_iclk_parents, apll_pcie_clkvcoldo_ops);
+
 static const struct clk_div_table l3init_60m_fclk_rates[] = {
        { .div = 1, .val = 0 },
        { .div = 8, .val = 1 },
@@ -1950,6 +1964,7 @@ static struct omap_clk dra7xx_clks[] = {
        CLK(NULL,       "hdmi_div_clk",                 &hdmi_div_clk,  CK_7XX),
        CLK(NULL,       "hdmi_dpll_clk_mux",            &hdmi_dpll_clk_mux,     CK_7XX),
        CLK(NULL,       "l3_iclk_div",                  &l3_iclk_div,   CK_7XX),
+       CLK(NULL,       "gpu_l3_iclk",                  &gpu_l3_iclk,   CK_7XX),
        CLK(NULL,       "l3init_60m_fclk",              &l3init_60m_fclk,       CK_7XX),
        CLK(NULL,       "l4_root_clk_div",              &l4_root_clk_div,       CK_7XX),
        CLK(NULL,       "mlb_clk",                      &mlb_clk,       CK_7XX),
index b648382f25bf124083d1e7f6b0fe6fdf1fec0f18..e8d09dfbaf6ca88b268ebba23f4a54139b34ae4c 100644 (file)
@@ -1039,6 +1039,47 @@ static struct omap_hwmod dra7xx_gpmc_hwmod = {
        },
 };
 
+/*
+ * 'gpu' class
+ * 2d/3d graphics accelerator
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_gpu_sysc = {
+       .rev_offs       = 0x0000,
+       .sysc_offs      = 0x0010,
+       .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+       .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                          SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+                          MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+       .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_gpu_hwmod_class = {
+       .name   = "gpu",
+       .sysc   = &dra7xx_gpu_sysc,
+};
+
+/* gpu */
+static struct omap_hwmod_irq_info dra7xx_gpu_irqs[] = {
+       { .irq = 21 + DRA7XX_IRQ_GIC_START },
+       { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_gpu_hwmod = {
+       .name           = "gpu",
+       .class          = &dra7xx_gpu_hwmod_class,
+       .clkdm_name     = "gpu_clkdm",
+       .mpu_irqs       = dra7xx_gpu_irqs,
+       .main_clk       = "gpu_core_gclk_mux",
+       .prcm = {
+               .omap4 = {
+                       .clkctrl_offs = DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET,
+                       .context_offs = DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET,
+                       .modulemode   = MODULEMODE_SWCTRL,
+               },
+       },
+};
+
 /*
  * 'hdq1w' class
  *
@@ -4165,6 +4206,45 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space dra7xx_gpu_addrs[] = {
+       {
+               .name           = "klio",
+               .pa_start       = 0x56000000,
+               .pa_end         = 0x56001fff,
+       },
+       {
+               .name           = "hydra2",
+               .pa_start       = 0x56004000,
+               .pa_end         = 0x56004fff,
+       },
+       {
+               .name           = "klio_0",
+               .pa_start       = 0x56008000,
+               .pa_end         = 0x56009fff,
+       },
+       {
+               .name           = "klio_1",
+               .pa_start       = 0x5600c000,
+               .pa_end         = 0x5600dfff,
+       },
+       {
+               .name           = "klio_hl",
+               .pa_start       = 0x5600fe00,
+               .pa_end         = 0x5600ffff,
+               .flags          = ADDR_TYPE_RT
+       },
+       { }
+};
+
+/* l3_main_1 -> gpu */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpu = {
+       .master         = &dra7xx_l3_main_1_hwmod,
+       .slave          = &dra7xx_gpu_hwmod,
+       .clk            = "gpu_l3_iclk",
+       .addr           = dra7xx_gpu_addrs,
+       .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
        {
                .pa_start       = 0x480b2000,
@@ -6122,6 +6202,7 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
        &dra7xx_l4_per1__gpio7,
        &dra7xx_l4_per1__gpio8,
        &dra7xx_l3_main_1__gpmc,
+       &dra7xx_l3_main_1__gpu,
        &dra7xx_l4_per1__hdq1w,
        &dra7xx_l4_per1__i2c1,
        &dra7xx_l4_per1__i2c2,