ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA

Erratum i892 as will be documented in the upcoming G or later revision
of DRA7xx/ AM57xx errata documentation (SPRZ398F) states that L3 clock
needs to be kept active all the time to ensure that asymmetric aging
degradation is minimal and within the design allowed margin.

by allowing core domain to transition to INA and allowing L3 clock to be
turned off for extended periods of time, there is a risk of functional
issues.

Due to this change, there is a minimal impact on power numbers in low
power state.

Signed-off-by: Nishanth Menon <nm@ti.com>
[cherrypick to 3.14 baseline]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
Change-Id: I8140ea33686758fc2c03b09a3009e656b4a94294

diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
index 287a2037aa161885933bbb5de25e9e7d42bc7b57..f2b4557124f392f9a75125a4c572bc7df9af2433 100644 (file)
--- a/arch/arm/mach-omap2/powerdomains7xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -160,7 +160,7 @@ static struct powerdomain core_7xx_pwrdm = {
        .name             = "core_pwrdm",
        .prcm_offs        = DRA7XX_PRM_CORE_INST,
        .prcm_partition   = DRA7XX_PRM_PARTITION,
-       .pwrsts           = PWRSTS_INA_ON,
+       .pwrsts           = PWRSTS_ON,
        .pwrsts_logic_ret = PWRSTS_RET,
        .banks            = 5,
        .pwrsts_mem_ret = {