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raw | patch | inline | side by side (parent: c4a1ea2)
raw | patch | inline | side by side (parent: c4a1ea2)
author | Rajendra Nayak <rnayak@ti.com> | |
Tue, 6 Nov 2012 22:28:25 +0000 (15:28 -0700) | ||
committer | Paul Walmsley <paul@pwsan.com> | |
Tue, 13 Nov 2012 02:18:50 +0000 (19:18 -0700) |
Clean all #ifdef's added to OMAP4 clock code to make it COMMON clk
ready, now that CONFIG_COMMON_CLK is enabled.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul@pwsan.com: remove some ifdefs in mach-omap2/io.c]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
ready, now that CONFIG_COMMON_CLK is enabled.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@ti.com>
[paul@pwsan.com: remove some ifdefs in mach-omap2/io.c]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
arch/arm/mach-omap2/dpll44xx.c | patch | blob | history | |
arch/arm/mach-omap2/io.c | patch | blob | history |
index aa75a3c100267942f36b01f2611034427b95f2b8..d3326c474fdc4b2847bc5c2834838cce39002768 100644 (file)
#include "cm-regbits-44xx.h"
/* Supported only on OMAP4 */
-#ifdef CONFIG_COMMON_CLK
int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
-#else
-int omap4_dpllmx_gatectrl_read(struct clk *clk)
-#endif
{
u32 v;
u32 mask;
return v;
}
-#ifdef CONFIG_COMMON_CLK
void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
-#else
-void omap4_dpllmx_allow_gatectrl(struct clk *clk)
-#endif
{
u32 v;
u32 mask;
__raw_writel(v, clk->clksel_reg);
}
-#ifdef CONFIG_COMMON_CLK
void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
-#else
-void omap4_dpllmx_deny_gatectrl(struct clk *clk)
-#endif
{
u32 v;
u32 mask;
__raw_writel(v, clk->clksel_reg);
}
-#ifdef CONFIG_COMMON_CLK
const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
.allow_idle = omap4_dpllmx_allow_gatectrl,
.deny_idle = omap4_dpllmx_deny_gatectrl,
};
-#else
-const struct clkops clkops_omap4_dpllmx_ops = {
- .allow_idle = omap4_dpllmx_allow_gatectrl,
- .deny_idle = omap4_dpllmx_deny_gatectrl,
-};
-#endif
/**
* omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
* OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
* upon success, or 0 upon error.
*/
-#ifdef CONFIG_COMMON_CLK
unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-unsigned long omap4_dpll_regm4xen_recalc(struct clk *clk)
-{
-#endif
u32 v;
unsigned long rate;
struct dpll_data *dd;
* M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
* ~0 if an error occurred in omap2_dpll_round_rate().
*/
-#ifdef CONFIG_COMMON_CLK
long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
unsigned long target_rate,
unsigned long *parent_rate)
{
struct clk_hw_omap *clk = to_clk_hw_omap(hw);
-#else
-long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
-{
-#endif
u32 v;
struct dpll_data *dd;
long r;
@@ -174,11 +145,7 @@ long omap4_dpll_regm4xen_round_rate(struct clk *clk, unsigned long target_rate)
if (v)
target_rate = target_rate / OMAP4430_REGM4XEN_MULT;
-#ifdef CONFIG_COMMON_CLK
r = omap2_dpll_round_rate(hw, target_rate, NULL);
-#else
- r = omap2_dpll_round_rate(clk, target_rate);
-#endif
if (r == ~0)
return r;
index 41c601311b3ec8b585315b185b1e8d16104c2ad7..4332080731cda35b92fd6bd5c0e6d4e16fc5924c 100644 (file)
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
omap_mux_late_init();
omap2_common_pm_late_init();
omap2_pm_init();
-#ifdef CONFIG_COMMON_CLK
omap2_clk_enable_autoidle_all();
-#endif
}
#endif
omap_mux_late_init();
omap2_common_pm_late_init();
omap3_pm_init();
-#ifdef CONFIG_COMMON_CLK
omap2_clk_enable_autoidle_all();
-#endif
}
#endif
omap_mux_late_init();
omap2_common_pm_late_init();
omap4_pm_init();
-#ifdef CONFIG_COMMON_CLK
omap2_clk_enable_autoidle_all();
-#endif
}
#endif