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raw | patch | inline | side by side (parent: fd3d294)
raw | patch | inline | side by side (parent: fd3d294)
author | Suman Anna <s-anna@ti.com> | |
Wed, 5 Feb 2014 23:08:35 +0000 (17:08 -0600) | ||
committer | Suman Anna <s-anna@ti.com> | |
Wed, 5 Feb 2014 23:29:42 +0000 (17:29 -0600) |
The IPU1 functional clock is actually the output of a mux clock,
ipu1_gfclk_mux. The mux clock is sourced by default from the
DPLL_ABE_X2_CLK, and this results in a rather odd clock frequency
(361 MHz) for the IPU1 functional clock. Reconfigure the mux clock
to be sourced from CORE_IPU_ISS_BOOST_CLK (dpll_core_h22x2_ck), so
that both the IPU1 and IPU2 are running from the same clock and
clocked at the same nominal frequency of 425 MHz.
Signed-off-by: Suman Anna <s-anna@ti.com>
ipu1_gfclk_mux. The mux clock is sourced by default from the
DPLL_ABE_X2_CLK, and this results in a rather odd clock frequency
(361 MHz) for the IPU1 functional clock. Reconfigure the mux clock
to be sourced from CORE_IPU_ISS_BOOST_CLK (dpll_core_h22x2_ck), so
that both the IPU1 and IPU2 are running from the same clock and
clocked at the same nominal frequency of 425 MHz.
Signed-off-by: Suman Anna <s-anna@ti.com>
arch/arm/mach-omap2/cclock7xx_data.c | patch | blob | history |
index 4934ef437dbdb743354f65f39925a01a2ba8c2a9..17ad141f285bdd83647ef809358c1f8f6c9dbc69 100644 (file)
static struct reparent_init_clks reparent_clks[] = {
{ .name = "abe_dpll_sys_clk_mux", .parent = "sys_clkin2" },
+ { .name = "ipu1_gfclk_mux", .parent = "dpll_core_h22x2_ck" },
};
static struct rate_init_clks rate_clks[] = {