arm64: barriers: make use of barrier options with explicit barriers

When calling our low-level barrier macros directly, we can often suffice
with more relaxed behaviour than the default "all accesses, full system"
option.

This patch updates the users of dsb() to specify the option which they
actually require.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
(cherry picked from commit 98f7685ee69f871ba991089cb9685f0da07517ea)
Signed-off-by: Mark Brown <broonie@linaro.org>

diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index 409ca370cfe2ddccd245efc3f3b0a20fe2360d49..5c436e3457dde828d4e195ded7f993335c96aabf 100644 (file)
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -27,7 +27,7 @@
 #define isb()          asm volatile("isb" : : : "memory")
 #define dsb(opt)       asm volatile("dsb sy" : : : "memory")
 
-#define mb()           dsb()
+#define mb()           dsb(sy)
 #define rmb()          asm volatile("dsb ld" : : : "memory")
 #define wmb()          asm volatile("dsb st" : : : "memory")
 

diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
index 4c60e64a801c5cf3a3c5e379a3270ea3ff31eea5..a5176cf32dadd8e61723d321b12df3cd541a79fe 100644 (file)
--- a/arch/arm64/include/asm/cacheflush.h
+++ b/arch/arm64/include/asm/cacheflush.h
@@ -123,7 +123,7 @@ extern void flush_dcache_page(struct page *);
 static inline void __flush_icache_all(void)
 {
        asm("ic ialluis");
-       dsb();
+       dsb(ish);
 }
 
 #define flush_dcache_mmap_lock(mapping) \
@@ -150,7 +150,7 @@ static inline void flush_cache_vmap(unsigned long start, unsigned long end)
         * set_pte_at() called from vmap_pte_range() does not
         * have a DSB after cleaning the cache line.
         */
-       dsb();
+       dsb(ish);
 }
 
 static inline void flush_cache_vunmap(unsigned long start, unsigned long end)

diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 6b3fe2b6b58f75b9316627f7d78c2776f21f8770..49323844780598891500bd10c671619a0aaf60ba 100644 (file)
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -300,7 +300,7 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
 {
        *pmdp = pmd;
-       dsb();
+       dsb(ishst);
 }
 
 static inline void pmd_clear(pmd_t *pmdp)
@@ -330,7 +330,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd)
 static inline void set_pud(pud_t *pudp, pud_t pud)
 {
        *pudp = pud;
-       dsb();
+       dsb(ishst);
 }
 
 static inline void pud_clear(pud_t *pudp)

diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 8b482035cfc2434bdba34d3e24e6308ac01f423e..3083a08f96225c152822d5fb169b3336cc7f9648 100644 (file)
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -72,9 +72,9 @@ extern struct cpu_tlb_fns cpu_tlb;
  */
 static inline void flush_tlb_all(void)
 {
-       dsb();
+       dsb(ishst);
        asm("tlbi       vmalle1is");
-       dsb();
+       dsb(ish);
        isb();
 }
 
@@ -82,9 +82,9 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
 {
        unsigned long asid = (unsigned long)ASID(mm) << 48;
 
-       dsb();
+       dsb(ishst);
        asm("tlbi       aside1is, %0" : : "r" (asid));
-       dsb();
+       dsb(ish);
 }
 
 static inline void flush_tlb_page(struct vm_area_struct *vma,
@@ -93,9 +93,9 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,
        unsigned long addr = uaddr >> 12 |
                ((unsigned long)ASID(vma->vm_mm) << 48);
 
-       dsb();
+       dsb(ishst);
        asm("tlbi       vae1is, %0" : : "r" (addr));
-       dsb();
+       dsb(ish);
 }
 
 /*
@@ -114,7 +114,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
         * set_pte() does not have a DSB, so make sure that the page table
         * write is visible.
         */
-       dsb();
+       dsb(ishst);
 }
 
 #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0)

diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c
index 1c0a9be2ffa85ad87245ac5837c94149e246533a..8e78cb238376ebab43b9136abf8a3c8334f8ecce 100644 (file)
--- a/arch/arm64/kernel/process.c
+++ b/arch/arm64/kernel/process.c
@@ -294,7 +294,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
         * Complete any pending TLB or cache maintenance on this CPU in case
         * the thread migrates to a different CPU.
         */
-       dsb();
+       dsb(ish);
 
        /* the actual thread switch */
        last = cpu_switch_to(prev, next);

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 02e9d09e1d804b4e9344427037dd5a2b88d378ba..d800dbc8693abd1bb05909bb56164341ea1a852c 100644 (file)
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -70,13 +70,13 @@ static u32 get_ccsidr(u32 csselr)
 static void do_dc_cisw(u32 val)
 {
        asm volatile("dc cisw, %x0" : : "r" (val));
-       dsb();
+       dsb(ish);
 }
 
 static void do_dc_csw(u32 val)
 {
        asm volatile("dc csw, %x0" : : "r" (val));
-       dsb();
+       dsb(ish);
 }
 
 /* See note at ARM ARM B1.14.4 */