Merge branch 'platform-ti-linux-3.14.y' of git://git.ti.com/~rrnayak/ti-linux-kernel...

Resync with the latest platform base code. Relevant
fixes include fixes on DPLL bypass clock settings
and support for Timers 12 through 16.

* 'platform-ti-linux-3.14.y' of git://git.ti.com/~rrnayak/ti-linux-kernel/platform-linux-feature-tree: (127 commits)
  ARM: OMAP: Check for clocks which do not have parents
  ARM: OMAP: DRA7: clockdomain: Implement timer workaround for errata i874
  ARM: dts: DRA7: Add DT node for AES2 IP
  ARM: DRA7: hwmod: Add data for AES2 IP
  crypto: omap-aes - Add support for multiple cores
  crypto: omap-aes - Fix registration of Algos
  crypto: omap-aes - Fix enabling clocks
  crypto: tcrypt - Added speed tests for Async AEAD crypto alogrithms
  crypto: omap-aes - Add support for GCM mode
  crypto: omap-aes - Fix configuring of AES mode
  crypto: omap-aes - Add support for lengths not aligned with AES_BLOCK_SIZE
  crypto: omap-des: Fix unmapping of dma channels
  dmaenegine: edma: allow pause/resume for non-cyclic mode
  ARM: common: edma: clear completion interrupts on stop
  bus: omap_l3_noc: Fix master id address decoding for OMAP5
  ARM: edma: Clear IRQ if we get interrupted by a unknown event
  bus: omap_l3_noc: Fix connID for OMAP4
  bus: omap_l3_noc: Fix offset for DRA7 CLK1_HOST_CLK1_2 instance
  crypto: omap-sham: Use pm_runtime_irq_safe()
  crypto: omap-sham: Add the offset of sg page to vaddr
  ...

Signed-off-by: Suman Anna <s-anna@ti.com>

diff --cc arch/arm/boot/dts/am33xx.dtsi
Simple merge

diff --cc arch/arm/boot/dts/am57xx-beagle-x15.dts
index 89c4c0705e0d50eaec017db589cdb44c8c3dad4d,34e9b6dbd55c2a68c8628f185856fee70af604a0..6f71853f77205ff8a0b860fcaa1c00e1071994e1
--- 1/arch/arm/boot/dts/am57xx-beagle-x15.dts
--- 2/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@@ -24,43 -24,9 +24,43 @@@
  
        memory {
                device_type = "memory";
-               reg = <0x80000000 0x40000000>; /* 1GB to start. Target 2GB */
+               reg = <0x80000000 0x80000000>;
        };
  
 +      reserved-memory {
 +              #address-cells = <1>;
 +              #size-cells = <1>;
 +              ranges;
 +
 +              ipu2_cma_pool: ipu2_cma@95800000 {
 +                      compatible = "shared-dma-pool";
 +                      reg = <0x95800000 0x3800000>;
 +                      reusable;
 +                      status = "okay";
 +              };
 +
 +              dsp1_cma_pool: dsp1_cma@99000000 {
 +                      compatible = "shared-dma-pool";
 +                      reg = <0x99000000 0x4000000>;
 +                      reusable;
 +                      status = "okay";
 +              };
 +
 +              ipu1_cma_pool: ipu1_cma@9d000000 {
 +                      compatible = "shared-dma-pool";
 +                      reg = <0x9d000000 0x2000000>;
 +                      reusable;
 +                      status = "okay";
 +              };
 +
 +              dsp2_cma_pool: dsp2_cma@9f000000 {
 +                      compatible = "shared-dma-pool";
 +                      reg = <0x9f000000 0x800000>;
 +                      reusable;
 +                      status = "okay";
 +              };
 +      };
 +
        vdd_3v3: fixedregulator-vdd_3v3 {
                compatible = "regulator-fixed";
                regulator-name = "vdd_3v3";

diff --cc arch/arm/boot/dts/dra7-evm.dts
Simple merge

diff --cc arch/arm/boot/dts/dra7.dtsi
Simple merge

diff --cc arch/arm/boot/dts/dra72-evm.dts
Simple merge

diff --cc arch/arm/boot/dts/omap4.dtsi
Simple merge

diff --cc arch/arm/boot/dts/omap5.dtsi
Simple merge

diff --cc arch/arm/mach-omap2/Makefile
Simple merge

diff --cc arch/arm/mach-omap2/clockdomains7xx_data.c
Simple merge

diff --cc arch/arm/mach-omap2/control.h
index d221a584136174b4776f4200756c5f5ec7c21bef,7bd7d91ec24e802198f063b6da7d89df10dcd643..82e0ed1d7daa082c8b3ccae26004819eea0377da
--- 1/arch/arm/mach-omap2/control.h
--- 2/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@@ -258,11 -258,10 +258,15 @@@
  #define OMAP5XXX_CONTROL_STATUS                0x134
  #define OMAP5_DEVICETYPE_MASK          (0x7 << 6)
  
 +/* DRA7XX DSP Reset Vector boot register */
 +#define DRA7XX_CTRL_CORE_CONTROL_DSP1_RST_VECT        0x55C
 +#define DRA7XX_CTRL_CORE_DSP_RST_VECT_MASK    (0x3FFFFF << 0)
 +#define DRA7XX_CTRL_CORE_DSP_RST_VECT_SHIFT   10
 +
+ /* DRA7XX CONTROL CORE BOOTSTRAP */
+ #define DRA7_CTRL_CORE_BOOTSTRAP      0x6c4
+ #define DRA7_SPEEDSELECT_MASK         (0x3 << 8)
+ 
  /*
   * REVISIT: This list of registers is not comprehensive - there are more
   * that should be added.

diff --cc arch/arm/mach-omap2/omap_hwmod_44xx_data.c
Simple merge

diff --cc arch/arm/mach-omap2/omap_hwmod_54xx_data.c
Simple merge

diff --cc arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 008a34fdeda171cb501bb6cc06e39984205441b7,ac2f5c5851b0f46a958d5d2245fd90384eab1e6a..0e026cf102c03726ca9f3e8dd898c9b93a82f51e
--- 1/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
--- 2/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@@ -3482,9 -3286,9 +3947,10 @@@ static struct omap_hwmod_ocp_if *dra7xx
        &dra7xx_l4_cfg__dma_system,
        &dra7xx_l3_main_1__dss,
        &dra7xx_l3_main_1__dispc,
 +      &dra7xx_dsp1__l3_main_1,
        &dra7xx_l3_main_1__hdmi,
-       &dra7xx_l3_main_1__aes,
+       &dra7xx_l3_main_1__aes1,
+       &dra7xx_l3_main_1__aes2,
        &dra7xx_l3_main_1__sha0,
        &dra7xx_l4_per1__elm,
        &dra7xx_l4_wkup__gpio1,

diff --cc drivers/clk/ti/clk-7xx.c
index 1379f0b3af23c6339cc6c8b08b0fcd73be9c5e1e,b90bec1d86409adda24d0d2d3381849b39b884d4..b374507af1471423442163b4256d4bc966520853
--- 1/drivers/clk/ti/clk-7xx.c
--- 2/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@@ -16,12 -16,10 +16,14 @@@
  #include <linux/clkdev.h>
  #include <linux/clk/ti.h>
  
- #define DRA7_DPLL_ABE_DEFFREQ                         361267200
+ #define DRA7_DPLL_ABE_DEFFREQ                         180633600
  #define DRA7_DPLL_GMAC_DEFFREQ                                1000000000
 +#define DRA7_DPLL_DSP_DEFFREQ                         600000000
 +#define DRA7_DPLL_DSP_GFCLK_NOMFREQ                   600000000
 +#define DRA7_DPLL_EVE_GCLK_NOMFREQ                    400000000
 +
+ #define DRA7_ATL_DEFFREQ                              5644800
+ #define DRA7_DPLL_USB_DEFFREQ                         960000000
  
  static struct ti_dt_clk dra7xx_clks[] = {
        DT_CLK(NULL, "atl_clkin0_ck", "atl_clkin0_ck"),
@@@ -311,8 -316,7 +320,9 @@@ int __init dra7xx_dt_clk_init(void
  {
        int rc;
        struct clk *abe_dpll_mux, *sys_clkin2, *dpll_ck, *dss_deshdcp_ck;
 +      struct clk *ipu1_gfclk, *ipu1_gfclk_parent;
 +      struct clk *dsp_dpll, *dsp_m2_dpll, *dsp_m3x2_dpll;
+       struct clk *atl_fck, *atl_parent;
  
        ti_dt_clocks_register(dra7xx_clks);
  
@@@ -338,29 -347,31 +353,55 @@@
        if (rc)
                pr_err("%s: failed to enable DESHDCP clock\n", __func__);
  
 +      ipu1_gfclk = clk_get_sys(NULL, "ipu1_gfclk_mux");
 +      ipu1_gfclk_parent = clk_get_sys(NULL, "dpll_core_h22x2_ck");
 +      rc = clk_set_parent(ipu1_gfclk, ipu1_gfclk_parent);
 +      if (rc)
 +              pr_err("%s: failed to reparent ipu1_gfclk_mux\n", __func__);
 +
 +      dsp_dpll = clk_get_sys(NULL, "dpll_dsp_ck");
 +      rc = clk_set_rate(dsp_dpll, DRA7_DPLL_DSP_DEFFREQ);
 +      if (!rc) {
 +              dsp_m2_dpll = clk_get_sys(NULL, "dpll_dsp_m2_ck");
 +              rc = clk_set_rate(dsp_m2_dpll, DRA7_DPLL_DSP_GFCLK_NOMFREQ);
 +              if (rc)
 +                      pr_err("%s: failed to configure DSP DPLL m2 output!\n",
 +                             __func__);
 +
 +              dsp_m3x2_dpll = clk_get_sys(NULL, "dpll_dsp_m3x2_ck");
 +              rc = clk_set_rate(dsp_m3x2_dpll, DRA7_DPLL_EVE_GCLK_NOMFREQ);
 +              if (rc)
 +                      pr_err("%s: failed to configure DSP DPLL m3x2 divider!\n",
 +                             __func__);
 +      } else {
 +              pr_err("%s: failed to configure DSP DPLL!\n", __func__);
 +      }
 +
+       atl_fck = clk_get_sys(NULL, "atl_gfclk_mux");
+       atl_parent = clk_get_sys(NULL, "dpll_abe_m2_ck");
+       rc = clk_set_parent(atl_fck, atl_parent);
+       if (rc)
+               pr_err("%s: failed to reparent atl_gfclk_mux\n", __func__);
+ 
+       atl_fck = clk_get_sys(NULL, "atl_clkin2_ck");
+       rc = clk_set_rate(atl_fck, DRA7_ATL_DEFFREQ);
+       if (rc)
+               pr_err("%s: failed to set atl_clkin2_ck\n", __func__);
+ 
+       atl_fck = clk_get_sys(NULL, "atl_clkin1_ck");
+       rc = clk_set_rate(atl_fck, DRA7_ATL_DEFFREQ);
+       if (rc)
+               pr_err("%s: failed to set atl_clkin1_ck\n", __func__);
+ 
+       dpll_ck = clk_get_sys(NULL, "dpll_usb_ck");
+       rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ);
+       if (rc)
+               pr_err("%s: failed to configure USB DPLL!\n", __func__);
+ 
+       dpll_ck = clk_get_sys(NULL, "dpll_usb_m2_ck");
+       rc = clk_set_rate(dpll_ck, DRA7_DPLL_USB_DEFFREQ/2);
+       if (rc)
+               pr_err("%s: failed to set USB_DPLL M2 OUT\n", __func__);
+ 
        return rc;
  }