| author | Praneeth Bajjuri <praneeth@ti.com> | |
| Thu, 13 Jun 2013 23:22:51 +0000 (18:22 -0500) | ||
| committer | Praneeth Bajjuri <praneeth@ti.com> | |
| Thu, 13 Jun 2013 23:22:51 +0000 (18:22 -0500) |
* p-ti-linux-3.8.y: (406 commits)
ARM: OMAP4+: omap2plus_defconfig: Enable audio via TWL6040 as module
ASoC: OMAP4+: AESS: aess_mem: Activate AESS for memory/register access
ARM: dts: OMAP5: AESS: Fix AESS L3 Interconnect address
ASoC: OMAP: ABE: Pick working ABE support from LDC audio branch
TI-Integration: ARM: OMAP2+: Fix merege by restoring omap_mcasp_init() call
omapdss: TFCS panel: Check for successful TLC driver registration before using it
omapdss: DSS DPLLs: Ignore PLL_PWR_STATUS on DRA7
ARM: DRA7: dts: Add the sdma dt node and corresponding dma request lines for mmc
ARM: dra7: dts: Add a fixed regulator node needed for eMMC
arm/dts: dra7: Add ldo regulator for mmc1
arm/dts: dra7: Add mmc controller nodes and board data
ARM: DRA: hwmod: Correct the dma line names for mmc
arch: arm: configs: Add support for DRA7 evm in omap2plus_defconfig
arm: dts: dra7-evm: Add pinmux configs needed for display
HACK: pinctrl: pinctrl single: Make pinctrl-single init early
OMAPDSS:HDMI: Change PLL calculations
omapdss: hdmi: fix deepcolor mode configuration
ARM: dts: DRA7x: Add DMM bindings
omapdrm: hack: Assign managers/channel to outputs in a more trivial way
gpu: drm: omap: Use bitmaps for placement
...
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
ARM: OMAP4+: omap2plus_defconfig: Enable audio via TWL6040 as module
ASoC: OMAP4+: AESS: aess_mem: Activate AESS for memory/register access
ARM: dts: OMAP5: AESS: Fix AESS L3 Interconnect address
ASoC: OMAP: ABE: Pick working ABE support from LDC audio branch
TI-Integration: ARM: OMAP2+: Fix merege by restoring omap_mcasp_init() call
omapdss: TFCS panel: Check for successful TLC driver registration before using it
omapdss: DSS DPLLs: Ignore PLL_PWR_STATUS on DRA7
ARM: DRA7: dts: Add the sdma dt node and corresponding dma request lines for mmc
ARM: dra7: dts: Add a fixed regulator node needed for eMMC
arm/dts: dra7: Add ldo regulator for mmc1
arm/dts: dra7: Add mmc controller nodes and board data
ARM: DRA: hwmod: Correct the dma line names for mmc
arch: arm: configs: Add support for DRA7 evm in omap2plus_defconfig
arm: dts: dra7-evm: Add pinmux configs needed for display
HACK: pinctrl: pinctrl single: Make pinctrl-single init early
OMAPDSS:HDMI: Change PLL calculations
omapdss: hdmi: fix deepcolor mode configuration
ARM: dts: DRA7x: Add DMM bindings
omapdrm: hack: Assign managers/channel to outputs in a more trivial way
gpu: drm: omap: Use bitmaps for placement
...
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
495 files changed:
diff --git a/Documentation/devicetree/bindings/arm/omap/dmm.txt b/Documentation/devicetree/bindings/arm/omap/dmm.txt
--- /dev/null
@@ -0,0 +1,17 @@
+OMAP Dynamic Memory Manager (DMM) bindings
+
+Required properties:
+- compatible: Must be "ti,omap4-dmm" for OMAP4 family
+ Must be "ti,omap5-dmm" for OMAP5 family
+- reg: Contains timer register address range (base address and length)
+- interrupts: Contains interrupt information (source, etc) for the DMM IRQ
+- ti,hwmods: Name of the hwmod associated to the counter, which is typically
+ "dmm"
+
+Example:
+
+dmm: dmm@4e000000 {
+ compatible = "ti,omap4-dmm";
+ reg = <0x4e000000 0x800>;
+ ti,hwmods = "dmm";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index d0051a7505873e14d17c5a8718179f19475a78bc..4f87488af6cb7e402126b8a766d482fa38492638 100644 (file)
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
+
+- DRA7 EVM: Software Developement Board for DRA7XX
+ compatible = "ti,dra7-evm", "ti,dra7"
diff --git a/Documentation/devicetree/bindings/clock/palmas-clk.txt b/Documentation/devicetree/bindings/clock/palmas-clk.txt
--- /dev/null
@@ -0,0 +1,27 @@
+* palmas and palmas-charger resource clock IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-clk
+ ti,twl6036-clk
+ ti,twl6037-clk
+ ti,tps65913-clk
+ ti,tps65914-clk
+ ti,tps80036-clk
+and also the generic series names
+ ti,palmas-clk
+
+Optional properties:
+- ti,clk32g-mode-sleep - mode to adopt in pmic sleep 0 - off, 1 - on
+- ti,clkg32kgaudio-mode-sleep - see above
+
+Example:
+
+clk {
+ compatible = "ti,twl6035-clk", "ti,palmas-clk";
+ ti,clk32kg-mode-sleep = <0>;
+ ti,clk32kgaudio-mode-sleep = <0>;
+ #clock-cells = <1>;
+ clock-frequency = <32000000>;
+ clock-names = "clk32kg", "clk32kgaudio";
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-palmas.txt b/Documentation/devicetree/bindings/gpio/gpio-palmas.txt
--- /dev/null
@@ -0,0 +1,35 @@
+* palmas and palmas charger GPIO IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-gpio
+ ti,twl6036-gpio
+ ti,twl6037-gpio
+ ti,tps65913-gpio
+ ti,tps65914-gpio
+ ti,tps80036-gpio
+
+and also the generic series names
+
+ ti,palmas-gpio
+
+- gpio-controller: mark the device as a GPIO controller
+- gpio-cells = <1>: GPIO lines are provided.
+- interrupt-controller : palmas has its own internal IRQs
+- #interrupt-cells : should be set to 2 for IRQ number and flags
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as the trigger masks from
+ Documentation/devicetree/bindings/interrupts.txt
+- interrupt-parent : The parent interrupt controller.
+
+Example:
+
+gpio {
+ compatible = "ti,twl6035-gpio", "ti,palmas-gpio";
+
+ gpio-controller;
+ #gpio-cells = <1>;
+ interrupt-parent = <&palmas>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt b/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt
--- /dev/null
@@ -0,0 +1,26 @@
+* palmas and palmas-charger Button IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-pwrbutton
+ ti,twl6036-pwrbutton
+ ti,twl6037-pwrbutton
+ ti,tps65913-pwrbutton
+ ti,tps65914-pwrbutton
+ ti,tps80036-pwrbutton
+and also the generic series names
+ ti,palmas-pwrbutton
+
+- interrupts: the interrupt outputs of the controller.
+- interrupt-names : Should be the name of irq resource. Each interrupt
+ binds its interrupt-name.
+- interrupt-parent : The parent interrupt controller.
+
+Example:
+
+pwrbutton {
+ compatible = "ti,twl6035-pwrbutton", "ti,palmas-pwrbutton";
+ interrupt-parent = <&palmas>;
+ interrupts = <1 0>;
+ interrupt-names = "pwron-irq";
+};
diff --git a/Documentation/devicetree/bindings/leds/leds-palmas.txt b/Documentation/devicetree/bindings/leds/leds-palmas.txt
--- /dev/null
@@ -0,0 +1,36 @@
+* palmas and palmas-charger LED IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-leds
+ ti,twl6036-leds
+ ti,twl6037-leds
+ ti,tps65913-leds
+ ti,tps65914-leds
+ ti,tps80036-leds
+and also the generic series names
+ ti,palmas-leds
+
+Optional properties:
+-ti,led1-current - sink current setting 0 - 0mA, 1 - 25mA, 2 - 5mA,
+ 3 - 0mA, 4 - 5mA, 5 - 5mA, 6 - 10.0mA, 7 - 0mA
+-ti,led2-current - see above
+-ti,led3-current - see above
+-ti,led4-current - see above
+-ti,chrg-led-mode - only valid for charger - mode for charging led operation
+ 0 - Charging indicator
+ 1 - controlled as a general purpose LED
+-ti,chrg-led-vbat-low - only valid for charger - blinking of low battery led
+ 0 - blinking is enabled,
+ 1 - blinking is disabled
+
+Example:
+leds {
+ compatible = "ti,twl6035-leds", "ti,palmas-leds";
+ ti,led1-current = <0>;
+ ti,led2-current = <0>;
+ ti,led3-current = <0>;
+ ti,led4-current = <0>;
+ ti,chrg-led-mode = <0>;
+ ti,chrg-led-vbat-low = <0>;
+};
diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt
index 94a0c12789461f399244d206f130adf2081b564a..3defba700eed5a3414689396325ca73049bd007f 100644 (file)
-Texas Instruments Palmas family
-
-The Palmas familly are Integrated Power Management Chips.
-These chips are connected to an i2c bus.
+* palmas and palmas-charger device tree bindings
+The TI palmas family current members :-
+twl6035 (palmas)
+twl6036 (palmas-charger)
+twl6037 (palmas)
+tps65913 (palmas)
+tps65914 (palmas)
+tps80036 (palmas-charger)
Required properties:
-- compatible : Must be "ti,palmas";
- For Integrated power-management in the palmas series, twl6035, twl6037,
- tps65913
-- interrupts : This i2c device has an IRQ line connected to the main SoC
-- interrupt-controller : Since the palmas support several interrupts internally,
- it is considered as an interrupt controller cascaded to the SoC one.
-- #interrupt-cells = <1>;
+- compatible : Should be from the list
+ ti,twl6035
+ ti,twl6036
+ ti,twl6037
+ ti,tps65913
+ ti,tps65914
+ ti,tps80036
+ ti,tps659038
+and also the generic series names
+ ti,palmas
+ ti,palmas-charger
+- interrupt-controller : palmas has its own internal IRQs
+- #interrupt-cells : should be set to 2 for IRQ number and flags
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as the trigger masks from
+ Documentation/devicetree/bindings/interrupts.txt
- interrupt-parent : The parent interrupt controller.
-Optional node:
-- Child nodes contain in the palmas. The palmas family is made of several
- variants that support a different number of features.
- The child nodes will thus depend of the capability of the variant.
-- mux_pad1 if a value is given it will be used for the pad1 mux
-- mux_pad2 if a value us given it will be used for the pad2 mux
-- power_ctrl if a value is given it will be written to the POWER_CTRL register
+Optional properties:
+ ti,mux_padX : set the pad register X (1-2) to the correct muxing for the
+ hardware, if not set will use muxing in OTP.
Example:
-/*
- * Integrated Power Management Chip Palmas
- */
-palmas@48 {
- compatible = "ti,palmas";
- reg = <0x48>;
- interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,mux_pad1 = <0x00>;
- ti,mux_pad2 = <0x00>;
- ti,power_ctrl = <0x03>;
+palmas {
+ compatible = "ti,twl6035", "ti,palmas";
+ reg = <0x48>
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,mux-pad1 = <0>;
+ ti,mux-pad2 = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic {
+ compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+ ....
+ }
+
+ gpio {
+ compatible = "ti,twl6035-gpio", "ti,palmas-gpio";
+ ....
+ };
+
+ wdt {
+ compatible = "ti,twl6035-wdt", "ti,palmas-wdt";
+ ....
+ };
+
+ rtc {
+ compatible = "ti,twl6035-rtc", "ti,palmas-rtc";
+ ....
+ };
- palmas_pmic {
- compatible = "ti,palmas_pmic";
- regulators {
- smps12_reg: smps12 {
- regulator-min-microvolt = < 600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- ti,warm_sleep = <0>;
- ti,roof_floor = <0>;
- ti,mode_sleep = <0>;
- ti,warm_reset = <0>;
- ti,tstep = <0>;
- ti,vsel = <0>;
- };
- };
- ti,ldo6_vibrator = <0>;
+ pwrbutton {
+ compatible = "ti,twl6035-pwrbutton", "ti,palmas-pwrbutton";
+ ....
};
- palmas_rtc {
- compatible = "ti,palmas_rtc";
- interrupts = <8 9>;
- reg = <0>;
- };
-};
+ leds {
+ compatible = "ti,twl6035-leds", "ti-palmas-leds";
+ }
+
+ clk {
+ compatible = "ti,twl6035-clk", "ti,palmas-clk";
+ ....
+ };
+}
diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
--- /dev/null
@@ -0,0 +1,169 @@
+* palmas and palmas-charger regulator IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-pmic
+ ti,twl6036-pmic
+ ti,twl6037-pmic
+ ti,tps65913-pmic
+ ti,tps65914-pmic
+ ti,tps80036-pmic
+ ti,tps659038-pmic
+and also the generic series names
+ ti,palmas-pmic
+
+Optional properties:
+- ti,ldo6-vibrator : ldo6 is in vibrator mode
+
+Optional nodes:
+- regulators : should contain the constrains and init information for the
+ regulators. It should contain a subnode per regulator from the
+ list.
+ For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
+ smps45, smps457, smps7 depending on varient, smps6, smps[8-10],
+ ldo[1-9], ldoln, ldousb
+ For ti,palmas-charger-pmic - smps12, smps123, smps3 depending on OTP,
+ smps[6-9], boost, ldo[1-14], ldoln, ldousb
+
+ optional chip specific regulator fields :-
+ ti,warm-reset - maintain voltage during warm reset
+ ti,roof-floor - control voltage selection by pin
+ ti,sleep-mode - mode to adopt in pmic sleep 0 - off, 1 - auto,
+ 2 - eco, 3 - forced pwm
+ ti,tstep - slope control 0 - Jump, 1 10mV/us, 2 5mV/us, 3 2.5mV/us
+ ti,smps-range - OTP has the wrong range set for the hardware so override
+ 0 - low range, 1 - high range
+
+Example:
+
+pmic@0 {
+ compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+ interrupt-parent = <&palmas>;
+ interrupts = <14 0>;
+ interrupt-name = "short-irq";
+
+ ti,ldo6_vibrator;
+
+ regulators {
+ smps12_reg : smps12 {
+ regulator-name = "smps12";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,warm-reset;
+ ti,roof-floor;
+ ti,mode-sleep = <0>;
+ ti,tstep = <0>;
+ ti,smps-range = <1>;
+ };
+
+ smps3_reg: smps3 {
+ regulator-name = "smps3";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ };
+
+ smps45_reg: smps45 {
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ };
+
+ smps6_reg: smps6 {
+ regulator-name = "smps6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ smps7_reg: smps7 {
+ regulator-name = "smps7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ smps8_reg: smps8 {
+ regulator-name = "smps8";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ };
+
+ smps9_reg: smps9 {
+ regulator-name = "smps9";
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ smps10_reg: smps10 {
+ regulator-name = "smps10";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldoln_reg: ldoln {
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldousb_reg: ldousb {
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3250000>;
+ regulator-max-microvolt = <3250000>;
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/regulator/ti-avs-class0.txt b/Documentation/devicetree/bindings/regulator/ti-avs-class0.txt
--- /dev/null
@@ -0,0 +1,66 @@
+Texas Instrument SmartReflex AVS Class 0 Regulator
+
+Required properties:
+- compatible: "ti,avsclass0"
+- reg: Should contain Efuse registers location and length
+- avs-supply: The supply for AVS block
+- efuse-settings: An array of 2-tuples items, and each item consists
+ of Voltage index and efuse offset(from reg) like: <voltage offset>
+ voltage: Voltage index in microvolts (also called nominal voltage)
+ offset: ofset in bytes from base provided in reg
+ NOTE: min_uV, max_uV are pickedup from this list
+
+Optional properties:
+- voltage-tolerance: Specify the voltage tolerance in percentage
+- ti,avsclass0-microvolt-values: Boolean property indicating that the efuse
+ values are in microvolts
+
+Example #1: single rails:
+soc.dtsi:
+avs_mpu: regulator-avs@0x40200000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40200000 0x20>;
+ efuse-settings = <975000 0
+ 1075000 4
+ 1200000 8>;
+};
+
+avs_core: regulator-avs@0x40300000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40300000 0x20>;
+ efuse-settings = <975000 0
+ 1050000 4>;
+};
+
+board.dtsi:
+&avs_mpu {
+ avs-supply = <&vcc>;
+};
+&avs_core {
+ avs-supply = <&smps2>;
+};
+
+Example #2: Ganged (combined) rails:
+soc.dtsi:
+avs_mpu: regulator-avs@0x40200000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40200000 0x20>;
+ efuse-settings = <975000 0
+ 1075000 4
+ 1200000 8>;
+};
+
+avs_core: regulator-avs@0x40300000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40300000 0x20>;
+ efuse-settings = <975000 0
+ 1050000 4>;
+};
+
+board.dtsi:
+&avs_mpu {
+ avs-supply = <&smps3>;
+};
+&avs_core {
+ avs-supply = <&smps3>;
+};
diff --git a/Documentation/devicetree/bindings/rtc/palmas-rtc.txt b/Documentation/devicetree/bindings/rtc/palmas-rtc.txt
--- /dev/null
@@ -0,0 +1,21 @@
+* palmas and palmas-charger RTC IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-rtc
+ ti,twl6036-rtc
+ ti,twl6037-rtc
+ ti,tps65913-rtc
+ ti,tps65914-rtc
+ ti,tps80036-rtc
+and also the generic series names
+ ti,palmas-rtc
+
+Examples:
+
+rtc {
+ compatible = "ti,twl6035-rtc", "ti,palmas-rtc";
+ interrupt-parent = <&palmas>;
+ interrupts = <8 0 9 0>;
+ interrupt-name = "alarm-irq", "timer-irq";
+};
diff --git a/Documentation/devicetree/bindings/watchdog/palmas-wdt.txt b/Documentation/devicetree/bindings/watchdog/palmas-wdt.txt
--- /dev/null
@@ -0,0 +1,21 @@
+* palmas and palmas-charger Watchdog IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-wdt
+ ti,twl6036-wdt
+ ti,twl6037-wdt
+ ti,tps65913-wdt
+ ti,tps65914-wdt
+ ti,tps80036-wdt
+and also the generic series names
+ ti,palmas-wdt
+
+Examples:
+
+wdt {
+ compatible = "ti,twl6035-wdt", "ti,palmas-wdt";
+ interrupt-parent = <&palmas>;
+ interrupts = <10 0>;
+ interrupt-name = "watchdog-irq";
+};
diff --git a/Makefile b/Makefile
index 7684f9518e04a14956f9975a725a49d25f340594..183eff3e92d3c226481af48f42e1bf217f81ef27 100644 (file)
--- a/Makefile
+++ b/Makefile
VERSION = 3
PATCHLEVEL = 8
-SUBLEVEL = 8
+SUBLEVEL = 13
EXTRAVERSION =
NAME = Displaced Humerus Anterior
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5f23fb1ef9c886845d0a77417e9e2f04baadfc77..1def7c896b50902dc72b60cd61706fef9416bad1 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 355 if ARCH_U8500
default 264 if MACH_H4700
- default 512 if SOC_OMAP5
+ default 512 if SOC_OMAP5 || SOC_DRA7XX
default 288 if ARCH_VT8500
default 0
help
index 5cad8a6dadb021fd2aef0a4ef1a77c40173041e7..dfe56872a7a997e88fff99bab5ce42de077e3614 100644 (file)
endif
ccflags-y := -fpic -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all -DZIMAGE
+asflags-y := -DZIMAGE
# Supply kernel BSS size to the decompressor via a linker symbol.
KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
index 4324416e26d5aa56664676c69f52209e15e3b567..0ccfd668bd8fd2cde51ad96dc79116e27837142a 100644 (file)
* to cover all 32bit address and cacheable and bufferable.
*/
__armv4_mpu_cache_on:
+ .arch armv4
mov r0, #0x3f @ 4G, the whole
mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
mcr p15, 0, r0, c6, c7, 1
@ Enable unaligned access on v6, to allow better code generation
@ for the decompressor C code:
__armv6_mmu_cache_on:
+ .arch armv6
mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
bic r0, r0, #2 @ A (no unaligned access fault)
orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
__arm926ejs_mmu_cache_on:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+ .arch armv5
mov r0, #4 @ put dcache in WT mode
mcr p15, 7, r0, c15, c0, 0
#endif
__armv4_mmu_cache_on:
+ .arch armv4
mov r12, lr
#ifdef CONFIG_MMU
mov r6, #CB_BITS | 0x12 @ U
mov pc, r12
__armv7_mmu_cache_on:
+ .arch armv7-a
mov r12, lr
#ifdef CONFIG_MMU
mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
mov r3, #16
b call_cache_fn
+ .arch armv4
__armv4_mpu_cache_flush:
mov r2, #1
mov r3, #0
mov pc, lr
__armv6_mmu_cache_flush:
+ .arch armv6
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
+ .arch armv7-a
__armv7_mmu_cache_flush:
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
mcr p15, 0, r10, c7, c5, 4 @ ISB
mov pc, lr
+ .arch armv5
__armv5tej_mmu_cache_flush:
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
+ .arch armv4
__armv4_mmu_cache_flush:
mov r2, #64*1024 @ default: 32K dcache size (*2)
mov r11, #32 @ default: 32 byte line size
mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
mov pc, lr
+ .arch armv4
+
/*
* Various debugging routines for printing hex characters and
* memory, which again must be relocatable.
index 55ce4dff88b46bc91e15713807585724458aeaed..101fed319815346ee54a96bae8f30fd0131a9ffa 100644 (file)
omap5-sevm.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
- am335x-bone.dtb
+ am335x-bone.dtb \
+ am335x-boneblack.dtb \
+ dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
index ecac1e7b0b4913959d05858ccba4a49aba9e0734..725aa632b5bc9f3bea8d058500616e803d92339f 100644 (file)
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <>;
+ pinctrl-0 = <&clkout2_pin>;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN | MODE0 */
>;
};
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ >;
+ };
};
ocp {
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
--- /dev/null
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "am33xx.dtsi"
+
+/ {
+ model = "TI AM335x BeagleBone Black";
+ compatible = "ti,am335x-boneblack", "ti,am335x-bone", "ti,am33xx";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&dcdc2_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ am33xx_pinmux: pinmux@44e10800 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkout2_pin>;
+
+ userled_pins: pinmux_userled_pins {
+ pinctrl-single,pins = <
+ 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
+ 0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
+ 0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
+ 0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+ >;
+ };
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ 0x188 0x70 /* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */
+ 0x18c 0x70 /* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP |INPUTENABLE | MODE0 */
+ 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN | MODE0 */
+ >;
+ };
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ >;
+ };
+ };
+
+ ocp: ocp {
+ uart0: serial@44e09000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+ };
+
+ i2c0: i2c@44e0b000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@24 {
+ reg = <0x24>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "at,24c256";
+ reg = <0x50>;
+ };
+ };
+
+ rtc@44e3e000 {
+ ti,system-power-controller;
+ };
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&userled_pins>;
+
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "beaglebone:green:heartbeat";
+ gpios = <&gpio1 21 0>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led1 {
+ label = "beaglebone:green:mmc0";
+ gpios = <&gpio1 22 0>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio1 23 0>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio1 24 0>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+ };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+ ti,pmic-shutdown-controller;
+
+ regulators {
+ dcdc1_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1325000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@3 {
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@6 {
+ regulator-always-on;
+ };
+ };
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
index ae4189be800568bd509d564dee82b1f34bbc7a28..b0ca6277212dfa228b5848f7f3b253878dfb588b 100644 (file)
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+ pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
matrix_keypad_s0: matrix_keypad_s0 {
pinctrl-single,pins = <
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN | MODE0 */
>;
};
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ >;
+ };
};
ocp {
&aes {
status = "okay";
};
+
+&tscadc {
+ tsc {
+ ti,wires = <4>;
+ ti,x-plate-resistance = <200>;
+ ti,steps-to-configure = <5>;
+ ti,wire-config = <0x00 0x11 0x22 0x33>;
+ };
+
+ adc {
+ ti,adc-channels = <4>;
+ };
+};
index b7c9e68c112d462b46a76a4485ac012b922b75e3..caa7f9a75efa9e68358eeac9c68d00b203d17ae8 100644 (file)
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_s0>;
+ pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN | MODE0 */
>;
};
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ >;
+ };
};
ocp {
index 970c015acb83a318b0564dd4e1fd6816072e7640..8b6ae5765591af656d17f3719e23a1e16796124f 100644 (file)
&edma 5>;
dma-names = "tx", "rx";
};
+
+ tscadc: tscadc@44e0d000 {
+ compatible = "ti,ti-tscadc";
+ reg = <0x44e0d000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <16>;
+ ti,hwmods = "adc_tsc";
+ status = "disabled";
+ };
};
};
index cb7bcc51608d81cd51bba98ec29455973ca9daf0..02b70a404a1fafbd951423a697f28e64cfc6958c 100644 (file)
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <2 6 0x1 0x1 /* PB6 periph A with pullup */
- 2 7 0x1 0x0>; /* PB7 periph A */
+ <1 6 0x1 0x1 /* PB6 periph A with pullup */
+ 1 7 0x1 0x0>; /* PB7 periph A */
};
pinctrl_usart1_rts: usart1_rts-0 {
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <2 10 0x1 0x1 /* PB10 periph A with pullup */
- 2 11 0x1 0x0>; /* PB11 periph A */
+ <1 10 0x1 0x1 /* PB10 periph A with pullup */
+ 1 11 0x1 0x0>; /* PB11 periph A */
};
pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
- <3 8 0x2 0x0>; /* PB8 periph B */
+ <2 8 0x2 0x0>; /* PC8 periph B */
};
pinctrl_usart3_cts: usart3_cts-0 {
atmel,pins =
- <3 10 0x2 0x0>; /* PB10 periph B */
+ <2 10 0x2 0x0>; /* PC10 periph B */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
- <2 12 0x1 0x1 /* PB12 periph A with pullup */
- 2 13 0x1 0x0>; /* PB13 periph A */
+ <1 12 0x1 0x1 /* PB12 periph A with pullup */
+ 1 13 0x1 0x0>; /* PB13 periph A */
};
};
index fbe7a7089c2adbc82da7d3ef995b6506c1089d1d..28467fd6bf9689901d6d41e59369bb5278079630 100644 (file)
/ {
model = "Atmel AT91SAM9G15 SoC";
- compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9g15", "atmel,at91sam9x5";
ahb {
apb {
index 86dd3f6d938ff272334102894fd4e2d9e17c4457..5427b2dba87e34150e1fb2f4dd0e60652fcf5d2d 100644 (file)
/include/ "at91sam9x5ek.dtsi"
/ {
- model = "Atmel AT91SAM9G25-EK";
+ model = "Atmel AT91SAM9G15-EK";
compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
};
index 05a718fb83c49b4cfa1fcb35be13b4e9ff2d2ec6..5fd32df03f25d9551494fd40b5793882b6a966c3 100644 (file)
/ {
model = "Atmel AT91SAM9G25 SoC";
- compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9g25", "atmel,at91sam9x5";
ahb {
apb {
index f9d14a722794eb0f927ecb03eeac0d790f0efff7..d6fa8af50724ab6bb37b96426950bf7aa86fccca 100644 (file)
/ {
model = "Atmel AT91SAM9G35 SoC";
- compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9g35", "atmel,at91sam9x5";
ahb {
apb {
index 54eb33ba6d22ba6e308d756518e8481056a19890..9ac2bc2b4f07cd36eca29c2172607d4e84c631bb 100644 (file)
/ {
model = "Atmel AT91SAM9X25 SoC";
- compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9x25", "atmel,at91sam9x5";
ahb {
apb {
index fb102d6126ce696234133a2869c7f84a5db888ee..ba67d83d17ac5d3821f5018773a54a0342f98081 100644 (file)
/ {
model = "Atmel AT91SAM9X35 SoC";
- compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9x35", "atmel,at91sam9x5";
ahb {
apb {
index 8a7cf1d9cf5db6f71ee002725151a6d968da40fa..ccab2568b0d7921ecb972db631b20d8f785d9299 100644 (file)
compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
- bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+ bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
};
ahb {
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
--- /dev/null
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "dra7.dtsi"
+
+/ {
+ model = "TI DRA7";
+ compatible = "ti,dra7-evm", "ti,dra7";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&avs_mpu>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+
+ vmmc2_fixed: fixedregulator-mmc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc2_fixed";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+};
+
+&dra7_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &vout1_pins
+ >;
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ 0x408 0x60000 /* i2c2_sda INPUT | MODE0 */
+ 0x40C 0x60000 /* i2c2_scl INPUT | MODE0 */
+ >;
+ };
+
+ vout1_pins: pinmux_vout1_pins {
+ pinctrl-single,pins = <
+ 0x1C8 0x0 /* vout1_clk OUTPUT | MODE0 */
+ 0x1CC 0x0 /* vout1_de OUTPUT | MODE0 */
+ 0x1D0 0x0 /* vout1_fld OUTPUT | MODE0 */
+ 0x1D4 0x0 /* vout1_hsync OUTPUT | MODE0 */
+ 0x1D8 0x0 /* vout1_vsync OUTPUT | MODE0 */
+ 0x1DC 0x0 /* vout1_d0 OUTPUT | MODE0 */
+ 0x1E0 0x0 /* vout1_d1 OUTPUT | MODE0 */
+ 0x1E4 0x0 /* vout1_d2 OUTPUT | MODE0 */
+ 0x1E8 0x0 /* vout1_d3 OUTPUT | MODE0 */
+ 0x1EC 0x0 /* vout1_d4 OUTPUT | MODE0 */
+ 0x1F0 0x0 /* vout1_d5 OUTPUT | MODE0 */
+ 0x1F4 0x0 /* vout1_d6 OUTPUT | MODE0 */
+ 0x1F8 0x0 /* vout1_d7 OUTPUT | MODE0 */
+ 0x1FC 0x0 /* vout1_d8 OUTPUT | MODE0 */
+ 0x200 0x0 /* vout1_d9 OUTPUT | MODE0 */
+ 0x204 0x0 /* vout1_d10 OUTPUT | MODE0 */
+ 0x208 0x0 /* vout1_d11 OUTPUT | MODE0 */
+ 0x20C 0x0 /* vout1_d12 OUTPUT | MODE0 */
+ 0x210 0x0 /* vout1_d13 OUTPUT | MODE0 */
+ 0x214 0x0 /* vout1_d14 OUTPUT | MODE0 */
+ 0x218 0x0 /* vout1_d15 OUTPUT | MODE0 */
+ 0x21C 0x0 /* vout1_d16 OUTPUT | MODE0 */
+ 0x220 0x0 /* vout1_d17 OUTPUT | MODE0 */
+ 0x224 0x0 /* vout1_d18 OUTPUT | MODE0 */
+ 0x228 0x0 /* vout1_d19 OUTPUT | MODE0 */
+ 0x22C 0x0 /* vout1_d20 OUTPUT | MODE0 */
+ 0x230 0x0 /* vout1_d21 OUTPUT | MODE0 */
+ 0x234 0x0 /* vout1_d22 OUTPUT | MODE0 */
+ 0x238 0x0 /* vout1_d23 OUTPUT | MODE0 */
+ >;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+
+ tps659038: tps659038@58 {
+ reg = <0x58>;
+ };
+
+ pcf_lcd: pcf8575@20 {
+ compatible = "ti,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ /* TLC chip for LCD panel power and backlight */
+ tlc59108: tlc59108@40 {
+ compatible = "ti,tlc59108";
+ reg = <0x40>;
+ gpios = <&pcf_lcd 15 0>; /* P15, CON_LCD_PWR_DN */
+ };
+};
+
+/include/ "tps659038.dtsi"
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ clock-frequency = <400000>;
+
+ pcf_hdmi: pcf8575@26 {
+ compatible = "ti,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+};
+
+&mmc1 {
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vmmc2_fixed>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&mmc3 {
+ bus-width = <8>;
+ ti,non-removable;
+ status = "disabled";
+};
+
+&mmc4 {
+ bus-width = <4>;
+ status = "disabled";
+};
+
+&avs_mpu {
+ avs-supply = <&smps123_reg>;
+};
+
+&avs_core {
+ avs-supply = <&smps7_reg>;
+};
+
+&avs_gpu {
+ avs-supply = <&smps6_reg>;
+};
+
+&avs_dspeve {
+ avs-supply = <&smps45_reg>;
+};
+
+&avs_iva {
+ avs-supply = <&smps8_reg>;
+};
+
+&dpi1 {
+ lcd {
+ compatible = "ti,tfc_s9700";
+ tlc = <&tlc59108>;
+ data-lines = <24>;
+ };
+};
+
+&hdmi {
+ tpd12s015: tpd12s015 {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&pcf_hdmi 4 0>, /* pcf8575@22 P4, CT_CP_HDP */
+ <&pcf_hdmi 5 0>, /* pcf8575@22 P5, LS_OE */
+ <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
+
+ hdmi_ddc = <&i2c2>;
+
+ hdmi-monitor {
+ compatible = "ti,hdmi_panel";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
--- /dev/null
@@ -0,0 +1,536 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "ti,dra7xx";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ operating-points = <
+ /* kHz uV */
+ /* The OPP_HIGH Only for DVFS enabled Samples Hence commenting*/
+ 1000000 1090000
+ /* 1176000 1210000 */
+ >;
+ clocks = <&dpll_mpu>;
+ clock-names = "cpu";
+ timer {
+ compatible = "arm,armv7-timer";
+ /*
+ * PPI secure/nonsecure IRQ,
+ * active low level-sensitive
+ */
+ interrupts = <1 13 0x308>,
+ <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /*
+ * PPI secure/nonsecure IRQ,
+ * active low level-sensitive
+ */
+ interrupts = <1 13 0x308>,
+ <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
+ };
+ };
+
+ gic: interrupt-controller@48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48211000 0x1000>,
+ <0x48212000 0x1000>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is uses for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap5-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the SOC interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since that will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap4-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2";
+
+ counter32k: counter@4ae04000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4ae04000 0x40>;
+ ti,hwmods = "counter_32k";
+ };
+
+ dra7_pmx_core: pinmux@4a003400 {
+ compatible = "pinctrl-single";
+ reg = <0x4a003400 0x0464>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x3fffffff>;
+ };
+
+ dpll_mpu: dpll_mpu {
+ #clock-cells = <0>;
+ compatible = "ti,omap-clock";
+ };
+
+ sdma: dma-controller@4a056000 {
+ compatible = "ti,omap4430-sdma";
+ reg = <0x4a056000 0x1000>;
+ interrupts = <0 12 0x4>,
+ <0 13 0x4>,
+ <0 14 0x4>,
+ <0 15 0x4>;
+ #dma-cells = <1>;
+ #dma-channels = <32>;
+ #dma-requests = <127>;
+ };
+
+ gpio1: gpio@4ae10000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4ae10000 0x200>;
+ interrupts = <0 29 0x4>;
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio2: gpio@48055000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48055000 0x200>;
+ interrupts = <0 30 0x4>;
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio3: gpio@48057000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48057000 0x200>;
+ interrupts = <0 31 0x4>;
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio4: gpio@48059000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48059000 0x200>;
+ interrupts = <0 32 0x4>;
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio5: gpio@4805b000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805b000 0x200>;
+ interrupts = <0 33 0x4>;
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio6: gpio@4805d000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805d000 0x200>;
+ interrupts = <0 34 0x4>;
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio7: gpio@48051000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48051000 0x200>;
+ interrupts = <0 35 0x4>;
+ ti,hwmods = "gpio7";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio8: gpio@48053000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48053000 0x200>;
+ interrupts = <0 121 0x4>;
+ ti,hwmods = "gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806a000 0x100>;
+ interrupts = <0 72 0x4>;
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806c000 0x100>;
+ interrupts = <0 73 0x4>;
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@48020000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48020000 0x100>;
+ interrupts = <0 74 0x4>;
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ uart4: serial@4806e000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806e000 0x100>;
+ interrupts = <0 70 0x4>;
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
+
+ uart5: serial@48066000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48066000 0x100>;
+ interrupts = <0 105 0x4>;
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ };
+
+ uart6: serial@48068000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48068000 0x100>;
+ interrupts = <0 106 0x4>;
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ };
+
+ timer1: timer@4ae18000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4ae18000 0x80>;
+ interrupts = <0 37 0x4>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer@48032000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48032000 0x80>;
+ interrupts = <0 38 0x4>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@48034000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48034000 0x80>;
+ interrupts = <0 39 0x4>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer@48036000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48036000 0x80>;
+ interrupts = <0 40 0x4>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer@48820000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48820000 0x80>;
+ interrupts = <0 41 0x4>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer@48822000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48822000 0x80>;
+ interrupts = <0 42 0x4>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer7: timer@48824000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48824000 0x80>;
+ interrupts = <0 43 0x4>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer@48826000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48826000 0x80>;
+ interrupts = <0 44 0x4>;
+ ti,hwmods = "timer8";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer9: timer@4803e000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4803e000 0x80>;
+ interrupts = <0 45 0x4>;
+ ti,hwmods = "timer9";
+ };
+
+ timer10: timer@48086000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48086000 0x80>;
+ interrupts = <0 46 0x4>;
+ ti,hwmods = "timer10";
+ };
+
+ timer11: timer@48088000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48088000 0x80>;
+ interrupts = <0 47 0x4>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
+
+ wdt2: wdt@4ae14000 {
+ compatible = "ti,omap4-wdt";
+ reg = <0x4ae14000 0x80>;
+ interrupts = <0 80 0x4>;
+ ti,hwmods = "wd_timer2";
+ };
+
+ dmm: dmm@4e000000 {
+ compatible = "ti,omap5-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
+ bandgap {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50>;
+ compatible = "ti,dra752-bandgap";
+ interrupts = <0 126 4>; /* talert */
+ };
+
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48070000 0x100>;
+ interrupts = <0 56 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48072000 0x100>;
+ interrupts = <0 57 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48060000 0x100>;
+ interrupts = <0 61 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ };
+
+ i2c4: i2c@4807a000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807a000 0x100>;
+ interrupts = <0 62 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c4";
+ };
+
+ i2c5: i2c@4807c000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807c000 0x100>;
+ interrupts = <0 60 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c5";
+ };
+
+ mmc1: mmc@4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x4809c000 0x400>;
+ interrupts = <0 83 0x4>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc2: mmc@480b4000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480b4000 0x400>;
+ interrupts = <0 86 0x4>;
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc3: mmc@480ad000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480ad000 0x400>;
+ interrupts = <0 94 0x4>;
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc4: mmc@480d1000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480d1000 0x400>;
+ interrupts = <0 96 0x4>;
+ ti,hwmods = "mmc4";
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ };
+
+ avs_mpu: regulator-avs@0x4A003B18 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A003B18 0x20>;
+ efuse-settings = <1090000 8
+ 1210000 12
+ 1280000 16>;
+ };
+
+ avs_core: regulator-avs@0x4A0025EC {
+ compatible = "ti,avsclass0";
+ reg = <0x4A0025EC 0x20>;
+ efuse-settings = <1030000 8>;
+ };
+
+ avs_gpu: regulator-avs@0x4A003B00 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A003B00 0x20>;
+ efuse-settings = <1090000 8
+ 1210000 12
+ 1280000 16>;
+ };
+
+ avs_dspeve: regulator-avs@0x4A0025D8 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A0025D8 0x20>;
+ efuse-settings = <1055000 8
+ 1150000 12
+ 1250000 16>;
+ };
+
+ avs_iva: regulator-avs@0x4A0025C4 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A0025C4 0x20>;
+ efuse-settings = <1055000 8
+ 1150000 12
+ 1250000 16>;
+ };
+
+ dss {
+ compatible = "ti,omap4-dss";
+ ti,hwmods = "dss_core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vdda_video-supply = <&ldoln_reg>;
+
+ dispc {
+ compatible = "ti,omap4-dispc";
+ ti,hwmods = "dss_dispc";
+ };
+
+ dpi1: dpi@1 {
+ compatible = "ti,dra7xx-dpi";
+ reg = <0>;
+ video-source = <0>;
+ };
+
+ dpi2: dpi@2 {
+ compatible = "ti,dra7xx-dpi";
+ reg = <1>;
+ video-source = <2>;
+ };
+
+ dpi3: dpi@3 {
+ compatible = "ti,dra7xx-dpi";
+ reg = <2>;
+ video-source = <3>;
+ };
+
+ hdmi: hdmi {
+ compatible = "ti,omap4-hdmi", "simple-bus";
+ ti,hwmods = "dss_hdmi";
+ vdda_hdmi_dac-supply = <&ldo3_reg>;
+ video-source = <1>;
+ };
+ };
+ };
+};
index 122fd99f7bf82d021403882561ef21e20f892e71..1676973af1c0b63e118971beddff9dde6a62b213 100644 (file)
reg = <0x80000000 0x40000000>; /* 1 GB */
};
- leds {
+ leds: leds {
compatible = "gpio-leds";
heartbeat {
label = "pandaboard::status1";
ti,mclk-freq = <38400000>;
ti,mcpdm = <&mcpdm>;
+ ti,mcbsp1 = <&mcbsp1>;
+ ti,mcbsp2 = <&mcbsp2>;
+ ti,aess = <&aess>;
ti,twl6040 = <&twl6040>;
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"AFML", "Line In",
- "AFMR", "Line In";
+ "AFMR", "Line In",
+ "Headset Playback", "PDM_DL1",
+ "Handsfree Playback", "PDM_DL2",
+ "PDM_UL1", "Capture",
+ "40122000.mcbsp Playback", "BT_VX_DL",
+ "BT_VX_UL", "40122000.mcbsp Capture",
+ "40124000.mcbsp Playback", "MM_EXT_DL",
+ "MM_EXT_UL", "40124000.mcbsp Capture";
+ };
+
+ sound_hdmi {
+ compatible = "ti,omap-hdmi-tpd12s015-audio";
+ ti,model = "OMAP4HDMI";
+
+ ti,hdmi_audio = <&hdmi>;
+ ti,level_shifter = <&tpd12s015>;
+ };
+
+ /* HS USB Port 1 RESET */
+ hsusb1_reset: hsusb1_reset_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb1_reset";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 30 0>; /* gpio_62 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ /* HS USB Port 1 Power */
+ hsusb1_power: hsusb1_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 1 0>; /* gpio_1 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 1 */
+ hsusb1_phy: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ reset-supply = <&hsusb1_reset>;
+ vcc-supply = <&hsusb1_power>;
+ };
+
+ /* hsusb1_phy is clocked by FREF_CLK3 i.e. auxclk3 */
+ clock_alias {
+ clock-name = "auxclk3_ck";
+ clock-alias = "main_clk";
+ device = <&hsusb1_phy>;
};
};
&mcbsp1_pins
&dss_hdmi_pins
&tpd12s015_pins
+ &hsusbb1_pins
+ &led_gpio_pins
>;
twl6040_pins: pinmux_twl6040_pins {
>;
};
+ hsusbb1_pins: pinmux_hsusbb1_pins {
+ pinctrl-single,pins = <
+ 0x82 0x10C /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk INPUT | PULLDOWN */
+ 0x84 0x4 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
+ 0x86 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
+ 0x88 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
+ 0x8a 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
+ 0x8c 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
+ 0x8e 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
+ 0x90 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
+ 0x92 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
+ 0x94 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
+ 0x96 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
+ 0x98 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+ >;
+ };
+
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
+
+ led_gpio_pins: pinmux_leds_pins {
+ pinctrl-single,pins = <
+ >;
+ };
+};
+
+&omap4_pmx_wkup {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &led_wkgpio_pins
+ >;
+
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins = <
+ 0x1a 0x3 /* gpio_wk7 OUTPUT | MODE 3 */
+ 0x1c 0x3 /* gpio_wk8 OUTPUT | MODE 3 */
+ >;
+ };
};
&i2c1 {
twl6040: twl@4b {
compatible = "ti,twl6040";
- reg = <0x4b>;
/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
interrupt-parent = <&gic>;
};
/include/ "twl6030.dtsi"
+/include/ "twl6040.dtsi"
&i2c2 {
pinctrl-names = "default";
device-handle = <&elpida_ECB240ABACN>;
};
-&mcbsp2 {
- status = "disabled";
-};
-
&mcbsp3 {
status = "disabled";
};
status = "disabled";
};
+&dpi {
+ dvi {
+ compatible = "ti,tfp410";
+ data-lines = <24>;
+ gpios = <&gpio1 0 0>; /* 0, power-down */
+ i2c-bus = <&i2c3>;
+ };
+};
+
+&hdmi {
+ tpd12s015: tpd12s015 {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&gpio2 28 0>, /* 60, CT CP HPD */
+ <&gpio2 9 0>, /* 41, LS OE */
+ <&gpio2 31 0>; /* 63, HPD */
+
+ hdmi {
+ compatible = "ti,hdmi_panel";
+ };
+
+ };
+};
+
&twl_usb_comparator {
usb-supply = <&vusb>;
};
+
+&usbhshost {
+ port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <&hsusb1_phy>;
+};
+
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+ power = <50>;
+};
index b1195f70225f88ae4224ba18e28898de55697f01..c9ba4372a7ed9d434c4346e6424ce4edd776edaf 100644 (file)
/include/ "omap4460.dtsi"
/include/ "omap4-panda-common.dtsi"
+&leds {
+ compatible = "gpio-leds";
+ heartbeat {
+ label = "pandaboard::status1";
+ gpios = <&gpio4 14 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ mmc {
+ label = "pandaboard::status2";
+ gpios = <&gpio1 8 0>;
+ linux,default-trigger = "gpio";
+ };
+};
+
+&led_gpio_pins {
+ pinctrl-single,pins = <
+ 0xb6 0x3 /* gpio_110 OUTPUT | MODE 3 */
+ >;
+};
+
+&omap4_pmx_wkup {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &led_wkgpio_pins
+ >;
+
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins = <
+ 0x1c 0x3 /* gpio_wk8 OUTPUT | MODE 3 */
+ >;
+ };
+};
+
/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
&sound {
ti,model = "PandaBoardES";
index f8b221f0168ee05920c8f4e2d91a905f3362ab62..1a23f5a7b362c0ee5bb240c97f35b0d077d51571 100644 (file)
*/
/dts-v1/;
-/include/ "omap443x.dtsi"
+/include/ "omap4.dtsi"
/include/ "omap4-panda-common.dtsi"
index 587b6651dfb334f44f7f1fc25582c7419e004aaa..403b879c6d87f4eecc84da59db971cf644190c1b 100644 (file)
pinctrl-single,function-mask = <0x7fff>;
};
+ sdma: dma-controller@4a056000 {
+ compatible = "ti,omap4430-sdma";
+ reg = <0x4a056000 0x1000>;
+ interrupts = <0 12 0x4>,
+ <0 13 0x4>,
+ <0 14 0x4>,
+ <0 15 0x4>;
+ #dma-cells = <1>;
+ #dma-channels = <32>;
+ #dma-requests = <127>;
+ };
+
+ dmm: dmm@4e000000 {
+ compatible = "ti,omap4-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
dss {
compatible = "ti,omap4-dss";
ti,hwmods = "dss_core";
vdda_hdmi_dac-supply = <&vdac>;
video-source = <1>;
};
- };
-
- sdma: dma-controller@4a056000 {
- compatible = "ti,omap4430-sdma";
- reg = <0x4a056000 0x1000>;
- interrupts = <0 12 0x4>,
- <0 13 0x4>,
- <0 14 0x4>,
- <0 15 0x4>;
- #dma-cells = <1>;
- #dma-channels = <32>;
- #dma-requests = <127>;
};
gpio1: gpio@4a310000 {
index b7a80eae30d39772876c3a8c335b8cf13d73319b..7b7b5347ef15df576b93d0c27864171bd8ca1a81 100644 (file)
ti,hdmi_audio = <&hdmi>;
ti,level_shifter = <&tpd12s015>;
};
+
+ leds {
+ compatible = "gpio-leds";
+ led@1 {
+ label = "omap5:blue:usr1";
+ gpios = <&gpio5 25 0>; /* gpio5_153 D1 LED */
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
};
&omap5_pmx_core {
&tpd12s015_pins
&tca6424a_pins
&palmas_pins
+ &led_gpio_pins
>;
twl6040_pins: pinmux_twl6040_pins {
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
0x0fc 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
- 0x100 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
- 0x102 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+ 0x100 0x106 /* GPIO7_194, DDC-SCL */
+ 0x102 0x106 /* GPIO7_195, DDC-SDA */
>;
};
0x140 0x11f /* MSLEEP INPUT | PULLUP | MODE7 */
>;
};
+
+ led_gpio_pins: pinmux_led_gpio_pins {
+ pinctrl-single,pins = <
+ 0x196 0x6 /* uart3_cts_rctx.gpio5_153 OUTPUT | MODE6 */
+ >;
+ };
};
&omap5_pmx_wkup {
gpios = <&tca6424a 0 0>, /* TCA6424A P01, CT_CP_HDP */
<&tca6424a 1 0>, /* TCA6424A P00, LS_OE*/
- <&gpio7 1 0>; /* 193, HPD */
+ <&gpio7 1 0>, /* 193, HPD */
+ <&gpio7 2 0>, /* 194, SCL */
+ <&gpio7 3 0>; /* 195, SDA */
+
hdmi-monitor {
compatible = "ti,hdmi_panel";
index f20e10ebfdc03d64e930d16592ec62469088b85e..3f1846ae98a6827208e9bf7b60db6f0dff05187f 100644 (file)
<0x401a0000 0x1fff>, /* CMEM - MPU */
<0x401c0000 0x5fff>, /* SMEM - MPU */
<0x401e0000 0x1fff>, /* PMEM - MPU */
- <0x4901f000 0x3ff>, /* L3 Interconnect */
+ <0x490f1000 0x3ff>, /* L3 Interconnect */
<0x49080000 0xffff>, /* DMEM - MPU */
<0x490a0000 0x1fff>, /* CMEM - MPU */
<0x490ce000 0x5fff>, /* SMEM - MPU */
ti,timer-pwm;
};
+ dmm: dmm@4e000000 {
+ compatible = "ti,omap5-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
emif1: emif@0x4c000000 {
compatible = "ti,emif-4d5";
ti,hwmods = "emif1";
diff --git a/arch/arm/boot/dts/tps659038.dtsi b/arch/arm/boot/dts/tps659038.dtsi
--- /dev/null
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/*
+ * TPS659038 is an Integrated Power Management Chip from Texas Instruments
+ * Data Manual - TPS659039-Q1 POWER MANAGEMENT UNIT (PMU) FOR PROCESSOR Data Manual
+ * Register Manual - TPS659038/39-Q1 Functional Register Descriptions.
+ */
+
+&tps659038 {
+ compatible = "ti,tps659038";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+ ti,ldo6_vibrator = <0>;
+ ti,smps10 = <0>;
+
+ regulators {
+ smps123_reg: smps123 {
+ regulator-name = "smps123";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps45_reg: smps45 {
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps6_reg: smps6 {
+ regulator-name = "smps6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps7_reg: smps7 {
+ regulator-name = "smps7";
+ regulator-min-microvolt = <1030000>;
+ regulator-max-microvolt = <1030000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps8_reg: smps8 {
+ regulator-name = "smps8";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps9_reg: smps9 {
+ regulator-name = "smps9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldoln_reg: ldoln {
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3250000>;
+ regulator-max-microvolt = <3250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
index 606d48f3b8f81c10370b718d7b2b3475818b9a03..8aab786863dfabac6854bf6ce1c6054074f61a28 100644 (file)
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_SDIO_UART=m
CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_ATMELMCI_DMA=y
CONFIG_LEDS_ATMEL_PWM=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGER_TIMER=y
index 15cd735d9259635b4fbb4e9e4109d0706c0bc324..8edf3b640a9df3e8ffe3020744b3821edecbceb6 100644 (file)
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_OMAP_MUX_DEBUG=y
CONFIG_SOC_OMAP5=y
+CONFIG_SOC_DRA7XX=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
CONFIG_SMP=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_GENERIC_CPUFREQ_CPU0=y
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
CONFIG_FPE_NWFPE=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PLATFORM=m
CONFIG_BT=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_H4=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SENSORS_TSL2550=m
+CONFIG_SENSORS_LIS3_I2C=m
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_TWL4030=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TWL4030=y
CONFIG_W1=y
CONFIG_POWER_SUPPLY=y
-CONFIG_WATCHDOG=y
+CONFIG_SENSORS_LM75=m
CONFIG_THERMAL=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_CPU_THERMAL=y
+CONFIG_WATCHDOG=y
CONFIG_OMAP_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=y
CONFIG_PALMAS_WATCHDOG=y
CONFIG_MFD_TPS65217=y
+CONFIG_TWL6040_CORE=y
CONFIG_REGULATOR_TWL4030=y
CONFIG_MFD_PALMAS=y
CONFIG_MFD_PALMAS_GPADC=y
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
CONFIG_USB_GSPCA=m
CONFIG_DRM=y
+CONFIG_DRM_OMAP=y
+CONFIG_DRM_OMAP_NUM_CRTCS=3
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_DRA7XX_DPI=y
CONFIG_OMAP2_DSS_RFBI=y
CONFIG_OMAP2_DSS_SDI=y
CONFIG_OMAP2_DSS_DSI=y
-CONFIG_FB_OMAP_LCD_VGA=y
-CONFIG_FB_OMAP2=m
-CONFIG_PANEL_GENERIC_DPI=m
-CONFIG_PANEL_SHARP_LS037V7DW01=m
-CONFIG_PANEL_NEC_NL8048HL11_01B=m
-CONFIG_PANEL_TAAL=m
-CONFIG_PANEL_TPO_TD043MTEA1=m
-CONFIG_PANEL_ACX565AKM=m
+CONFIG_PANEL_GENERIC_DPI=y
+CONFIG_PANEL_TFP410=y
+CONFIG_PANEL_LGPHILIPS_LB035Q02=y
+CONFIG_PANEL_SHARP_LS037V7DW01=y
+CONFIG_PANEL_NEC_NL8048HL11_01B=y
+CONFIG_PANEL_PICODLP=y
+CONFIG_PANEL_TFCS9700=y
+CONFIG_PANEL_TAAL=y
+CONFIG_PANEL_LG4591=y
+CONFIG_PANEL_TPO_TD043MTEA1=y
+CONFIG_PANEL_ACX565AKM=y
+CONFIG_PANEL_N8X0=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FONTS=y
CONFIG_SND_SOC=m
CONFIG_SND_OMAP_SOC=m
CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
+CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_SDIO_UART=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
+CONFIG_RTC_DRV_PALMAS=y
CONFIG_RTC_DRV_TWL92330=y
CONFIG_RTC_DRV_TWL4030=y
-CONFIG_RTC_DRV_PALMAS=y
+CONFIG_RTC_DRV_OMAP=y
CONFIG_DMADEVICES=y
CONFIG_TI_EDMA=y
CONFIG_DMA_OMAP=y
CONFIG_STAGING=y
-CONFIG_DRM_OMAP=y
-CONFIG_DRM_OMAP_NUM_CRTCS=3
CONFIG_TI_SOC_THERMAL=y
CONFIG_TI_THERMAL=y
CONFIG_OMAP4_THERMAL=y
CONFIG_OMAP5_THERMAL=y
+CONFIG_DRA752_THERMAL=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DAVINCI_CPDMA=y
index 02fe2fbe2477078b4fa8da59c6f2a416fdb71913..ed94b1a366ae62d9535c66847ebe85abf4f4f0c0 100644 (file)
* IOP3XX processor registers
*/
#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
-#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
+#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
#define IOP3XX_PERIPHERAL_SIZE 0x00002000
#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
IOP3XX_PERIPHERAL_SIZE - 1)
index f9e8657dd24122cf67362e4def103d41cfd25329..23fa6a21e228d15da6698d41a3bff2aae63ff5b9 100644 (file)
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
struct pmu *leader_pmu = event->group_leader->pmu;
- if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
+ if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
+ return 1;
+
+ if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
return 1;
return armpmu->get_event_idx(hw_events, event) >= 0;
index bd6f56b9ec2101534b7477c11c9f6ef0a3a6e68b..59d2adb764a995f9174a6494bd2bcc1974c10e73 100644 (file)
static u32 __read_mostly (*read_sched_clock)(void) = jiffy_sched_clock_read;
-static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
+static inline u64 notrace cyc_to_ns(u64 cyc, u32 mult, u32 shift)
{
return (cyc * mult) >> shift;
}
-static unsigned long long cyc_to_sched_clock(u32 cyc, u32 mask)
+static unsigned long long notrace cyc_to_sched_clock(u32 cyc, u32 mask)
{
u64 epoch_ns;
u32 epoch_cyc;
index 4b678478cf95d9f60d6a4484b4a490ee46228d45..6b4608d58da284bba765701ddc06a0ddbd57b443 100644 (file)
of_id = of_match_node(rstc_ids, np);
if (!of_id)
- panic("AT91: rtsc no restart function availlable\n");
+ panic("AT91: rtsc no restart function available\n");
arm_pm_restart = of_id->data;
index 0edce4bf3ae7a8328445783f8d35dd0176867325..5e3ca7a10438d3cae3c25db73acfb2be61a3efee 100644 (file)
clk_prepare_enable(clk[gpio3_gate]);
clk_prepare_enable(clk[iim_gate]);
clk_prepare_enable(clk[emi_gate]);
+ clk_prepare_enable(clk[max_gate]);
+ clk_prepare_enable(clk[iomuxc_gate]);
/*
* SCC is needed to boot via mmc after a watchdog reset. The clock code
index 6cf9c1cc2bef3cf3fa7749d134a0edb64bdf8644..612bd1cc257c147255eb9baefb86ff6d0a6a2497 100644 (file)
#define cpu_is_omap34xx() 0
#define cpu_is_omap44xx() 0
#define soc_is_omap54xx() 0
+#define soc_is_dra7xx() 0
#define soc_is_am33xx() 0
#define cpu_class_is_omap1() 1
#define cpu_class_is_omap2() 0
index 3ceda910e4b98ac1c369fed8c79c4e0d043b428f..ed1b71e10663cf37731410e6e89562e20eac8326 100644 (file)
select I2C
select I2C_OMAP
select MENELAUS if ARCH_OMAP2
- select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
+ select NEON if CPU_V7
select PM_RUNTIME
select REGULATOR
select SERIAL_OMAP
config SOC_HAS_REALTIME_COUNTER
bool "Real time free running counter"
- depends on SOC_OMAP5
+ depends on SOC_OMAP5 || SOC_DRA7XX
default y
config ARCH_OMAP2
config SOC_OMAP5
bool "TI OMAP5"
select ARCH_HAS_BANDGAP
+ select ARCH_HAS_OPP
select ARM_ARCH_TIMER
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ARCH_HAS_XHCI if USB_SUPPORT
select ARCH_NEEDS_CPU_IDLE_COUPLED
+ select PM_OPP if PM
+
+config SOC_DRA7XX
+ bool "TI DRA7XX"
+ select ARCH_HAS_BANDGAP
+ select ARM_ARCH_TIMER
+ select CPU_V7
+ select ARM_GIC
+ select HAVE_SMP
+ select COMMON_CLK
comment "OMAP Core Type"
depends on ARCH_OMAP2
index b123e80ad730b9fd7f4abd8f3a0d7740ac42668b..af35320f7bfe332be5e13cd7fa696378a896c28a 100644 (file)
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common)
ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
obj-y += mcbsp.o
sleep_omap4plus.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common)
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_SOC_OMAP5) += $(omap4plus-common-pm)
obj-$(CONFIG_SOC_AM33XX) += pm33xx.o sleep33xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
+obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
vc44xx_data.o vp44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common)
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
+obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
+obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clock-common) cclock54xx_data.o
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
+obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX) += cclock7xx_data.o
# OMAP2 clock rate set data (old "OPP" data)
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
index 02c55e7b523380e2c3a0a8dbe3346a5ae3df3a6f..d60b2059954e3b56ba772cba5638655e9c6312d9 100644 (file)
.restart = omap44xx_restart,
MACHINE_END
#endif
+
+#ifdef CONFIG_SOC_DRA7XX
+static const char *dra7xx_boards_compat[] __initdata = {
+ "ti,dra7",
+ NULL,
+};
+
+DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
+ .reserve = omap_reserve,
+ .smp = smp_ops(omap4_smp_ops),
+ .map_io = omap5_map_io,
+ .init_early = dra7xx_init_early,
+ .init_irq = omap_gic_of_init,
+ .handle_irq = gic_handle_irq,
+ .init_machine = omap_generic_init,
+ .init_late = dra7xx_init_late,
+ .timer = &omap5_timer,
+ .dt_compat = dra7xx_boards_compat,
+ .restart = omap44xx_restart,
+MACHINE_END
+#endif
index da15beadda41771a5759c14fb1c17c7041dbce6e..30dadcdcd1fd40933c671bfe7a7e5fe63e1a620c 100644 (file)
CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck, CK_AM33XX),
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_AM33XX),
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_AM33XX),
+ CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
};
"l4hs_gclk",
"l4fw_gclk",
"l4ls_gclk",
+ "clkout2_ck", /* Required for external peripherals like, Audio codecs */
};
static struct reparent_init_clks reparent_clks[] = {
diff --git a/arch/arm/mach-omap2/cclock7xx_data.c b/arch/arm/mach-omap2/cclock7xx_data.c
--- /dev/null
@@ -0,0 +1,2149 @@
+/*
+ * DRA7xx Clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Mike Turquette (mturquette@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock7xx.h"
+#include "cm1_7xx.h"
+#include "cm2_7xx.h"
+#include "cm-regbits-7xx.h"
+#include "prm7xx.h"
+#include "prm-regbits-7xx.h"
+#include "control.h"
+
+#define DRA7_DPLL_ABE_DEFFREQ 361267200
+#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
+
+/* Root clocks */
+
+DEFINE_CLK_FIXED_RATE(atl_clkin0_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(atl_clkin1_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(atl_clkin2_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(atlclkin3_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(hdmi_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mlb_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mlbp_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(pciesref_acs_clk_ck, CLK_IS_ROOT, 100000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin0_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin1_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin2_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin3_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(rmii_clk_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(sdvenc_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_20000000_ck, CLK_IS_ROOT, 20000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
+
+static const struct clksel_rate div_1_8_rates[] = {
+ { .div = 1, .val = 8, .flags = RATE_IN_7XX },
+ { .div = 0 },
+};
+
+
+static const char *sys_clkin1_parents[] = {
+ "virt_12000000_ck", "virt_20000000_ck",
+ "virt_16800000_ck", "virt_19200000_ck", "virt_26000000_ck",
+ "virt_27000000_ck", "virt_38400000_ck",
+};
+
+DEFINE_CLK_MUX(sys_clkin1, sys_clkin1_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_SYS,
+ DRA7XX_SYS_CLKSEL_SHIFT, DRA7XX_SYS_CLKSEL_WIDTH,
+ CLK_MUX_INDEX_ONE, NULL);
+
+
+DEFINE_CLK_FIXED_RATE(sys_clkin2, CLK_IS_ROOT, 22579200, 0x0);
+
+DEFINE_CLK_FIXED_RATE(usb_otg_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video1_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video1_m2_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video2_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video2_m2_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+/* Module clocks and DPLL outputs */
+
+static const char *abe_dpll_sys_clk_mux_parents[] = {
+ "sys_clkin1", "sys_clkin2",
+};
+
+DEFINE_CLK_MUX(abe_dpll_sys_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_PLL_SYS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *abe_dpll_bypass_clk_mux_parents[] = {
+ "abe_dpll_sys_clk_mux", "sys_32k_ck",
+};
+
+DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL,
+ 0x0, DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(abe_dpll_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_PLL_REF, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+/* DPLL_ABE */
+static struct dpll_data dpll_abe_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_ABE,
+ .clk_bypass = &abe_dpll_bypass_clk_mux,
+ .clk_ref = &abe_dpll_clk_mux,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_ABE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_ABE,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_ABE,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .m4xen_mask = DRA7XX_DPLL_REGM4XEN_MASK,
+ .lpmode_mask = DRA7XX_DPLL_LPMODE_EN_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_abe_ck_parents[] = {
+ "abe_dpll_clk_mux", "abe_dpll_bypass_clk_mux"
+};
+
+static struct clk dpll_abe_ck;
+
+static const struct clk_ops dpll_abe_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap4_dpll_regm4xen_recalc,
+ .round_rate = &omap4_dpll_regm4xen_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_abe_ck_hw = {
+ .hw = {
+ .clk = &dpll_abe_ck,
+ },
+ .dpll_data = &dpll_abe_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
+
+static const char *dpll_abe_x2_ck_parents[] = {
+ "dpll_abe_ck",
+};
+
+static struct clk dpll_abe_x2_ck;
+
+static const struct clk_ops dpll_abe_x2_ck_ops = {
+ .recalc_rate = &omap3_clkoutx2_recalc,
+};
+
+static struct clk_hw_omap dpll_abe_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_abe_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+static const struct clk_ops omap_hsdivider_ops = {
+ .set_rate = &omap2_clksel_set_rate,
+ .recalc_rate = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M2_DPLL_ABE, DRA7XX_DIVHS_MASK);
+
+static const struct clk_div_table abe_24m_fclk_rates[] = {
+ { .div = 8, .val = 0 },
+ { .div = 16, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_ABE_24M, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, abe_24m_fclk_rates,
+ NULL);
+
+DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_ABE, DRA7XX_CLKSEL_OPP_SHIFT,
+ DRA7XX_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
+ DRA7XX_CM_CLKSEL_AESS_FCLK_DIV, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(abe_giclk_div, "aess_fclk", &aess_fclk, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_GICLK_DIV, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const struct clk_div_table abe_lp_clk_div_rates[] = {
+ { .div = 16, .val = 0 },
+ { .div = 32, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(abe_lp_clk_div, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_ABE_LP_CLK,
+ DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0,
+ abe_lp_clk_div_rates, NULL);
+
+DEFINE_CLK_DIVIDER(abe_sys_clk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_SYS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *adc_gfclk_mux_parents[] = {
+ "sys_clkin1", "sys_clkin2", "sys_32k_ck",
+};
+
+DEFINE_CLK_MUX(adc_gfclk_mux, adc_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_ADC_GFCLK, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+/* DPLL_PCIE_REF */
+static struct dpll_data dpll_pcie_ref_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PCIE_REF,
+ .clk_bypass = &sys_clkin1,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_PCIE_REF,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PCIE_REF,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+};
+
+static const char *dpll_pcie_ref_ck_parents[] = {
+ "sys_clkin1",
+};
+
+static struct clk dpll_pcie_ref_ck;
+
+static const struct clk_ops dpll_pcie_ref_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_pcie_ref_ck_hw = {
+ .hw = {
+ .clk = &dpll_pcie_ref_ck,
+ },
+ .dpll_data = &dpll_pcie_ref_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_pcie_ref_ck, dpll_pcie_ref_ck_parents,
+ dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_pcie_ref_m2ldo_ck, "dpll_pcie_ref_ck",
+ &dpll_pcie_ref_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_PCIE_REF,
+ DRA7XX_DIVHS_MASK);
+
+/* APLL_PCIE */
+static struct dpll_data apll_pcie_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PCIE_REF,
+ .clk_bypass = &dpll_pcie_ref_ck,
+ .clk_ref = &dpll_pcie_ref_ck,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_PCIE_REF,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PCIE_REF,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = -1,
+ .max_divider = 0,
+ .min_divider = 1,
+};
+
+static const char *apll_pcie_ck_parents[] = {
+ "BUGGED",
+};
+
+static struct clk apll_pcie_ck;
+
+static struct clk_hw_omap apll_pcie_ck_hw = {
+ .hw = {
+ .clk = &apll_pcie_ck,
+ },
+ .dpll_data = &apll_pcie_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(apll_pcie_ck, apll_pcie_ck_parents, dpll_pcie_ref_ck_ops);
+
+static const char *apll_pcie_clkvcoldo_parents[] = {
+ "apll_pcie_ck",
+};
+
+static struct clk apll_pcie_clkvcoldo;
+
+static const struct clk_ops apll_pcie_clkvcoldo_ops = {
+};
+
+static struct clk_hw_omap apll_pcie_clkvcoldo_hw = {
+ .hw = {
+ .clk = &apll_pcie_clkvcoldo,
+ },
+ .clksel_reg = DRA7XX_CM_CLKVCOLDO_APLL_PCIE,
+};
+
+DEFINE_STRUCT_CLK(apll_pcie_clkvcoldo, apll_pcie_clkvcoldo_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk apll_pcie_clkvcoldo_div;
+
+static struct clk_hw_omap apll_pcie_clkvcoldo_div_hw = {
+ .hw = {
+ .clk = &apll_pcie_clkvcoldo_div,
+ },
+ .clksel_reg = DRA7XX_CM_CLKVCOLDO_APLL_PCIE,
+};
+
+DEFINE_STRUCT_CLK(apll_pcie_clkvcoldo_div, apll_pcie_clkvcoldo_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(apll_pcie_m2_ck, "apll_pcie_ck", &apll_pcie_ck, 0x0,
+ DRA7XX_CM_DIV_M2_APLL_PCIE, DRA7XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_DIVIDER(sys_clk1_dclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(sys_clk2_dclk_div, "sys_clkin2", &sys_clkin2, 0x0,
+ DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_ABE, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(per_abe_x1_dclk_div, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M3_DPLL_ABE, DRA7XX_DIVHS_MASK);
+
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_CORE,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_CORE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_CORE,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_CORE,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_core_ck_parents[] = {
+ "sys_clkin1", "dpll_abe_m3x2_ck"
+};
+
+static struct clk dpll_core_ck;
+
+static const struct clk_ops dpll_core_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_core_ck_hw = {
+ .hw = {
+ .clk = &dpll_core_ck,
+ },
+ .dpll_data = &dpll_core_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
+
+static const char *dpll_core_x2_ck_parents[] = {
+ "dpll_core_ck",
+};
+
+static struct clk dpll_core_x2_ck;
+
+static struct clk_hw_omap dpll_core_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_core_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h12x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+static const char *mpu_dpll_hs_clk_div_parents[] = {
+ "dpll_core_h12x2_ck",
+};
+
+static struct clk mpu_dpll_hs_clk_div;
+
+static struct clk_hw_omap mpu_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &mpu_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(mpu_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_MPU,
+ .clk_bypass = &mpu_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_MPU,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_MPU,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_MPU,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_mpu_ck_parents[] = {
+ "sys_clkin1", "mpu_dpll_hs_clk_div"
+};
+
+static struct clk dpll_mpu_ck;
+
+static const struct clk_ops dpll_mpu_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap5_mpu_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_mpu_ck_hw = {
+ .hw = {
+ .clk = &dpll_mpu_ck,
+ },
+ .dpll_data = &dpll_mpu_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_mpu_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_MPU, DRA7XX_DIVHS_MASK);
+
+static const char *mpu_dclk_div_parents[] = {
+ "dpll_mpu_m2_ck",
+};
+
+static struct clk mpu_dclk_div;
+
+static struct clk_hw_omap mpu_dclk_div_hw = {
+ .hw = {
+ .clk = &mpu_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(mpu_dclk_div, mpu_dclk_div_parents, apll_pcie_clkvcoldo_ops);
+
+static struct clk dsp_dpll_hs_clk_div;
+
+static struct clk_hw_omap dsp_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &dsp_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(dsp_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_DSP */
+static struct dpll_data dpll_dsp_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_DSP,
+ .clk_bypass = &dsp_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_DSP,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_DSP,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_DSP,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_dsp_ck_parents[] = {
+ "sys_clkin1", "dsp_dpll_hs_clk_div"
+};
+
+static struct clk dpll_dsp_ck;
+
+static struct clk_hw_omap dpll_dsp_ck_hw = {
+ .hw = {
+ .clk = &dpll_dsp_ck,
+ },
+ .dpll_data = &dpll_dsp_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_dsp_ck, dpll_dsp_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_dsp_m2_ck, "dpll_dsp_ck", &dpll_dsp_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_DSP, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(dsp_gclk_div, "dpll_dsp_m2_ck", &dpll_dsp_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk iva_dpll_hs_clk_div;
+
+static struct clk_hw_omap iva_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &iva_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(iva_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_IVA */
+static struct dpll_data dpll_iva_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_IVA,
+ .clk_bypass = &iva_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_IVA,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_IVA,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_IVA,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_iva_ck_parents[] = {
+ "sys_clkin1", "iva_dpll_hs_clk_div"
+};
+
+static struct clk dpll_iva_ck;
+
+static struct clk_hw_omap dpll_iva_ck_hw = {
+ .hw = {
+ .clk = &dpll_iva_ck,
+ },
+ .dpll_data = &dpll_iva_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_iva_m2_ck, "dpll_iva_ck", &dpll_iva_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_IVA, DRA7XX_DIVHS_MASK);
+
+static const char *iva_dclk_parents[] = {
+ "dpll_iva_m2_ck",
+};
+
+static struct clk iva_dclk;
+
+static struct clk_hw_omap iva_dclk_hw = {
+ .hw = {
+ .clk = &iva_dclk,
+ },
+};
+
+DEFINE_STRUCT_CLK(iva_dclk, iva_dclk_parents, apll_pcie_clkvcoldo_ops);
+
+/* DPLL_GPU */
+static struct dpll_data dpll_gpu_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_GPU,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_GPU,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_GPU,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_GPU,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static struct clk dpll_gpu_ck;
+
+static struct clk_hw_omap dpll_gpu_ck_hw = {
+ .hw = {
+ .clk = &dpll_gpu_ck,
+ },
+ .dpll_data = &dpll_gpu_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_gpu_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gpu_m2_ck, "dpll_gpu_ck", &dpll_gpu_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_GPU, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(gpu_dclk, "dpll_gpu_m2_ck", &dpll_gpu_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_CORE, DRA7XX_DIVHS_MASK);
+
+static const char *core_dpll_out_dclk_div_parents[] = {
+ "dpll_core_m2_ck",
+};
+
+static struct clk core_dpll_out_dclk_div;
+
+static struct clk_hw_omap core_dpll_out_dclk_div_hw = {
+ .hw = {
+ .clk = &core_dpll_out_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(core_dpll_out_dclk_div, core_dpll_out_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_DDR */
+static struct dpll_data dpll_ddr_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_DDR,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_DDR,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_DDR,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_DDR,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static struct clk dpll_ddr_ck;
+
+static struct clk_hw_omap dpll_ddr_ck_hw = {
+ .hw = {
+ .clk = &dpll_ddr_ck,
+ },
+ .dpll_data = &dpll_ddr_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_DDR, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(emif_phy_dclk_div, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+/* DPLL_GMAC */
+static struct dpll_data dpll_gmac_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_GMAC,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_GMAC,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_GMAC,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_GMAC,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static struct clk dpll_gmac_ck;
+
+static struct clk_hw_omap dpll_gmac_ck_hw = {
+ .hw = {
+ .clk = &dpll_gmac_ck,
+ },
+ .dpll_data = &dpll_gmac_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_gmac_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_m2_ck, "dpll_gmac_ck", &dpll_gmac_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_GMAC, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(gmac_250m_dclk_div, "dpll_gmac_m2_ck", &dpll_gmac_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static const char *video2_dclk_div_parents[] = {
+ "video2_m2_clkin",
+};
+
+static struct clk video2_dclk_div;
+
+static struct clk_hw_omap video2_dclk_div_hw = {
+ .hw = {
+ .clk = &video2_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video2_dclk_div, video2_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const char *video1_dclk_div_parents[] = {
+ "video1_m2_clkin",
+};
+
+static struct clk video1_dclk_div;
+
+static struct clk_hw_omap video1_dclk_div_hw = {
+ .hw = {
+ .clk = &video1_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video1_dclk_div, video1_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const char *hdmi_dclk_div_parents[] = {
+ "hdmi_clkin",
+};
+
+static struct clk hdmi_dclk_div;
+
+static struct clk_hw_omap hdmi_dclk_div_hw = {
+ .hw = {
+ .clk = &hdmi_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(hdmi_dclk_div, hdmi_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_FIXED_FACTOR(per_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
+ &dpll_abe_m3x2_ck, 0x0, 1, 2);
+
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PER,
+ .clk_bypass = &per_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_PER,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PER,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PER,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_per_ck_parents[] = {
+ "sys_clkin1", "per_dpll_hs_clk_div"
+};
+
+static struct clk dpll_per_ck;
+
+static struct clk_hw_omap dpll_per_ck_hw = {
+ .hw = {
+ .clk = &dpll_per_ck,
+ },
+ .dpll_data = &dpll_per_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_PER, DRA7XX_DIVHS_MASK);
+
+static const char *func_96m_aon_dclk_div_parents[] = {
+ "dpll_per_m2_ck",
+};
+
+static struct clk func_96m_aon_dclk_div;
+
+static struct clk_hw_omap func_96m_aon_dclk_div_hw = {
+ .hw = {
+ .clk = &func_96m_aon_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(func_96m_aon_dclk_div, func_96m_aon_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_FIXED_FACTOR(usb_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
+ &dpll_abe_m3x2_ck, 0x0, 1, 3);
+
+/* DPLL_USB */
+static struct dpll_data dpll_usb_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_USB,
+ .clk_bypass = &usb_dpll_hs_clk_div,
+ .flags = DPLL_J_TYPE,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_USB,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_USB,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_USB,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .sddiv_mask = DRA7XX_DPLL_SD_DIV_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+};
+
+static const char *dpll_usb_ck_parents[] = {
+ "sys_clkin1", "usb_dpll_hs_clk_div"
+};
+
+static struct clk dpll_usb_ck;
+
+static const struct clk_ops dpll_usb_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+ .init = &omap2_init_clk_clkdm,
+};
+
+static struct clk_hw_omap dpll_usb_ck_hw = {
+ .hw = {
+ .clk = &dpll_usb_ck,
+ },
+ .dpll_data = &dpll_usb_dd,
+ .clkdm_name = "coreaon_clkdm",
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_USB, DRA7XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_DIVIDER(l3init_480m_dclk_div, "dpll_usb_m2_ck", &dpll_usb_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(usb_otg_dclk_div, "usb_otg_clkin_ck", &usb_otg_clkin_ck, 0x0,
+ DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(sata_dclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_pcie_ref_m2_ck, "dpll_pcie_ref_ck",
+ &dpll_pcie_ref_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_PCIE_REF,
+ DRA7XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_DIVIDER(pcie2_dclk_div, "dpll_pcie_ref_m2_ck", &dpll_pcie_ref_m2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(pcie_dclk_div, "apll_pcie_m2_ck", &apll_pcie_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(emu_dclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(secure_32k_dclk_div, "secure_32k_clk_src_ck",
+ &secure_32k_clk_src_ck, 0x0,
+ DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk eve_dpll_hs_clk_div;
+
+static struct clk_hw_omap eve_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &eve_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(eve_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_EVE */
+static struct dpll_data dpll_eve_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_EVE,
+ .clk_bypass = &eve_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_EVE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_EVE,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_EVE,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_eve_ck_parents[] = {
+ "sys_clkin1", "eve_dpll_hs_clk_div"
+};
+
+static struct clk dpll_eve_ck;
+
+static struct clk_hw_omap dpll_eve_ck_hw = {
+ .hw = {
+ .clk = &dpll_eve_ck,
+ },
+ .dpll_data = &dpll_eve_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_eve_ck, dpll_eve_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_eve_m2_ck, "dpll_eve_ck", &dpll_eve_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_EVE, DRA7XX_DIVHS_MASK);
+
+static const char *eve_dclk_div_parents[] = {
+ "dpll_eve_m2_ck",
+};
+
+static struct clk eve_dclk_div;
+
+static struct clk_hw_omap eve_dclk_div_hw = {
+ .hw = {
+ .clk = &eve_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(eve_dclk_div, eve_dclk_div_parents, apll_pcie_clkvcoldo_ops);
+
+static const char *clkoutmux0_clk_mux_parents[] = {
+ "sys_clk1_dclk_div", "sys_clk2_dclk_div", "per_abe_x1_dclk_div",
+ "mpu_dclk_div", "dsp_gclk_div", "iva_dclk",
+ "gpu_dclk", "core_dpll_out_dclk_div", "emif_phy_dclk_div",
+ "gmac_250m_dclk_div", "video2_dclk_div", "video1_dclk_div",
+ "hdmi_dclk_div", "func_96m_aon_dclk_div", "l3init_480m_dclk_div",
+ "usb_otg_dclk_div", "sata_dclk_div", "pcie2_dclk_div",
+ "pcie_dclk_div", "emu_dclk_div", "secure_32k_dclk_div",
+ "eve_dclk_div",
+};
+
+DEFINE_CLK_MUX(clkoutmux0_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_CLKOUTMUX0, DRA7XX_CLKSEL_0_4_SHIFT,
+ DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(clkoutmux1_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_CLKOUTMUX1, DRA7XX_CLKSEL_0_4_SHIFT,
+ DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(clkoutmux2_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_CLKOUTMUX2, DRA7XX_CLKSEL_0_4_SHIFT,
+ DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_FIXED_FACTOR(custefuse_sys_gfclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ 1, 2);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h13x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h14x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H14_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h22x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H22_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h23x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H23_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h24x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H24_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+static const char *dpll_ddr_x2_ck_parents[] = {
+ "dpll_ddr_ck",
+};
+
+static struct clk dpll_ddr_x2_ck;
+
+static struct clk_hw_omap dpll_ddr_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_ddr_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_ddr_x2_ck, dpll_ddr_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_ddr_h11x2_ck, "dpll_ddr_x2_ck",
+ &dpll_ddr_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_DDR,
+ DRA7XX_DIVHS_0_5_MASK);
+
+static const char *dpll_dsp_x2_ck_parents[] = {
+ "dpll_dsp_ck",
+};
+
+static struct clk dpll_dsp_x2_ck;
+
+static struct clk_hw_omap dpll_dsp_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_dsp_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_dsp_x2_ck, dpll_dsp_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_dsp_m3x2_ck, "dpll_dsp_x2_ck", &dpll_dsp_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M3_DPLL_DSP, DRA7XX_DIVHS_MASK);
+
+static const char *dpll_gmac_x2_ck_parents[] = {
+ "dpll_gmac_ck",
+};
+
+static struct clk dpll_gmac_x2_ck;
+
+static struct clk_hw_omap dpll_gmac_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_gmac_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_gmac_x2_ck, dpll_gmac_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h11x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_GMAC,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h12x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_GMAC,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h13x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_GMAC,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_m3x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_M3_DPLL_GMAC,
+ DRA7XX_DIVHS_MASK);
+
+static const char *dpll_per_x2_ck_parents[] = {
+ "dpll_per_ck",
+};
+
+static struct clk dpll_per_x2_ck;
+
+static struct clk_hw_omap dpll_per_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_per_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h11x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h12x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h13x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h14x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H14_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M2_DPLL_PER, DRA7XX_DIVHS_MASK);
+
+static const char *dpll_usb_clkdcoldo_parents[] = {
+ "dpll_usb_ck",
+};
+
+static struct clk dpll_usb_clkdcoldo;
+
+static struct clk_hw_omap dpll_usb_clkdcoldo_hw = {
+ .hw = {
+ .clk = &dpll_usb_clkdcoldo,
+ },
+ .clksel_reg = DRA7XX_CM_CLKDCOLDO_DPLL_USB,
+};
+
+DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo, dpll_usb_clkdcoldo_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const char *eve_clk_parents[] = {
+ "dpll_eve_m2_ck", "dpll_dsp_m3x2_ck",
+};
+
+DEFINE_CLK_MUX(eve_clk, eve_clk_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_EVE_CLK,
+ DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_FIXED_FACTOR(func_128m_clk, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck,
+ 0x0, 1, 2);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 16);
+
+DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
+ 4);
+
+DEFINE_CLK_FIXED_FACTOR(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 4);
+
+DEFINE_CLK_FIXED_FACTOR(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 2);
+
+DEFINE_CLK_FIXED_FACTOR(gmii_m_clk_div, "dpll_gmac_h11x2_ck",
+ &dpll_gmac_h11x2_ck, 0x0, 1, 2);
+
+static struct clk hdmi_clk2_div;
+
+static struct clk_hw_omap hdmi_clk2_div_hw = {
+ .hw = {
+ .clk = &hdmi_clk2_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(hdmi_clk2_div, hdmi_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk hdmi_div_clk;
+
+static struct clk_hw_omap hdmi_div_clk_hw = {
+ .hw = {
+ .clk = &hdmi_div_clk,
+ },
+};
+
+DEFINE_STRUCT_CLK(hdmi_div_clk, hdmi_dclk_div_parents, apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_MUX(hdmi_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static struct clk l3_iclk_div;
+
+static struct clk_hw_omap l3_iclk_div_hw = {
+ .hw = {
+ .clk = &l3_iclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(l3_iclk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const struct clk_div_table l3init_60m_fclk_rates[] = {
+ { .div = 1, .val = 0 },
+ { .div = 8, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(l3init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_USB_60MHZ,
+ DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0,
+ l3init_60m_fclk_rates, NULL);
+
+static const char *l4_root_clk_div_parents[] = {
+ "l3_iclk_div",
+};
+
+static struct clk l4_root_clk_div;
+
+static struct clk_hw_omap l4_root_clk_div_hw = {
+ .hw = {
+ .clk = &l4_root_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(l4_root_clk_div, l4_root_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_DIVIDER(mlb_clk, "mlb_clkin_ck", &mlb_clkin_ck, 0x0,
+ DRA7XX_CM_CLKSEL_MLB_MCASP, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(mlbp_clk, "mlbp_clkin_ck", &mlbp_clkin_ck, 0x0,
+ DRA7XX_CM_CLKSEL_MLBP_MCASP, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(per_abe_x1_gfclk2_div, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(timer_sys_clk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_TIMER_SYS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *video1_clk2_div_parents[] = {
+ "video1_clkin",
+};
+
+static struct clk video1_clk2_div;
+
+static struct clk_hw_omap video1_clk2_div_hw = {
+ .hw = {
+ .clk = &video1_clk2_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video1_clk2_div, video1_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk video1_div_clk;
+
+static struct clk_hw_omap video1_div_clk_hw = {
+ .hw = {
+ .clk = &video1_div_clk,
+ },
+};
+
+DEFINE_STRUCT_CLK(video1_div_clk, video1_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_MUX(video1_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static const char *video2_clk2_div_parents[] = {
+ "video2_clkin",
+};
+
+static struct clk video2_clk2_div;
+
+static struct clk_hw_omap video2_clk2_div_hw = {
+ .hw = {
+ .clk = &video2_clk2_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video2_clk2_div, video2_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk video2_div_clk;
+
+static struct clk_hw_omap video2_div_clk_hw = {
+ .hw = {
+ .clk = &video2_div_clk,
+ },
+};
+
+DEFINE_STRUCT_CLK(video2_div_clk, video2_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_MUX(video2_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static const char *wkupaon_iclk_mux_parents[] = {
+ "sys_clkin1", "abe_lp_clk_div",
+};
+
+DEFINE_CLK_MUX(wkupaon_iclk_mux, wkupaon_iclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_WKUPAON, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+/* Leaf clocks controlled by modules */
+
+DEFINE_CLK_GATE(dss_32khz_clk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_32KHZ_CLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(dss_48mhz_clk, "func_48m_fclk", &func_48m_fclk, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_48MHZ_CLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_DSSCLK_SHIFT, 0x0,
+ NULL);
+
+DEFINE_CLK_GATE(dss_hdmi_clk, "hdmi_dpll_clk_mux", &hdmi_dpll_clk_mux, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_HDMI_CLK_SHIFT, 0x0,
+ NULL);
+
+DEFINE_CLK_GATE(dss_video1_clk, "video1_dpll_clk_mux", &video1_dpll_clk_mux,
+ 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL,
+ DRA7XX_OPTFCLKEN_VIDEO1_CLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(dss_video2_clk, "video2_dpll_clk_mux", &video2_dpll_clk_mux,
+ 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL,
+ DRA7XX_OPTFCLKEN_VIDEO2_CLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO2_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO3_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO4_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO5_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO6_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio7_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO7_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio8_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO8_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc1_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc2_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc3_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc4_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(sata_ref_clk, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_L3INIT_SATA_CLKCTRL, DRA7XX_OPTFCLKEN_REF_CLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_otg_ss1_refclk960m, "dpll_usb_clkdcoldo",
+ &dpll_usb_clkdcoldo, 0x0, DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL,
+ DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_otg_ss2_refclk960m, "dpll_usb_clkdcoldo",
+ &dpll_usb_clkdcoldo, 0x0, DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL,
+ DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_phy1_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL,
+ DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_phy2_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL,
+ DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_phy3_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL,
+ DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+
+/* Remaining optional clocks */
+static const char *atl_dpll_clk_mux_parents[] = {
+ "sys_32k_ck", "video1_clkin", "video2_clkin",
+ "hdmi_clkin",
+};
+
+DEFINE_CLK_MUX(atl_dpll_clk_mux, atl_dpll_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_ATL_ATL_CLKCTRL, DRA7XX_CLKSEL_SOURCE1_SHIFT,
+ DRA7XX_CLKSEL_SOURCE1_WIDTH, 0x0, NULL);
+
+static const char *atl_gfclk_mux_parents[] = {
+ "l3_iclk_div", "dpll_abe_m2_ck", "atl_dpll_clk_mux",
+};
+
+DEFINE_CLK_MUX(atl_gfclk_mux, atl_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_ATL_ATL_CLKCTRL, DRA7XX_CLKSEL_SOURCE2_SHIFT,
+ DRA7XX_CLKSEL_SOURCE2_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(dcan1_sys_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+static const struct clk_div_table gmac_gmii_ref_clk_div_rates[] = {
+ { .div = 2, .val = 0 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(gmac_gmii_ref_clk_div, "dpll_gmac_m2_ck",
+ &dpll_gmac_m2_ck, 0x0, DRA7XX_CM_GMAC_GMAC_CLKCTRL,
+ DRA7XX_CLKSEL_REF_SHIFT, DRA7XX_CLKSEL_REF_WIDTH, 0x0,
+ gmac_gmii_ref_clk_div_rates, NULL);
+
+static const char *gmac_rft_clk_mux_parents[] = {
+ "video1_clkin", "video2_clkin", "dpll_abe_m2_ck",
+ "hdmi_clkin", "l3_iclk_div",
+};
+
+DEFINE_CLK_MUX(gmac_rft_clk_mux, gmac_rft_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_GMAC_GMAC_CLKCTRL, DRA7XX_CLKSEL_RFT_SHIFT,
+ DRA7XX_CLKSEL_RFT_WIDTH, 0x0, NULL);
+
+static const char *gpu_core_gclk_mux_parents[] = {
+ "dpll_core_h14x2_ck", "dpll_per_h14x2_ck", "dpll_gpu_m2_ck",
+};
+
+DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_CORE_CLK_SHIFT,
+ DRA7XX_CLKSEL_CORE_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_HYD_CLK_SHIFT,
+ DRA7XX_CLKSEL_HYD_CLK_WIDTH, 0x0, NULL);
+
+static const char *ipu1_gfclk_mux_parents[] = {
+ "dpll_abe_m2x2_ck", "dpll_core_h22x2_ck",
+};
+
+DEFINE_CLK_MUX(ipu1_gfclk_mux, ipu1_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU1_IPU1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+static const struct clk_div_table l3instr_ts_gclk_div_rates[] = {
+ { .div = 8, .val = 0 },
+ { .div = 16, .val = 1 },
+ { .div = 32, .val = 2 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(l3instr_ts_gclk_div, "wkupaon_iclk_mux",
+ &wkupaon_iclk_mux, 0x0,
+ DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ DRA7XX_CLKSEL_24_25_SHIFT, DRA7XX_CLKSEL_24_25_WIDTH,
+ 0x0, l3instr_ts_gclk_div_rates, NULL);
+
+static const char *mcasp1_ahclkr_mux_parents[] = {
+ "abe_24m_fclk", "abe_sys_clk_div", "func_24m_clk",
+ "atlclkin3", "atl_clkin2", "atl_clkin1",
+ "atl_clkin0", "sys_clkin2", "ref_clkin0",
+ "ref_clkin1", "ref_clkin2", "ref_clkin3",
+ "mlb_clk", "mlbp_clk",
+};
+
+DEFINE_CLK_MUX(mcasp1_ahclkr_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT,
+ DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp1_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+static const char *mcasp1_aux_gfclk_mux_parents[] = {
+ "per_abe_x1_gfclk2_div", "video1_clk2_div", "video2_clk2_div",
+ "hdmi_clk2_div",
+};
+
+DEFINE_CLK_MUX(mcasp1_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp2_ahclkr_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT,
+ DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp2_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT,
+ DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp2_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp3_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP3_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp3_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP3_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp4_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP4_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp4_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP4_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp5_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP5_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp5_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP5_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp6_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP6_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp6_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP6_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp7_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP7_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp7_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP7_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp8_ahclk_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP8_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp8_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP8_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+static const char *mmc1_fclk_mux_parents[] = {
+ "func_128m_clk", "dpll_per_m2x2_ck",
+};
+
+DEFINE_CLK_MUX(mmc1_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_CLKSEL_SOURCE_SHIFT,
+ DRA7XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc1_fclk_div, "mmc1_fclk_mux", &mmc1_fclk_mux, 0x0,
+ DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_MUX(mmc2_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_CLKSEL_SOURCE_SHIFT,
+ DRA7XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc2_fclk_div, "mmc2_fclk_mux", &mmc2_fclk_mux, 0x0,
+ DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static const char *mmc3_gfclk_mux_parents[] = {
+ "func_48m_fclk", "dpll_per_m2x2_ck",
+};
+
+DEFINE_CLK_MUX(mmc3_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_CLKSEL_MUX_SHIFT,
+ DRA7XX_CLKSEL_MUX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc3_gfclk_div, "mmc3_gfclk_mux", &mmc3_gfclk_mux, 0x0,
+ DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_MUX(mmc4_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_CLKSEL_MUX_SHIFT,
+ DRA7XX_CLKSEL_MUX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc4_gfclk_div, "mmc4_gfclk_mux", &mmc4_gfclk_mux, 0x0,
+ DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static const char *qspi_gfclk_mux_parents[] = {
+ "func_128m_clk", "dpll_per_h13x2_ck",
+};
+
+DEFINE_CLK_MUX(qspi_gfclk_mux, qspi_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_QSPI_CLKCTRL, DRA7XX_CLKSEL_SOURCE_SHIFT,
+ DRA7XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(qspi_gfclk_div, "qspi_gfclk_mux", &qspi_gfclk_mux, 0x0,
+ DRA7XX_CM_L4PER2_QSPI_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static const char *timer10_gfclk_mux_parents[] = {
+ "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2",
+ "ref_clkin0", "ref_clkin1", "ref_clkin2",
+ "ref_clkin3", "abe_giclk_div", "video1_div_clk",
+ "video2_div_clk", "hdmi_div_clk",
+};
+
+DEFINE_CLK_MUX(timer10_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER10_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer11_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER11_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer13_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER3_TIMER13_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer14_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER3_TIMER14_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer15_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER3_TIMER15_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer16_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER3_TIMER16_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer1_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer2_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER2_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer3_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER3_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer4_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER4_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+static const char *timer5_gfclk_mux_parents[] = {
+ "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2",
+ "ref_clkin0", "ref_clkin1", "ref_clkin2",
+ "ref_clkin3", "abe_giclk_div", "video1_div_clk",
+ "video2_div_clk", "hdmi_div_clk", "clkoutmux0_clk_mux",
+};
+
+DEFINE_CLK_MUX(timer5_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_TIMER5_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer6_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_TIMER6_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer7_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_TIMER7_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer8_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_TIMER8_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer9_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER9_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart10_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_WKUPAON_UART10_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart1_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart2_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART2_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart3_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART3_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart4_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART4_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart5_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART5_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart6_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_UART6_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart7_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_UART7_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart8_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_UART8_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart9_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_UART9_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+static const char *vip1_gclk_mux_parents[] = {
+ "l3_iclk_div", "dpll_core_h23x2_ck",
+};
+
+DEFINE_CLK_MUX(vip1_gclk_mux, vip1_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CAM_VIP1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(vip2_gclk_mux, vip1_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CAM_VIP2_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(vip3_gclk_mux, vip1_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CAM_VIP3_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+/*
+ * clkdev
+ */
+
+static struct omap_clk dra7xx_clks[] = {
+ CLK(NULL, "atl_clkin0_ck", &atl_clkin0_ck, CK_7XX),
+ CLK(NULL, "atl_clkin1_ck", &atl_clkin1_ck, CK_7XX),
+ CLK(NULL, "atl_clkin2_ck", &atl_clkin2_ck, CK_7XX),
+ CLK(NULL, "atlclkin3_ck", &atlclkin3_ck, CK_7XX),
+ CLK(NULL, "hdmi_clkin_ck", &hdmi_clkin_ck, CK_7XX),
+ CLK(NULL, "mlb_clkin_ck", &mlb_clkin_ck, CK_7XX),
+ CLK(NULL, "mlbp_clkin_ck", &mlbp_clkin_ck, CK_7XX),
+ CLK(NULL, "pciesref_acs_clk_ck", &pciesref_acs_clk_ck, CK_7XX),
+ CLK(NULL, "ref_clkin0_ck", &ref_clkin0_ck, CK_7XX),
+ CLK(NULL, "ref_clkin1_ck", &ref_clkin1_ck, CK_7XX),
+ CLK(NULL, "ref_clkin2_ck", &ref_clkin2_ck, CK_7XX),
+ CLK(NULL, "ref_clkin3_ck", &ref_clkin3_ck, CK_7XX),
+ CLK(NULL, "rmii_clk_ck", &rmii_clk_ck, CK_7XX),
+ CLK(NULL, "sdvenc_clkin_ck", &sdvenc_clkin_ck, CK_7XX),
+ CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_7XX),
+ CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_7XX),
+ CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_7XX),
+ CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_7XX),
+ CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_7XX),
+ CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_7XX),
+ CLK(NULL, "virt_20000000_ck", &virt_20000000_ck, CK_7XX),
+ CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_7XX),
+ CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_7XX),
+ CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_7XX),
+ CLK(NULL, "sys_clkin1", &sys_clkin1, CK_7XX),
+ CLK(NULL, "sys_clkin2", &sys_clkin2, CK_7XX),
+ CLK(NULL, "usb_otg_clkin_ck", &usb_otg_clkin_ck, CK_7XX),
+ CLK(NULL, "video1_clkin_ck", &video1_clkin_ck, CK_7XX),
+ CLK(NULL, "video1_m2_clkin_ck", &video1_m2_clkin_ck, CK_7XX),
+ CLK(NULL, "video2_clkin_ck", &video2_clkin_ck, CK_7XX),
+ CLK(NULL, "video2_m2_clkin_ck", &video2_m2_clkin_ck, CK_7XX),
+ CLK(NULL, "abe_dpll_sys_clk_mux", &abe_dpll_sys_clk_mux, CK_7XX),
+ CLK(NULL, "abe_dpll_bypass_clk_mux", &abe_dpll_bypass_clk_mux, CK_7XX),
+ CLK(NULL, "abe_dpll_clk_mux", &abe_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_7XX),
+ CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_7XX),
+ CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_7XX),
+ CLK(NULL, "abe_clk", &abe_clk, CK_7XX),
+ CLK(NULL, "aess_fclk", &aess_fclk, CK_7XX),
+ CLK(NULL, "abe_giclk_div", &abe_giclk_div, CK_7XX),
+ CLK(NULL, "abe_lp_clk_div", &abe_lp_clk_div, CK_7XX),
+ CLK(NULL, "abe_sys_clk_div", &abe_sys_clk_div, CK_7XX),
+ CLK(NULL, "adc_gfclk_mux", &adc_gfclk_mux, CK_7XX),
+ CLK(NULL, "dpll_pcie_ref_ck", &dpll_pcie_ref_ck, CK_7XX),
+ CLK(NULL, "dpll_pcie_ref_m2ldo_ck", &dpll_pcie_ref_m2ldo_ck, CK_7XX),
+ CLK(NULL, "apll_pcie_ck", &apll_pcie_ck, CK_7XX),
+ CLK(NULL, "apll_pcie_clkvcoldo", &apll_pcie_clkvcoldo, CK_7XX),
+ CLK(NULL, "apll_pcie_clkvcoldo_div", &apll_pcie_clkvcoldo_div, CK_7XX),
+ CLK(NULL, "apll_pcie_m2_ck", &apll_pcie_m2_ck, CK_7XX),
+ CLK(NULL, "sys_clk1_dclk_div", &sys_clk1_dclk_div, CK_7XX),
+ CLK(NULL, "sys_clk2_dclk_div", &sys_clk2_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_7XX),
+ CLK(NULL, "per_abe_x1_dclk_div", &per_abe_x1_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_7XX),
+ CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h12x2_ck", &dpll_core_h12x2_ck, CK_7XX),
+ CLK(NULL, "mpu_dpll_hs_clk_div", &mpu_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_7XX),
+ CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_7XX),
+ CLK(NULL, "mpu_dclk_div", &mpu_dclk_div, CK_7XX),
+ CLK(NULL, "dsp_dpll_hs_clk_div", &dsp_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_dsp_ck", &dpll_dsp_ck, CK_7XX),
+ CLK(NULL, "dpll_dsp_m2_ck", &dpll_dsp_m2_ck, CK_7XX),
+ CLK(NULL, "dsp_gclk_div", &dsp_gclk_div, CK_7XX),
+ CLK(NULL, "iva_dpll_hs_clk_div", &iva_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_7XX),
+ CLK(NULL, "dpll_iva_m2_ck", &dpll_iva_m2_ck, CK_7XX),
+ CLK(NULL, "iva_dclk", &iva_dclk, CK_7XX),
+ CLK(NULL, "dpll_gpu_ck", &dpll_gpu_ck, CK_7XX),
+ CLK(NULL, "dpll_gpu_m2_ck", &dpll_gpu_m2_ck, CK_7XX),
+ CLK(NULL, "gpu_dclk", &gpu_dclk, CK_7XX),
+ CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_7XX),
+ CLK(NULL, "core_dpll_out_dclk_div", &core_dpll_out_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_7XX),
+ CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_7XX),
+ CLK(NULL, "emif_phy_dclk_div", &emif_phy_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_gmac_ck", &dpll_gmac_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_m2_ck", &dpll_gmac_m2_ck, CK_7XX),
+ CLK(NULL, "gmac_250m_dclk_div", &gmac_250m_dclk_div, CK_7XX),
+ CLK(NULL, "video2_dclk_div", &video2_dclk_div, CK_7XX),
+ CLK(NULL, "video1_dclk_div", &video1_dclk_div, CK_7XX),
+ CLK(NULL, "hdmi_dclk_div", &hdmi_dclk_div, CK_7XX),
+ CLK(NULL, "per_dpll_hs_clk_div", &per_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_7XX),
+ CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_7XX),
+ CLK(NULL, "func_96m_aon_dclk_div", &func_96m_aon_dclk_div, CK_7XX),
+ CLK(NULL, "usb_dpll_hs_clk_div", &usb_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_7XX),
+ CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_7XX),
+ CLK(NULL, "l3init_480m_dclk_div", &l3init_480m_dclk_div, CK_7XX),
+ CLK(NULL, "usb_otg_dclk_div", &usb_otg_dclk_div, CK_7XX),
+ CLK(NULL, "sata_dclk_div", &sata_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_pcie_ref_m2_ck", &dpll_pcie_ref_m2_ck, CK_7XX),
+ CLK(NULL, "pcie2_dclk_div", &pcie2_dclk_div, CK_7XX),
+ CLK(NULL, "pcie_dclk_div", &pcie_dclk_div, CK_7XX),
+ CLK(NULL, "emu_dclk_div", &emu_dclk_div, CK_7XX),
+ CLK(NULL, "secure_32k_dclk_div", &secure_32k_dclk_div, CK_7XX),
+ CLK(NULL, "eve_dpll_hs_clk_div", &eve_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_eve_ck", &dpll_eve_ck, CK_7XX),
+ CLK(NULL, "dpll_eve_m2_ck", &dpll_eve_m2_ck, CK_7XX),
+ CLK(NULL, "eve_dclk_div", &eve_dclk_div, CK_7XX),
+ CLK(NULL, "clkoutmux0_clk_mux", &clkoutmux0_clk_mux, CK_7XX),
+ CLK(NULL, "clkoutmux1_clk_mux", &clkoutmux1_clk_mux, CK_7XX),
+ CLK(NULL, "clkoutmux2_clk_mux", &clkoutmux2_clk_mux, CK_7XX),
+ CLK(NULL, "custefuse_sys_gfclk_div", &custefuse_sys_gfclk_div, CK_7XX),
+ CLK(NULL, "dpll_core_h13x2_ck", &dpll_core_h13x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h14x2_ck", &dpll_core_h14x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h22x2_ck", &dpll_core_h22x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h23x2_ck", &dpll_core_h23x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h24x2_ck", &dpll_core_h24x2_ck, CK_7XX),
+ CLK(NULL, "dpll_ddr_x2_ck", &dpll_ddr_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_ddr_h11x2_ck", &dpll_ddr_h11x2_ck, CK_7XX),
+ CLK(NULL, "dpll_dsp_x2_ck", &dpll_dsp_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_dsp_m3x2_ck", &dpll_dsp_m3x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_x2_ck", &dpll_gmac_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_h11x2_ck", &dpll_gmac_h11x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_h12x2_ck", &dpll_gmac_h12x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_h13x2_ck", &dpll_gmac_h13x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_m3x2_ck", &dpll_gmac_m3x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_h13x2_ck", &dpll_per_h13x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_h14x2_ck", &dpll_per_h14x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_7XX),
+ CLK(NULL, "dpll_usb_clkdcoldo", &dpll_usb_clkdcoldo, CK_7XX),
+ CLK(NULL, "eve_clk", &eve_clk, CK_7XX),
+ CLK(NULL, "func_128m_clk", &func_128m_clk, CK_7XX),
+ CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_7XX),
+ CLK(NULL, "func_24m_clk", &func_24m_clk, CK_7XX),
+ CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_7XX),
+ CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_7XX),
+ CLK(NULL, "gmii_m_clk_div", &gmii_m_clk_div, CK_7XX),
+ CLK(NULL, "hdmi_clk2_div", &hdmi_clk2_div, CK_7XX),
+ CLK(NULL, "hdmi_div_clk", &hdmi_div_clk, CK_7XX),
+ CLK(NULL, "hdmi_dpll_clk_mux", &hdmi_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "l3_iclk_div", &l3_iclk_div, CK_7XX),
+ CLK(NULL, "l3init_60m_fclk", &l3init_60m_fclk, CK_7XX),
+ CLK(NULL, "l4_root_clk_div", &l4_root_clk_div, CK_7XX),
+ CLK(NULL, "mlb_clk", &mlb_clk, CK_7XX),
+ CLK(NULL, "mlbp_clk", &mlbp_clk, CK_7XX),
+ CLK(NULL, "per_abe_x1_gfclk2_div", &per_abe_x1_gfclk2_div, CK_7XX),
+ CLK(NULL, "timer_sys_clk_div", &timer_sys_clk_div, CK_7XX),
+ CLK(NULL, "video1_clk2_div", &video1_clk2_div, CK_7XX),
+ CLK(NULL, "video1_div_clk", &video1_div_clk, CK_7XX),
+ CLK(NULL, "video1_dpll_clk_mux", &video1_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "video2_clk2_div", &video2_clk2_div, CK_7XX),
+ CLK(NULL, "video2_div_clk", &video2_div_clk, CK_7XX),
+ CLK(NULL, "video2_dpll_clk_mux", &video2_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "wkupaon_iclk_mux", &wkupaon_iclk_mux, CK_7XX),
+ CLK(NULL, "dss_32khz_clk", &dss_32khz_clk, CK_7XX),
+ CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_7XX),
+ CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_7XX),
+ CLK(NULL, "dss_hdmi_clk", &dss_hdmi_clk, CK_7XX),
+ CLK(NULL, "dss_video1_clk", &dss_video1_clk, CK_7XX),
+ CLK(NULL, "dss_video2_clk", &dss_video2_clk, CK_7XX),
+ CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_7XX),
+ CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_7XX),
+ CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_7XX),
+ CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_7XX),
+ CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_7XX),
+ CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_7XX),
+ CLK(NULL, "gpio7_dbclk", &gpio7_dbclk, CK_7XX),
+ CLK(NULL, "gpio8_dbclk", &gpio8_dbclk, CK_7XX),
+ CLK(NULL, "mmc1_clk32k", &mmc1_clk32k, CK_7XX),
+ CLK(NULL, "mmc2_clk32k", &mmc2_clk32k, CK_7XX),
+ CLK(NULL, "mmc3_clk32k", &mmc3_clk32k, CK_7XX),
+ CLK(NULL, "mmc4_clk32k", &mmc4_clk32k, CK_7XX),
+ CLK(NULL, "sata_ref_clk", &sata_ref_clk, CK_7XX),
+ CLK(NULL, "usb_otg_ss1_refclk960m", &usb_otg_ss1_refclk960m, CK_7XX),
+ CLK(NULL, "usb_otg_ss2_refclk960m", &usb_otg_ss2_refclk960m, CK_7XX),
+ CLK(NULL, "usb_phy1_always_on_clk32k", &usb_phy1_always_on_clk32k, CK_7XX),
+ CLK(NULL, "usb_phy2_always_on_clk32k", &usb_phy2_always_on_clk32k, CK_7XX),
+ CLK(NULL, "usb_phy3_always_on_clk32k", &usb_phy3_always_on_clk32k, CK_7XX),
+ CLK(NULL, "atl_dpll_clk_mux", &atl_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "atl_gfclk_mux", &atl_gfclk_mux, CK_7XX),
+ CLK(NULL, "dcan1_sys_clk_mux", &dcan1_sys_clk_mux, CK_7XX),
+ CLK(NULL, "gmac_gmii_ref_clk_div", &gmac_gmii_ref_clk_div, CK_7XX),
+ CLK(NULL, "gmac_rft_clk_mux", &gmac_rft_clk_mux, CK_7XX),
+ CLK(NULL, "gpu_core_gclk_mux", &gpu_core_gclk_mux, CK_7XX),
+ CLK(NULL, "gpu_hyd_gclk_mux", &gpu_hyd_gclk_mux, CK_7XX),
+ CLK(NULL, "ipu1_gfclk_mux", &ipu1_gfclk_mux, CK_7XX),
+ CLK(NULL, "l3instr_ts_gclk_div", &l3instr_ts_gclk_div, CK_7XX),
+ CLK(NULL, "mcasp1_ahclkr_mux", &mcasp1_ahclkr_mux, CK_7XX),
+ CLK(NULL, "mcasp1_ahclkx_mux", &mcasp1_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp1_aux_gfclk_mux", &mcasp1_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp2_ahclkr_mux", &mcasp2_ahclkr_mux, CK_7XX),
+ CLK(NULL, "mcasp2_ahclkx_mux", &mcasp2_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp2_aux_gfclk_mux", &mcasp2_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp3_ahclkx_mux", &mcasp3_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp3_aux_gfclk_mux", &mcasp3_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp4_ahclkx_mux", &mcasp4_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp4_aux_gfclk_mux", &mcasp4_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp5_ahclkx_mux", &mcasp5_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp5_aux_gfclk_mux", &mcasp5_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp6_ahclkx_mux", &mcasp6_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp6_aux_gfclk_mux", &mcasp6_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp7_ahclkx_mux", &mcasp7_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp7_aux_gfclk_mux", &mcasp7_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp8_ahclk_mux", &mcasp8_ahclk_mux, CK_7XX),
+ CLK(NULL, "mcasp8_aux_gfclk_mux", &mcasp8_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mmc1_fclk_mux", &mmc1_fclk_mux, CK_7XX),
+ CLK(NULL, "mmc1_fclk_div", &mmc1_fclk_div, CK_7XX),
+ CLK(NULL, "mmc2_fclk_mux", &mmc2_fclk_mux, CK_7XX),
+ CLK(NULL, "mmc2_fclk_div", &mmc2_fclk_div, CK_7XX),
+ CLK(NULL, "mmc3_gfclk_mux", &mmc3_gfclk_mux, CK_7XX),
+ CLK(NULL, "mmc3_gfclk_div", &mmc3_gfclk_div, CK_7XX),
+ CLK(NULL, "mmc4_gfclk_mux", &mmc4_gfclk_mux, CK_7XX),
+ CLK(NULL, "mmc4_gfclk_div", &mmc4_gfclk_div, CK_7XX),
+ CLK(NULL, "qspi_gfclk_mux", &qspi_gfclk_mux, CK_7XX),
+ CLK(NULL, "qspi_gfclk_div", &qspi_gfclk_div, CK_7XX),
+ CLK(NULL, "timer10_gfclk_mux", &timer10_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer11_gfclk_mux", &timer11_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer13_gfclk_mux", &timer13_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer14_gfclk_mux", &timer14_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer15_gfclk_mux", &timer15_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer16_gfclk_mux", &timer16_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer1_gfclk_mux", &timer1_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer2_gfclk_mux", &timer2_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer3_gfclk_mux", &timer3_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer4_gfclk_mux", &timer4_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer5_gfclk_mux", &timer5_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer6_gfclk_mux", &timer6_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer7_gfclk_mux", &timer7_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer8_gfclk_mux", &timer8_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer9_gfclk_mux", &timer9_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart10_gfclk_mux", &uart10_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart1_gfclk_mux", &uart1_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart2_gfclk_mux", &uart2_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart3_gfclk_mux", &uart3_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart4_gfclk_mux", &uart4_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart5_gfclk_mux", &uart5_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart6_gfclk_mux", &uart6_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart7_gfclk_mux", &uart7_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart8_gfclk_mux", &uart8_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart9_gfclk_mux", &uart9_gfclk_mux, CK_7XX),
+ CLK(NULL, "vip1_gclk_mux", &vip1_gclk_mux, CK_7XX),
+ CLK(NULL, "vip2_gclk_mux", &vip2_gclk_mux, CK_7XX),
+ CLK(NULL, "vip3_gclk_mux", &vip3_gclk_mux, CK_7XX),
+ CLK(NULL, "gpmc_ck", &dummy_ck, CK_7XX),
+ CLK("omap_i2c.1", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_i2c.2", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_i2c.3", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_i2c.4", "ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "mailboxes_ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_7XX),
+ CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_7XX),
+ CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_7XX),
+ CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_7XX),
+ CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_7XX),
+ CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_7XX),
+ CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_7XX),
+ CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_7XX),
+ CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "uart1_ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "uart2_ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "uart3_ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "uart4_ick", &dummy_ck, CK_7XX),
+ CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_7XX),
+ CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_7XX),
+ CLK("omap_wdt", "ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_7XX),
+ CLK("4ae18000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48032000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48034000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48036000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("4803e000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48086000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48088000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48820000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX),
+ CLK("48822000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX),
+ CLK("48824000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX),
+ CLK("48826000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX),
+ CLK(NULL, "sys_clkin", &sys_clkin1, CK_7XX),
+};
+
+/*
+ * Prepare and enable a list of clocks.
+ * XXX Deprecated: Only needed until these clocks are properly claimed
+ * and enabled by the drivers or core code thats uses them.
+ */
+
+static const char *enable_init_clks[] = {
+};
+
+static struct reparent_init_clks reparent_clks[] = {
+ { .name = "abe_dpll_sys_clk_mux", .parent = "sys_clkin2" },
+};
+
+static struct rate_init_clks rate_clks[] = {
+ { .name = "dpll_abe_ck", .rate = DRA7_DPLL_ABE_DEFFREQ },
+ { .name = "dpll_gmac_ck", .rate = DRA7_DPLL_GMAC_DEFFREQ },
+};
+
+int __init dra7xx_clk_init(void)
+{
+ u32 cpu_clkflg;
+ struct omap_clk *c;
+
+ if (soc_is_dra7xx()) {
+ cpu_mask = RATE_IN_7XX;
+ cpu_clkflg = CK_7XX;
+ }
+
+ /*
+ * Must stay commented until all OMAP SoC drivers are
+ * converted to runtime PM, or drivers may start crashing
+ *
+ * omap2_clk_disable_clkdm_control();
+ */
+
+ for (c = dra7xx_clks; c < dra7xx_clks + ARRAY_SIZE(dra7xx_clks);
+ c++) {
+ if (c->cpu & cpu_clkflg) {
+ clkdev_add(&c->lk);
+ if (!__clk_init(NULL, c->lk.clk))
+ omap2_init_clk_hw_omap_clocks(c->lk.clk);
+ }
+ }
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_reparent_init_clocks(reparent_clks,
+ ARRAY_SIZE(reparent_clks));
+ omap2_clk_rate_init_clocks(rate_clks, ARRAY_SIZE(rate_clks));
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ return 0;
+}
index 9874ebea4f2240440d128064fcd4af28a9fbae87..35a3050390b9ed396c0be01c4ccb5792ffb16817 100644 (file)
#define CK_446X (1 << 8)
#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
#define CK_54XX (1 << 10) /* OMAP54xx specific clocks */
+#define CK_7XX (1 << 11)
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
#define RATE_IN_AM33XX (1 << 8)
#define RATE_IN_TI814X (1 << 9)
#define RATE_IN_54XX (1 << 10)
+#define RATE_IN_7XX (1 << 11)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
diff --git a/arch/arm/mach-omap2/clock7xx.h b/arch/arm/mach-omap2/clock7xx.h
--- /dev/null
@@ -0,0 +1,24 @@
+/*
+ * DRA7xx clock function prototypes and macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_DRA_CLOCK7xx_H
+#define __ARCH_ARM_MACH_DRA_CLOCK7xx_H
+
+int dra7xx_clk_init(void);
+
+#endif
index c918efb465af5a8a70ac4065c269735c56feaa25..6109807b9da9fefd5be1244b537325c8964d9dbd 100644 (file)
/* clksel_rate blocks shared between OMAP44xx and AM33xx */
const struct clksel_rate div_1_0_rates[] = {
- { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
};
const struct clksel_rate div_1_1_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div_1_2_rates[] = {
- { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div_1_3_rates[] = {
- { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div_1_4_rates[] = {
- { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div31_1to31_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div63_1to63_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_54XX },
- { .div = 2, .val = 2, .flags = RATE_IN_54XX },
- { .div = 3, .val = 3, .flags = RATE_IN_54XX },
- { .div = 4, .val = 4, .flags = RATE_IN_54XX },
- { .div = 5, .val = 5, .flags = RATE_IN_54XX },
- { .div = 6, .val = 6, .flags = RATE_IN_54XX },
- { .div = 7, .val = 7, .flags = RATE_IN_54XX },
- { .div = 8, .val = 8, .flags = RATE_IN_54XX },
- { .div = 9, .val = 9, .flags = RATE_IN_54XX },
- { .div = 10, .val = 10, .flags = RATE_IN_54XX },
- { .div = 11, .val = 11, .flags = RATE_IN_54XX },
- { .div = 12, .val = 12, .flags = RATE_IN_54XX },
- { .div = 13, .val = 13, .flags = RATE_IN_54XX },
- { .div = 14, .val = 14, .flags = RATE_IN_54XX },
- { .div = 15, .val = 15, .flags = RATE_IN_54XX },
- { .div = 16, .val = 16, .flags = RATE_IN_54XX },
- { .div = 17, .val = 17, .flags = RATE_IN_54XX },
- { .div = 18, .val = 18, .flags = RATE_IN_54XX },
- { .div = 19, .val = 19, .flags = RATE_IN_54XX },
- { .div = 20, .val = 20, .flags = RATE_IN_54XX },
- { .div = 21, .val = 21, .flags = RATE_IN_54XX },
- { .div = 22, .val = 22, .flags = RATE_IN_54XX },
- { .div = 23, .val = 23, .flags = RATE_IN_54XX },
- { .div = 24, .val = 24, .flags = RATE_IN_54XX },
- { .div = 25, .val = 25, .flags = RATE_IN_54XX },
- { .div = 26, .val = 26, .flags = RATE_IN_54XX },
- { .div = 27, .val = 27, .flags = RATE_IN_54XX },
- { .div = 28, .val = 28, .flags = RATE_IN_54XX },
- { .div = 29, .val = 29, .flags = RATE_IN_54XX },
- { .div = 30, .val = 30, .flags = RATE_IN_54XX },
- { .div = 31, .val = 31, .flags = RATE_IN_54XX },
- { .div = 32, .val = 32, .flags = RATE_IN_54XX },
- { .div = 33, .val = 33, .flags = RATE_IN_54XX },
- { .div = 34, .val = 34, .flags = RATE_IN_54XX },
- { .div = 35, .val = 35, .flags = RATE_IN_54XX },
- { .div = 36, .val = 36, .flags = RATE_IN_54XX },
- { .div = 37, .val = 37, .flags = RATE_IN_54XX },
- { .div = 38, .val = 38, .flags = RATE_IN_54XX },
- { .div = 39, .val = 39, .flags = RATE_IN_54XX },
- { .div = 40, .val = 40, .flags = RATE_IN_54XX },
- { .div = 41, .val = 41, .flags = RATE_IN_54XX },
- { .div = 42, .val = 42, .flags = RATE_IN_54XX },
- { .div = 43, .val = 43, .flags = RATE_IN_54XX },
- { .div = 44, .val = 44, .flags = RATE_IN_54XX },
- { .div = 45, .val = 45, .flags = RATE_IN_54XX },
- { .div = 46, .val = 46, .flags = RATE_IN_54XX },
- { .div = 47, .val = 47, .flags = RATE_IN_54XX },
- { .div = 48, .val = 48, .flags = RATE_IN_54XX },
- { .div = 49, .val = 49, .flags = RATE_IN_54XX },
- { .div = 50, .val = 50, .flags = RATE_IN_54XX },
- { .div = 51, .val = 51, .flags = RATE_IN_54XX },
- { .div = 52, .val = 52, .flags = RATE_IN_54XX },
- { .div = 53, .val = 53, .flags = RATE_IN_54XX },
- { .div = 54, .val = 54, .flags = RATE_IN_54XX },
- { .div = 55, .val = 55, .flags = RATE_IN_54XX },
- { .div = 56, .val = 56, .flags = RATE_IN_54XX },
- { .div = 57, .val = 57, .flags = RATE_IN_54XX },
- { .div = 58, .val = 58, .flags = RATE_IN_54XX },
- { .div = 59, .val = 59, .flags = RATE_IN_54XX },
- { .div = 60, .val = 60, .flags = RATE_IN_54XX },
- { .div = 61, .val = 61, .flags = RATE_IN_54XX },
- { .div = 62, .val = 62, .flags = RATE_IN_54XX },
- { .div = 63, .val = 63, .flags = RATE_IN_54XX },
+ { .div = 1, .val = 1, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 7, .val = 7, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 10, .val = 10, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 11, .val = 11, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 13, .val = 13, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 14, .val = 14, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 15, .val = 15, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 17, .val = 17, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 18, .val = 18, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 19, .val = 19, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 20, .val = 20, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 21, .val = 21, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 22, .val = 22, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 23, .val = 23, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 24, .val = 24, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 25, .val = 25, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 26, .val = 26, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 27, .val = 27, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 28, .val = 28, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 29, .val = 29, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 30, .val = 30, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 31, .val = 31, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 32, .val = 32, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 33, .val = 33, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 34, .val = 34, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 35, .val = 35, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 36, .val = 36, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 37, .val = 37, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 38, .val = 38, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 39, .val = 39, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 40, .val = 40, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 41, .val = 41, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 42, .val = 42, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 43, .val = 43, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 44, .val = 44, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 45, .val = 45, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 46, .val = 46, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 47, .val = 47, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 48, .val = 48, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 49, .val = 49, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 50, .val = 50, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 51, .val = 51, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 52, .val = 52, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 53, .val = 53, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 54, .val = 54, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 55, .val = 55, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 56, .val = 56, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 57, .val = 57, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 58, .val = 58, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 59, .val = 59, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 60, .val = 60, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 61, .val = 61, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 62, .val = 62, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 63, .val = 63, .flags = RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
index aa800679c80a2f3fa224665ca87b016c924a6fc6..d767b0199874afe9f2fbf258ef82896b1818281b 100644 (file)
extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
+extern void __init dra7xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
--- /dev/null
@@ -0,0 +1,739 @@
+/*
+ * DRA7xx Clock domains framework
+ *
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm1_7xx.h"
+#include "cm2_7xx.h"
+
+#include "cm-regbits-7xx.h"
+#include "prm7xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu7xx.h"
+
+/* Static Dependencies for DRA7xx Clock Domains */
+
+static struct clkdm_dep cam_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dma_wkup_sleep_deps[] = {
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "cam_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "cam_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dss_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep eve1_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep eve2_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep eve3_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep eve4_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep gmac_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep gpu_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep iva_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep l3init_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
+ { .clkdm_name = "cam_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep pcie_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "cam_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep vpe_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { NULL },
+};
+
+static struct clockdomain l4per3_7xx_clkdm = {
+ .name = "l4per3_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
+ .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4per2_7xx_clkdm = {
+ .name = "l4per2_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
+ .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
+ .wkdep_srcs = l4per2_wkup_sleep_deps,
+ .sleepdep_srcs = l4per2_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mpu0_7xx_clkdm = {
+ .name = "mpu0_clkdm",
+ .pwrdm = { .name = "cpu0_pwrdm" },
+ .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
+ .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST,
+ .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain iva_7xx_clkdm = {
+ .name = "iva_clkdm",
+ .pwrdm = { .name = "iva_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_IVA_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
+ .dep_bit = DRA7XX_IVA_STATDEP_SHIFT,
+ .wkdep_srcs = iva_wkup_sleep_deps,
+ .sleepdep_srcs = iva_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain coreaon_7xx_clkdm = {
+ .name = "coreaon_clkdm",
+ .pwrdm = { .name = "coreaon_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_COREAON_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu1_7xx_clkdm = {
+ .name = "ipu1_clkdm",
+ .pwrdm = { .name = "ipu_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
+ .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT,
+ .wkdep_srcs = ipu1_wkup_sleep_deps,
+ .sleepdep_srcs = ipu1_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain ipu2_7xx_clkdm = {
+ .name = "ipu2_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
+ .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT,
+ .wkdep_srcs = ipu2_wkup_sleep_deps,
+ .sleepdep_srcs = ipu2_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l3init_7xx_clkdm = {
+ .name = "l3init_clkdm",
+ .pwrdm = { .name = "l3init_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
+ .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT,
+ .wkdep_srcs = l3init_wkup_sleep_deps,
+ .sleepdep_srcs = l3init_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4sec_7xx_clkdm = {
+ .name = "l4sec_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
+ .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
+ .wkdep_srcs = l4sec_wkup_sleep_deps,
+ .sleepdep_srcs = l4sec_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l3main1_7xx_clkdm = {
+ .name = "l3main1_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
+ .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain vpe_7xx_clkdm = {
+ .name = "vpe_clkdm",
+ .pwrdm = { .name = "vpe_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
+ .dep_bit = DRA7XX_VPE_STATDEP_SHIFT,
+ .wkdep_srcs = vpe_wkup_sleep_deps,
+ .sleepdep_srcs = vpe_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mpu_7xx_clkdm = {
+ .name = "mpu_clkdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
+ .wkdep_srcs = mpu_wkup_sleep_deps,
+ .sleepdep_srcs = mpu_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain custefuse_7xx_clkdm = {
+ .name = "custefuse_clkdm",
+ .pwrdm = { .name = "custefuse_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu_7xx_clkdm = {
+ .name = "ipu_clkdm",
+ .pwrdm = { .name = "ipu_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
+ .dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mpu1_7xx_clkdm = {
+ .name = "mpu1_clkdm",
+ .pwrdm = { .name = "cpu1_pwrdm" },
+ .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
+ .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST,
+ .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain gmac_7xx_clkdm = {
+ .name = "gmac_clkdm",
+ .pwrdm = { .name = "l3init_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
+ .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT,
+ .wkdep_srcs = gmac_wkup_sleep_deps,
+ .sleepdep_srcs = gmac_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4cfg_7xx_clkdm = {
+ .name = "l4cfg_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
+ .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain dma_7xx_clkdm = {
+ .name = "dma_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
+ .wkdep_srcs = dma_wkup_sleep_deps,
+ .sleepdep_srcs = dma_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain rtc_7xx_clkdm = {
+ .name = "rtc_clkdm",
+ .pwrdm = { .name = "rtc_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain pcie_7xx_clkdm = {
+ .name = "pcie_clkdm",
+ .pwrdm = { .name = "l3init_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
+ .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
+ .wkdep_srcs = pcie_wkup_sleep_deps,
+ .sleepdep_srcs = pcie_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain atl_7xx_clkdm = {
+ .name = "atl_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
+ .dep_bit = DRA7XX_ATL_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3instr_7xx_clkdm = {
+ .name = "l3instr_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
+};
+
+static struct clockdomain dss_7xx_clkdm = {
+ .name = "dss_clkdm",
+ .pwrdm = { .name = "dss_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_DSS_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
+ .dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
+ .wkdep_srcs = dss_wkup_sleep_deps,
+ .sleepdep_srcs = dss_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain emif_7xx_clkdm = {
+ .name = "emif_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
+ .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain emu_7xx_clkdm = {
+ .name = "emu_clkdm",
+ .pwrdm = { .name = "emu_pwrdm" },
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .cm_inst = DRA7XX_PRM_EMU_CM_INST,
+ .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain dsp2_7xx_clkdm = {
+ .name = "dsp2_clkdm",
+ .pwrdm = { .name = "dsp2_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
+ .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT,
+ .wkdep_srcs = dsp2_wkup_sleep_deps,
+ .sleepdep_srcs = dsp2_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dsp1_7xx_clkdm = {
+ .name = "dsp1_clkdm",
+ .pwrdm = { .name = "dsp1_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
+ .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT,
+ .wkdep_srcs = dsp1_wkup_sleep_deps,
+ .sleepdep_srcs = dsp1_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain cam_7xx_clkdm = {
+ .name = "cam_clkdm",
+ .pwrdm = { .name = "cam_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CAM_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
+ .dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
+ .wkdep_srcs = cam_wkup_sleep_deps,
+ .sleepdep_srcs = cam_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4per_7xx_clkdm = {
+ .name = "l4per_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
+ .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain gpu_7xx_clkdm = {
+ .name = "gpu_clkdm",
+ .pwrdm = { .name = "gpu_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_GPU_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
+ .dep_bit = DRA7XX_GPU_STATDEP_SHIFT,
+ .wkdep_srcs = gpu_wkup_sleep_deps,
+ .sleepdep_srcs = gpu_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain eve4_7xx_clkdm = {
+ .name = "eve4_clkdm",
+ .pwrdm = { .name = "eve4_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
+ .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT,
+ .wkdep_srcs = eve4_wkup_sleep_deps,
+ .sleepdep_srcs = eve4_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain eve2_7xx_clkdm = {
+ .name = "eve2_clkdm",
+ .pwrdm = { .name = "eve2_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
+ .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT,
+ .wkdep_srcs = eve2_wkup_sleep_deps,
+ .sleepdep_srcs = eve2_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain eve3_7xx_clkdm = {
+ .name = "eve3_clkdm",
+ .pwrdm = { .name = "eve3_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
+ .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT,
+ .wkdep_srcs = eve3_wkup_sleep_deps,
+ .sleepdep_srcs = eve3_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain wkupaon_7xx_clkdm = {
+ .name = "wkupaon_clkdm",
+ .pwrdm = { .name = "wkupaon_pwrdm" },
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST,
+ .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
+ .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain eve1_7xx_clkdm = {
+ .name = "eve1_clkdm",
+ .pwrdm = { .name = "eve1_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
+ .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT,
+ .wkdep_srcs = eve1_wkup_sleep_deps,
+ .sleepdep_srcs = eve1_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+/* As clockdomains are added or removed above, this list must also be changed */
+static struct clockdomain *clockdomains_dra7xx[] __initdata = {
+ &l4per3_7xx_clkdm,
+ &l4per2_7xx_clkdm,
+ &mpu0_7xx_clkdm,
+ &iva_7xx_clkdm,
+ &coreaon_7xx_clkdm,
+ &ipu1_7xx_clkdm,
+ &ipu2_7xx_clkdm,
+ &l3init_7xx_clkdm,
+ &l4sec_7xx_clkdm,
+ &l3main1_7xx_clkdm,
+ &vpe_7xx_clkdm,
+ &mpu_7xx_clkdm,
+ &custefuse_7xx_clkdm,
+ &ipu_7xx_clkdm,
+ &mpu1_7xx_clkdm,
+ &gmac_7xx_clkdm,
+ &l4cfg_7xx_clkdm,
+ &dma_7xx_clkdm,
+ &rtc_7xx_clkdm,
+ &pcie_7xx_clkdm,
+ &atl_7xx_clkdm,
+ &l3instr_7xx_clkdm,
+ &dss_7xx_clkdm,
+ &emif_7xx_clkdm,
+ &emu_7xx_clkdm,
+ &dsp2_7xx_clkdm,
+ &dsp1_7xx_clkdm,
+ &cam_7xx_clkdm,
+ &l4per_7xx_clkdm,
+ &gpu_7xx_clkdm,
+ &eve4_7xx_clkdm,
+ &eve2_7xx_clkdm,
+ &eve3_7xx_clkdm,
+ &wkupaon_7xx_clkdm,
+ &eve1_7xx_clkdm,
+ NULL
+};
+
+void __init dra7xx_clockdomains_init(void)
+{
+ clkdm_register_platform_funcs(&omap4_clkdm_operations);
+ clkdm_register_clkdms(clockdomains_dra7xx);
+ clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h
--- /dev/null
@@ -0,0 +1,2207 @@
+/*
+ * DRA7xx Clock Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
+
+/* Used by CM_L4PER2_DYNAMICDEP */
+#define DRA7XX_ATL_DYNDEP_SHIFT 6
+#define DRA7XX_ATL_DYNDEP_WIDTH 0x1
+#define DRA7XX_ATL_DYNDEP_MASK (1 << 6)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_DSP2_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_ATL_STATDEP_SHIFT 30
+#define DRA7XX_ATL_STATDEP_WIDTH 0x1
+#define DRA7XX_ATL_STATDEP_MASK (1 << 30)
+
+/*
+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR,
+ * CM_AUTOIDLE_DPLL_DSP, CM_AUTOIDLE_DPLL_EVE, CM_AUTOIDLE_DPLL_GMAC,
+ * CM_AUTOIDLE_DPLL_GPU, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
+ * CM_AUTOIDLE_DPLL_PCIE_REF, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_USB
+ */
+#define DRA7XX_AUTO_DPLL_MODE_SHIFT 0
+#define DRA7XX_AUTO_DPLL_MODE_WIDTH 0x3
+#define DRA7XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
+
+/* Used by CM_IPU2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP */
+#define DRA7XX_CAM_DYNDEP_SHIFT 9
+#define DRA7XX_CAM_DYNDEP_WIDTH 0x1
+#define DRA7XX_CAM_DYNDEP_MASK (1 << 9)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_CAM_STATDEP_SHIFT 9
+#define DRA7XX_CAM_STATDEP_WIDTH 0x1
+#define DRA7XX_CAM_STATDEP_MASK (1 << 9)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ABE_GICLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 16)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ADC_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_ADC_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ADC_GFCLK_MASK (1 << 10)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ADC_L3_GICLK_SHIFT 19
+#define DRA7XX_CLKACTIVITY_ADC_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ADC_L3_GICLK_MASK (1 << 19)
+
+/* Used by CM_ATL_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ATL_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_ATL_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ATL_GFCLK_MASK (1 << 9)
+
+/* Used by CM_ATL_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ATL_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_ATL_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ATL_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8)
+
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8)
+
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DCAN1_SYS_CLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_DCAN1_SYS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DCAN1_SYS_CLK_MASK (1 << 16)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DCAN2_SYS_CLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_DCAN2_SYS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DCAN2_SYS_CLK_MASK (1 << 15)
+
+/* Used by CM_DMA_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_DSP1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSP1_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_DSP1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSP1_GFCLK_MASK (1 << 8)
+
+/* Used by CM_DSP2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSP2_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_DSP2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSP2_GFCLK_MASK (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSS_L4_GICLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_DSS_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSS_L4_GICLK_MASK (1 << 15)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 16)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EMIF_DLL_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_EMIF_DLL_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EMIF_DLL_GCLK_MASK (1 << 9)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8)
+
+/* Used by CM_EVE1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EVE1_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EVE1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EVE1_GFCLK_MASK (1 << 8)
+
+/* Used by CM_EVE2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EVE2_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EVE2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EVE2_GFCLK_MASK (1 << 8)
+
+/* Used by CM_EVE3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EVE3_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EVE3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EVE3_GFCLK_MASK (1 << 8)
+
+/* Used by CM_EVE4_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EVE4_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EVE4_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EVE4_GFCLK_MASK (1 << 8)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GMAC_MAIN_CLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_GMAC_MAIN_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GMAC_MAIN_CLK_MASK (1 << 12)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GMAC_RFT_CLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_GMAC_RFT_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GMAC_RFT_CLK_MASK (1 << 11)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GMII_250MHZ_CLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_GMII_250MHZ_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GMII_250MHZ_CLK_MASK (1 << 8)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GPIO_GFCLK_SHIFT 24
+#define DRA7XX_CLKACTIVITY_GPIO_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GPIO_GFCLK_MASK (1 << 24)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GPU_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_GPU_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GPU_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 17
+#define DRA7XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 17)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_HDMI_DPLL_CLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_HDMI_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_HDMI_DPLL_CLK_MASK (1 << 11)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 18
+#define DRA7XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 18)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_HSI_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 14)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ICSS_CLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_ICSS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ICSS_CLK_MASK (1 << 8)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ICSS_IEP_CLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_ICSS_IEP_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ICSS_IEP_CLK_MASK (1 << 14)
+
+/* Used by CM_IPU1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IPU1_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_IPU1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IPU1_GFCLK_MASK (1 << 8)
+
+/* Used by CM_IPU2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IPU2_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_IPU2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IPU2_GFCLK_MASK (1 << 8)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IPU_96M_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_IPU_96M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IPU_96M_GFCLK_MASK (1 << 13)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IPU_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_IPU_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IPU_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_IVA_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IVA_GCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_32K_GFCLK_SHIFT 23
+#define DRA7XX_CLKACTIVITY_L3INIT_32K_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_32K_GFCLK_MASK (1 << 23)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_480M_GFCLK_SHIFT 21
+#define DRA7XX_CLKACTIVITY_L3INIT_480M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_480M_GFCLK_MASK (1 << 21)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_960M_GFCLK_SHIFT 22
+#define DRA7XX_CLKACTIVITY_L3INIT_960M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_960M_GFCLK_MASK (1 << 22)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_MASK (1 << 10)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10)
+
+/* Used by CM_L3MAIN1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L3MAIN1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L4_GICLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L4_GICLK_MASK (1 << 9)
+
+/* Used by CM_L4CFG_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4CFG_L3_GICLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_L4CFG_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4CFG_L3_GICLK_MASK (1 << 9)
+
+/* Used by CM_L4CFG_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4PER2_L3_GICLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_L4PER2_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4PER2_L3_GICLK_MASK (1 << 16)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4PER3_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L4PER3_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4PER3_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4PER_32K_GFCLK_SHIFT 27
+#define DRA7XX_CLKACTIVITY_L4PER_32K_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4PER_32K_GFCLK_MASK (1 << 27)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4PER_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L4PER_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4PER_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_LVDSRX_96M_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_LVDSRX_96M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_LVDSRX_96M_GFCLK_MASK (1 << 12)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_LVDSRX_L4_GICLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_LVDSRX_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_LVDSRX_L4_GICLK_MASK (1 << 11)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKR_SHIFT 18
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKR_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKR_MASK (1 << 18)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKX_SHIFT 17
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKX_MASK (1 << 17)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP1_AUX_GFCLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_MCASP1_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP1_AUX_GFCLK_MASK (1 << 16)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKR_SHIFT 18
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKR_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKR_MASK (1 << 18)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKX_SHIFT 17
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKX_MASK (1 << 17)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP2_AUX_GFCLK_SHIFT 19
+#define DRA7XX_CLKACTIVITY_MCASP2_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP2_AUX_GFCLK_MASK (1 << 19)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP3_AHCLKX_SHIFT 20
+#define DRA7XX_CLKACTIVITY_MCASP3_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP3_AHCLKX_MASK (1 << 20)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP3_AUX_GFCLK_SHIFT 21
+#define DRA7XX_CLKACTIVITY_MCASP3_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP3_AUX_GFCLK_MASK (1 << 21)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP4_AHCLKX_SHIFT 22
+#define DRA7XX_CLKACTIVITY_MCASP4_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP4_AHCLKX_MASK (1 << 22)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP4_AUX_GFCLK_SHIFT 23
+#define DRA7XX_CLKACTIVITY_MCASP4_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP4_AUX_GFCLK_MASK (1 << 23)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP5_AHCLKX_SHIFT 25
+#define DRA7XX_CLKACTIVITY_MCASP5_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP5_AHCLKX_MASK (1 << 25)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP5_AUX_GFCLK_SHIFT 24
+#define DRA7XX_CLKACTIVITY_MCASP5_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP5_AUX_GFCLK_MASK (1 << 24)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP6_AHCLKX_SHIFT 26
+#define DRA7XX_CLKACTIVITY_MCASP6_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP6_AHCLKX_MASK (1 << 26)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP6_AUX_GFCLK_SHIFT 27
+#define DRA7XX_CLKACTIVITY_MCASP6_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP6_AUX_GFCLK_MASK (1 << 27)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP7_AHCLKX_SHIFT 28
+#define DRA7XX_CLKACTIVITY_MCASP7_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP7_AHCLKX_MASK (1 << 28)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP7_AUX_GFCLK_SHIFT 29
+#define DRA7XX_CLKACTIVITY_MCASP7_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP7_AUX_GFCLK_MASK (1 << 29)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP8_AHCLKX_SHIFT 30
+#define DRA7XX_CLKACTIVITY_MCASP8_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP8_AHCLKX_MASK (1 << 30)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP8_AUX_GFCLK_SHIFT 31
+#define DRA7XX_CLKACTIVITY_MCASP8_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP8_AUX_GFCLK_MASK (1 << 31)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MLB_SHB_L3_GICLK_SHIFT 17
+#define DRA7XX_CLKACTIVITY_MLB_SHB_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MLB_SHB_L3_GICLK_MASK (1 << 17)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MLB_SPB_L4_GICLK_SHIFT 18
+#define DRA7XX_CLKACTIVITY_MLB_SPB_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MLB_SPB_L4_GICLK_MASK (1 << 18)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MLB_SYS_L3_GFCLK_SHIFT 19
+#define DRA7XX_CLKACTIVITY_MLB_SYS_L3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MLB_SYS_L3_GFCLK_MASK (1 << 19)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 15)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 16)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MMC3_GFCLK_SHIFT 22
+#define DRA7XX_CLKACTIVITY_MMC3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MMC3_GFCLK_MASK (1 << 22)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MMC4_GFCLK_SHIFT 23
+#define DRA7XX_CLKACTIVITY_MMC4_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MMC4_GFCLK_MASK (1 << 23)
+
+/* Used by CM_MPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MPU_GCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_32K_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_PCIE_32K_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_32K_GFCLK_MASK (1 << 13)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_PCIE_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_DIV_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_DIV_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_DIV_GCLK_MASK (1 << 10)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_GCLK_MASK (1 << 9)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_REF_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_PCIE_REF_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_REF_GFCLK_MASK (1 << 11)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_SYS_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_PCIE_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_SYS_GFCLK_MASK (1 << 12)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 19
+#define DRA7XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 19)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_MASK (1 << 13)
+
+/* Renamed from CLKACTIVITY_PER_192M_GFCLK Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_25_25_SHIFT 25
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_25_25_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_25_25_MASK (1 << 25)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 20
+#define DRA7XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 20)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 21
+#define DRA7XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 21)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_QSPI_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_QSPI_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_QSPI_GFCLK_MASK (1 << 12)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_RGMII_5MHZ_CLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_RGMII_5MHZ_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_RGMII_5MHZ_CLK_MASK (1 << 9)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_RMII_50MHZ_CLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_RMII_50MHZ_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_RMII_50MHZ_CLK_MASK (1 << 10)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_RTC_AUX_CLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_RTC_AUX_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_RTC_AUX_CLK_MASK (1 << 10)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_RTC_L4_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_RTC_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_RTC_L4_GICLK_MASK (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 24
+#define DRA7XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 24)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SDVENC_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_SDVENC_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SDVENC_GFCLK_MASK (1 << 14)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_MASK (1 << 13)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_GPU_SYS_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_SR_GPU_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_GPU_SYS_GFCLK_MASK (1 << 10)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_IVAHD_SYS_GFCLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_SR_IVAHD_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_IVAHD_SYS_GFCLK_MASK (1 << 15)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SYS_CLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15
+#define DRA7XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14
+#define DRA7XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER13_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_TIMER13_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER13_GFCLK_MASK (1 << 9)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER14_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_TIMER14_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER14_GFCLK_MASK (1 << 10)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER15_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_TIMER15_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER15_GFCLK_MASK (1 << 11)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER16_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_TIMER16_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER16_GFCLK_MASK (1 << 12)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER1_GFCLK_SHIFT 17
+#define DRA7XX_CLKACTIVITY_TIMER1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER1_GFCLK_MASK (1 << 17)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER5_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_TIMER5_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER5_GFCLK_MASK (1 << 9)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER6_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_TIMER6_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER6_GFCLK_MASK (1 << 10)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER7_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_TIMER7_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER7_GFCLK_MASK (1 << 11)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER8_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_TIMER8_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER8_GFCLK_MASK (1 << 12)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART10_GFCLK_SHIFT 18
+#define DRA7XX_CLKACTIVITY_UART10_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART10_GFCLK_MASK (1 << 18)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART1_GFCLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_UART1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART1_GFCLK_MASK (1 << 15)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART2_GFCLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_UART2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART2_GFCLK_MASK (1 << 16)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART3_GFCLK_SHIFT 17
+#define DRA7XX_CLKACTIVITY_UART3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART3_GFCLK_MASK (1 << 17)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART4_GFCLK_SHIFT 18
+#define DRA7XX_CLKACTIVITY_UART4_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART4_GFCLK_MASK (1 << 18)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART5_GFCLK_SHIFT 26
+#define DRA7XX_CLKACTIVITY_UART5_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART5_GFCLK_MASK (1 << 26)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART6_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_UART6_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART6_GFCLK_MASK (1 << 14)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART7_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_UART7_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART7_GFCLK_MASK (1 << 9)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART8_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_UART8_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART8_GFCLK_MASK (1 << 10)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART9_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_UART9_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART9_GFCLK_MASK (1 << 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 12)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 13)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 20
+#define DRA7XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 20)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIDEO1_DPLL_CLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_VIDEO1_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIDEO1_DPLL_CLK_MASK (1 << 10)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIDEO2_DPLL_CLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_VIDEO2_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIDEO2_DPLL_CLK_MASK (1 << 12)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIP1_GCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_VIP1_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIP1_GCLK_MASK (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIP2_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_VIP2_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIP2_GCLK_MASK (1 << 9)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIP3_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_VIP3_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIP3_GCLK_MASK (1 << 10)
+
+/* Used by CM_VPE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VPE_GCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_VPE_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VPE_GCLK_MASK (1 << 8)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_WKUPAON_SYS_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_WKUPAON_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_WKUPAON_SYS_GFCLK_MASK (1 << 11)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_CLKDIV_BYPASS_SHIFT 8
+#define DRA7XX_CLKDIV_BYPASS_WIDTH 0x1
+#define DRA7XX_CLKDIV_BYPASS_MASK (1 << 8)
+
+/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
+#define DRA7XX_CLKEN_SRCOMP_FCLK_SHIFT 8
+#define DRA7XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1
+#define DRA7XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8)
+
+/* Used by CM_DIV_M2_DPLL_PCIE_REF */
+#define DRA7XX_CLKLDOST_SHIFT 10
+#define DRA7XX_CLKLDOST_WIDTH 0x1
+#define DRA7XX_CLKLDOST_MASK (1 << 10)
+
+/*
+ * Used by CM_CLKSEL_ABE_CLK_DIV, CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX,
+ * CM_CLKSEL_DSP_GFCLK_CLKOUTMUX, CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,
+ * CM_CLKSEL_EMU_CLK_CLKOUTMUX, CM_CLKSEL_EVE_GFCLK_CLKOUTMUX,
+ * CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX, CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,
+ * CM_CLKSEL_GPU_GCLK_CLKOUTMUX, CM_CLKSEL_HDMI_CLK_CLKOUTMUX,
+ * CM_CLKSEL_HDMI_MCASP_AUX, CM_CLKSEL_HDMI_TIMER,
+ * CM_CLKSEL_IVA_GCLK_CLKOUTMUX, CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,
+ * CM_CLKSEL_MLBP_MCASP, CM_CLKSEL_MLB_MCASP, CM_CLKSEL_MPU_GCLK_CLKOUTMUX,
+ * CM_CLKSEL_PCIE1_CLK_CLKOUTMUX, CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,
+ * CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX, CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,
+ * CM_CLKSEL_SATA_CLK_CLKOUTMUX, CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX,
+ * CM_CLKSEL_SYS_CLK1_CLKOUTMUX, CM_CLKSEL_SYS_CLK2_CLKOUTMUX,
+ * CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX, CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX,
+ * CM_CLKSEL_VIDEO1_MCASP_AUX, CM_CLKSEL_VIDEO1_TIMER,
+ * CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX, CM_CLKSEL_VIDEO2_MCASP_AUX,
+ * CM_CLKSEL_VIDEO2_TIMER
+ */
+#define DRA7XX_CLKSEL_SHIFT 0
+#define DRA7XX_CLKSEL_WIDTH 0x3
+#define DRA7XX_CLKSEL_MASK (0x7 << 0)
+
+/*
+ * Renamed from CLKSEL Used by CM_CLKSEL_ABE_24M, CM_CLKSEL_ABE_GICLK_DIV,
+ * CM_CLKSEL_ABE_LP_CLK, CM_CLKSEL_ABE_PLL_BYPAS, CM_CLKSEL_ABE_PLL_REF,
+ * CM_CLKSEL_ABE_PLL_SYS, CM_CLKSEL_ABE_SYS, CM_CLKSEL_AESS_FCLK_DIV,
+ * CM_CLKSEL_EVE_CLK, CM_CLKSEL_HDMI_PLL_SYS, CM_CLKSEL_MCASP_SYS,
+ * CM_CLKSEL_SYSCLK1, CM_CLKSEL_SYS_CLK1_32K, CM_CLKSEL_TIMER_SYS,
+ * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_VIDEO1_PLL_SYS, CM_CLKSEL_VIDEO2_PLL_SYS,
+ * CM_CLKSEL_WKUPAON
+ */
+#define DRA7XX_CLKSEL_0_0_SHIFT 0
+#define DRA7XX_CLKSEL_0_0_WIDTH 0x1
+#define DRA7XX_CLKSEL_0_0_MASK (1 << 0)
+
+/*
+ * Renamed from CLKSEL Used by CM_CAM_VIP1_CLKCTRL, CM_CAM_VIP2_CLKCTRL,
+ * CM_CAM_VIP3_CLKCTRL, CM_IPU1_IPU1_CLKCTRL, CM_IPU_UART6_CLKCTRL,
+ * CM_L4PER2_UART7_CLKCTRL, CM_L4PER2_UART8_CLKCTRL, CM_L4PER2_UART9_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4PER_UART5_CLKCTRL, CM_WKUPAON_DCAN1_CLKCTRL,
+ * CM_WKUPAON_UART10_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_24_24_SHIFT 24
+#define DRA7XX_CLKSEL_24_24_WIDTH 0x1
+#define DRA7XX_CLKSEL_24_24_MASK (1 << 24)
+
+/*
+ * Renamed from CLKSEL Used by CM_IPU_TIMER5_CLKCTRL, CM_IPU_TIMER6_CLKCTRL,
+ * CM_IPU_TIMER7_CLKCTRL, CM_IPU_TIMER8_CLKCTRL, CM_L4PER3_TIMER13_CLKCTRL,
+ * CM_L4PER3_TIMER14_CLKCTRL, CM_L4PER3_TIMER15_CLKCTRL,
+ * CM_L4PER3_TIMER16_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_24_27_SHIFT 24
+#define DRA7XX_CLKSEL_24_27_WIDTH 0x4
+#define DRA7XX_CLKSEL_24_27_MASK (0xf << 24)
+
+/*
+ * Renamed from CLKSEL Used by CM_BYPCLK_DPLL_DSP, CM_BYPCLK_DPLL_EVE,
+ * CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU, CM_CLKSEL_ADC_GFCLK
+ */
+#define DRA7XX_CLKSEL_0_1_SHIFT 0
+#define DRA7XX_CLKSEL_0_1_WIDTH 0x2
+#define DRA7XX_CLKSEL_0_1_MASK (0x3 << 0)
+
+/*
+ * Renamed from CLKSEL Used by CM_CLKSEL_CLKOUTMUX0, CM_CLKSEL_CLKOUTMUX1,
+ * CM_CLKSEL_CLKOUTMUX2
+ */
+#define DRA7XX_CLKSEL_0_4_SHIFT 0
+#define DRA7XX_CLKSEL_0_4_WIDTH 0x5
+#define DRA7XX_CLKSEL_0_4_MASK (0x1f << 0)
+
+/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
+#define DRA7XX_CLKSEL_24_25_SHIFT 24
+#define DRA7XX_CLKSEL_24_25_WIDTH 0x2
+#define DRA7XX_CLKSEL_24_25_MASK (0x3 << 24)
+
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define DRA7XX_CLKSEL_ABE_DIV_MODE_SHIFT 26
+#define DRA7XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
+#define DRA7XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
+
+/* Used by CM_IPU_MCASP1_CLKCTRL, CM_L4PER2_MCASP2_CLKCTRL */
+#define DRA7XX_CLKSEL_AHCLKR_SHIFT 28
+#define DRA7XX_CLKSEL_AHCLKR_WIDTH 0x4
+#define DRA7XX_CLKSEL_AHCLKR_MASK (0xf << 28)
+
+/*
+ * Used by CM_IPU_MCASP1_CLKCTRL, CM_L4PER2_MCASP2_CLKCTRL,
+ * CM_L4PER2_MCASP3_CLKCTRL, CM_L4PER2_MCASP4_CLKCTRL,
+ * CM_L4PER2_MCASP5_CLKCTRL, CM_L4PER2_MCASP6_CLKCTRL,
+ * CM_L4PER2_MCASP7_CLKCTRL, CM_L4PER2_MCASP8_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_AHCLKX_SHIFT 24
+#define DRA7XX_CLKSEL_AHCLKX_WIDTH 0x4
+#define DRA7XX_CLKSEL_AHCLKX_MASK (0xf << 24)
+
+/*
+ * Used by CM_IPU_MCASP1_CLKCTRL, CM_L4PER2_MCASP2_CLKCTRL,
+ * CM_L4PER2_MCASP3_CLKCTRL, CM_L4PER2_MCASP4_CLKCTRL,
+ * CM_L4PER2_MCASP5_CLKCTRL, CM_L4PER2_MCASP6_CLKCTRL,
+ * CM_L4PER2_MCASP7_CLKCTRL, CM_L4PER2_MCASP8_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_AUX_CLK_SHIFT 22
+#define DRA7XX_CLKSEL_AUX_CLK_WIDTH 0x2
+#define DRA7XX_CLKSEL_AUX_CLK_MASK (0x3 << 22)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define DRA7XX_CLKSEL_CORE_CLK_SHIFT 24
+#define DRA7XX_CLKSEL_CORE_CLK_WIDTH 0x2
+#define DRA7XX_CLKSEL_CORE_CLK_MASK (0x3 << 24)
+
+/*
+ * Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L4PER2_QSPI_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_DIV_SHIFT 25
+#define DRA7XX_CLKSEL_DIV_WIDTH 0x2
+#define DRA7XX_CLKSEL_DIV_MASK (0x3 << 25)
+
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define DRA7XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define DRA7XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2
+#define DRA7XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define DRA7XX_CLKSEL_HYD_CLK_SHIFT 26
+#define DRA7XX_CLKSEL_HYD_CLK_WIDTH 0x2
+#define DRA7XX_CLKSEL_HYD_CLK_MASK (0x3 << 26)
+
+/* Used by CM_CLKSEL_CORE */
+#define DRA7XX_CLKSEL_L3_SHIFT 4
+#define DRA7XX_CLKSEL_L3_WIDTH 0x1
+#define DRA7XX_CLKSEL_L3_MASK (1 << 4)
+
+/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+#define DRA7XX_CLKSEL_L3_1_1_SHIFT 1
+#define DRA7XX_CLKSEL_L3_1_1_WIDTH 0x1
+#define DRA7XX_CLKSEL_L3_1_1_MASK (1 << 1)
+
+/* Used by CM_CLKSEL_CORE */
+#define DRA7XX_CLKSEL_L4_SHIFT 8
+#define DRA7XX_CLKSEL_L4_WIDTH 0x1
+#define DRA7XX_CLKSEL_L4_MASK (1 << 8)
+
+/* Used by CM_EMIF_EMIF1_CLKCTRL */
+#define DRA7XX_CLKSEL_LL_SHIFT 24
+#define DRA7XX_CLKSEL_LL_WIDTH 0x1
+#define DRA7XX_CLKSEL_LL_MASK (1 << 24)
+
+/* Used by CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL */
+#define DRA7XX_CLKSEL_MUX_SHIFT 24
+#define DRA7XX_CLKSEL_MUX_WIDTH 0x1
+#define DRA7XX_CLKSEL_MUX_MASK (1 << 24)
+
+/* Used by CM_CLKSEL_ABE */
+#define DRA7XX_CLKSEL_OPP_SHIFT 0
+#define DRA7XX_CLKSEL_OPP_WIDTH 0x2
+#define DRA7XX_CLKSEL_OPP_MASK (0x3 << 0)
+
+/* Used by CM_GMAC_GMAC_CLKCTRL */
+#define DRA7XX_CLKSEL_REF_SHIFT 24
+#define DRA7XX_CLKSEL_REF_WIDTH 0x1
+#define DRA7XX_CLKSEL_REF_MASK (1 << 24)
+
+/* Used by CM_GMAC_GMAC_CLKCTRL */
+#define DRA7XX_CLKSEL_RFT_SHIFT 25
+#define DRA7XX_CLKSEL_RFT_WIDTH 0x3
+#define DRA7XX_CLKSEL_RFT_MASK (0x7 << 25)
+
+/*
+ * Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L4PER2_QSPI_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_SOURCE_SHIFT 24
+#define DRA7XX_CLKSEL_SOURCE_WIDTH 0x1
+#define DRA7XX_CLKSEL_SOURCE_MASK (1 << 24)
+
+/* Used by CM_ATL_ATL_CLKCTRL */
+#define DRA7XX_CLKSEL_SOURCE1_SHIFT 24
+#define DRA7XX_CLKSEL_SOURCE1_WIDTH 0x2
+#define DRA7XX_CLKSEL_SOURCE1_MASK (0x3 << 24)
+
+/* Used by CM_ATL_ATL_CLKCTRL */
+#define DRA7XX_CLKSEL_SOURCE2_SHIFT 26
+#define DRA7XX_CLKSEL_SOURCE2_WIDTH 0x2
+#define DRA7XX_CLKSEL_SOURCE2_MASK (0x3 << 26)
+
+/*
+ * Used by CM_CLKVCOLDO_APLL_PCIE, CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_DDR,
+ * CM_DIV_H11_DPLL_GMAC, CM_DIV_H11_DPLL_PER, CM_DIV_H12_DPLL_CORE,
+ * CM_DIV_H12_DPLL_GMAC, CM_DIV_H12_DPLL_PER, CM_DIV_H13_DPLL_CORE,
+ * CM_DIV_H13_DPLL_GMAC, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_GMAC, CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE,
+ * CM_DIV_H22_DPLL_CORE, CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE,
+ * CM_DIV_M2_APLL_PCIE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DSP, CM_DIV_M2_DPLL_EVE,
+ * CM_DIV_M2_DPLL_GMAC, CM_DIV_M2_DPLL_GPU, CM_DIV_M2_DPLL_IVA,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PCIE_REF, CM_DIV_M2_DPLL_PER,
+ * CM_DIV_M2_DPLL_USB, CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_DDR, CM_DIV_M3_DPLL_DSP, CM_DIV_M3_DPLL_EVE,
+ * CM_DIV_M3_DPLL_GMAC, CM_DIV_M3_DPLL_GPU, CM_DIV_M3_DPLL_IVA,
+ * CM_DIV_M3_DPLL_PER
+ */
+#define DRA7XX_CLKST_SHIFT 9
+#define DRA7XX_CLKST_WIDTH 0x1
+#define DRA7XX_CLKST_MASK (1 << 9)
+
+/*
+ * Used by CM_ATL_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_COREAON_CLKSTCTRL,
+ * CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL, CM_DSP1_CLKSTCTRL,
+ * CM_DSP2_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
+ * CM_EVE1_CLKSTCTRL, CM_EVE2_CLKSTCTRL, CM_EVE3_CLKSTCTRL, CM_EVE4_CLKSTCTRL,
+ * CM_GMAC_CLKSTCTRL, CM_GPU_CLKSTCTRL, CM_IPU1_CLKSTCTRL, CM_IPU2_CLKSTCTRL,
+ * CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
+ * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L4CFG_CLKSTCTRL,
+ * CM_L4PER2_CLKSTCTRL, CM_L4PER3_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
+ * CM_L4SEC_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_PCIE_CLKSTCTRL, CM_RTC_CLKSTCTRL,
+ * CM_VPE_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
+ */
+#define DRA7XX_CLKTRCTRL_SHIFT 0
+#define DRA7XX_CLKTRCTRL_WIDTH 0x2
+#define DRA7XX_CLKTRCTRL_MASK (0x3 << 0)
+
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
+#define DRA7XX_CLKX2ST_SHIFT 11
+#define DRA7XX_CLKX2ST_WIDTH 0x1
+#define DRA7XX_CLKX2ST_MASK (1 << 11)
+
+/* Used by CM_CLKVCOLDO_APLL_PCIE */
+#define DRA7XX_CLK_DIVST_SHIFT 10
+#define DRA7XX_CLK_DIVST_WIDTH 0x1
+#define DRA7XX_CLK_DIVST_MASK (1 << 10)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define DRA7XX_COREAON_DYNDEP_SHIFT 16
+#define DRA7XX_COREAON_DYNDEP_WIDTH 0x1
+#define DRA7XX_COREAON_DYNDEP_MASK (1 << 16)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_DSP2_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_COREAON_STATDEP_SHIFT 16
+#define DRA7XX_COREAON_STATDEP_WIDTH 0x1
+#define DRA7XX_COREAON_STATDEP_MASK (1 << 16)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define DRA7XX_CUSTEFUSE_DYNDEP_SHIFT 17
+#define DRA7XX_CUSTEFUSE_DYNDEP_WIDTH 0x1
+#define DRA7XX_CUSTEFUSE_DYNDEP_MASK (1 << 17)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_DSP2_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_CUSTEFUSE_STATDEP_SHIFT 17
+#define DRA7XX_CUSTEFUSE_STATDEP_WIDTH 0x1
+#define DRA7XX_CUSTEFUSE_STATDEP_MASK (1 << 17)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_CUSTOM_SHIFT 6
+#define DRA7XX_CUSTOM_WIDTH 0x2
+#define DRA7XX_CUSTOM_MASK (0x3 << 6)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR,
+ * CM_CLKSEL_DPLL_DSP, CM_CLKSEL_DPLL_EVE, CM_CLKSEL_DPLL_GMAC,
+ * CM_CLKSEL_DPLL_GPU, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU,
+ * CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_USB
+ */
+#define DRA7XX_DCC_EN_SHIFT 22
+#define DRA7XX_DCC_EN_WIDTH 0x1
+#define DRA7XX_DCC_EN_MASK (1 << 22)
+
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_DDR, CM_SSC_DELTAMSTEP_DPLL_DSP,
+ * CM_SSC_DELTAMSTEP_DPLL_EVE, CM_SSC_DELTAMSTEP_DPLL_GMAC,
+ * CM_SSC_DELTAMSTEP_DPLL_GPU, CM_SSC_DELTAMSTEP_DPLL_IVA,
+ * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER
+ */
+#define DRA7XX_DELTAMSTEP_SHIFT 0
+#define DRA7XX_DELTAMSTEP_WIDTH 0x14
+#define DRA7XX_DELTAMSTEP_MASK (0xfffff << 0)
+
+/*
+ * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_PCIE_REF,
+ * CM_SSC_DELTAMSTEP_DPLL_USB
+ */
+#define DRA7XX_DELTAMSTEP_0_20_SHIFT 0
+#define DRA7XX_DELTAMSTEP_0_20_WIDTH 0x15
+#define DRA7XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
+
+/*
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDR,
+ * CM_DIV_M2_DPLL_DSP, CM_DIV_M2_DPLL_EVE, CM_DIV_M2_DPLL_GMAC,
+ * CM_DIV_M2_DPLL_GPU, CM_DIV_M2_DPLL_IVA, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_DDR, CM_DIV_M3_DPLL_DSP, CM_DIV_M3_DPLL_EVE,
+ * CM_DIV_M3_DPLL_GMAC, CM_DIV_M3_DPLL_GPU, CM_DIV_M3_DPLL_IVA,
+ * CM_DIV_M3_DPLL_PER
+ */
+#define DRA7XX_DIVHS_SHIFT 0
+#define DRA7XX_DIVHS_WIDTH 0x5
+#define DRA7XX_DIVHS_MASK (0x1f << 0)
+
+/*
+ * Renamed from DIVHS Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_DDR,
+ * CM_DIV_H11_DPLL_GMAC, CM_DIV_H11_DPLL_PER, CM_DIV_H12_DPLL_CORE,
+ * CM_DIV_H12_DPLL_GMAC, CM_DIV_H12_DPLL_PER, CM_DIV_H13_DPLL_CORE,
+ * CM_DIV_H13_DPLL_GMAC, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_GMAC, CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE,
+ * CM_DIV_H22_DPLL_CORE, CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
+ */
+#define DRA7XX_DIVHS_0_5_SHIFT 0
+#define DRA7XX_DIVHS_0_5_WIDTH 0x6
+#define DRA7XX_DIVHS_0_5_MASK (0x3f << 0)
+
+/*
+ * Renamed from DIVHS Used by CM_DIV_M2_APLL_PCIE, CM_DIV_M2_DPLL_PCIE_REF,
+ * CM_DIV_M2_DPLL_USB
+ */
+#define DRA7XX_DIVHS_0_6_SHIFT 0
+#define DRA7XX_DIVHS_0_6_WIDTH 0x7
+#define DRA7XX_DIVHS_0_6_MASK (0x7f << 0)
+
+/* Used by CM_DLL_CTRL */
+#define DRA7XX_DLL_OVERRIDE_SHIFT 0
+#define DRA7XX_DLL_OVERRIDE_WIDTH 0x1
+#define DRA7XX_DLL_OVERRIDE_MASK (1 << 0)
+
+/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_DLL_OVERRIDE_2_2_SHIFT 2
+#define DRA7XX_DLL_OVERRIDE_2_2_WIDTH 0x1
+#define DRA7XX_DLL_OVERRIDE_2_2_MASK (1 << 2)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_DLL_RESET_SHIFT 3
+#define DRA7XX_DLL_RESET_WIDTH 0x1
+#define DRA7XX_DLL_RESET_MASK (1 << 3)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR,
+ * CM_CLKSEL_DPLL_DSP, CM_CLKSEL_DPLL_EVE, CM_CLKSEL_DPLL_GMAC,
+ * CM_CLKSEL_DPLL_GPU, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU,
+ * CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_USB
+ */
+#define DRA7XX_DPLL_BYP_CLKSEL_SHIFT 23
+#define DRA7XX_DPLL_BYP_CLKSEL_WIDTH 0x1
+#define DRA7XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
+
+/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_GMAC, CM_CLKSEL_DPLL_GPU */
+#define DRA7XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
+#define DRA7XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
+#define DRA7XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define DRA7XX_DPLL_CORE_H12_DIV_SHIFT 2
+#define DRA7XX_DPLL_CORE_H12_DIV_WIDTH 0x6
+#define DRA7XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_DPLL_DDR_DPLL_EN_SHIFT 16
+#define DRA7XX_DPLL_DDR_DPLL_EN_WIDTH 0x3
+#define DRA7XX_DPLL_DDR_DPLL_EN_MASK (0x7 << 16)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_DPLL_DDR_M2_DIV_SHIFT 11
+#define DRA7XX_DPLL_DDR_M2_DIV_WIDTH 0x5
+#define DRA7XX_DPLL_DDR_M2_DIV_MASK (0x1f << 11)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR,
+ * CM_CLKSEL_DPLL_DSP, CM_CLKSEL_DPLL_EVE, CM_CLKSEL_DPLL_GMAC,
+ * CM_CLKSEL_DPLL_GPU, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU,
+ * CM_CLKSEL_DPLL_PER
+ */
+#define DRA7XX_DPLL_DIV_SHIFT 0
+#define DRA7XX_DPLL_DIV_WIDTH 0x7
+#define DRA7XX_DPLL_DIV_MASK (0x7f << 0)
+
+/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_USB */
+#define DRA7XX_DPLL_DIV_PCIE_REF_SHIFT 0
+#define DRA7XX_DPLL_DIV_PCIE_REF_WIDTH 0x8
+#define DRA7XX_DPLL_DIV_PCIE_REF_MASK (0xff << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PER
+ */
+#define DRA7XX_DPLL_DRIFTGUARD_EN_SHIFT 8
+#define DRA7XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1
+#define DRA7XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PCIE_REF, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB
+ */
+#define DRA7XX_DPLL_EN_SHIFT 0
+#define DRA7XX_DPLL_EN_WIDTH 0x3
+#define DRA7XX_DPLL_EN_MASK (0x7 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PER
+ */
+#define DRA7XX_DPLL_LPMODE_EN_SHIFT 10
+#define DRA7XX_DPLL_LPMODE_EN_WIDTH 0x1
+#define DRA7XX_DPLL_LPMODE_EN_MASK (1 << 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR,
+ * CM_CLKSEL_DPLL_DSP, CM_CLKSEL_DPLL_EVE, CM_CLKSEL_DPLL_GMAC,
+ * CM_CLKSEL_DPLL_GPU, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU,
+ * CM_CLKSEL_DPLL_PER
+ */
+#define DRA7XX_DPLL_MULT_SHIFT 8
+#define DRA7XX_DPLL_MULT_WIDTH 0xb
+#define DRA7XX_DPLL_MULT_MASK (0x7ff << 8)
+
+/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_USB */
+#define DRA7XX_DPLL_MULT_8_19_SHIFT 8
+#define DRA7XX_DPLL_MULT_8_19_WIDTH 0xc
+#define DRA7XX_DPLL_MULT_8_19_MASK (0xfff << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PER
+ */
+#define DRA7XX_DPLL_REGM4XEN_SHIFT 11
+#define DRA7XX_DPLL_REGM4XEN_WIDTH 0x1
+#define DRA7XX_DPLL_REGM4XEN_MASK (1 << 11)
+
+/* Used by CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_USB */
+#define DRA7XX_DPLL_SD_DIV_SHIFT 24
+#define DRA7XX_DPLL_SD_DIV_WIDTH 0x8
+#define DRA7XX_DPLL_SD_DIV_MASK (0xff << 24)
+
+/* Used by CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_USB */
+#define DRA7XX_DPLL_SELFREQDCO_SHIFT 21
+#define DRA7XX_DPLL_SELFREQDCO_WIDTH 0x1
+#define DRA7XX_DPLL_SELFREQDCO_MASK (1 << 21)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PCIE_REF, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB
+ */
+#define DRA7XX_DPLL_SSC_ACK_SHIFT 13
+#define DRA7XX_DPLL_SSC_ACK_WIDTH 0x1
+#define DRA7XX_DPLL_SSC_ACK_MASK (1 << 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PCIE_REF, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB
+ */
+#define DRA7XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
+#define DRA7XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
+#define DRA7XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PCIE_REF, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB
+ */
+#define DRA7XX_DPLL_SSC_EN_SHIFT 12
+#define DRA7XX_DPLL_SSC_EN_WIDTH 0x1
+#define DRA7XX_DPLL_SSC_EN_MASK (1 << 12)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_DSP1_DYNDEP_SHIFT 1
+#define DRA7XX_DSP1_DYNDEP_WIDTH 0x1
+#define DRA7XX_DSP1_DYNDEP_MASK (1 << 1)
+
+/*
+ * Used by CM_DSP2_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP,
+ * CM_L4PER2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_DSP1_STATDEP_SHIFT 1
+#define DRA7XX_DSP1_STATDEP_WIDTH 0x1
+#define DRA7XX_DSP1_STATDEP_MASK (1 << 1)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_DSP2_DYNDEP_SHIFT 20
+#define DRA7XX_DSP2_DYNDEP_WIDTH 0x1
+#define DRA7XX_DSP2_DYNDEP_MASK (1 << 20)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP,
+ * CM_L4PER2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_DSP2_STATDEP_SHIFT 18
+#define DRA7XX_DSP2_STATDEP_WIDTH 0x1
+#define DRA7XX_DSP2_STATDEP_MASK (1 << 18)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define DRA7XX_DSS_DYNDEP_SHIFT 8
+#define DRA7XX_DSS_DYNDEP_WIDTH 0x1
+#define DRA7XX_DSS_DYNDEP_MASK (1 << 8)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_DSS_STATDEP_SHIFT 8
+#define DRA7XX_DSS_STATDEP_WIDTH 0x1
+#define DRA7XX_DSS_STATDEP_MASK (1 << 8)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP */
+#define DRA7XX_EMIF_DYNDEP_SHIFT 4
+#define DRA7XX_EMIF_DYNDEP_WIDTH 0x1
+#define DRA7XX_EMIF_DYNDEP_MASK (1 << 4)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_DSS_STATICDEP, CM_EVE1_STATICDEP, CM_EVE2_STATICDEP,
+ * CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_GMAC_STATICDEP, CM_GPU_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_IVA_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP, CM_VPE_STATICDEP
+ */
+#define DRA7XX_EMIF_STATDEP_SHIFT 4
+#define DRA7XX_EMIF_STATDEP_WIDTH 0x1
+#define DRA7XX_EMIF_STATDEP_MASK (1 << 4)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_EVE1_DYNDEP_SHIFT 28
+#define DRA7XX_EVE1_DYNDEP_WIDTH 0x1
+#define DRA7XX_EVE1_DYNDEP_MASK (1 << 28)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_EVE2_STATICDEP, CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_EVE1_STATDEP_SHIFT 19
+#define DRA7XX_EVE1_STATDEP_WIDTH 0x1
+#define DRA7XX_EVE1_STATDEP_MASK (1 << 19)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_EVE2_DYNDEP_SHIFT 29
+#define DRA7XX_EVE2_DYNDEP_WIDTH 0x1
+#define DRA7XX_EVE2_DYNDEP_MASK (1 << 29)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_EVE1_STATICDEP, CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_EVE2_STATDEP_SHIFT 20
+#define DRA7XX_EVE2_STATDEP_WIDTH 0x1
+#define DRA7XX_EVE2_STATDEP_MASK (1 << 20)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_EVE3_DYNDEP_SHIFT 30
+#define DRA7XX_EVE3_DYNDEP_WIDTH 0x1
+#define DRA7XX_EVE3_DYNDEP_MASK (1 << 30)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_EVE1_STATICDEP, CM_EVE2_STATICDEP, CM_EVE4_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_EVE3_STATDEP_SHIFT 21
+#define DRA7XX_EVE3_STATDEP_WIDTH 0x1
+#define DRA7XX_EVE3_STATDEP_MASK (1 << 21)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_EVE4_DYNDEP_SHIFT 31
+#define DRA7XX_EVE4_DYNDEP_WIDTH 0x1
+#define DRA7XX_EVE4_DYNDEP_MASK (1 << 31)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_EVE1_STATICDEP, CM_EVE2_STATICDEP, CM_EVE3_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_EVE4_STATDEP_SHIFT 22
+#define DRA7XX_EVE4_STATDEP_WIDTH 0x1
+#define DRA7XX_EVE4_STATDEP_MASK (1 << 22)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_FREQ_UPDATE_SHIFT 0
+#define DRA7XX_FREQ_UPDATE_WIDTH 0x1
+#define DRA7XX_FREQ_UPDATE_MASK (1 << 0)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_FUNC_SHIFT 16
+#define DRA7XX_FUNC_WIDTH 0xc
+#define DRA7XX_FUNC_MASK (0xfff << 16)
+
+/* Used by CM_L4PER2_DYNAMICDEP */
+#define DRA7XX_GMAC_DYNDEP_SHIFT 22
+#define DRA7XX_GMAC_DYNDEP_WIDTH 0x1
+#define DRA7XX_GMAC_DYNDEP_MASK (1 << 22)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_GMAC_STATDEP_SHIFT 25
+#define DRA7XX_GMAC_STATDEP_WIDTH 0x1
+#define DRA7XX_GMAC_STATDEP_MASK (1 << 25)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define DRA7XX_GPMC_FREQ_UPDATE_SHIFT 0
+#define DRA7XX_GPMC_FREQ_UPDATE_WIDTH 0x1
+#define DRA7XX_GPMC_FREQ_UPDATE_MASK (1 << 0)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_GPU_DYNDEP_SHIFT 10
+#define DRA7XX_GPU_DYNDEP_WIDTH 0x1
+#define DRA7XX_GPU_DYNDEP_MASK (1 << 10)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_DSP2_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_GPU_STATDEP_SHIFT 10
+#define DRA7XX_GPU_STATDEP_WIDTH 0x1
+#define DRA7XX_GPU_STATDEP_MASK (1 << 10)
+
+/*
+ * Used by CM_ATL_ATL_CLKCTRL, CM_CAM_CSI1_CLKCTRL, CM_CAM_CSI2_CLKCTRL,
+ * CM_CAM_LVDSRX_CLKCTRL, CM_CAM_VIP1_CLKCTRL, CM_CAM_VIP2_CLKCTRL,
+ * CM_CAM_VIP3_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL, CM_COREAON_SMARTREFLEX_GPU_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP1_DSP1_CLKCTRL, CM_DSP2_DSP2_CLKCTRL, CM_DSS_BB2D_CLKCTRL,
+ * CM_DSS_DSS_CLKCTRL, CM_DSS_SDVENC_CLKCTRL, CM_EMIF_DMM_CLKCTRL,
+ * CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, CM_EMIF_EMIF_OCP_FW_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_EVE1_EVE1_CLKCTRL,
+ * CM_EVE2_EVE2_CLKCTRL, CM_EVE3_EVE3_CLKCTRL, CM_EVE4_EVE4_CLKCTRL,
+ * CM_GMAC_GMAC_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU1_IPU1_CLKCTRL,
+ * CM_IPU2_IPU2_CLKCTRL, CM_IPU_I2C5_CLKCTRL, CM_IPU_MCASP1_CLKCTRL,
+ * CM_IPU_TIMER5_CLKCTRL, CM_IPU_TIMER6_CLKCTRL, CM_IPU_TIMER7_CLKCTRL,
+ * CM_IPU_TIMER8_CLKCTRL, CM_IPU_UART6_CLKCTRL, CM_IVA_IVA_CLKCTRL,
+ * CM_IVA_SL2_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
+ * CM_L3INIT_MLB_SS_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_USB_OTG_SS1_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS2_CLKCTRL, CM_L3INIT_USB_OTG_SS3_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS4_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_2_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_GPMC_CLKCTRL, CM_L3MAIN1_L3_MAIN_1_CLKCTRL,
+ * CM_L3MAIN1_MMU_EDMA_CLKCTRL, CM_L3MAIN1_OCMC_RAM1_CLKCTRL,
+ * CM_L3MAIN1_OCMC_RAM2_CLKCTRL, CM_L3MAIN1_OCMC_RAM3_CLKCTRL,
+ * CM_L3MAIN1_OCMC_ROM_CLKCTRL, CM_L3MAIN1_SPARE_CME_CLKCTRL,
+ * CM_L3MAIN1_SPARE_HDMI_CLKCTRL, CM_L3MAIN1_SPARE_ICM_CLKCTRL,
+ * CM_L3MAIN1_SPARE_IVA2_CLKCTRL, CM_L3MAIN1_SPARE_SATA2_CLKCTRL,
+ * CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL, CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL,
+ * CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL, CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL,
+ * CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL, CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL,
+ * CM_L3MAIN1_TPCC_CLKCTRL, CM_L3MAIN1_TPTC1_CLKCTRL, CM_L3MAIN1_TPTC2_CLKCTRL,
+ * CM_L3MAIN1_VCP1_CLKCTRL, CM_L3MAIN1_VCP2_CLKCTRL,
+ * CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX10_CLKCTRL, CM_L4CFG_MAILBOX11_CLKCTRL,
+ * CM_L4CFG_MAILBOX12_CLKCTRL, CM_L4CFG_MAILBOX13_CLKCTRL,
+ * CM_L4CFG_MAILBOX1_CLKCTRL, CM_L4CFG_MAILBOX2_CLKCTRL,
+ * CM_L4CFG_MAILBOX3_CLKCTRL, CM_L4CFG_MAILBOX4_CLKCTRL,
+ * CM_L4CFG_MAILBOX5_CLKCTRL, CM_L4CFG_MAILBOX6_CLKCTRL,
+ * CM_L4CFG_MAILBOX7_CLKCTRL, CM_L4CFG_MAILBOX8_CLKCTRL,
+ * CM_L4CFG_MAILBOX9_CLKCTRL, CM_L4CFG_OCP2SCP2_CLKCTRL,
+ * CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL,
+ * CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL,
+ * CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL, CM_L4CFG_SPINLOCK_CLKCTRL,
+ * CM_L4PER2_DCAN2_CLKCTRL, CM_L4PER2_L4_PER2_CLKCTRL,
+ * CM_L4PER2_MCASP2_CLKCTRL, CM_L4PER2_MCASP3_CLKCTRL,
+ * CM_L4PER2_MCASP4_CLKCTRL, CM_L4PER2_MCASP5_CLKCTRL,
+ * CM_L4PER2_MCASP6_CLKCTRL, CM_L4PER2_MCASP7_CLKCTRL,
+ * CM_L4PER2_MCASP8_CLKCTRL, CM_L4PER2_PRUSS1_CLKCTRL,
+ * CM_L4PER2_PRUSS2_CLKCTRL, CM_L4PER2_PWMSS1_CLKCTRL,
+ * CM_L4PER2_PWMSS2_CLKCTRL, CM_L4PER2_PWMSS3_CLKCTRL, CM_L4PER2_QSPI_CLKCTRL,
+ * CM_L4PER2_UART7_CLKCTRL, CM_L4PER2_UART8_CLKCTRL, CM_L4PER2_UART9_CLKCTRL,
+ * CM_L4PER3_L4_PER3_CLKCTRL, CM_L4PER3_TIMER13_CLKCTRL,
+ * CM_L4PER3_TIMER14_CLKCTRL, CM_L4PER3_TIMER15_CLKCTRL,
+ * CM_L4PER3_TIMER16_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_L4_PER1_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL,
+ * CM_L4PER_TIMER10_CLKCTRL, CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL,
+ * CM_L4PER_TIMER3_CLKCTRL, CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4PER_UART5_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L4SEC_SHA2MD52_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_RTC_RTCSS_CLKCTRL, CM_VPE_VPE_CLKCTRL,
+ * CM_WKUPAON_ADC_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_DCAN1_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_SPARE_SAFETY1_CLKCTRL, CM_WKUPAON_SPARE_SAFETY2_CLKCTRL,
+ * CM_WKUPAON_SPARE_SAFETY3_CLKCTRL, CM_WKUPAON_SPARE_SAFETY4_CLKCTRL,
+ * CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL, CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_UART10_CLKCTRL, CM_WKUPAON_WD_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define DRA7XX_IDLEST_SHIFT 16
+#define DRA7XX_IDLEST_WIDTH 0x2
+#define DRA7XX_IDLEST_MASK (0x3 << 16)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_INPSEL_SHIFT 3
+#define DRA7XX_INPSEL_WIDTH 0x3
+#define DRA7XX_INPSEL_MASK (0x7 << 3)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_IPU1_DYNDEP_SHIFT 18
+#define DRA7XX_IPU1_DYNDEP_WIDTH 0x1
+#define DRA7XX_IPU1_DYNDEP_MASK (1 << 18)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_L4PER2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_IPU1_STATDEP_SHIFT 23
+#define DRA7XX_IPU1_STATDEP_WIDTH 0x1
+#define DRA7XX_IPU1_STATDEP_MASK (1 << 23)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_IPU2_DYNDEP_SHIFT 0
+#define DRA7XX_IPU2_DYNDEP_WIDTH 0x1
+#define DRA7XX_IPU2_DYNDEP_MASK (1 << 0)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_L4PER2_STATICDEP, CM_MPU_STATICDEP
+ */
+#define DRA7XX_IPU2_STATDEP_SHIFT 0
+#define DRA7XX_IPU2_STATDEP_WIDTH 0x1
+#define DRA7XX_IPU2_STATDEP_MASK (1 << 0)
+
+/*
+ * Used by CM_L3MAIN1_DYNAMICDEP, CM_L4PER2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP
+ */
+#define DRA7XX_IPU_DYNDEP_SHIFT 3
+#define DRA7XX_IPU_DYNDEP_WIDTH 0x1
+#define DRA7XX_IPU_DYNDEP_MASK (1 << 3)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_IPU_STATDEP_SHIFT 24
+#define DRA7XX_IPU_STATDEP_WIDTH 0x1
+#define DRA7XX_IPU_STATDEP_MASK (1 << 24)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_IVA_DYNDEP_SHIFT 2
+#define DRA7XX_IVA_DYNDEP_WIDTH 0x1
+#define DRA7XX_IVA_DYNDEP_MASK (1 << 2)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_DSS_STATICDEP, CM_EVE1_STATICDEP, CM_EVE2_STATICDEP,
+ * CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_GPU_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_IVA_STATDEP_SHIFT 2
+#define DRA7XX_IVA_STATDEP_WIDTH 0x1
+#define DRA7XX_IVA_STATDEP_MASK (1 << 2)
+
+/*
+ * Used by CM_L4CFG_DYNAMICDEP, CM_L4PER2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP
+ */
+#define DRA7XX_L3INIT_DYNDEP_SHIFT 7
+#define DRA7XX_L3INIT_DYNDEP_WIDTH 0x1
+#define DRA7XX_L3INIT_DYNDEP_MASK (1 << 7)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L3INIT_STATDEP_SHIFT 7
+#define DRA7XX_L3INIT_STATDEP_WIDTH 0x1
+#define DRA7XX_L3INIT_STATDEP_MASK (1 << 7)
+
+/*
+ * Used by CM_DMA_DYNAMICDEP, CM_DSP1_DYNAMICDEP, CM_DSP2_DYNAMICDEP,
+ * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GMAC_DYNAMICDEP,
+ * CM_IPU1_DYNAMICDEP, CM_IPU2_DYNAMICDEP, CM_IVA_DYNAMICDEP,
+ * CM_L3INIT_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER3_DYNAMICDEP,
+ * CM_L4SEC_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define DRA7XX_L3MAIN1_DYNDEP_SHIFT 5
+#define DRA7XX_L3MAIN1_DYNDEP_WIDTH 0x1
+#define DRA7XX_L3MAIN1_DYNDEP_MASK (1 << 5)
+
+/* Renamed from L3MAIN1_DYNDEP Used by CM_GPU_DYNAMICDEP */
+#define DRA7XX_L3MAIN1_DYNDEP_6_6_SHIFT 6
+#define DRA7XX_L3MAIN1_DYNDEP_6_6_WIDTH 0x1
+#define DRA7XX_L3MAIN1_DYNDEP_6_6_MASK (1 << 6)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_DSS_STATICDEP, CM_EVE1_STATICDEP, CM_EVE2_STATICDEP,
+ * CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_GMAC_STATICDEP, CM_GPU_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_IVA_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_L4PER2_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_VPE_STATICDEP
+ */
+#define DRA7XX_L3MAIN1_STATDEP_SHIFT 5
+#define DRA7XX_L3MAIN1_STATDEP_WIDTH 0x1
+#define DRA7XX_L3MAIN1_STATDEP_MASK (1 << 5)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP, CM_L4PER2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP */
+#define DRA7XX_L4CFG_DYNDEP_SHIFT 12
+#define DRA7XX_L4CFG_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4CFG_DYNDEP_MASK (1 << 12)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L4CFG_STATDEP_SHIFT 12
+#define DRA7XX_L4CFG_STATDEP_WIDTH 0x1
+#define DRA7XX_L4CFG_STATDEP_MASK (1 << 12)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_L4PER2_DYNDEP_SHIFT 22
+#define DRA7XX_L4PER2_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4PER2_DYNDEP_MASK (1 << 22)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_GMAC_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP,
+ * CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L4PER2_STATDEP_SHIFT 26
+#define DRA7XX_L4PER2_STATDEP_WIDTH 0x1
+#define DRA7XX_L4PER2_STATDEP_MASK (1 << 26)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_L4PER3_DYNDEP_SHIFT 23
+#define DRA7XX_L4PER3_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4PER3_DYNDEP_MASK (1 << 23)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP, CM_VPE_STATICDEP
+ */
+#define DRA7XX_L4PER3_STATDEP_SHIFT 27
+#define DRA7XX_L4PER3_STATDEP_WIDTH 0x1
+#define DRA7XX_L4PER3_STATDEP_MASK (1 << 27)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_L4PER_DYNDEP_SHIFT 13
+#define DRA7XX_L4PER_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4PER_DYNDEP_MASK (1 << 13)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L4PER_STATDEP_SHIFT 13
+#define DRA7XX_L4PER_STATDEP_WIDTH 0x1
+#define DRA7XX_L4PER_STATDEP_MASK (1 << 13)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define DRA7XX_L4SEC_DYNDEP_SHIFT 14
+#define DRA7XX_L4SEC_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4SEC_DYNDEP_MASK (1 << 14)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ * CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L4SEC_STATDEP_SHIFT 14
+#define DRA7XX_L4SEC_STATDEP_WIDTH 0x1
+#define DRA7XX_L4SEC_STATDEP_MASK (1 << 14)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_MODE_SHIFT 2
+#define DRA7XX_MODE_WIDTH 0x1
+#define DRA7XX_MODE_MASK (1 << 2)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_MODE_SELECT_SHIFT 0
+#define DRA7XX_MODE_SELECT_WIDTH 0x2
+#define DRA7XX_MODE_SELECT_MASK (0x3 << 0)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_DDR, CM_SSC_MODFREQDIV_DPLL_DSP,
+ * CM_SSC_MODFREQDIV_DPLL_EVE, CM_SSC_MODFREQDIV_DPLL_GMAC,
+ * CM_SSC_MODFREQDIV_DPLL_GPU, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PCIE_REF,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define DRA7XX_MODFREQDIV_EXPONENT_SHIFT 8
+#define DRA7XX_MODFREQDIV_EXPONENT_WIDTH 0x3
+#define DRA7XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_DDR, CM_SSC_MODFREQDIV_DPLL_DSP,
+ * CM_SSC_MODFREQDIV_DPLL_EVE, CM_SSC_MODFREQDIV_DPLL_GMAC,
+ * CM_SSC_MODFREQDIV_DPLL_GPU, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PCIE_REF,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define DRA7XX_MODFREQDIV_MANTISSA_SHIFT 0
+#define DRA7XX_MODFREQDIV_MANTISSA_WIDTH 0x7
+#define DRA7XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
+
+/*
+ * Used by CM_ATL_ATL_CLKCTRL, CM_CAM_CSI1_CLKCTRL, CM_CAM_CSI2_CLKCTRL,
+ * CM_CAM_LVDSRX_CLKCTRL, CM_CAM_VIP1_CLKCTRL, CM_CAM_VIP2_CLKCTRL,
+ * CM_CAM_VIP3_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL, CM_COREAON_SMARTREFLEX_GPU_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP1_DSP1_CLKCTRL, CM_DSP2_DSP2_CLKCTRL, CM_DSS_BB2D_CLKCTRL,
+ * CM_DSS_DSS_CLKCTRL, CM_DSS_SDVENC_CLKCTRL, CM_EMIF_DMM_CLKCTRL,
+ * CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, CM_EMIF_EMIF_OCP_FW_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_EVE1_EVE1_CLKCTRL,
+ * CM_EVE2_EVE2_CLKCTRL, CM_EVE3_EVE3_CLKCTRL, CM_EVE4_EVE4_CLKCTRL,
+ * CM_GMAC_GMAC_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU1_IPU1_CLKCTRL,
+ * CM_IPU2_IPU2_CLKCTRL, CM_IPU_I2C5_CLKCTRL, CM_IPU_MCASP1_CLKCTRL,
+ * CM_IPU_TIMER5_CLKCTRL, CM_IPU_TIMER6_CLKCTRL, CM_IPU_TIMER7_CLKCTRL,
+ * CM_IPU_TIMER8_CLKCTRL, CM_IPU_UART6_CLKCTRL, CM_IVA_IVA_CLKCTRL,
+ * CM_IVA_SL2_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
+ * CM_L3INIT_MLB_SS_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_USB_OTG_SS1_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS2_CLKCTRL, CM_L3INIT_USB_OTG_SS3_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS4_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_2_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_GPMC_CLKCTRL, CM_L3MAIN1_L3_MAIN_1_CLKCTRL,
+ * CM_L3MAIN1_MMU_EDMA_CLKCTRL, CM_L3MAIN1_OCMC_RAM1_CLKCTRL,
+ * CM_L3MAIN1_OCMC_RAM2_CLKCTRL, CM_L3MAIN1_OCMC_RAM3_CLKCTRL,
+ * CM_L3MAIN1_OCMC_ROM_CLKCTRL, CM_L3MAIN1_SPARE_CME_CLKCTRL,
+ * CM_L3MAIN1_SPARE_HDMI_CLKCTRL, CM_L3MAIN1_SPARE_ICM_CLKCTRL,
+ * CM_L3MAIN1_SPARE_IVA2_CLKCTRL, CM_L3MAIN1_SPARE_SATA2_CLKCTRL,
+ * CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL, CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL,
+ * CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL, CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL,
+ * CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL, CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL,
+ * CM_L3MAIN1_TPCC_CLKCTRL, CM_L3MAIN1_TPTC1_CLKCTRL, CM_L3MAIN1_TPTC2_CLKCTRL,
+ * CM_L3MAIN1_VCP1_CLKCTRL, CM_L3MAIN1_VCP2_CLKCTRL,
+ * CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX10_CLKCTRL, CM_L4CFG_MAILBOX11_CLKCTRL,
+ * CM_L4CFG_MAILBOX12_CLKCTRL, CM_L4CFG_MAILBOX13_CLKCTRL,
+ * CM_L4CFG_MAILBOX1_CLKCTRL, CM_L4CFG_MAILBOX2_CLKCTRL,
+ * CM_L4CFG_MAILBOX3_CLKCTRL, CM_L4CFG_MAILBOX4_CLKCTRL,
+ * CM_L4CFG_MAILBOX5_CLKCTRL, CM_L4CFG_MAILBOX6_CLKCTRL,
+ * CM_L4CFG_MAILBOX7_CLKCTRL, CM_L4CFG_MAILBOX8_CLKCTRL,
+ * CM_L4CFG_MAILBOX9_CLKCTRL, CM_L4CFG_OCP2SCP2_CLKCTRL,
+ * CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL,
+ * CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL,
+ * CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL, CM_L4CFG_SPINLOCK_CLKCTRL,
+ * CM_L4PER2_DCAN2_CLKCTRL, CM_L4PER2_L4_PER2_CLKCTRL,
+ * CM_L4PER2_MCASP2_CLKCTRL, CM_L4PER2_MCASP3_CLKCTRL,
+ * CM_L4PER2_MCASP4_CLKCTRL, CM_L4PER2_MCASP5_CLKCTRL,
+ * CM_L4PER2_MCASP6_CLKCTRL, CM_L4PER2_MCASP7_CLKCTRL,
+ * CM_L4PER2_MCASP8_CLKCTRL, CM_L4PER2_PRUSS1_CLKCTRL,
+ * CM_L4PER2_PRUSS2_CLKCTRL, CM_L4PER2_PWMSS1_CLKCTRL,
+ * CM_L4PER2_PWMSS2_CLKCTRL, CM_L4PER2_PWMSS3_CLKCTRL, CM_L4PER2_QSPI_CLKCTRL,
+ * CM_L4PER2_UART7_CLKCTRL, CM_L4PER2_UART8_CLKCTRL, CM_L4PER2_UART9_CLKCTRL,
+ * CM_L4PER3_L4_PER3_CLKCTRL, CM_L4PER3_TIMER13_CLKCTRL,
+ * CM_L4PER3_TIMER14_CLKCTRL, CM_L4PER3_TIMER15_CLKCTRL,
+ * CM_L4PER3_TIMER16_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_L4_PER1_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL,
+ * CM_L4PER_TIMER10_CLKCTRL, CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL,
+ * CM_L4PER_TIMER3_CLKCTRL, CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4PER_UART5_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L4SEC_SHA2MD52_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_RTC_RTCSS_CLKCTRL, CM_VPE_VPE_CLKCTRL,
+ * CM_WKUPAON_ADC_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_DCAN1_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_SPARE_SAFETY1_CLKCTRL, CM_WKUPAON_SPARE_SAFETY2_CLKCTRL,
+ * CM_WKUPAON_SPARE_SAFETY3_CLKCTRL, CM_WKUPAON_SPARE_SAFETY4_CLKCTRL,
+ * CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL, CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_UART10_CLKCTRL, CM_WKUPAON_WD_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define DRA7XX_MODULEMODE_SHIFT 0
+#define DRA7XX_MODULEMODE_WIDTH 0x2
+#define DRA7XX_MODULEMODE_MASK (0x3 << 0)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define DRA7XX_MPU_DYNDEP_SHIFT 19
+#define DRA7XX_MPU_DYNDEP_WIDTH 0x1
+#define DRA7XX_MPU_DYNDEP_MASK (1 << 19)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11
+#define DRA7XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9
+#define DRA7XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
+
+/* Used by CM_COREAON_DUMMY_MODULE4_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_ABE_GICLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_ABE_GICLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_ABE_GICLK_MASK (1 << 8)
+
+/*
+ * Used by CM_COREAON_USB_PHY1_CORE_CLKCTRL, CM_COREAON_USB_PHY2_CORE_CLKCTRL,
+ * CM_COREAON_USB_PHY3_CORE_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL
+ */
+#define DRA7XX_OPTFCLKEN_CLK32K_SHIFT 8
+#define DRA7XX_OPTFCLKEN_CLK32K_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_CLK32K_MASK (1 << 8)
+
+/* Used by CM_COREAON_DUMMY_MODULE1_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX1_CLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX1_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX1_CLK_MASK (1 << 8)
+
+/* Used by CM_COREAON_DUMMY_MODULE2_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX2_CLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX2_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX2_CLK_MASK (1 << 8)
+
+/*
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
+ * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
+ */
+#define DRA7XX_OPTFCLKEN_DBCLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_DBCLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_DBCLK_MASK (1 << 8)
+
+/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_DLL_CLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_DSSCLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_DSSCLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_DSSCLK_MASK (1 << 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_HDMI_CLK_SHIFT 10
+#define DRA7XX_OPTFCLKEN_HDMI_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_HDMI_CLK_MASK (1 << 10)
+
+/* Used by CM_COREAON_DUMMY_MODULE3_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_L3INIT_60M_GFCLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_L3INIT_60M_GFCLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_L3INIT_60M_GFCLK_MASK (1 << 8)
+
+/* Used by CM_L3INIT_USB_OTG_SS1_CLKCTRL, CM_L3INIT_USB_OTG_SS2_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT 8
+#define DRA7XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8)
+
+/* Used by CM_L3INIT_SATA_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_REF_CLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_REF_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_REF_CLK_MASK (1 << 8)
+
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_SCRM_CORE_SHIFT 8
+#define DRA7XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
+
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_SCRM_PER_SHIFT 9
+#define DRA7XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_VIDEO1_CLK_SHIFT 12
+#define DRA7XX_OPTFCLKEN_VIDEO1_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_VIDEO1_CLK_MASK (1 << 12)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_VIDEO2_CLK_SHIFT 13
+#define DRA7XX_OPTFCLKEN_VIDEO2_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_VIDEO2_CLK_MASK (1 << 13)
+
+/* Used by CM_CORE_AON_DEBUG_OUT */
+#define DRA7XX_OUTPUT_SHIFT 0
+#define DRA7XX_OUTPUT_WIDTH 0x20
+#define DRA7XX_OUTPUT_MASK (0xffffffff << 0)
+
+/* Used by CM_CLKSEL_ABE */
+#define DRA7XX_PAD_CLKS_GATE_SHIFT 8
+#define DRA7XX_PAD_CLKS_GATE_WIDTH 0x1
+#define DRA7XX_PAD_CLKS_GATE_MASK (1 << 8)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_PCIE_DYNDEP_SHIFT 21
+#define DRA7XX_PCIE_DYNDEP_WIDTH 0x1
+#define DRA7XX_PCIE_DYNDEP_MASK (1 << 21)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP
+ */
+#define DRA7XX_PCIE_STATDEP_SHIFT 29
+#define DRA7XX_PCIE_STATDEP_WIDTH 0x1
+#define DRA7XX_PCIE_STATDEP_MASK (1 << 29)
+
+/* Used by CM_RESTORE_ST */
+#define DRA7XX_PHASE1_COMPLETED_SHIFT 0
+#define DRA7XX_PHASE1_COMPLETED_WIDTH 0x1
+#define DRA7XX_PHASE1_COMPLETED_MASK (1 << 0)
+
+/* Used by CM_RESTORE_ST */
+#define DRA7XX_PHASE2A_COMPLETED_SHIFT 1
+#define DRA7XX_PHASE2A_COMPLETED_WIDTH 0x1
+#define DRA7XX_PHASE2A_COMPLETED_MASK (1 << 1)
+
+/* Used by CM_RESTORE_ST */
+#define DRA7XX_PHASE2B_COMPLETED_SHIFT 2
+#define DRA7XX_PHASE2B_COMPLETED_WIDTH 0x1
+#define DRA7XX_PHASE2B_COMPLETED_MASK (1 << 2)
+
+/* Used by CM_DYN_DEP_PRESCAL */
+#define DRA7XX_PRESCAL_SHIFT 0
+#define DRA7XX_PRESCAL_WIDTH 0x6
+#define DRA7XX_PRESCAL_MASK (0x3f << 0)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_REFSEL_SHIFT 7
+#define DRA7XX_REFSEL_WIDTH 0x1
+#define DRA7XX_REFSEL_MASK (1 << 7)
+
+/* Used by CM_L4PER3_DYNAMICDEP */
+#define DRA7XX_RTC_DYNDEP_SHIFT 23
+#define DRA7XX_RTC_DYNDEP_WIDTH 0x1
+#define DRA7XX_RTC_DYNDEP_MASK (1 << 23)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_R_RTL_SHIFT 11
+#define DRA7XX_R_RTL_WIDTH 0x5
+#define DRA7XX_R_RTL_MASK (0x1f << 11)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_SCHEME_SHIFT 30
+#define DRA7XX_SCHEME_WIDTH 0x2
+#define DRA7XX_SCHEME_MASK (0x3 << 30)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define DRA7XX_SDMA_DYNDEP_SHIFT 11
+#define DRA7XX_SDMA_DYNDEP_WIDTH 0x1
+#define DRA7XX_SDMA_DYNDEP_MASK (1 << 11)
+
+/*
+ * Used by CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP,
+ * CM_PCIE_STATICDEP
+ */
+#define DRA7XX_SDMA_STATDEP_SHIFT 11
+#define DRA7XX_SDMA_STATDEP_WIDTH 0x1
+#define DRA7XX_SDMA_STATDEP_MASK (1 << 11)
+
+/* Used by CM_CORE_AON_DEBUG_CFG0 */
+#define DRA7XX_SEL0_SHIFT 0
+#define DRA7XX_SEL0_WIDTH 0xa
+#define DRA7XX_SEL0_MASK (0x3ff << 0)
+
+/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
+#define DRA7XX_SEL0_CORE_DEBUG_CFG_SHIFT 0
+#define DRA7XX_SEL0_CORE_DEBUG_CFG_WIDTH 0x8
+#define DRA7XX_SEL0_CORE_DEBUG_CFG_MASK (0xff << 0)
+
+/* Used by CM_CORE_AON_DEBUG_CFG1 */
+#define DRA7XX_SEL1_SHIFT 0
+#define DRA7XX_SEL1_WIDTH 0xa
+#define DRA7XX_SEL1_MASK (0x3ff << 0)
+
+/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
+#define DRA7XX_SEL1_CORE_DEBUG_CFG_SHIFT 8
+#define DRA7XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8
+#define DRA7XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8)
+
+/* Used by CM_CORE_AON_DEBUG_CFG2 */
+#define DRA7XX_SEL2_SHIFT 0
+#define DRA7XX_SEL2_WIDTH 0xa
+#define DRA7XX_SEL2_MASK (0x3ff << 0)
+
+/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
+#define DRA7XX_SEL2_CORE_DEBUG_CFG_SHIFT 16
+#define DRA7XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8
+#define DRA7XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16)
+
+/* Used by CM_CORE_AON_DEBUG_CFG3 */
+#define DRA7XX_SEL3_SHIFT 0
+#define DRA7XX_SEL3_WIDTH 0xa
+#define DRA7XX_SEL3_MASK (0x3ff << 0)
+
+/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
+#define DRA7XX_SEL3_24_31_SHIFT 24
+#define DRA7XX_SEL3_24_31_WIDTH 0x8
+#define DRA7XX_SEL3_24_31_MASK (0xff << 24)
+
+/* Used by CM_CLKSEL_ABE */
+#define DRA7XX_SLIMBUS1_CLK_GATE_SHIFT 10
+#define DRA7XX_SLIMBUS1_CLK_GATE_WIDTH 0x1
+#define DRA7XX_SLIMBUS1_CLK_GATE_MASK (1 << 10)
+
+/*
+ * Used by CM_CAM_CSI1_CLKCTRL, CM_CAM_CSI2_CLKCTRL, CM_CAM_VIP1_CLKCTRL,
+ * CM_CAM_VIP2_CLKCTRL, CM_CAM_VIP3_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP1_DSP1_CLKCTRL, CM_DSP2_DSP2_CLKCTRL, CM_DSS_BB2D_CLKCTRL,
+ * CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_EVE1_EVE1_CLKCTRL,
+ * CM_EVE2_EVE2_CLKCTRL, CM_EVE3_EVE3_CLKCTRL, CM_EVE4_EVE4_CLKCTRL,
+ * CM_GMAC_GMAC_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU1_IPU1_CLKCTRL,
+ * CM_IPU2_IPU2_CLKCTRL, CM_IVA_IVA_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
+ * CM_L3INIT_MLB_SS_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_USB_OTG_SS1_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS2_CLKCTRL, CM_L3INIT_USB_OTG_SS3_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS4_CLKCTRL, CM_L3MAIN1_TPTC1_CLKCTRL,
+ * CM_L3MAIN1_TPTC2_CLKCTRL, CM_L4PER2_PRUSS1_CLKCTRL,
+ * CM_L4PER2_PRUSS2_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_VPE_VPE_CLKCTRL
+ */
+#define DRA7XX_STBYST_SHIFT 18
+#define DRA7XX_STBYST_WIDTH 0x1
+#define DRA7XX_STBYST_MASK (1 << 18)
+
+/* Used by CM_IDLEST_APLL_PCIE */
+#define DRA7XX_ST_APLL_CLK_SHIFT 0
+#define DRA7XX_ST_APLL_CLK_WIDTH 0x1
+#define DRA7XX_ST_APLL_CLK_MASK (1 << 0)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR,
+ * CM_IDLEST_DPLL_DSP, CM_IDLEST_DPLL_EVE, CM_IDLEST_DPLL_GMAC,
+ * CM_IDLEST_DPLL_GPU, CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU,
+ * CM_IDLEST_DPLL_PCIE_REF, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_USB
+ */
+#define DRA7XX_ST_DPLL_CLK_SHIFT 0
+#define DRA7XX_ST_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_ST_DPLL_CLK_MASK (1 << 0)
+
+/* Used by CM_CLKDCOLDO_DPLL_USB */
+#define DRA7XX_ST_DPLL_CLKDCOLDO_SHIFT 9
+#define DRA7XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1
+#define DRA7XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR,
+ * CM_IDLEST_DPLL_DSP, CM_IDLEST_DPLL_EVE, CM_IDLEST_DPLL_GMAC,
+ * CM_IDLEST_DPLL_GPU, CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU,
+ * CM_IDLEST_DPLL_PCIE_REF, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_USB
+ */
+#define DRA7XX_ST_DPLL_INIT_SHIFT 4
+#define DRA7XX_ST_DPLL_INIT_WIDTH 0x1
+#define DRA7XX_ST_DPLL_INIT_MASK (1 << 4)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR,
+ * CM_IDLEST_DPLL_DSP, CM_IDLEST_DPLL_EVE, CM_IDLEST_DPLL_GMAC,
+ * CM_IDLEST_DPLL_GPU, CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU,
+ * CM_IDLEST_DPLL_PCIE_REF, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_USB
+ */
+#define DRA7XX_ST_DPLL_MODE_SHIFT 1
+#define DRA7XX_ST_DPLL_MODE_WIDTH 0x3
+#define DRA7XX_ST_DPLL_MODE_MASK (0x7 << 1)
+
+/* Used by CM_CLKSEL_SYS */
+#define DRA7XX_SYS_CLKSEL_SHIFT 0
+#define DRA7XX_SYS_CLKSEL_WIDTH 0x3
+#define DRA7XX_SYS_CLKSEL_MASK (0x7 << 0)
+
+/* Used by CM_L4PER3_DYNAMICDEP */
+#define DRA7XX_VPE_DYNDEP_SHIFT 31
+#define DRA7XX_VPE_DYNDEP_WIDTH 0x1
+#define DRA7XX_VPE_DYNDEP_MASK (1 << 31)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_VPE_STATDEP_SHIFT 28
+#define DRA7XX_VPE_STATDEP_WIDTH 0x1
+#define DRA7XX_VPE_STATDEP_MASK (1 << 28)
+
+/*
+ * Used by CM_DSP1_DYNAMICDEP, CM_DSP2_DYNAMICDEP, CM_EMU_DYNAMICDEP,
+ * CM_IPU1_DYNAMICDEP, CM_IPU2_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP, CM_L4PER2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define DRA7XX_WINDOWSIZE_SHIFT 24
+#define DRA7XX_WINDOWSIZE_WIDTH 0x4
+#define DRA7XX_WINDOWSIZE_MASK (0xf << 24)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_WKUPAON_DYNDEP_SHIFT 15
+#define DRA7XX_WKUPAON_DYNDEP_WIDTH 0x1
+#define DRA7XX_WKUPAON_DYNDEP_MASK (1 << 15)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define DRA7XX_WKUPAON_STATDEP_SHIFT 15
+#define DRA7XX_WKUPAON_STATDEP_WIDTH 0x1
+#define DRA7XX_WKUPAON_STATDEP_MASK (1 << 15)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_X_MAJOR_SHIFT 8
+#define DRA7XX_X_MAJOR_WIDTH 0x3
+#define DRA7XX_X_MAJOR_MASK (0x7 << 8)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_Y_MINOR_SHIFT 0
+#define DRA7XX_Y_MINOR_WIDTH 0x6
+#define DRA7XX_Y_MINOR_MASK (0x3f << 0)
+#endif
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
--- /dev/null
@@ -0,0 +1,326 @@
+/*
+ * DRA7xx CM1 instance offset macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
+
+/* CM1 base address */
+#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
+
+#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
+ OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
+
+/* CM_CORE_AON instances */
+#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
+#define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
+#define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
+#define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
+#define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
+#define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
+#define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
+#define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
+#define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
+#define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700
+#define DRA7XX_CM_CORE_AON_RTC_INST 0x0740
+#define DRA7XX_CM_CORE_AON_VPE_INST 0x0760
+#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00
+#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00
+
+/* CM_CORE_AON clockdomain register offsets (from instance start) */
+#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040
+#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000
+
+/* CM_CORE_AON */
+
+/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
+#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000
+#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
+#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc
+
+/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
+#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000
+#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
+#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008
+#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
+#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010
+#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
+#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
+#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
+#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
+#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
+#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
+#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
+#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
+#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
+#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
+#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
+#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
+#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
+#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
+#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
+#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
+#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
+#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
+#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
+#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
+#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
+#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
+#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
+#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
+#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
+#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
+#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
+#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
+#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
+#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
+#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
+#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
+#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
+#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
+#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
+#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
+#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
+#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
+#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
+#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
+#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
+#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
+#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
+#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
+#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
+#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
+#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
+#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
+#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0
+#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
+#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4
+#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
+#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
+#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
+#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
+#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
+#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
+#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
+#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
+#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
+#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
+#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
+#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
+#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
+#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
+#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
+#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110
+#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
+#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114
+#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
+#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118
+#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
+#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c
+#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
+#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120
+#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
+#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124
+#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
+#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128
+#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130
+#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134
+#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
+#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138
+#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
+#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c
+#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
+#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140
+#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
+#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144
+#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
+#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148
+#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150
+#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154
+#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
+#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
+#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
+#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
+#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180
+#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184
+#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
+#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188
+#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
+#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c
+#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
+#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190
+#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
+#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194
+#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
+#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198
+#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0
+#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4
+#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
+#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8
+#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
+#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac
+#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
+#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0
+#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
+#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4
+#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
+#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8
+#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
+#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc
+#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
+#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0
+#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
+#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4
+#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
+#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8
+#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
+#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc
+#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4
+#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8
+#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
+#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc
+#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
+#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0
+#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
+#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4
+#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
+#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8
+#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
+#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec
+#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4
+
+/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
+#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
+#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
+
+/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
+#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
+
+/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
+#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
+#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040
+#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
+#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
+#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060
+#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
+#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068
+#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
+#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070
+#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
+#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
+#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080
+#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
+
+/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
+#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
+
+/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
+
+/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
+
+/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
+
+/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
+
+/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
+#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004
+#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
+
+/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
+#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004
+#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
+#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008
+
+/* Function prototypes */
+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
--- /dev/null
@@ -0,0 +1,515 @@
+/*
+ * DRA7xx CM2 instance offset macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
+
+/* CM2 base address */
+#define DRA7XX_CM_CORE_BASE 0x4a008000
+
+#define DRA7XX_CM_CORE_REGADDR(inst, reg) \
+ OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
+
+/* CM_CORE instances */
+#define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
+#define DRA7XX_CM_CORE_CKGEN_INST 0x0104
+#define DRA7XX_CM_CORE_COREAON_INST 0x0600
+#define DRA7XX_CM_CORE_CORE_INST 0x0700
+#define DRA7XX_CM_CORE_IVA_INST 0x0f00
+#define DRA7XX_CM_CORE_CAM_INST 0x1000
+#define DRA7XX_CM_CORE_DSS_INST 0x1100
+#define DRA7XX_CM_CORE_GPU_INST 0x1200
+#define DRA7XX_CM_CORE_L3INIT_INST 0x1300
+#define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600
+#define DRA7XX_CM_CORE_L4PER_INST 0x1700
+#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18
+
+/* CM_CORE clockdomain register offsets (from instance start) */
+#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200
+#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
+#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
+#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520
+#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
+#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
+#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0
+#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0
+#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180
+#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc
+#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210
+
+/* CM_CORE */
+
+/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
+#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000
+#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
+#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0
+
+/* CM_CORE.CKGEN_CM_CORE register offsets */
+#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000
+#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
+#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c
+#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
+#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040
+#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
+#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044
+#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
+#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048
+#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
+#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c
+#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
+#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050
+#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
+#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054
+#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
+#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058
+#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
+#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c
+#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
+#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060
+#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068
+#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c
+#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
+#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080
+#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
+#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084
+#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
+#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088
+#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
+#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c
+#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8
+#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0
+#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
+#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc
+#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
+#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100
+#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
+#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104
+#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
+#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108
+#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
+#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c
+#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114
+#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118
+#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
+#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c
+#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
+#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120
+#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
+#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124
+#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
+
+/* CM_CORE.COREAON_CM_CORE register offsets */
+#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
+#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
+#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
+#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068
+#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
+#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
+#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098
+#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
+
+/* CM_CORE.CORE_CM_CORE register offsets */
+#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
+#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
+#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
+#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068
+#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
+#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070
+#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
+#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
+#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080
+#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
+#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
+#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090
+#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
+#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098
+#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
+#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
+#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8
+#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
+#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0
+#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
+#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8
+#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
+#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200
+#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204
+#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208
+#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220
+#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
+#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
+#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304
+#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
+#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
+#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
+#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
+#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
+#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
+#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
+#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
+#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
+#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
+#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
+#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
+#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
+#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
+#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500
+#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
+#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520
+#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
+#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
+#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
+#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
+#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
+#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
+#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630
+#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
+#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
+#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
+#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
+#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
+#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648
+#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
+#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650
+#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
+#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658
+#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
+#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660
+#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
+#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668
+#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
+#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670
+#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
+#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678
+#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
+#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680
+#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
+#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688
+#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
+#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690
+#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
+#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698
+#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
+#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0
+#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
+#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0
+#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
+#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
+#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720
+#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
+#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
+#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
+#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
+#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
+#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
+#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
+#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
+#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
+
+/* CM_CORE.IVA_CM_CORE register offsets */
+#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
+#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
+
+/* CM_CORE.CAM_CM_CORE register offsets */
+#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
+#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
+#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
+#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038
+#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
+#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
+#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048
+#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
+
+/* CM_CORE.DSS_CM_CORE register offsets */
+#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
+#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
+#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c
+#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
+
+/* CM_CORE.GPU_CM_CORE register offsets */
+#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
+
+/* CM_CORE.L3INIT_CM_CORE register offsets */
+#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
+#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048
+#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
+#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
+#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
+#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
+#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
+#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
+#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
+#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
+#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
+#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
+#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
+#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0
+#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
+
+/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
+#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
+
+/* CM_CORE.L4PER_CM_CORE register offsets */
+#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c
+#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
+#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014
+#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
+#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018
+#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
+#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
+#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
+#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
+#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038
+#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
+#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
+#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048
+#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
+#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
+#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
+#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
+#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
+#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
+#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
+#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
+#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
+#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
+#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
+#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
+#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
+#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090
+#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
+#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098
+#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
+#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
+#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
+#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
+#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
+#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
+#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
+#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
+#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
+#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4
+#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
+#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8
+#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
+#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
+#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8
+#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
+#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
+#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
+#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
+#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
+#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
+#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
+#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
+#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
+#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110
+#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
+#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118
+#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
+#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120
+#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
+#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128
+#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
+#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130
+#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
+#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138
+#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
+#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
+#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
+#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
+#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
+#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
+#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
+#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
+#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
+#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160
+#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
+#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168
+#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
+#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170
+#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
+#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178
+#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
+#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
+#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184
+#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
+#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190
+#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
+#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198
+#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
+#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
+#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
+#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
+#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
+#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
+#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
+#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8
+#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
+#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
+#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
+#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
+#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
+#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0
+#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
+#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8
+#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
+#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0
+#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
+#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8
+#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
+#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0
+#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
+#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8
+#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
+#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc
+#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200
+#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204
+#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
+#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208
+#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
+#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c
+#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210
+#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214
+
+/* Function prototypes */
+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
index a6d95614d7a415a4b37d56ca894ff8155d0ceb19..f263327116357ac807c034407795220b1f28511e 100644 (file)
void ti81xx_init_late(void);
void omap5_init_late(void);
int omap2_common_pm_late_init(void);
+void dra7xx_init_early(void);
+void dra7xx_init_late(void);
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
void omap2xxx_restart(char mode, const char *cmd);
}
#endif
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX)
void omap44xx_restart(char mode, const char *cmd);
#else
static inline void omap44xx_restart(char mode, const char *cmd)
index 371e9aeb6ae654974f7181ba65a9c2f397006911..379b14bab5e3cc2567a73cb77c0d18f129c2c8f1 100644 (file)
#define OMAP5XXX_CONTROL_STATUS 0x134
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
+/* DRA7XX BOOTSTRAP register */
+#define DRA7XX_BOOTSTRAP_CONTROL 0x6C4
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
#define AM33XX_DDR_DATA0_IOCTRL 0x1440
#define AM33XX_DDR_DATA1_IOCTRL 0x1444
+/* DEV Feature register to identify AM33XX features */
+#define AM33XX_DEV_FEATURE 0x604
+#define AM33XX_SGX_SHIFT 29
+#define AM33XX_SGX_MASK (1 << AM33XX_SGX_SHIFT)
+
/* CONTROL OMAP STATUS register to identify OMAP3 features */
#define OMAP3_CONTROL_OMAP_STATUS 0x044c
index 41652015fda9e03d0ad8da61272a5219b37d291d..4ee41febde49a92aaf55dc4a094866019a29fbfe 100644 (file)
static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
static struct cpuidle_driver omap3_idle_driver = {
- .name = "omap3_idle",
- .owner = THIS_MODULE,
+ .name = "omap3_idle",
+ .owner = THIS_MODULE,
+ .en_core_tk_irqen = 1,
.states = {
{
.enter = omap3_enter_idle_bm,
index 20ccfff7ecc5354f088c4f3492a2caa40d660b7f..2d4f9c02dccf29cae8b5e322f046fed2ca252cb4 100644 (file)
omap_init_dmic();
omap_init_mcpdm();
omap_init_mcspi();
+ omap_init_mcasp();
omap_init_sham();
omap_init_aes();
}
index 86ade1756959afaa354edacc0d41da7a75eab37a..502196efd57f48ac48b0f692319ec5a00b4b822e 100644 (file)
static struct platform_device *omap_drm_device;
#endif
-static int omapdrm_init(void)
+static __init int omapdrm_init(void)
{
struct omap_hwmod *oh;
- struct platform_device *dmm_pdev;
int r = 0;
/* create DRM and DMM device */
if (omap_drm_device != NULL) {
- oh = omap_hwmod_lookup("dmm");
- if (oh) {
- dmm_pdev = omap_device_build(oh->name, -1, oh, NULL, 0,
- NULL, 0, false);
- WARN(IS_ERR(dmm_pdev),
- "Could not build omap_device for %s\n",
- oh->name);
+ if (!of_find_compatible_node(NULL, NULL, "ti,omap4-dmm") &&
+ !of_find_compatible_node(NULL, NULL, "ti,omap5-dmm")) {
+
+ /* fallback to search within hwmod data */
+ oh = omap_hwmod_lookup("dmm");
+
+ if (oh)
+ WARN(IS_ERR(omap_device_build(oh->name, -1, oh,
+ NULL, 0, NULL, 0, false)),
+ "Could not build omap_device for %s\n",
+ oh->name);
}
platform_drm_data.omaprev = GET_OMAP_TYPE;
return OMAPDSS_VER_OMAP4;
else if (soc_is_omap54xx())
return OMAPDSS_VER_OMAP5;
+ else if (soc_is_dra7xx())
+ return OMAPDSS_VER_DRA7xx;
else
return OMAPDSS_VER_UNKNOWN;
}
index 2890968ca349173ddc4f387ba496313e057fe3db..2216df75af0fe2945f5d186096ebe7b75c62944f 100644 (file)
_omap3_noncore_dpll_bypass(clk);
/*
- * Set jitter correction. No jitter correction for OMAP4 and 3630
- * since freqsel field is no longer present
+ * Set jitter correction. Jitter correction is applicable only for
+ * OMAP343x devices since its the only one which supports freqsel
*/
- if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()
- && !soc_is_omap54xx()) {
+ if (cpu_is_omap343x()) {
v = __raw_readl(dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
if (dd->last_rounded_rate == 0)
return -EINVAL;
- /* No freqsel on AM335x, OMAP4 and OMAP3630 */
- if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
- !cpu_is_omap3630() && !soc_is_omap54xx()) {
+ /* Freqsel is available only on OMAP343X devices */
+ if (cpu_is_omap343x()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
WARN_ON(!freqsel);
index 6f83650707c273c2c3f39d15850581656a54325f..a688bfa30e4de6f47ad39f3b6dc4ba80a2da4eb4 100644 (file)
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
- } else if (soc_is_omap54xx()) {
+ } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
val &= OMAP5_DEVICETYPE_MASK;
val >>= 6;
mask |= OMAP2_SYSBOOT_6_MASK | OMAP2_SYSBOOT_7_MASK;
} else if (soc_is_omap54xx()) {
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
+ } else if (soc_is_dra7xx()) {
+ val = omap_ctrl_readl(DRA7XX_BOOTSTRAP_CONTROL);
} else {
pr_err("Cannot detect omap type!\n");
}
void omap_get_die_id(struct omap_die_id *odi)
{
- if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+ if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
omap3_cpuinfo();
}
+void __init am33xx_check_features(void)
+{
+ u32 status;
+
+ omap_features = OMAP3_HAS_NEON;
+
+ status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
+ if (status & AM33XX_SGX_MASK)
+ omap_features |= OMAP3_HAS_SGX;
+
+ omap3_cpuinfo();
+}
+
void __init omap3xxx_check_revision(void)
{
u32 cpuid, idcode;
omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
}
+void __init dra7xx_check_revision(void)
+{
+ u32 idcode;
+ u16 hawkeye;
+ u8 rev;
+
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+ switch (hawkeye) {
+ case 0xb990:
+ switch (rev) {
+ case 0:
+ default:
+ omap_revision = DRA752_REV_ES1_0;
+ }
+ break;
+ default:
+ /* Unknown. Default to latest silicon revision */
+ omap_revision = DRA752_REV_ES1_0;
+ }
+
+ pr_info("DRA%03x ES%d.%d\n", omap_rev() >> 16,
+ ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
+}
+
/*
* Set up things for map_io and processor detection later on. Gets called
* pretty much first thing from board init. For multi-omap, this gets
index 26ee4b388404316b55821638dc25e502406e950d..216f1969400388c800a1a92add92fbb4249922d5 100644 (file)
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
#include "clock3xxx.h"
#include "clock44xx.h"
#include "clock54xx.h"
+#include "clock7xx.h"
#include "omap-pm.h"
#include "sdrc.h"
#include "control.h"
};
#endif
-#ifdef CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
static struct map_desc omap54xx_io_desc[] __initdata = {
{
.virtual = L3_54XX_VIRT,
}
#endif
-#ifdef CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
void __init omap5_map_io(void)
{
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
omap3xxx_check_revision();
- ti81xx_check_features();
+ am33xx_check_features();
am33xx_voltagedomains_init();
am33xx_powerdomains_init();
am33xx_clockdomains_init();
}
#endif
+#ifdef CONFIG_SOC_DRA7XX
+void __init dra7xx_init_early(void)
+{
+ omap2_set_globals_tap(DRA7XX_CLASS,
+ OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
+ omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+ OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
+ omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
+ omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
+ OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
+ omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+ omap_prm_base_init();
+ omap_cm_base_init();
+ dra7xx_check_revision();
+ omap44xx_prm_init();
+ dra7xx_powerdomains_init();
+ dra7xx_clockdomains_init();
+ dra7xx_hwmod_init();
+ omap_hwmod_init_postsetup();
+ dra7xx_clk_init();
+}
+
+void __init dra7xx_init_late(void)
+{
+ omap2_common_pm_late_init();
+ omap4_pm_init();
+ omap2_clk_enable_autoidle_all();
+}
+#endif
+
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
index 539082a5a991fe017a19a6948211ddf5449f16bf..8a15f77d4f94f9acae8ff6e82094f973d05c6899 100644 (file)
#include "omap-wakeupgen.h"
#include "common.h"
#include "powerdomain.h"
+#include "soc.h"
/*
* platform-specific code to shutdown a CPU
/*
* Enter into low power state
*/
- omap4_mpuss_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_OFF);
+ if (soc_is_dra7xx())
+ omap4_mpuss_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_CSWR);
+ else
+ omap4_mpuss_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_OFF);
if (omap_secure_apis_support())
boot_cpu = omap_read_auxcoreboot0();
index 8380b3240a61ae7a531e0228cc63585af01e205f..d46a2693efbd29ab4bc297b8a9fe48a81bbfc899 100644 (file)
* XXX should not be writing directly into another IP block's
* address space!
*/
- __raw_writel(addr, pm_info->wkup_sar_addr);
+ if (pm_info->wkup_sar_addr)
+ __raw_writel(addr, pm_info->wkup_sar_addr);
}
/*
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
u32 scu_pwr_st;
+ if (!pm_info->scu_sar_addr)
+ return;
+
switch (fpwrst) {
case PWRDM_FUNC_PWRST_CSWR:
case PWRDM_FUNC_PWRST_OSWR: /* XXX is this accurate? */
* XXX should not be writing directly into another IP block's
* address space!
*/
- __raw_writel(save_state, pm_info->l2x0_sar_addr);
+ if (pm_info->l2x0_sar_addr)
+ __raw_writel(save_state, pm_info->l2x0_sar_addr);
}
/*
else if (soc_is_omap54xx())
cpu_wakeup_addr = OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
pm_info = &per_cpu(omap4_pm_info, 0x0);
- pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
- pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
- pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+ if (sar_base) {
+ pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
+ pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
+ pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+ }
pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
if (!pm_info->pwrdm) {
pr_err("Lookup failed for CPU0 pwrdm\n");
else if (soc_is_omap54xx())
cpu_wakeup_addr = OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
pm_info = &per_cpu(omap4_pm_info, 0x1);
- pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
- pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
- pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+ if (sar_base) {
+ pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
+ pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
+ pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+ }
pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
if (!pm_info->pwrdm) {
mpuss_clear_prev_logic_pwrst();
/* Save device type on scratchpad for low level code to use */
- if (omap_type() != OMAP2_DEVICE_TYPE_GP)
- __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
- else
- __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
+ if (sar_base) {
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+ __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
+ else
+ __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
- save_l2x0_context();
+ save_l2x0_context();
+ }
if (cpu_is_omap44xx()) {
omap_pm_ops.finish_suspend = omap4_finish_suspend;
omap_pm_ops.resume = omap4_cpu_resume;
omap_pm_ops.scu_prepare = scu_pwrst_prepare;
cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
- } else if (soc_is_omap54xx()) {
+ } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
omap_pm_ops.finish_suspend = omap5_finish_suspend;
omap_pm_ops.hotplug_restart = omap5_secondary_startup;
omap_pm_ops.resume = omap5_cpu_resume;
index f57b0b8ccdd01ea91112187f3a0689fc08e5bb71..996636a443e9d6226fec81919f0bb99310091681 100644 (file)
static void __init irq_pm_init(void)
{
- cpu_pm_register_notifier(&irq_notifier_block);
+ /* No OFF mode support on dra7xx */
+ if (!soc_is_dra7xx())
+ cpu_pm_register_notifier(&irq_notifier_block);
}
#else
static void __init irq_pm_init(void)
index 18865459abb9333948b879cba6fa2abfca9b7c0f..f585e6f9506f776a74232f6f157e3a3cd3cdc452 100644 (file)
void __iomem *omap4_get_sar_ram_base(void)
{
- return sar_ram_base;
+ if (sar_ram_base)
+ return sar_ram_base;
+ else
+ return NULL;
}
/*
index a086ba15868b2c4a32ea24de917e5cbd6d734675..92395cc59bb19d04430d85367beb166dd9530c7c 100644 (file)
#define OMAP54XX_CTRL_BASE 0x4a002800
#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
+#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
+#define DRA7XX_CTRL_BASE 0x4a003400
+#define DRA7XX_TAP_BASE 0x4ae0c000
#endif /* __ASM_SOC_OMAP555554XX_H */
index e065daa537c07bd8c8946d394d9ab60c0b120c3b..1a737328d9d90d214ed41b4dbf8905b12c59c977 100644 (file)
r->name = dev_name(&pdev->dev);
}
- if (of_get_property(node, "ti,no_idle_on_suspend", NULL))
- omap_device_disable_idle_on_suspend(pdev);
-
pdev->dev.pm_domain = &omap_device_pm_domain;
odbfd_exit1:
if (!ret && !pm_runtime_status_suspended(dev)) {
if (pm_generic_runtime_suspend(dev) == 0) {
- if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
- omap_device_idle(pdev);
+ omap_device_idle(pdev);
od->flags |= OMAP_DEVICE_SUSPENDED;
}
}
if ((od->flags & OMAP_DEVICE_SUSPENDED) &&
!pm_runtime_status_suspended(dev)) {
od->flags &= ~OMAP_DEVICE_SUSPENDED;
- if (!(od->flags & OMAP_DEVICE_NO_IDLE_ON_SUSPEND))
- omap_device_enable(pdev);
+ omap_device_enable(pdev);
pm_generic_runtime_resume(dev);
}
index 0933c599bf896a7002c448e99fa97ef3a97425dc..0181f61ffdd619887e76d9fd8fe45e716a018546 100644 (file)
/* omap_device.flags values */
#define OMAP_DEVICE_SUSPENDED BIT(0)
-#define OMAP_DEVICE_NO_IDLE_ON_SUSPEND BIT(1)
/**
* struct omap_device - omap_device wrapper for platform_devices
{
return pdev ? pdev->archdata.od : NULL;
}
-
-static inline
-void omap_device_disable_idle_on_suspend(struct platform_device *pdev)
-{
- struct omap_device *od = to_omap_device(pdev);
-
- od->flags |= OMAP_DEVICE_NO_IDLE_ON_SUSPEND;
-}
-
#endif
index ac1cb40cd1deda543d6b277e80d7049c8cff91c5..0052068a9fb701053391921fd4f3e73e2f8bc55a 100644 (file)
*/
static int __init omap_hwmod_setup_all(void)
{
+ void __iomem *base = ioremap(0x4A002000, SZ_2K);
+
_ensure_mpu_hwmod_is_setup(NULL);
+ /* enable DES HDCP clock CTRL_CORE_CONTROL_IO_2 */
+ __raw_writel(0x1, base + 0x558);
+
omap_hwmod_for_each(_init, NULL);
omap_hwmod_for_each(_setup, NULL);
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
- } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+ } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
soc_ops.wait_target_ready = _omap4_wait_target_ready;
index 82ec62daa8b6e4323d759d4c4e2af2df66e7f4be..9f536eccab51644b3f807d01127dcdf363439010 100644 (file)
extern int omap44xx_hwmod_init(void);
extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
+extern int dra7xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
--- /dev/null
@@ -0,0 +1,6244 @@
+/*
+ * Hardware modules present on the DRA7xx chips
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/power/smartreflex.h>
+#include <linux/platform_data/omap_ocp2scp.h>
+#include <linux/i2c-omap.h>
+
+#include <linux/omap-dma.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <plat/dmtimer.h>
+
+#include "omap_hwmod.h"
+#include "omap_hwmod_common_data.h"
+#include "cm1_7xx.h"
+#include "cm2_7xx.h"
+#include "prm7xx.h"
+#include "prm-regbits-7xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "wd_timer.h"
+
+/* Base offset for all DRA7XX interrupts external to MPUSS */
+#define DRA7XX_IRQ_GIC_START 32
+
+/* Base offset for all DRA7XX dma requests */
+#define DRA7XX_DMA_REQ_START 1
+
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
+ .name = "dmm",
+};
+
+/* dmm */
+static struct omap_hwmod_irq_info dra7xx_dmm_irqs[] = {
+ { .irq = 113 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_dmm_hwmod = {
+ .name = "dmm",
+ .class = &dra7xx_dmm_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .mpu_irqs = dra7xx_dmm_irqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'emif_ocp_fw' class
+ * instance(s): emif_ocp_fw
+ */
+static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
+ .name = "emif_ocp_fw",
+};
+
+/* emif_ocp_fw */
+static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
+ .name = "emif_ocp_fw",
+ .class = &dra7xx_emif_ocp_fw_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2
+ */
+static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
+ .name = "l3",
+};
+
+/* l3_instr */
+static struct omap_hwmod dra7xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &dra7xx_l3_hwmod_class,
+ .clkdm_name = "l3instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* l3_main_1 */
+static struct omap_hwmod_irq_info dra7xx_l3_main_1_irqs[] = {
+ { .name = "dbg_err", .irq = 9 + DRA7XX_IRQ_GIC_START },
+ { .name = "app_err", .irq = 10 + DRA7XX_IRQ_GIC_START },
+ { .name = "stat_alarm", .irq = 16 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
+ .name = "l3_main_1",
+ .class = &dra7xx_l3_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .mpu_irqs = dra7xx_l3_main_1_irqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* l3_main_2 */
+static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
+ .name = "l3_main_2",
+ .class = &dra7xx_l3_hwmod_class,
+ .clkdm_name = "l3instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
+ */
+static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
+ .name = "l4",
+};
+
+/* l4_cfg */
+static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
+ .name = "l4_cfg",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* l4_per1 */
+static struct omap_hwmod dra7xx_l4_per1_hwmod = {
+ .name = "l4_per1",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/* l4_per2 */
+static struct omap_hwmod dra7xx_l4_per2_hwmod = {
+ .name = "l4_per2",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/* l4_per3 */
+static struct omap_hwmod dra7xx_l4_per3_hwmod = {
+ .name = "l4_per3",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/* l4_wkup */
+static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class dra7xx_mpu_bus_hwmod_class = {
+ .name = "mpu_bus",
+};
+
+/* mpu_private */
+static struct omap_hwmod dra7xx_mpu_private_hwmod = {
+ .name = "mpu_private",
+ .class = &dra7xx_mpu_bus_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/*
+ * 'ocp_wp_noc' class
+ * instance(s): ocp_wp_noc
+ */
+static struct omap_hwmod_class dra7xx_ocp_wp_noc_hwmod_class = {
+ .name = "ocp_wp_noc",
+};
+
+/* ocp_wp_noc */
+static struct omap_hwmod dra7xx_ocp_wp_noc_hwmod = {
+ .name = "ocp_wp_noc",
+ .class = &dra7xx_ocp_wp_noc_hwmod_class,
+ .clkdm_name = "l3instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'atl' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
+ .name = "atl",
+};
+
+/* atl */
+static struct omap_hwmod dra7xx_atl_hwmod = {
+ .name = "atl",
+ .class = &dra7xx_atl_hwmod_class,
+ .clkdm_name = "atl_clkdm",
+ .main_clk = "atl_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'bb2d' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
+ .name = "bb2d",
+};
+
+/* bb2d */
+static struct omap_hwmod_irq_info dra7xx_bb2d_irqs[] = {
+ { .irq = 125 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_bb2d_hwmod = {
+ .name = "bb2d",
+ .class = &dra7xx_bb2d_hwmod_class,
+ .clkdm_name = "dss_clkdm",
+ .mpu_irqs = dra7xx_bb2d_irqs,
+ .main_clk = "dpll_core_h24x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'counter' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
+ .name = "counter",
+ .sysc = &dra7xx_counter_sysc,
+};
+
+/* counter_32k */
+static struct omap_hwmod dra7xx_counter_32k_hwmod = {
+ .name = "counter_32k",
+ .class = &dra7xx_counter_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE,
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'ctrl_module' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
+ .name = "ctrl_module",
+};
+
+/* ctrl_module_wkup */
+static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
+ .name = "ctrl_module_wkup",
+ .class = &dra7xx_ctrl_module_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/*
+ * 'dcan' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
+ .name = "dcan",
+};
+
+/* dcan1 */
+static struct omap_hwmod dra7xx_dcan1_hwmod = {
+ .name = "dcan1",
+ .class = &dra7xx_dcan_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "dcan1_sys_clk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* dcan2 */
+static struct omap_hwmod dra7xx_dcan2_hwmod = {
+ .name = "dcan2",
+ .class = &dra7xx_dcan_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "sys_clkin1",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'dma' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x002c,
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
+ .name = "dma",
+ .sysc = &dra7xx_dma_sysc,
+};
+
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+ IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+ .lch_count = 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
+ { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
+ { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
+ { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
+ { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_dma_system_hwmod = {
+ .name = "dma_system",
+ .class = &dra7xx_dma_hwmod_class,
+ .clkdm_name = "dma_clkdm",
+ .mpu_irqs = dra7xx_dma_system_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &dma_dev_attr,
+};
+
+/*
+ * 'dss' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
+ .rev_offs = 0x0000,
+ .syss_offs = 0x0014,
+ .sysc_flags = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
+ .name = "dss",
+ .sysc = &dra7xx_dss_sysc,
+ .reset = omap_dss_reset,
+};
+
+/* dss */
+static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
+ { .dma_req = 75 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+ { .role = "dss_clk", .clk = "dss_dss_clk" },
+ { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
+ { .role = "32khz_clk", .clk = "dss_32khz_clk" },
+ { .role = "video2_clk", .clk = "dss_video2_clk" },
+ { .role = "video1_clk", .clk = "dss_video1_clk" },
+ { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
+};
+
+static struct omap_hwmod dra7xx_dss_hwmod = {
+ .name = "dss_core",
+ .class = &dra7xx_dss_hwmod_class,
+ .clkdm_name = "dss_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .sdma_reqs = dra7xx_dss_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = dss_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
+ .name = "dispc",
+ .sysc = &dra7xx_dispc_sysc,
+};
+
+/* dss_dispc */
+static struct omap_hwmod_irq_info dra7xx_dss_dispc_irqs[] = {
+ { .irq = 25 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_dss_dispc_sdma_reqs[] = {
+ { .dma_req = 5 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* dss_dispc dev_attr */
+static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
+ .has_framedonetv_irq = 1,
+ .manager_count = 4,
+};
+
+static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &dra7xx_dispc_hwmod_class,
+ .clkdm_name = "dss_clkdm",
+ .mpu_irqs = dra7xx_dss_dispc_irqs,
+ .sdma_reqs = dra7xx_dss_dispc_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+ .dev_attr = &dss_dispc_dev_attr,
+};
+
+/*
+ * 'hdmi' class
+ * hdmi controller
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
+ .name = "hdmi",
+ .sysc = &dra7xx_hdmi_sysc,
+};
+
+/* dss_hdmi */
+static struct omap_hwmod_irq_info dra7xx_dss_hdmi_irqs[] = {
+ { .irq = 101 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_dss_hdmi_sdma_reqs[] = {
+ { .dma_req = 75 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
+ { .role = "sys_clk", .clk = "dss_hdmi_clk" },
+};
+
+static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
+ .name = "dss_hdmi",
+ .class = &dra7xx_hdmi_hwmod_class,
+ .clkdm_name = "dss_clkdm",
+ .mpu_irqs = dra7xx_dss_hdmi_irqs,
+ .sdma_reqs = dra7xx_dss_hdmi_sdma_reqs,
+ .main_clk = "dss_48mhz_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+ .opt_clks = dss_hdmi_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
+};
+
+/*
+ * 'elm' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
+ .name = "elm",
+ .sysc = &dra7xx_elm_sysc,
+};
+
+/* elm */
+static struct omap_hwmod_irq_info dra7xx_elm_irqs[] = {
+ { .irq = 4 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_elm_hwmod = {
+ .name = "elm",
+ .class = &dra7xx_elm_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_elm_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'emif' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_emif_sysc = {
+ .rev_offs = 0x0000,
+};
+
+static struct omap_hwmod_class dra7xx_emif_hwmod_class = {
+ .name = "emif",
+ .sysc = &dra7xx_emif_sysc,
+};
+
+/* emif1 */
+static struct omap_hwmod_irq_info dra7xx_emif1_irqs[] = {
+ { .irq = 110 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_emif1_hwmod = {
+ .name = "emif1",
+ .class = &dra7xx_emif_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_emif1_irqs,
+ .main_clk = "dpll_ddr_h11x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* emif2 */
+static struct omap_hwmod_irq_info dra7xx_emif2_irqs[] = {
+ { .irq = 111 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_emif2_hwmod = {
+ .name = "emif2",
+ .class = &dra7xx_emif_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_emif2_irqs,
+ .main_clk = "dpll_ddr_h11x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'gpio' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &dra7xx_gpio_sysc,
+ .rev = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info dra7xx_gpio1_irqs[] = {
+ { .irq = 29 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio1_hwmod = {
+ .name = "gpio1",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .mpu_irqs = dra7xx_gpio1_irqs,
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info dra7xx_gpio2_irqs[] = {
+ { .irq = 30 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio2_hwmod = {
+ .name = "gpio2",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio2_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info dra7xx_gpio3_irqs[] = {
+ { .irq = 31 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio3_hwmod = {
+ .name = "gpio3",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio3_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info dra7xx_gpio4_irqs[] = {
+ { .irq = 32 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio4_hwmod = {
+ .name = "gpio4",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio4_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio5 */
+static struct omap_hwmod_irq_info dra7xx_gpio5_irqs[] = {
+ { .irq = 33 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio5_hwmod = {
+ .name = "gpio5",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio5_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio5_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio6 */
+static struct omap_hwmod_irq_info dra7xx_gpio6_irqs[] = {
+ { .irq = 34 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio6_hwmod = {
+ .name = "gpio6",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio6_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio6_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio7 */
+static struct omap_hwmod_irq_info dra7xx_gpio7_irqs[] = {
+ { .irq = 35 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio7_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio7_hwmod = {
+ .name = "gpio7",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio7_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio7_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio8 */
+static struct omap_hwmod_irq_info dra7xx_gpio8_irqs[] = {
+ { .irq = 121 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio8_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio8_hwmod = {
+ .name = "gpio8",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio8_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio8_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/*
+ * 'gpmc' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
+ .name = "gpmc",
+ .sysc = &dra7xx_gpmc_sysc,
+};
+
+/* gpmc */
+static struct omap_hwmod_irq_info dra7xx_gpmc_irqs[] = {
+ { .irq = 20 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_gpmc_sdma_reqs[] = {
+ { .dma_req = 3 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_gpmc_hwmod = {
+ .name = "gpmc",
+ .class = &dra7xx_gpmc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_gpmc_irqs,
+ .sdma_reqs = dra7xx_gpmc_sdma_reqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'hdq1w' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0014,
+ .syss_offs = 0x0018,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
+ .name = "hdq1w",
+ .sysc = &dra7xx_hdq1w_sysc,
+};
+
+/* hdq1w */
+static struct omap_hwmod_irq_info dra7xx_hdq1w_irqs[] = {
+ { .irq = 58 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_hdq1w_hwmod = {
+ .name = "hdq1w",
+ .class = &dra7xx_hdq1w_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_hdq1w_irqs,
+ .main_clk = "func_12m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'i2c' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0090,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .clockact = CLOCKACT_TEST_ICLK,
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
+ .name = "i2c",
+ .sysc = &dra7xx_i2c_sysc,
+ .reset = &omap_i2c_reset,
+ .rev = OMAP_I2C_IP_VERSION_2,
+};
+
+/* i2c dev_attr */
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info dra7xx_i2c1_irqs[] = {
+ { .irq = 56 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_i2c1_sdma_reqs[] = {
+ { .name = "27", .dma_req = 26 + DRA7XX_DMA_REQ_START },
+ { .name = "28", .dma_req = 27 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c1_irqs,
+ .sdma_reqs = dra7xx_i2c1_sdma_reqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c2 */
+static struct omap_hwmod_irq_info dra7xx_i2c2_irqs[] = {
+ { .irq = 57 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_i2c2_sdma_reqs[] = {
+ { .name = "29", .dma_req = 28 + DRA7XX_DMA_REQ_START },
+ { .name = "30", .dma_req = 29 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c2_irqs,
+ .sdma_reqs = dra7xx_i2c2_sdma_reqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod_irq_info dra7xx_i2c3_irqs[] = {
+ { .irq = 61 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_i2c3_sdma_reqs[] = {
+ { .name = "25", .dma_req = 24 + DRA7XX_DMA_REQ_START },
+ { .name = "26", .dma_req = 25 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c3_irqs,
+ .sdma_reqs = dra7xx_i2c3_sdma_reqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c4 */
+static struct omap_hwmod_irq_info dra7xx_i2c4_irqs[] = {
+ { .irq = 62 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_i2c4_sdma_reqs[] = {
+ { .name = "124", .dma_req = 123 + DRA7XX_DMA_REQ_START },
+ { .name = "125", .dma_req = 124 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c4_hwmod = {
+ .name = "i2c4",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c4_irqs,
+ .sdma_reqs = dra7xx_i2c4_sdma_reqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c5 */
+static struct omap_hwmod_irq_info dra7xx_i2c5_irqs[] = {
+ { .irq = 60 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c5_hwmod = {
+ .name = "i2c5",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c5_irqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/*
+ * 'mailbox' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &dra7xx_mailbox_sysc,
+};
+
+/* mailbox1 */
+static struct omap_hwmod dra7xx_mailbox1_hwmod = {
+ .name = "mailbox1",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox2 */
+static struct omap_hwmod dra7xx_mailbox2_hwmod = {
+ .name = "mailbox2",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox3 */
+static struct omap_hwmod dra7xx_mailbox3_hwmod = {
+ .name = "mailbox3",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox4 */
+static struct omap_hwmod dra7xx_mailbox4_hwmod = {
+ .name = "mailbox4",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox5 */
+static struct omap_hwmod dra7xx_mailbox5_hwmod = {
+ .name = "mailbox5",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox6 */
+static struct omap_hwmod dra7xx_mailbox6_hwmod = {
+ .name = "mailbox6",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox7 */
+static struct omap_hwmod dra7xx_mailbox7_hwmod = {
+ .name = "mailbox7",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox8 */
+static struct omap_hwmod dra7xx_mailbox8_hwmod = {
+ .name = "mailbox8",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox9 */
+static struct omap_hwmod dra7xx_mailbox9_hwmod = {
+ .name = "mailbox9",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox10 */
+static struct omap_hwmod dra7xx_mailbox10_hwmod = {
+ .name = "mailbox10",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox11 */
+static struct omap_hwmod dra7xx_mailbox11_hwmod = {
+ .name = "mailbox11",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox12 */
+static struct omap_hwmod dra7xx_mailbox12_hwmod = {
+ .name = "mailbox12",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox13 */
+static struct omap_hwmod dra7xx_mailbox13_hwmod = {
+ .name = "mailbox13",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'mcasp' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
+ .sysc_offs = 0x0004,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
+ .name = "mcasp",
+ .sysc = &dra7xx_mcasp_sysc,
+};
+
+/* mcasp1 */
+static struct omap_hwmod dra7xx_mcasp1_hwmod = {
+ .name = "mcasp1",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .main_clk = "mcasp1_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp2 */
+static struct omap_hwmod dra7xx_mcasp2_hwmod = {
+ .name = "mcasp2",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp2_ahclkr_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp3 */
+static struct omap_hwmod dra7xx_mcasp3_hwmod = {
+ .name = "mcasp3",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp3_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp4 */
+static struct omap_hwmod dra7xx_mcasp4_hwmod = {
+ .name = "mcasp4",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp4_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp5 */
+static struct omap_hwmod dra7xx_mcasp5_hwmod = {
+ .name = "mcasp5",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp5_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp6 */
+static struct omap_hwmod dra7xx_mcasp6_hwmod = {
+ .name = "mcasp6",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp6_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp7 */
+static struct omap_hwmod dra7xx_mcasp7_hwmod = {
+ .name = "mcasp7",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp7_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp8 */
+static struct omap_hwmod dra7xx_mcasp8_hwmod = {
+ .name = "mcasp8",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp8_ahclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mcspi' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &dra7xx_mcspi_sysc,
+ .rev = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod_irq_info dra7xx_mcspi1_irqs[] = {
+ { .irq = 65 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mcspi1_sdma_reqs[] = {
+ { .name = "35", .dma_req = 34 + DRA7XX_DMA_REQ_START },
+ { .name = "36", .dma_req = 35 + DRA7XX_DMA_REQ_START },
+ { .name = "37", .dma_req = 36 + DRA7XX_DMA_REQ_START },
+ { .name = "38", .dma_req = 37 + DRA7XX_DMA_REQ_START },
+ { .name = "39", .dma_req = 38 + DRA7XX_DMA_REQ_START },
+ { .name = "40", .dma_req = 39 + DRA7XX_DMA_REQ_START },
+ { .name = "41", .dma_req = 40 + DRA7XX_DMA_REQ_START },
+ { .name = "42", .dma_req = 41 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+ .num_chipselect = 4,
+};
+
+static struct omap_hwmod dra7xx_mcspi1_hwmod = {
+ .name = "mcspi1",
+ .class = &dra7xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mcspi1_irqs,
+ .sdma_reqs = dra7xx_mcspi1_sdma_reqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+static struct omap_hwmod_irq_info dra7xx_mcspi2_irqs[] = {
+ { .irq = 66 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mcspi2_sdma_reqs[] = {
+ { .name = "43", .dma_req = 42 + DRA7XX_DMA_REQ_START },
+ { .name = "44", .dma_req = 43 + DRA7XX_DMA_REQ_START },
+ { .name = "45", .dma_req = 44 + DRA7XX_DMA_REQ_START },
+ { .name = "46", .dma_req = 45 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+ .num_chipselect = 2,
+};
+
+static struct omap_hwmod dra7xx_mcspi2_hwmod = {
+ .name = "mcspi2",
+ .class = &dra7xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mcspi2_irqs,
+ .sdma_reqs = dra7xx_mcspi2_sdma_reqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi2_dev_attr,
+};
+
+/* mcspi3 */
+static struct omap_hwmod_irq_info dra7xx_mcspi3_irqs[] = {
+ { .irq = 91 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mcspi3_sdma_reqs[] = {
+ { .name = "15", .dma_req = 14 + DRA7XX_DMA_REQ_START },
+ { .name = "16", .dma_req = 15 + DRA7XX_DMA_REQ_START },
+ { .name = "23", .dma_req = 22 + DRA7XX_DMA_REQ_START },
+ { .name = "24", .dma_req = 23 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+ .num_chipselect = 2,
+};
+
+static struct omap_hwmod dra7xx_mcspi3_hwmod = {
+ .name = "mcspi3",
+ .class = &dra7xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mcspi3_irqs,
+ .sdma_reqs = dra7xx_mcspi3_sdma_reqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi3_dev_attr,
+};
+
+/* mcspi4 */
+static struct omap_hwmod_irq_info dra7xx_mcspi4_irqs[] = {
+ { .irq = 48 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mcspi4_sdma_reqs[] = {
+ { .name = "70", .dma_req = 69 + DRA7XX_DMA_REQ_START },
+ { .name = "71", .dma_req = 70 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+ .num_chipselect = 1,
+};
+
+static struct omap_hwmod dra7xx_mcspi4_hwmod = {
+ .name = "mcspi4",
+ .class = &dra7xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mcspi4_irqs,
+ .sdma_reqs = dra7xx_mcspi4_sdma_reqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi4_dev_attr,
+};
+
+/*
+ * 'mmc' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
+ .name = "mmc",
+ .sysc = &dra7xx_mmc_sysc,
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info dra7xx_mmc1_irqs[] = {
+ { .irq = 83 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mmc1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 60 + DRA7XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 61 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
+ { .role = "clk32k", .clk = "mmc1_clk32k" },
+};
+
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod dra7xx_mmc1_hwmod = {
+ .name = "mmc1",
+ .class = &dra7xx_mmc_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .mpu_irqs = dra7xx_mmc1_irqs,
+ .sdma_reqs = dra7xx_mmc1_sdma_reqs,
+ .main_clk = "mmc1_fclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mmc1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
+ .dev_attr = &mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info dra7xx_mmc2_irqs[] = {
+ { .irq = 86 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mmc2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = 46 + DRA7XX_DMA_REQ_START },
+ { .name = "rx", .dma_req = 47 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
+ { .role = "clk32k", .clk = "mmc2_clk32k" },
+};
+
+static struct omap_hwmod dra7xx_mmc2_hwmod = {
+ .name = "mmc2",
+ .class = &dra7xx_mmc_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .mpu_irqs = dra7xx_mmc2_irqs,
+ .sdma_reqs = dra7xx_mmc2_sdma_reqs,
+ .main_clk = "mmc2_fclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mmc2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
+};
+
+/* mmc3 */
+static struct omap_hwmod_irq_info dra7xx_mmc3_irqs[] = {
+ { .irq = 94 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mmc3_sdma_reqs[] = {
+ { .name = "77", .dma_req = 76 + DRA7XX_DMA_REQ_START },
+ { .name = "78", .dma_req = 77 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
+ { .role = "clk32k", .clk = "mmc3_clk32k" },
+};
+
+static struct omap_hwmod dra7xx_mmc3_hwmod = {
+ .name = "mmc3",
+ .class = &dra7xx_mmc_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mmc3_irqs,
+ .sdma_reqs = dra7xx_mmc3_sdma_reqs,
+ .main_clk = "mmc3_gfclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mmc3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
+};
+
+/* mmc4 */
+static struct omap_hwmod_irq_info dra7xx_mmc4_irqs[] = {
+ { .irq = 96 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mmc4_sdma_reqs[] = {
+ { .name = "57", .dma_req = 56 + DRA7XX_DMA_REQ_START },
+ { .name = "58", .dma_req = 57 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
+ { .role = "clk32k", .clk = "mmc4_clk32k" },
+};
+
+static struct omap_hwmod dra7xx_mmc4_hwmod = {
+ .name = "mmc4",
+ .class = &dra7xx_mmc_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mmc4_irqs,
+ .sdma_reqs = dra7xx_mmc4_sdma_reqs,
+ .main_clk = "mmc4_gfclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mmc4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
+};
+
+/*
+ * 'mpu' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
+ .name = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info dra7xx_mpu_irqs[] = {
+ { .irq = 132 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &dra7xx_mpu_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_mpu_irqs,
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'ocmc_ram' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_ocmc_ram_hwmod_class = {
+ .name = "ocmc_ram",
+};
+
+/* ocmc_ram1 */
+static struct omap_hwmod dra7xx_ocmc_ram1_hwmod = {
+ .name = "ocmc_ram1",
+ .class = &dra7xx_ocmc_ram_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* ocmc_ram2 */
+static struct omap_hwmod dra7xx_ocmc_ram2_hwmod = {
+ .name = "ocmc_ram2",
+ .class = &dra7xx_ocmc_ram_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* ocmc_ram3 */
+static struct omap_hwmod dra7xx_ocmc_ram3_hwmod = {
+ .name = "ocmc_ram3",
+ .class = &dra7xx_ocmc_ram_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'ocmc_rom' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_ocmc_rom_hwmod_class = {
+ .name = "ocmc_rom",
+};
+
+/* ocmc_rom */
+static struct omap_hwmod dra7xx_ocmc_rom_hwmod = {
+ .name = "ocmc_rom",
+ .class = &dra7xx_ocmc_rom_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'ocp2scp' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
+ .name = "ocp2scp",
+ .sysc = &dra7xx_ocp2scp_sysc,
+};
+
+/* ocp2scp1 */
+static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
+ .name = "ocp2scp1",
+ .class = &dra7xx_ocp2scp_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'pruss' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
+ .name = "pruss",
+};
+
+/* pruss1 */
+static struct omap_hwmod dra7xx_pruss1_hwmod = {
+ .name = "pruss1",
+ .class = &dra7xx_pruss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "dpll_per_m2x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pruss2 */
+static struct omap_hwmod dra7xx_pruss2_hwmod = {
+ .name = "pruss2",
+ .class = &dra7xx_pruss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "dpll_per_m2x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'pwmss' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pwmss_hwmod_class = {
+ .name = "pwmss",
+};
+
+/* pwmss1 */
+static struct omap_hwmod dra7xx_pwmss1_hwmod = {
+ .name = "pwmss1",
+ .class = &dra7xx_pwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pwmss2 */
+static struct omap_hwmod dra7xx_pwmss2_hwmod = {
+ .name = "pwmss2",
+ .class = &dra7xx_pwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pwmss3 */
+static struct omap_hwmod dra7xx_pwmss3_hwmod = {
+ .name = "pwmss3",
+ .class = &dra7xx_pwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'qspi' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
+ .sysc_offs = 0x0010,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
+ .name = "qspi",
+ .sysc = &dra7xx_qspi_sysc,
+};
+
+/* qspi */
+static struct omap_hwmod dra7xx_qspi_hwmod = {
+ .name = "qspi",
+ .class = &dra7xx_qspi_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "qspi_gfclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'rtcss' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
+ .sysc_offs = 0x0078,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
+ .name = "rtcss",
+ .sysc = &dra7xx_rtcss_sysc,
+};
+
+/* rtcss */
+static struct omap_hwmod dra7xx_rtcss_hwmod = {
+ .name = "rtcss",
+ .class = &dra7xx_rtcss_hwmod_class,
+ .clkdm_name = "rtc_clkdm",
+ .main_clk = "sys_32k_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'sata' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
+ .sysc_offs = 0x0000,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
+ .name = "sata",
+ .sysc = &dra7xx_sata_sysc,
+};
+
+/* sata */
+static struct omap_hwmod_irq_info dra7xx_sata_irqs[] = {
+ { .irq = 54 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk sata_opt_clks[] = {
+ { .role = "ref_clk", .clk = "sata_ref_clk" },
+};
+
+static struct omap_hwmod dra7xx_sata_hwmod = {
+ .name = "sata",
+ .class = &dra7xx_sata_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .mpu_irqs = dra7xx_sata_irqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = sata_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
+};
+
+/*
+ * 'smartreflex' class
+ *
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+ .sidle_shift = 24,
+ .enwkup_shift = 26,
+};
+
+static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
+ .sysc_offs = 0x0038,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
+};
+
+static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+ .sysc = &dra7xx_smartreflex_sysc,
+ .rev = 2,
+};
+
+/* smartreflex_core */
+static struct omap_hwmod_irq_info dra7xx_smartreflex_core_irqs[] = {
+ { .irq = 19 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+/* smartreflex_core dev_attr */
+static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
+ .sensor_voltdm_name = "core",
+};
+
+static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
+ .name = "smartreflex_core",
+ .class = &dra7xx_smartreflex_hwmod_class,
+ .clkdm_name = "coreaon_clkdm",
+ .mpu_irqs = dra7xx_smartreflex_core_irqs,
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &smartreflex_core_dev_attr,
+};
+
+/* smartreflex_dspeve */
+static struct omap_hwmod dra7xx_smartreflex_dspeve_hwmod = {
+ .name = "smartreflex_dspeve",
+ .class = &dra7xx_smartreflex_hwmod_class,
+ .clkdm_name = "coreaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* smartreflex_gpu */
+static struct omap_hwmod dra7xx_smartreflex_gpu_hwmod = {
+ .name = "smartreflex_gpu",
+ .class = &dra7xx_smartreflex_hwmod_class,
+ .clkdm_name = "coreaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* smartreflex_mpu */
+static struct omap_hwmod_irq_info dra7xx_smartreflex_mpu_irqs[] = {
+ { .irq = 18 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+/* smartreflex_mpu dev_attr */
+static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
+ .sensor_voltdm_name = "mpu",
+};
+
+static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
+ .name = "smartreflex_mpu",
+ .class = &dra7xx_smartreflex_hwmod_class,
+ .clkdm_name = "coreaon_clkdm",
+ .mpu_irqs = dra7xx_smartreflex_mpu_irqs,
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &smartreflex_mpu_dev_attr,
+};
+
+/*
+ * 'spare' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_spare_hwmod_class = {
+ .name = "spare",
+};
+
+/* spare_cme */
+static struct omap_hwmod dra7xx_spare_cme_hwmod = {
+ .name = "spare_cme",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_icm */
+static struct omap_hwmod dra7xx_spare_icm_hwmod = {
+ .name = "spare_icm",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_iva2 */
+static struct omap_hwmod dra7xx_spare_iva2_hwmod = {
+ .name = "spare_iva2",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_safety1 */
+static struct omap_hwmod dra7xx_spare_safety1_hwmod = {
+ .name = "spare_safety1",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_safety2 */
+static struct omap_hwmod dra7xx_spare_safety2_hwmod = {
+ .name = "spare_safety2",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_safety3 */
+static struct omap_hwmod dra7xx_spare_safety3_hwmod = {
+ .name = "spare_safety3",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_safety4 */
+static struct omap_hwmod dra7xx_spare_safety4_hwmod = {
+ .name = "spare_safety4",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown2 */
+static struct omap_hwmod dra7xx_spare_unknown2_hwmod = {
+ .name = "spare_unknown2",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown3 */
+static struct omap_hwmod dra7xx_spare_unknown3_hwmod = {
+ .name = "spare_unknown3",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown4 */
+static struct omap_hwmod dra7xx_spare_unknown4_hwmod = {
+ .name = "spare_unknown4",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown5 */
+static struct omap_hwmod dra7xx_spare_unknown5_hwmod = {
+ .name = "spare_unknown5",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown6 */
+static struct omap_hwmod dra7xx_spare_unknown6_hwmod = {
+ .name = "spare_unknown6",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_videopll1 */
+static struct omap_hwmod dra7xx_spare_videopll1_hwmod = {
+ .name = "spare_videopll1",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_videopll2 */
+static struct omap_hwmod dra7xx_spare_videopll2_hwmod = {
+ .name = "spare_videopll2",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_videopll3 */
+static struct omap_hwmod dra7xx_spare_videopll3_hwmod = {
+ .name = "spare_videopll3",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'spare_sata2' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_spare_sata2_hwmod_class = {
+ .name = "spare_sata2",
+};
+
+/* spare_sata2 */
+static struct omap_hwmod dra7xx_spare_sata2_hwmod = {
+ .name = "spare_sata2",
+ .class = &dra7xx_spare_sata2_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'spare_smartreflex' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_spare_smartreflex_hwmod_class = {
+ .name = "spare_smartreflex",
+};
+
+/* spare_smartreflex_rtc */
+static struct omap_hwmod dra7xx_spare_smartreflex_rtc_hwmod = {
+ .name = "spare_smartreflex_rtc",
+ .class = &dra7xx_spare_smartreflex_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_smartreflex_sdram */
+static struct omap_hwmod dra7xx_spare_smartreflex_sdram_hwmod = {
+ .name = "spare_smartreflex_sdram",
+ .class = &dra7xx_spare_smartreflex_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_smartreflex_wkup */
+static struct omap_hwmod dra7xx_spare_smartreflex_wkup_hwmod = {
+ .name = "spare_smartreflex_wkup",
+ .class = &dra7xx_spare_smartreflex_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'spinlock' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
+ .name = "spinlock",
+ .sysc = &dra7xx_spinlock_sysc,
+};
+
+/* spinlock */
+static struct omap_hwmod dra7xx_spinlock_hwmod = {
+ .name = "spinlock",
+ .class = &dra7xx_spinlock_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'timer' class
+ *
+ * This class contains several variants: ['timer_1ms', 'timer_secure',
+ * 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &dra7xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
+ .name = "timer",
+ .sysc = &dra7xx_timer_secure_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &dra7xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod_irq_info dra7xx_timer1_irqs[] = {
+ { .irq = 37 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &dra7xx_timer_1ms_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .mpu_irqs = dra7xx_timer1_irqs,
+ .main_clk = "timer1_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer2 */
+static struct omap_hwmod_irq_info dra7xx_timer2_irqs[] = {
+ { .irq = 38 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &dra7xx_timer_1ms_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer2_irqs,
+ .main_clk = "timer2_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer3 */
+static struct omap_hwmod_irq_info dra7xx_timer3_irqs[] = {
+ { .irq = 39 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer3_irqs,
+ .main_clk = "timer3_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer4 */
+static struct omap_hwmod_irq_info dra7xx_timer4_irqs[] = {
+ { .irq = 40 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &dra7xx_timer_secure_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer4_irqs,
+ .main_clk = "timer4_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer5 */
+static struct omap_hwmod_irq_info dra7xx_timer5_irqs[] = {
+ { .irq = 41 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_timer5_irqs,
+ .main_clk = "timer5_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer6 */
+static struct omap_hwmod_irq_info dra7xx_timer6_irqs[] = {
+ { .irq = 42 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_timer6_irqs,
+ .main_clk = "timer6_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer7 */
+static struct omap_hwmod_irq_info dra7xx_timer7_irqs[] = {
+ { .irq = 43 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_timer7_irqs,
+ .main_clk = "timer7_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer8 */
+static struct omap_hwmod_irq_info dra7xx_timer8_irqs[] = {
+ { .irq = 44 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer8_hwmod = {
+ .name = "timer8",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_timer8_irqs,
+ .main_clk = "timer8_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer9 */
+static struct omap_hwmod_irq_info dra7xx_timer9_irqs[] = {
+ { .irq = 45 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer9_hwmod = {
+ .name = "timer9",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer9_irqs,
+ .main_clk = "timer9_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer10 */
+static struct omap_hwmod_irq_info dra7xx_timer10_irqs[] = {
+ { .irq = 46 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer10_hwmod = {
+ .name = "timer10",
+ .class = &dra7xx_timer_1ms_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer10_irqs,
+ .main_clk = "timer10_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer11 */
+static struct omap_hwmod_irq_info dra7xx_timer11_irqs[] = {
+ { .irq = 47 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer11_hwmod = {
+ .name = "timer11",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer11_irqs,
+ .main_clk = "timer11_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer13 */
+static struct omap_hwmod dra7xx_timer13_hwmod = {
+ .name = "timer13",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .main_clk = "timer13_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer14 */
+static struct omap_hwmod dra7xx_timer14_hwmod = {
+ .name = "timer14",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .main_clk = "timer14_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer15 */
+static struct omap_hwmod dra7xx_timer15_hwmod = {
+ .name = "timer15",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .main_clk = "timer15_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer16 */
+static struct omap_hwmod dra7xx_timer16_hwmod = {
+ .name = "timer16",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .main_clk = "timer16_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'uart' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
+ .rev_offs = 0x0050,
+ .sysc_offs = 0x0054,
+ .syss_offs = 0x0058,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
+ .name = "uart",
+ .sysc = &dra7xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_irq_info dra7xx_uart1_irqs[] = {
+ { .irq = 72 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart1_sdma_reqs[] = {
+ { .name = "49", .dma_req = 48 + DRA7XX_DMA_REQ_START },
+ { .name = "50", .dma_req = 49 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_uart1_irqs,
+ .sdma_reqs = dra7xx_uart1_sdma_reqs,
+ .main_clk = "uart1_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart2 */
+static struct omap_hwmod_irq_info dra7xx_uart2_irqs[] = {
+ { .irq = 73 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart2_sdma_reqs[] = {
+ { .name = "51", .dma_req = 50 + DRA7XX_DMA_REQ_START },
+ { .name = "52", .dma_req = 51 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_uart2_irqs,
+ .sdma_reqs = dra7xx_uart2_sdma_reqs,
+ .main_clk = "uart2_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart3 */
+static struct omap_hwmod_irq_info dra7xx_uart3_irqs[] = {
+ { .irq = 74 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart3_sdma_reqs[] = {
+ { .name = "53", .dma_req = 52 + DRA7XX_DMA_REQ_START },
+ { .name = "54", .dma_req = 53 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+ HWMOD_SWSUP_SIDLE_ACT,
+ .mpu_irqs = dra7xx_uart3_irqs,
+ .sdma_reqs = dra7xx_uart3_sdma_reqs,
+ .main_clk = "uart3_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart4 */
+static struct omap_hwmod_irq_info dra7xx_uart4_irqs[] = {
+ { .irq = 70 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart4_sdma_reqs[] = {
+ { .name = "55", .dma_req = 54 + DRA7XX_DMA_REQ_START },
+ { .name = "56", .dma_req = 55 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_uart4_irqs,
+ .sdma_reqs = dra7xx_uart4_sdma_reqs,
+ .main_clk = "uart4_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart5 */
+static struct omap_hwmod_irq_info dra7xx_uart5_irqs[] = {
+ { .irq = 105 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart5_sdma_reqs[] = {
+ { .name = "63", .dma_req = 62 + DRA7XX_DMA_REQ_START },
+ { .name = "64", .dma_req = 63 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart5_hwmod = {
+ .name = "uart5",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_uart5_irqs,
+ .sdma_reqs = dra7xx_uart5_sdma_reqs,
+ .main_clk = "uart5_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart6 */
+static struct omap_hwmod_irq_info dra7xx_uart6_irqs[] = {
+ { .irq = 106 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart6_sdma_reqs[] = {
+ { .name = "79", .dma_req = 78 + DRA7XX_DMA_REQ_START },
+ { .name = "80", .dma_req = 79 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart6_hwmod = {
+ .name = "uart6",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_uart6_irqs,
+ .sdma_reqs = dra7xx_uart6_sdma_reqs,
+ .main_clk = "uart6_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart7 */
+static struct omap_hwmod dra7xx_uart7_hwmod = {
+ .name = "uart7",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "uart7_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart8 */
+static struct omap_hwmod dra7xx_uart8_hwmod = {
+ .name = "uart8",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "uart8_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart9 */
+static struct omap_hwmod dra7xx_uart9_hwmod = {
+ .name = "uart9",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "uart9_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart10 */
+static struct omap_hwmod dra7xx_uart10_hwmod = {
+ .name = "uart10",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "uart10_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'usb_otg_ss' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
+ .name = "usb_otg_ss",
+};
+
+/* usb_otg_ss1 */
+static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
+ { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
+};
+
+static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
+ .name = "usb_otg_ss1",
+ .class = &dra7xx_usb_otg_ss_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "dpll_core_h13x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = usb_otg_ss1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
+};
+
+/* usb_otg_ss2 */
+static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
+ { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
+};
+
+static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
+ .name = "usb_otg_ss2",
+ .class = &dra7xx_usb_otg_ss_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "dpll_core_h13x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = usb_otg_ss2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
+};
+
+/* usb_otg_ss3 */
+static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
+ .name = "usb_otg_ss3",
+ .class = &dra7xx_usb_otg_ss_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "dpll_core_h13x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* usb_otg_ss4 */
+static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
+ .name = "usb_otg_ss4",
+ .class = &dra7xx_usb_otg_ss_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "dpll_core_h13x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'vcp' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
+ .name = "vcp",
+};
+
+/* vcp1 */
+static struct omap_hwmod dra7xx_vcp1_hwmod = {
+ .name = "vcp1",
+ .class = &dra7xx_vcp_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* vcp2 */
+static struct omap_hwmod dra7xx_vcp2_hwmod = {
+ .name = "vcp2",
+ .class = &dra7xx_vcp_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'vip' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
+ .name = "vip",
+ .sysc = &dra7xx_vip_sysc,
+};
+
+/* vip1 */
+static struct omap_hwmod dra7xx_vip1_hwmod = {
+ .name = "vip1",
+ .class = &dra7xx_vip_hwmod_class,
+ .clkdm_name = "cam_clkdm",
+ .main_clk = "vip1_gclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* vip2 */
+static struct omap_hwmod dra7xx_vip2_hwmod = {
+ .name = "vip2",
+ .class = &dra7xx_vip_hwmod_class,
+ .clkdm_name = "cam_clkdm",
+ .main_clk = "vip2_gclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* vip3 */
+static struct omap_hwmod dra7xx_vip3_hwmod = {
+ .name = "vip3",
+ .class = &dra7xx_vip_hwmod_class,
+ .clkdm_name = "cam_clkdm",
+ .main_clk = "vip3_gclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'vpe' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
+ .name = "vpe",
+ .sysc = &dra7xx_vpe_sysc,
+};
+
+/* vpe */
+static struct omap_hwmod dra7xx_vpe_hwmod = {
+ .name = "vpe",
+ .class = &dra7xx_vpe_hwmod_class,
+ .clkdm_name = "vpe_clkdm",
+ .main_clk = "dpll_core_h23x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'wd_timer' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+ .sysc = &dra7xx_wd_timer_sysc,
+ .pre_shutdown = &omap2_wd_timer_disable,
+ .reset = &omap2_wd_timer_reset,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_irq_info dra7xx_wd_timer2_irqs[] = {
+ { .irq = 80 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+ .class = &dra7xx_wd_timer_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .mpu_irqs = dra7xx_wd_timer2_irqs,
+ .main_clk = "sys_32k_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/*
+ * Interfaces
+ */
+
+static struct omap_hwmod_addr_space dra7xx_dmm_addrs[] = {
+ {
+ .pa_start = 0x4e000000,
+ .pa_end = 0x4e0007ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_dmm_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dmm_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+/* dmm -> emif_ocp_fw */
+static struct omap_hwmod_ocp_if dra7xx_dmm__emif_ocp_fw = {
+ .master = &dra7xx_dmm_hwmod,
+ .slave = &dra7xx_emif_ocp_fw_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> emif_ocp_fw */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__emif_ocp_fw = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_emif_ocp_fw_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_instr */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
+ .master = &dra7xx_l3_main_2_hwmod,
+ .slave = &dra7xx_l3_instr_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ocp_wp_noc -> l3_instr */
+static struct omap_hwmod_ocp_if dra7xx_ocp_wp_noc__l3_instr = {
+ .master = &dra7xx_ocp_wp_noc_hwmod,
+ .slave = &dra7xx_l3_instr_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_l3_main_1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_l3_main_1_addrs[] = {
+ {
+ .pa_start = 0x44000000,
+ .pa_end = 0x44805fff,
+ },
+ { }
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
+ .master = &dra7xx_mpu_hwmod,
+ .slave = &dra7xx_l3_main_1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_l3_main_1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space dra7xx_l3_main_2_addrs[] = {
+ {
+ .pa_start = 0x45000000,
+ .pa_end = 0x4500afff,
+ },
+ { }
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l3_main_2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_l3_main_2_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_l3_main_2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_cfg_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_per1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_per1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_per2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_per2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_per3 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_per3_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_wkup */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_wkup_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if dra7xx_mpu__mpu_private = {
+ .master = &dra7xx_mpu_hwmod,
+ .slave = &dra7xx_mpu_private_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> ocp_wp_noc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_2__ocp_wp_noc = {
+ .master = &dra7xx_l3_main_2_hwmod,
+ .slave = &dra7xx_ocp_wp_noc_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_ocp_wp_noc_addrs[] = {
+ {
+ .pa_start = 0x4a102000,
+ .pa_end = 0x4a10207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> ocp_wp_noc */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp_wp_noc = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_ocp_wp_noc_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_ocp_wp_noc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4_per2 -> atl */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_atl_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_bb2d_addrs[] = {
+ {
+ .pa_start = 0x59000000,
+ .pa_end = 0x590007ff,
+ },
+ { }
+};
+
+/* l3_main_1 -> bb2d */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_bb2d_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_bb2d_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_counter_32k_addrs[] = {
+ {
+ .pa_start = 0x4ae04000,
+ .pa_end = 0x4ae0403f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_counter_32k_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_counter_32k_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_ctrl_module_wkup_addrs[] = {
+ {
+ .name = "avatar_control_wkup_ocpintf",
+ .pa_start = 0x4ae0c100,
+ .pa_end = 0x4ae0c8ff,
+ },
+ {
+ .name = "avatar_control_wkup_pad_ocpintf",
+ .pa_start = 0x4ae0c5a0,
+ .pa_end = 0x4ae0c61f,
+ },
+ { }
+};
+
+/* l4_wkup -> ctrl_module_wkup */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_ctrl_module_wkup_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_ctrl_module_wkup_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> dcan1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_dcan1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> dcan2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_dcan2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
+ {
+ .pa_start = 0x4a056000,
+ .pa_end = 0x4a056fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_dma_system_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dma_system_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
+ {
+ .name = "family",
+ .pa_start = 0x58000000,
+ .pa_end = 0x5800007f,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "pllctrl1",
+ .pa_start = 0x58004000,
+ .pa_end = 0x5800433f,
+ },
+ {
+ .name = "pllctrl2",
+ .pa_start = 0x58005000,
+ .pa_end = 0x5800533f,
+ },
+};
+
+/* l3_main_1 -> dss */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_dss_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
+ {
+ .name = "dispc",
+ .pa_start = 0x58001000,
+ .pa_end = 0x58001fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_1 -> dispc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_dss_dispc_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dss_dispc_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
+ {
+ .name = "hdmi_wp",
+ .pa_start = 0x58040000,
+ .pa_end = 0x580400ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "pllctrl",
+ .pa_start = 0x58040200,
+ .pa_end = 0x5804023f,
+ },
+ {
+ .name = "hdmitxphy",
+ .pa_start = 0x58040300,
+ .pa_end = 0x5804033f,
+ },
+ {
+ .name = "hdmi_core",
+ .pa_start = 0x58060000,
+ .pa_end = 0x58078fff,
+ },
+ {
+ .name = "deshdcp",
+ .pa_start = 0x58007000,
+ .pa_end = 0x5800707f,
+ },
+ { }
+};
+
+/* l3_main_1 -> dispc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_dss_hdmi_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dss_hdmi_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
+ {
+ .pa_start = 0x48078000,
+ .pa_end = 0x48078fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> elm */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_elm_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_elm_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* emif_ocp_fw -> emif1 */
+static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif1 = {
+ .master = &dra7xx_emif_ocp_fw_hwmod,
+ .slave = &dra7xx_emif1_hwmod,
+ .clk = "dpll_ddr_h11x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_emif1_addrs[] = {
+ {
+ .pa_start = 0x4c000000,
+ .pa_end = 0x4c0003ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if dra7xx_mpu__emif1 = {
+ .master = &dra7xx_mpu_hwmod,
+ .slave = &dra7xx_emif1_hwmod,
+ .clk = "dpll_ddr_h11x2_ck",
+ .addr = dra7xx_emif1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* emif_ocp_fw -> emif2 */
+static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif2 = {
+ .master = &dra7xx_emif_ocp_fw_hwmod,
+ .slave = &dra7xx_emif2_hwmod,
+ .clk = "dpll_ddr_h11x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_emif2_addrs[] = {
+ {
+ .pa_start = 0x4d000000,
+ .pa_end = 0x4d0003ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if dra7xx_mpu__emif2 = {
+ .master = &dra7xx_mpu_hwmod,
+ .slave = &dra7xx_emif2_hwmod,
+ .clk = "dpll_ddr_h11x2_ck",
+ .addr = dra7xx_emif2_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x4ae10000,
+ .pa_end = 0x4ae101ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_gpio1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x48055000,
+ .pa_end = 0x480551ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x48057000,
+ .pa_end = 0x480571ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio4_addrs[] = {
+ {
+ .pa_start = 0x48059000,
+ .pa_end = 0x480591ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio5_addrs[] = {
+ {
+ .pa_start = 0x4805b000,
+ .pa_end = 0x4805b1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio6_addrs[] = {
+ {
+ .pa_start = 0x4805d000,
+ .pa_end = 0x4805d1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio7_addrs[] = {
+ {
+ .pa_start = 0x48051000,
+ .pa_end = 0x480511ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio8_addrs[] = {
+ {
+ .pa_start = 0x48053000,
+ .pa_end = 0x480531ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
+ {
+ .pa_start = 0x50000000,
+ .pa_end = 0x500003ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> gpmc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_gpmc_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpmc_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
+ {
+ .pa_start = 0x480b2000,
+ .pa_end = 0x480b201f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> hdq1w */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_hdq1w_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_hdq1w_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c1_addrs[] = {
+ {
+ .pa_start = 0x48070000,
+ .pa_end = 0x480700ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c2_addrs[] = {
+ {
+ .pa_start = 0x48072000,
+ .pa_end = 0x480720ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c3_addrs[] = {
+ {
+ .pa_start = 0x48060000,
+ .pa_end = 0x480600ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c4_addrs[] = {
+ {
+ .pa_start = 0x4807a000,
+ .pa_end = 0x4807a0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c5_addrs[] = {
+ {
+ .pa_start = 0x4807c000,
+ .pa_end = 0x4807c0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox1_addrs[] = {
+ {
+ .pa_start = 0x4a0f4000,
+ .pa_end = 0x4a0f41ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> mailbox1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_mailbox1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox2_addrs[] = {
+ {
+ .pa_start = 0x4883a000,
+ .pa_end = 0x4883a1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox3_addrs[] = {
+ {
+ .pa_start = 0x4883c000,
+ .pa_end = 0x4883c1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox4_addrs[] = {
+ {
+ .pa_start = 0x4883e000,
+ .pa_end = 0x4883e1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox5_addrs[] = {
+ {
+ .pa_start = 0x48840000,
+ .pa_end = 0x488401ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox6_addrs[] = {
+ {
+ .pa_start = 0x48842000,
+ .pa_end = 0x488421ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox7_addrs[] = {
+ {
+ .pa_start = 0x48844000,
+ .pa_end = 0x488441ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox8_addrs[] = {
+ {
+ .pa_start = 0x48846000,
+ .pa_end = 0x488461ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox9_addrs[] = {
+ {
+ .pa_start = 0x4885e000,
+ .pa_end = 0x4885e1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox9 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox9_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox10_addrs[] = {
+ {
+ .pa_start = 0x48860000,
+ .pa_end = 0x488601ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox10 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox10_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox11_addrs[] = {
+ {
+ .pa_start = 0x48862000,
+ .pa_end = 0x488621ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox11 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox11_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox12_addrs[] = {
+ {
+ .pa_start = 0x48864000,
+ .pa_end = 0x488641ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox12 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox12_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox12_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox13_addrs[] = {
+ {
+ .pa_start = 0x48802000,
+ .pa_end = 0x488021ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox13 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox13_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox13_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_mcasp1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp1_addrs[] = {
+ {
+ .pa_start = 0x48460000,
+ .pa_end = 0x484603ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp2_addrs[] = {
+ {
+ .pa_start = 0x48464000,
+ .pa_end = 0x484643ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> mcasp2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_mcasp2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp3_addrs[] = {
+ {
+ .pa_start = 0x48468000,
+ .pa_end = 0x484683ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> mcasp3 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_mcasp3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp4_addrs[] = {
+ {
+ .pa_start = 0x4846c000,
+ .pa_end = 0x4846c3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp5_addrs[] = {
+ {
+ .pa_start = 0x48470000,
+ .pa_end = 0x484703ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp6_addrs[] = {
+ {
+ .pa_start = 0x48474000,
+ .pa_end = 0x484743ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp7_addrs[] = {
+ {
+ .pa_start = 0x48478000,
+ .pa_end = 0x484783ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp8_addrs[] = {
+ {
+ .pa_start = 0x4847c000,
+ .pa_end = 0x4847c3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcspi1_addrs[] = {
+ {
+ .pa_start = 0x48098000,
+ .pa_end = 0x480981ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mcspi1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mcspi1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcspi1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcspi2_addrs[] = {
+ {
+ .pa_start = 0x4809a000,
+ .pa_end = 0x4809a1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mcspi2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mcspi2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcspi2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcspi3_addrs[] = {
+ {
+ .pa_start = 0x480b8000,
+ .pa_end = 0x480b81ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mcspi3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mcspi3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcspi3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcspi4_addrs[] = {
+ {
+ .pa_start = 0x480ba000,
+ .pa_end = 0x480ba1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mcspi4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mcspi4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcspi4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mmc1_addrs[] = {
+ {
+ .pa_start = 0x4809c000,
+ .pa_end = 0x4809c3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mmc1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mmc1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mmc1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mmc2_addrs[] = {
+ {
+ .pa_start = 0x480b4000,
+ .pa_end = 0x480b43ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mmc2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mmc2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mmc2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mmc3_addrs[] = {
+ {
+ .pa_start = 0x480ad000,
+ .pa_end = 0x480ad3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mmc3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mmc3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mmc3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mmc4_addrs[] = {
+ {
+ .pa_start = 0x480d1000,
+ .pa_end = 0x480d13ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mmc4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mmc4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mmc4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mpu_addrs[] = {
+ {
+ .pa_start = 0x47000000,
+ .pa_end = 0x482af27f,
+ },
+ { }
+};
+
+/* l4_cfg -> mpu */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_mpu_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> ocmc_ram1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram1 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_ocmc_ram1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> ocmc_ram2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_ocmc_ram2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> ocmc_ram3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_ocmc_ram3_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> ocmc_rom */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__ocmc_rom = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_ocmc_rom_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
+ {
+ .pa_start = 0x4a080000,
+ .pa_end = 0x4a08001f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> ocp2scp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_ocp2scp1_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_ocp2scp1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_pruss1_addrs[] = {
+ {
+ .name = "u_intc",
+ .pa_start = 0x4b220000,
+ .pa_end = 0x4b221fff,
+ },
+ {
+ .name = "u_pru0_ctrl",
+ .pa_start = 0x4b222000,
+ .pa_end = 0x4b22203f,
+ },
+ {
+ .name = "u_pru0_debug",
+ .pa_start = 0x4b222400,
+ .pa_end = 0x4b2224ff,
+ },
+ {
+ .name = "u_pru1_ctrl",
+ .pa_start = 0x4b224000,
+ .pa_end = 0x4b22403f,
+ },
+ {
+ .name = "u_pru1_debug",
+ .pa_start = 0x4b224400,
+ .pa_end = 0x4b2244ff,
+ },
+ {
+ .name = "u_cfg",
+ .pa_start = 0x4b226000,
+ .pa_end = 0x4b22607f,
+ },
+ {
+ .name = "u_uart",
+ .pa_start = 0x4b228000,
+ .pa_end = 0x4b22803f,
+ },
+ {
+ .name = "u_iep",
+ .pa_start = 0x4b22e000,
+ .pa_end = 0x4b22e3ff,
+ },
+ {
+ .name = "u_ecap",
+ .pa_start = 0x4b230000,
+ .pa_end = 0x4b23007f,
+ },
+ {
+ .name = "u_mii_rt_cfg",
+ .pa_start = 0x4b232000,
+ .pa_end = 0x4b23207f,
+ },
+ {
+ .name = "u_mii_mdio",
+ .pa_start = 0x4b232400,
+ .pa_end = 0x4b2324ff,
+ },
+ { }
+};
+
+/* l3_main_1 -> pruss1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pruss1_hwmod,
+ .clk = "dpll_gmac_h13x2_ck",
+ .addr = dra7xx_pruss1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_pruss2_addrs[] = {
+ {
+ .name = "u_intc",
+ .pa_start = 0x4b2a0000,
+ .pa_end = 0x4b2a1fff,
+ },
+ {
+ .name = "u_pru0_ctrl",
+ .pa_start = 0x4b2a2000,
+ .pa_end = 0x4b2a203f,
+ },
+ {
+ .name = "u_pru0_debug",
+ .pa_start = 0x4b2a2400,
+ .pa_end = 0x4b2a24ff,
+ },
+ {
+ .name = "u_pru1_ctrl",
+ .pa_start = 0x4b2a4000,
+ .pa_end = 0x4b2a403f,
+ },
+ {
+ .name = "u_pru1_debug",
+ .pa_start = 0x4b2a4400,
+ .pa_end = 0x4b2a44ff,
+ },
+ {
+ .name = "u_cfg",
+ .pa_start = 0x4b2a6000,
+ .pa_end = 0x4b2a607f,
+ },
+ {
+ .name = "u_uart",
+ .pa_start = 0x4b2a8000,
+ .pa_end = 0x4b2a803f,
+ },
+ {
+ .name = "u_iep",
+ .pa_start = 0x4b2ae000,
+ .pa_end = 0x4b2ae3ff,
+ },
+ {
+ .name = "u_ecap",
+ .pa_start = 0x4b2b0000,
+ .pa_end = 0x4b2b007f,
+ },
+ {
+ .name = "u_mii_rt_cfg",
+ .pa_start = 0x4b2b2000,
+ .pa_end = 0x4b2b207f,
+ },
+ {
+ .name = "u_mii_mdio",
+ .pa_start = 0x4b2b2400,
+ .pa_end = 0x4b2b24ff,
+ },
+ { }
+};
+
+/* l3_main_1 -> pruss2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pruss2_hwmod,
+ .clk = "dpll_gmac_h13x2_ck",
+ .addr = dra7xx_pruss2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> pwmss1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss1 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_pwmss1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> pwmss2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss2 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_pwmss2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> pwmss3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss3 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_pwmss3_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
+ {
+ .pa_start = 0x4b300000,
+ .pa_end = 0x4b30007f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> qspi */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_qspi_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_qspi_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_rtcss_addrs[] = {
+ {
+ .pa_start = 0x48838000,
+ .pa_end = 0x488380ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> rtcss */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_rtcss_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_rtcss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
+ {
+ .name = "ahci",
+ .pa_start = 0x4a140000,
+ .pa_end = 0x4a1401ff,
+ },
+ {
+ .name = "sysc",
+ .pa_start = 0x4a141100,
+ .pa_end = 0x4a141107,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> sata */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_sata_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_sata_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
+ {
+ .pa_start = 0x4a0dd000,
+ .pa_end = 0x4a0dd07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_smartreflex_core_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_smartreflex_core_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_dspeve_addrs[] = {
+ {
+ .pa_start = 0x4a183000,
+ .pa_end = 0x4a18307f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_dspeve */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_dspeve = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_smartreflex_dspeve_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_smartreflex_dspeve_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_gpu_addrs[] = {
+ {
+ .pa_start = 0x4a185000,
+ .pa_end = 0x4a18507f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_gpu */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_gpu = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_smartreflex_gpu_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_smartreflex_gpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
+ {
+ .pa_start = 0x4a0d9000,
+ .pa_end = 0x4a0d907f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_smartreflex_mpu_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_smartreflex_mpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_cme */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_cme = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_cme_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_icm */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_icm = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_icm_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> spare_iva2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__spare_iva2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_spare_iva2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_safety1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety1 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_safety1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_safety2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety2 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_safety2_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_safety3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety3 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_safety3_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_safety4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety4 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_safety4_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_unknown2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown2 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_unknown2_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_unknown3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown3 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_unknown3_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> spare_unknown4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown4 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_spare_unknown4_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> spare_unknown5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown5 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_spare_unknown5_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> spare_unknown6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown6 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_spare_unknown6_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_videopll1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll1 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_videopll1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_videopll2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_videopll2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_videopll3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_videopll3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_sata2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_sata2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_sata2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> spare_smartreflex_rtc */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_rtc = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_spare_smartreflex_rtc_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> spare_smartreflex_sdram */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_sdram = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_spare_smartreflex_sdram_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> spare_smartreflex_wkup */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_wkup = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_spare_smartreflex_wkup_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
+ {
+ .pa_start = 0x4a0f6000,
+ .pa_end = 0x4a0f6fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_spinlock_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_spinlock_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer1_addrs[] = {
+ {
+ .pa_start = 0x4ae18000,
+ .pa_end = 0x4ae1807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_timer1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_timer1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer2_addrs[] = {
+ {
+ .pa_start = 0x48032000,
+ .pa_end = 0x4803207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer3_addrs[] = {
+ {
+ .pa_start = 0x48034000,
+ .pa_end = 0x4803407f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer4_addrs[] = {
+ {
+ .pa_start = 0x48036000,
+ .pa_end = 0x4803607f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer5_addrs[] = {
+ {
+ .pa_start = 0x48820000,
+ .pa_end = 0x4882007f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer6_addrs[] = {
+ {
+ .pa_start = 0x48822000,
+ .pa_end = 0x4882207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer7_addrs[] = {
+ {
+ .pa_start = 0x48824000,
+ .pa_end = 0x4882407f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer8_addrs[] = {
+ {
+ .pa_start = 0x48826000,
+ .pa_end = 0x4882607f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer9_addrs[] = {
+ {
+ .pa_start = 0x4803e000,
+ .pa_end = 0x4803e07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer9 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer9_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer10_addrs[] = {
+ {
+ .pa_start = 0x48086000,
+ .pa_end = 0x4808607f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer10 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer10_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer11_addrs[] = {
+ {
+ .pa_start = 0x48088000,
+ .pa_end = 0x4808807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer11 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer11_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer13_addrs[] = {
+ {
+ .pa_start = 0x48828000,
+ .pa_end = 0x4882807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer13 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer13_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer13_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer14_addrs[] = {
+ {
+ .pa_start = 0x4882a000,
+ .pa_end = 0x4882a07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer14 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer14_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer14_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer15_addrs[] = {
+ {
+ .pa_start = 0x4882c000,
+ .pa_end = 0x4882c07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer15 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer15_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer15_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer16_addrs[] = {
+ {
+ .pa_start = 0x4882e000,
+ .pa_end = 0x4882e07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer16 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer16_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer16_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart1_addrs[] = {
+ {
+ .pa_start = 0x4806a000,
+ .pa_end = 0x4806a0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart2_addrs[] = {
+ {
+ .pa_start = 0x4806c000,
+ .pa_end = 0x4806c0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart3_addrs[] = {
+ {
+ .pa_start = 0x48020000,
+ .pa_end = 0x480200ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart4_addrs[] = {
+ {
+ .pa_start = 0x4806e000,
+ .pa_end = 0x4806e0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart5_addrs[] = {
+ {
+ .pa_start = 0x48066000,
+ .pa_end = 0x480660ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart6_addrs[] = {
+ {
+ .pa_start = 0x48068000,
+ .pa_end = 0x480680ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart7_addrs[] = {
+ {
+ .pa_start = 0x48420000,
+ .pa_end = 0x484200ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> uart7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_uart7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart8_addrs[] = {
+ {
+ .pa_start = 0x48422000,
+ .pa_end = 0x484220ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> uart8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_uart8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart9_addrs[] = {
+ {
+ .pa_start = 0x48424000,
+ .pa_end = 0x484240ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> uart9 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_uart9_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart10_addrs[] = {
+ {
+ .pa_start = 0x4ae2b000,
+ .pa_end = 0x4ae2b0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> uart10 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_uart10_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_uart10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_usb_otg_ss1_hwmod,
+ .clk = "dpll_core_h13x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_usb_otg_ss2_hwmod,
+ .clk = "dpll_core_h13x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_usb_otg_ss3_hwmod,
+ .clk = "dpll_core_h13x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_usb_otg_ss4_hwmod,
+ .clk = "dpll_core_h13x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> vcp1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_vcp1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> vcp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_vcp1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> vcp2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_vcp2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> vcp2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_vcp2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_vip1_addrs[] = {
+ {
+ .name = "vip_top_level",
+ .pa_start = 0x48970000,
+ .pa_end = 0x489701ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "vip_slice0_parser",
+ .pa_start = 0x48975500,
+ .pa_end = 0x489755ff,
+ },
+ {
+ .name = "vip_slice0_csc",
+ .pa_start = 0x48975700,
+ .pa_end = 0x4897571f,
+ },
+ {
+ .name = "vip_slice0_sc",
+ .pa_start = 0x48975800,
+ .pa_end = 0x4897587f,
+ },
+ {
+ .name = "vip_slice1_parser",
+ .pa_start = 0x48975a00,
+ .pa_end = 0x48975aff,
+ },
+ {
+ .name = "vip_slice1_csc",
+ .pa_start = 0x48975c00,
+ .pa_end = 0x48975c1f,
+ },
+ {
+ .name = "vip_slice1_sc",
+ .pa_start = 0x48975d00,
+ .pa_end = 0x48975d7f,
+ },
+ {
+ .name = "vip_vpdma",
+ .pa_start = 0x4897d000,
+ .pa_end = 0x4897d3ff,
+ },
+ { }
+};
+
+/* l4_per3 -> vip1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_vip1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_vip1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_vip2_addrs[] = {
+ {
+ .name = "vip_top_level",
+ .pa_start = 0x48990000,
+ .pa_end = 0x489901ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "vip_slice0_parser",
+ .pa_start = 0x48995500,
+ .pa_end = 0x489955ff,
+ },
+ {
+ .name = "vip_slice0_csc",
+ .pa_start = 0x48995700,
+ .pa_end = 0x4899571f,
+ },
+ {
+ .name = "vip_slice0_sc",
+ .pa_start = 0x48995800,
+ .pa_end = 0x4899587f,
+ },
+ {
+ .name = "vip_slice1_parser",
+ .pa_start = 0x48995a00,
+ .pa_end = 0x48995aff,
+ },
+ {
+ .name = "vip_slice1_csc",
+ .pa_start = 0x48995c00,
+ .pa_end = 0x48995c1f,
+ },
+ {
+ .name = "vip_slice1_sc",
+ .pa_start = 0x48995d00,
+ .pa_end = 0x48995d7f,
+ },
+ {
+ .name = "vip_vpdma",
+ .pa_start = 0x4899d000,
+ .pa_end = 0x4899d3ff,
+ },
+ { }
+};
+
+/* l4_per3 -> vip2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_vip2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_vip2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_vip3_addrs[] = {
+ {
+ .name = "vip_top_level",
+ .pa_start = 0x489b0000,
+ .pa_end = 0x489b01ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "vip_slice0_parser",
+ .pa_start = 0x489b5500,
+ .pa_end = 0x489b55ff,
+ },
+ {
+ .name = "vip_slice0_csc",
+ .pa_start = 0x489b5700,
+ .pa_end = 0x489b571f,
+ },
+ {
+ .name = "vip_slice0_sc",
+ .pa_start = 0x489b5800,
+ .pa_end = 0x489b587f,
+ },
+ {
+ .name = "vip_slice1_parser",
+ .pa_start = 0x489b5a00,
+ .pa_end = 0x489b5aff,
+ },
+ {
+ .name = "vip_slice1_csc",
+ .pa_start = 0x489b5c00,
+ .pa_end = 0x489b5c1f,
+ },
+ {
+ .name = "vip_slice1_sc",
+ .pa_start = 0x489b5d00,
+ .pa_end = 0x489b5d7f,
+ },
+ {
+ .name = "vip_vpdma",
+ .pa_start = 0x489bd000,
+ .pa_end = 0x489bd3ff,
+ },
+ { }
+};
+
+/* l4_per3 -> vip3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_vip3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_vip3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_vpe_addrs[] = {
+ {
+ .name = "vpe0_vayu_register_inst_0",
+ .pa_start = 0x489d0000,
+ .pa_end = 0x489d01ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "dss_chr_us_register_inst_0",
+ .pa_start = 0x489d0300,
+ .pa_end = 0x489d033f,
+ },
+ {
+ .name = "dss_chr_us_register_inst_1",
+ .pa_start = 0x489d0400,
+ .pa_end = 0x489d043f,
+ },
+ {
+ .name = "dss_chr_us_register_inst_2",
+ .pa_start = 0x489d0500,
+ .pa_end = 0x489d053f,
+ },
+ {
+ .name = "dss_dei_register_inst_0",
+ .pa_start = 0x489d0600,
+ .pa_end = 0x489d063f,
+ },
+ {
+ .name = "dss_sc_m_register_inst_0",
+ .pa_start = 0x489d0700,
+ .pa_end = 0x489d077f,
+ },
+ {
+ .name = "dss_csc_register_inst_0",
+ .pa_start = 0x489d5700,
+ .pa_end = 0x489d571f,
+ },
+ {
+ .name = "hd_dss_centaurus_vpdma_register_inst_0",
+ .pa_start = 0x489dd000,
+ .pa_end = 0x489dd3ff,
+ },
+ { }
+};
+
+/* l4_per3 -> vpe */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_vpe_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_vpe_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_wd_timer2_addrs[] = {
+ {
+ .pa_start = 0x4ae14000,
+ .pa_end = 0x4ae1407f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_wd_timer2_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_wd_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
+ &dra7xx_l3_main_1__dmm,
+ &dra7xx_dmm__emif_ocp_fw,
+ &dra7xx_l4_cfg__emif_ocp_fw,
+ &dra7xx_l3_main_2__l3_instr,
+ &dra7xx_ocp_wp_noc__l3_instr,
+ &dra7xx_l4_cfg__l3_main_1,
+ &dra7xx_mpu__l3_main_1,
+ &dra7xx_l3_main_1__l3_main_2,
+ &dra7xx_l4_cfg__l3_main_2,
+ &dra7xx_l3_main_1__l4_cfg,
+ &dra7xx_l3_main_1__l4_per1,
+ &dra7xx_l3_main_1__l4_per2,
+ &dra7xx_l3_main_1__l4_per3,
+ &dra7xx_l3_main_1__l4_wkup,
+ &dra7xx_mpu__mpu_private,
+ &dra7xx_l3_main_2__ocp_wp_noc,
+ &dra7xx_l4_cfg__ocp_wp_noc,
+ &dra7xx_l4_per2__atl,
+ &dra7xx_l3_main_1__bb2d,
+ &dra7xx_l4_wkup__counter_32k,
+ &dra7xx_l4_wkup__ctrl_module_wkup,
+ &dra7xx_l4_wkup__dcan1,
+ &dra7xx_l4_per2__dcan2,
+ &dra7xx_l4_cfg__dma_system,
+ &dra7xx_l3_main_1__dss,
+ &dra7xx_l3_main_1__dispc,
+ &dra7xx_l3_main_1__hdmi,
+ &dra7xx_l4_per1__elm,
+ &dra7xx_emif_ocp_fw__emif1,
+ &dra7xx_mpu__emif1,
+ &dra7xx_emif_ocp_fw__emif2,
+ &dra7xx_mpu__emif2,
+ &dra7xx_l4_wkup__gpio1,
+ &dra7xx_l4_per1__gpio2,
+ &dra7xx_l4_per1__gpio3,
+ &dra7xx_l4_per1__gpio4,
+ &dra7xx_l4_per1__gpio5,
+ &dra7xx_l4_per1__gpio6,
+ &dra7xx_l4_per1__gpio7,
+ &dra7xx_l4_per1__gpio8,
+ &dra7xx_l3_main_1__gpmc,
+ &dra7xx_l4_per1__hdq1w,
+ &dra7xx_l4_per1__i2c1,
+ &dra7xx_l4_per1__i2c2,
+ &dra7xx_l4_per1__i2c3,
+ &dra7xx_l4_per1__i2c4,
+ &dra7xx_l4_per1__i2c5,
+ &dra7xx_l4_cfg__mailbox1,
+ &dra7xx_l4_per3__mailbox2,
+ &dra7xx_l4_per3__mailbox3,
+ &dra7xx_l4_per3__mailbox4,
+ &dra7xx_l4_per3__mailbox5,
+ &dra7xx_l4_per3__mailbox6,
+ &dra7xx_l4_per3__mailbox7,
+ &dra7xx_l4_per3__mailbox8,
+ &dra7xx_l4_per3__mailbox9,
+ &dra7xx_l4_per3__mailbox10,
+ &dra7xx_l4_per3__mailbox11,
+ &dra7xx_l4_per3__mailbox12,
+ &dra7xx_l4_per3__mailbox13,
+ &dra7xx_l3_main_1__mcasp1,
+ &dra7xx_l4_per2__mcasp1,
+ &dra7xx_l3_main_1__mcasp2,
+ &dra7xx_l3_main_1__mcasp3,
+ &dra7xx_l4_per2__mcasp4,
+ &dra7xx_l4_per2__mcasp5,
+ &dra7xx_l4_per2__mcasp6,
+ &dra7xx_l4_per2__mcasp7,
+ &dra7xx_l4_per2__mcasp8,
+ &dra7xx_l4_per1__mcspi1,
+ &dra7xx_l4_per1__mcspi2,
+ &dra7xx_l4_per1__mcspi3,
+ &dra7xx_l4_per1__mcspi4,
+ &dra7xx_l4_per1__mmc1,
+ &dra7xx_l4_per1__mmc2,
+ &dra7xx_l4_per1__mmc3,
+ &dra7xx_l4_per1__mmc4,
+ &dra7xx_l4_cfg__mpu,
+ &dra7xx_l4_per3__ocmc_ram1,
+ &dra7xx_l4_per3__ocmc_ram2,
+ &dra7xx_l4_per3__ocmc_ram3,
+ &dra7xx_l3_main_1__ocmc_rom,
+ &dra7xx_l4_cfg__ocp2scp1,
+ &dra7xx_l3_main_1__pruss1,
+ &dra7xx_l3_main_1__pruss2,
+ &dra7xx_l4_per2__pwmss1,
+ &dra7xx_l4_per2__pwmss2,
+ &dra7xx_l4_per2__pwmss3,
+ &dra7xx_l3_main_1__qspi,
+ &dra7xx_l4_per3__rtcss,
+ &dra7xx_l4_cfg__sata,
+ &dra7xx_l4_cfg__smartreflex_core,
+ &dra7xx_l4_cfg__smartreflex_dspeve,
+ &dra7xx_l4_cfg__smartreflex_gpu,
+ &dra7xx_l4_cfg__smartreflex_mpu,
+ &dra7xx_l4_per3__spare_cme,
+ &dra7xx_l4_per3__spare_icm,
+ &dra7xx_l3_main_1__spare_iva2,
+ &dra7xx_l4_wkup__spare_safety1,
+ &dra7xx_l4_wkup__spare_safety2,
+ &dra7xx_l4_wkup__spare_safety3,
+ &dra7xx_l4_wkup__spare_safety4,
+ &dra7xx_l4_wkup__spare_unknown2,
+ &dra7xx_l4_wkup__spare_unknown3,
+ &dra7xx_l4_per2__spare_unknown4,
+ &dra7xx_l4_per2__spare_unknown5,
+ &dra7xx_l4_per2__spare_unknown6,
+ &dra7xx_l4_per3__spare_videopll1,
+ &dra7xx_l4_per3__spare_videopll2,
+ &dra7xx_l4_per3__spare_videopll3,
+ &dra7xx_l4_per3__spare_sata2,
+ &dra7xx_l4_cfg__spare_smartreflex_rtc,
+ &dra7xx_l4_cfg__spare_smartreflex_sdram,
+ &dra7xx_l4_cfg__spare_smartreflex_wkup,
+ &dra7xx_l4_cfg__spinlock,
+ &dra7xx_l4_wkup__timer1,
+ &dra7xx_l4_per1__timer2,
+ &dra7xx_l4_per1__timer3,
+ &dra7xx_l4_per1__timer4,
+ &dra7xx_l4_per3__timer5,
+ &dra7xx_l4_per3__timer6,
+ &dra7xx_l4_per3__timer7,
+ &dra7xx_l4_per3__timer8,
+ &dra7xx_l4_per1__timer9,
+ &dra7xx_l4_per1__timer10,
+ &dra7xx_l4_per1__timer11,
+ &dra7xx_l4_per3__timer13,
+ &dra7xx_l4_per3__timer14,
+ &dra7xx_l4_per3__timer15,
+ &dra7xx_l4_per3__timer16,
+ &dra7xx_l4_per1__uart1,
+ &dra7xx_l4_per1__uart2,
+ &dra7xx_l4_per1__uart3,
+ &dra7xx_l4_per1__uart4,
+ &dra7xx_l4_per1__uart5,
+ &dra7xx_l4_per1__uart6,
+ &dra7xx_l4_per2__uart7,
+ &dra7xx_l4_per2__uart8,
+ &dra7xx_l4_per2__uart9,
+ &dra7xx_l4_wkup__uart10,
+ &dra7xx_l4_per3__usb_otg_ss1,
+ &dra7xx_l4_per3__usb_otg_ss2,
+ &dra7xx_l4_per3__usb_otg_ss3,
+ &dra7xx_l4_per3__usb_otg_ss4,
+ &dra7xx_l3_main_1__vcp1,
+ &dra7xx_l4_per2__vcp1,
+ &dra7xx_l3_main_1__vcp2,
+ &dra7xx_l4_per2__vcp2,
+ &dra7xx_l4_per3__vip1,
+ &dra7xx_l4_per3__vip2,
+ &dra7xx_l4_per3__vip3,
+ &dra7xx_l4_per3__vpe,
+ &dra7xx_l4_wkup__wd_timer2,
+ NULL,
+};
+
+int __init dra7xx_hwmod_init(void)
+{
+ omap_hwmod_init();
+ return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
+}
index 0265ed2802c60ffa02e5f52ea3938790154ec4d6..2389682d3d8a8e576969c5efe7363ca098d37738 100644 (file)
};
static LIST_HEAD(pwrst_list);
+u32 cpu_suspend_state;
+u32 pwrdm_next_state;
#ifdef CONFIG_SUSPEND
static int omap4_pm_suspend(void)
* domain CSWR is not supported by hardware.
* More details can be found in OMAP4430 TRM section 4.3.4.2.
*/
- omap4_mpuss_enter_lowpower(cpu_id, PWRDM_FUNC_PWRST_OFF);
+ omap4_mpuss_enter_lowpower(cpu_id, cpu_suspend_state);
/* Restore next powerdomain state */
list_for_each_entry(pwrst, &pwrst_list, node) {
* XXX This should be replaced by explicit lists of
* powerdomains with specific powerstates to set
*/
- pwrst->next_fpwrst = PWRDM_FUNC_PWRST_CSWR;
+ pwrst->next_fpwrst = pwrdm_next_state;
if (!pwrdm_supports_fpwrst(pwrdm, pwrst->next_fpwrst))
pwrst->next_fpwrst = PWRDM_FUNC_PWRST_ON;
list_add(&pwrst->node, &pwrst_list);
if (cpu_is_omap44xx())
ret = omap4_init_static_deps();
- else if (soc_is_omap54xx())
+ else if (soc_is_omap54xx() || soc_is_dra7xx())
ret = omap5_init_static_deps();
if (ret) {
if (cpu_is_omap44xx() || soc_is_omap54xx())
omap4_idle_init();
+ if (soc_is_dra7xx()) {
+ cpu_suspend_state = PWRDM_FUNC_PWRST_ON;
+ pwrdm_next_state = PWRDM_FUNC_PWRST_ON;
+ } else {
+ cpu_suspend_state = PWRDM_FUNC_PWRST_OFF;
+ pwrdm_next_state = PWRDM_FUNC_PWRST_CSWR;
+ }
+
err2:
return ret;
}
index 72d6ce042edc2a02da2af948f90328439403fb23..6aa4d572d1461ad9507bebb7c89e81ec6d934f62 100644 (file)
if (_pwrdm_lookup(pwrdm->name))
return -EEXIST;
+ if (arch_pwrdm && arch_pwrdm->pwrdm_has_voltdm)
+ if (!arch_pwrdm->pwrdm_has_voltdm())
+ goto skip_voltdm;
+
voltdm = voltdm_lookup(pwrdm->voltdm.name);
if (!voltdm) {
pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
pwrdm->voltdm.ptr = voltdm;
INIT_LIST_HEAD(&pwrdm->voltdm_node);
voltdm_add_pwrdm(voltdm, pwrdm);
- spin_lock_init(&pwrdm->_lock);
+skip_voltdm:
+ spin_lock_init(&pwrdm->_lock);
list_add(&pwrdm->node, &pwrdm_list);
/* Initialize the powerdomain's state counter */
index b8f3dbf564c13d0c00e3a1d689cb681702973875..55c1201c1943e045e9448b0d41c0943f434e272e 100644 (file)
* @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
* @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
* @pwrdm_wait_transition: Wait for a pd state transition to complete
+ * @pwrdm_has_voltdm; Check if a voltdm association is needed
*/
struct pwrdm_ops {
int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+ int (*pwrdm_has_voltdm)(void);
};
int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern void omap54xx_powerdomains_init(void);
+extern void dra7xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
--- /dev/null
@@ -0,0 +1,477 @@
+/*
+ * DRA7xx Power domains framework
+ *
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prm-regbits-7xx.h"
+#include "prm7xx.h"
+#include "prcm_mpu7xx.h"
+
+/* iva_7xx_pwrdm: IVA-HD power domain */
+static struct powerdomain iva_7xx_pwrdm = {
+ .name = "iva_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_IVA_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 4,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* hwa_mem */
+ [1] = PWRSTS_OFF_RET, /* sl2_mem */
+ [2] = PWRSTS_OFF_RET, /* tcm1_mem */
+ [3] = PWRSTS_OFF_RET, /* tcm2_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* hwa_mem */
+ [1] = PWRSTS_OFF_RET, /* sl2_mem */
+ [2] = PWRSTS_OFF_RET, /* tcm1_mem */
+ [3] = PWRSTS_OFF_RET, /* tcm2_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* rtc_7xx_pwrdm: */
+static struct powerdomain rtc_7xx_pwrdm = {
+ .name = "rtc_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_RTC_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+};
+
+/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain custefuse_7xx_pwrdm = {
+ .name = "custefuse_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* ipu_7xx_pwrdm: Audio back end power domain */
+static struct powerdomain ipu_7xx_pwrdm = {
+ .name = "ipu_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_IPU_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* aessmem */
+ [1] = PWRSTS_OFF_RET, /* periphmem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* aessmem */
+ [1] = PWRSTS_OFF_RET, /* periphmem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dss_7xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_7xx_pwrdm = {
+ .name = "dss_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_DSS_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* dss_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* dss_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* l4per_7xx_pwrdm: Target peripherals power domain */
+static struct powerdomain l4per_7xx_pwrdm = {
+ .name = "l4per_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_L4PER_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* nonretained_bank */
+ [1] = PWRSTS_OFF_RET, /* retained_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* nonretained_bank */
+ [1] = PWRSTS_OFF_RET, /* retained_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* gpu_7xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gpu_7xx_pwrdm = {
+ .name = "gpu_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_GPU_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* gpu_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* gpu_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* wkupaon_7xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkupaon_7xx_pwrdm = {
+ .name = "wkupaon_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* wkup_bank */
+ },
+};
+
+/* core_7xx_pwrdm: CORE power domain */
+static struct powerdomain core_7xx_pwrdm = {
+ .name = "core_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_CORE_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 5,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [2] = PWRSTS_OFF_RET, /* core_other_bank */
+ [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
+ [4] = PWRSTS_OFF_RET, /* ipu_unicache */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [2] = PWRSTS_OFF_RET, /* core_other_bank */
+ [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
+ [4] = PWRSTS_OFF_RET, /* ipu_unicache */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
+static struct powerdomain coreaon_7xx_pwrdm = {
+ .name = "coreaon_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_COREAON_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+};
+
+/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_7xx_pwrdm = {
+ .name = "cpu0_pwrdm",
+ .voltdm = { .name = "mpu" },
+ .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
+ .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* cpu0_l1 */
+ },
+};
+
+/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_7xx_pwrdm = {
+ .name = "cpu1_pwrdm",
+ .voltdm = { .name = "mpu" },
+ .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
+ .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* cpu1_l1 */
+ },
+};
+
+/* vpe_7xx_pwrdm: */
+static struct powerdomain vpe_7xx_pwrdm = {
+ .name = "vpe_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_VPE_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* vpe_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* vpe_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_7xx_pwrdm = {
+ .name = "mpu_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_MPU_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* mpu_l2 */
+ [1] = PWRSTS_RET, /* mpu_ram */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* mpu_l2 */
+ [1] = PWRSTS_OFF_RET, /* mpu_ram */
+ },
+};
+
+/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
+static struct powerdomain l3init_7xx_pwrdm = {
+ .name = "l3init_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_L3INIT_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* gmac_bank */
+ [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
+ [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* gmac_bank */
+ [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
+ [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve3_7xx_pwrdm: */
+static struct powerdomain eve3_7xx_pwrdm = {
+ .name = "eve3_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EVE3_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* eve3_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* eve3_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* emu_7xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_7xx_pwrdm = {
+ .name = "emu_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EMU_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* emu_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* emu_bank */
+ },
+};
+
+/* dsp2_7xx_pwrdm: */
+static struct powerdomain dsp2_7xx_pwrdm = {
+ .name = "dsp2_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_DSP2_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* dsp2_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* dsp2_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dsp1_7xx_pwrdm: Tesla processor power domain */
+static struct powerdomain dsp1_7xx_pwrdm = {
+ .name = "dsp1_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_DSP1_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* dsp1_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* dsp1_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cam_7xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_7xx_pwrdm = {
+ .name = "cam_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_CAM_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* vip_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* vip_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve4_7xx_pwrdm: */
+static struct powerdomain eve4_7xx_pwrdm = {
+ .name = "eve4_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EVE4_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* eve4_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* eve4_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve2_7xx_pwrdm: */
+static struct powerdomain eve2_7xx_pwrdm = {
+ .name = "eve2_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EVE2_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* eve2_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* eve2_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve1_7xx_pwrdm: */
+static struct powerdomain eve1_7xx_pwrdm = {
+ .name = "eve1_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EVE1_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* eve1_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* eve1_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/*
+ * The following power domains are not under SW control
+ *
+ * mpuaon
+ * mmaon
+ */
+
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_dra7xx[] __initdata = {
+ &iva_7xx_pwrdm,
+ &rtc_7xx_pwrdm,
+ &custefuse_7xx_pwrdm,
+ &ipu_7xx_pwrdm,
+ &dss_7xx_pwrdm,
+ &l4per_7xx_pwrdm,
+ &gpu_7xx_pwrdm,
+ &wkupaon_7xx_pwrdm,
+ &core_7xx_pwrdm,
+ &coreaon_7xx_pwrdm,
+ &cpu0_7xx_pwrdm,
+ &cpu1_7xx_pwrdm,
+ &vpe_7xx_pwrdm,
+ &mpu_7xx_pwrdm,
+ &l3init_7xx_pwrdm,
+ &eve3_7xx_pwrdm,
+ &emu_7xx_pwrdm,
+ &dsp2_7xx_pwrdm,
+ &dsp1_7xx_pwrdm,
+ &cam_7xx_pwrdm,
+ &eve4_7xx_pwrdm,
+ &eve2_7xx_pwrdm,
+ &eve1_7xx_pwrdm,
+ NULL
+};
+
+void __init dra7xx_powerdomains_init(void)
+{
+ pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+ pwrdm_register_pwrdms(powerdomains_dra7xx);
+ pwrdm_complete_init();
+}
index f429cdd5a118aa5ca3ea647b1ee3307b18c3bf20..4fea2cfdf2c3a8c08794baa169509c24ca158ba2 100644 (file)
#define OMAP54XX_SCRM_PARTITION 4
#define OMAP54XX_PRCM_MPU_PARTITION 5
+#define DRA7XX_PRM_PARTITION 1
+#define DRA7XX_CM_CORE_AON_PARTITION 2
+#define DRA7XX_CM_CORE_PARTITION 3
+#define DRA7XX_MPU_PRCM_PARTITION 5
+
/*
* OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
* IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * DRA7xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
+
+#define DRA7XX_PRCM_MPU_BASE 0x48243000
+
+#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
+ OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
+
+/* MPU_PRCM instances */
+#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
+#define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
+#define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
+#define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
+#define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
+#define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
+
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
+#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
+
+
+/* MPU_PRCM */
+
+/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
+#define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
+
+/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
+#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
+#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
+
+/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
+#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
+
+/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
+#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
+
+/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
+#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
+
+/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
+#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
+
+/* Function prototypes */
+# ifndef __ASSEMBLER__
+extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
+ s16 idx);
+# endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-7xx.h b/arch/arm/mach-omap2/prm-regbits-7xx.h
--- /dev/null
@@ -0,0 +1,6763 @@
+/*
+ * DRA7xx Power Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_7XX_H
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ABBOFF_ACT_SHIFT 1
+#define DRA7XX_ABBOFF_ACT_WIDTH 0x1
+#define DRA7XX_ABBOFF_ACT_MASK (1 << 1)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ABBOFF_SLEEP_SHIFT 2
+#define DRA7XX_ABBOFF_SLEEP_WIDTH 0x1
+#define DRA7XX_ABBOFF_SLEEP_MASK (1 << 2)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_ABB_DSPEVE_DONE_EN_SHIFT 29
+#define DRA7XX_ABB_DSPEVE_DONE_EN_WIDTH 0x1
+#define DRA7XX_ABB_DSPEVE_DONE_EN_MASK (1 << 29)
+
+/* Renamed from ABB_DSPEVE_DONE_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_ABB_DSPEVE_DONE_EN_30_30_SHIFT 30
+#define DRA7XX_ABB_DSPEVE_DONE_EN_30_30_WIDTH 0x1
+#define DRA7XX_ABB_DSPEVE_DONE_EN_30_30_MASK (1 << 30)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_ABB_DSPEVE_DONE_ST_SHIFT 29
+#define DRA7XX_ABB_DSPEVE_DONE_ST_WIDTH 0x1
+#define DRA7XX_ABB_DSPEVE_DONE_ST_MASK (1 << 29)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_ABB_GPU_DONE_EN_SHIFT 28
+#define DRA7XX_ABB_GPU_DONE_EN_WIDTH 0x1
+#define DRA7XX_ABB_GPU_DONE_EN_MASK (1 << 28)
+
+/* Renamed from ABB_GPU_DONE_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_ABB_GPU_DONE_EN_PRM_IRQENABLE_MPU_SHIFT 29
+#define DRA7XX_ABB_GPU_DONE_EN_PRM_IRQENABLE_MPU_WIDTH 0x1
+#define DRA7XX_ABB_GPU_DONE_EN_PRM_IRQENABLE_MPU_MASK (1 << 29)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_ABB_GPU_DONE_ST_SHIFT 28
+#define DRA7XX_ABB_GPU_DONE_ST_WIDTH 0x1
+#define DRA7XX_ABB_GPU_DONE_ST_MASK (1 << 28)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_ABB_IVA_DONE_EN_SHIFT 30
+#define DRA7XX_ABB_IVA_DONE_EN_WIDTH 0x1
+#define DRA7XX_ABB_IVA_DONE_EN_MASK (1 << 30)
+
+/* Renamed from ABB_IVA_DONE_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_ABB_IVA_DONE_EN_PRM_IRQENABLE_MPU_SHIFT 31
+#define DRA7XX_ABB_IVA_DONE_EN_PRM_IRQENABLE_MPU_WIDTH 0x1
+#define DRA7XX_ABB_IVA_DONE_EN_PRM_IRQENABLE_MPU_MASK (1 << 31)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_ABB_IVA_DONE_ST_SHIFT 30
+#define DRA7XX_ABB_IVA_DONE_ST_WIDTH 0x1
+#define DRA7XX_ABB_IVA_DONE_ST_MASK (1 << 30)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_ABB_MPU_DONE_EN_SHIFT 31
+#define DRA7XX_ABB_MPU_DONE_EN_WIDTH 0x1
+#define DRA7XX_ABB_MPU_DONE_EN_MASK (1 << 31)
+
+/* Renamed from ABB_MPU_DONE_EN Used by PRM_IRQENABLE_MPU_2 */
+#define DRA7XX_ABB_MPU_DONE_EN_7_7_SHIFT 7
+#define DRA7XX_ABB_MPU_DONE_EN_7_7_WIDTH 0x1
+#define DRA7XX_ABB_MPU_DONE_EN_7_7_MASK (1 << 7)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2
+ */
+#define DRA7XX_ABB_MPU_DONE_ST_SHIFT 31
+#define DRA7XX_ABB_MPU_DONE_ST_WIDTH 0x1
+#define DRA7XX_ABB_MPU_DONE_ST_MASK (1 << 31)
+
+/* Renamed from ABB_MPU_DONE_ST Used by PRM_IRQSTATUS_MPU_2 */
+#define DRA7XX_ABB_MPU_DONE_ST_7_7_SHIFT 7
+#define DRA7XX_ABB_MPU_DONE_ST_7_7_WIDTH 0x1
+#define DRA7XX_ABB_MPU_DONE_ST_7_7_MASK (1 << 7)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
+ * PRM_ABBLDO_MPU_SETUP
+ */
+#define DRA7XX_ACTIVE_FBB_SEL_SHIFT 2
+#define DRA7XX_ACTIVE_FBB_SEL_WIDTH 0x1
+#define DRA7XX_ACTIVE_FBB_SEL_MASK (1 << 2)
+
+/* Used by PM_IPU_PWRSTCTRL */
+#define DRA7XX_AESSMEM_ONSTATE_SHIFT 16
+#define DRA7XX_AESSMEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_AESSMEM_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_IPU_PWRSTCTRL */
+#define DRA7XX_AESSMEM_RETSTATE_SHIFT 8
+#define DRA7XX_AESSMEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_AESSMEM_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_IPU_PWRSTST */
+#define DRA7XX_AESSMEM_STATEST_SHIFT 4
+#define DRA7XX_AESSMEM_STATEST_WIDTH 0x2
+#define DRA7XX_AESSMEM_STATEST_MASK (0x3 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_AIPOFF_SHIFT 8
+#define DRA7XX_AIPOFF_WIDTH 0x1
+#define DRA7XX_AIPOFF_MASK (1 << 8)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0
+#define DRA7XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2
+#define DRA7XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_AUTO_CTRL_VDD_MM_L_SHIFT 4
+#define DRA7XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2
+#define DRA7XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2
+#define DRA7XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2
+#define DRA7XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_C2C_RST_SHIFT 10
+#define DRA7XX_C2C_RST_WIDTH 0x1
+#define DRA7XX_C2C_RST_MASK (1 << 10)
+
+/* Used by PRM_CLKREQCTRL */
+#define DRA7XX_CLKREQ_COND_SHIFT 0
+#define DRA7XX_CLKREQ_COND_WIDTH 0x3
+#define DRA7XX_CLKREQ_COND_MASK (0x7 << 0)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_CORE_OCMRAM_ONSTATE_SHIFT 18
+#define DRA7XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2
+#define DRA7XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_CORE_OCMRAM_RETSTATE_SHIFT 9
+#define DRA7XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1
+#define DRA7XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_CORE_OCMRAM_STATEST_SHIFT 6
+#define DRA7XX_CORE_OCMRAM_STATEST_WIDTH 0x2
+#define DRA7XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8
+#define DRA7XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_CORE_OTHER_BANK_STATEST_SHIFT 4
+#define DRA7XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_CUSTOM_SHIFT 6
+#define DRA7XX_CUSTOM_WIDTH 0x2
+#define DRA7XX_CUSTOM_MASK (0x3 << 6)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define DRA7XX_DEVICE_OFF_ENABLE_SHIFT 0
+#define DRA7XX_DEVICE_OFF_ENABLE_WIDTH 0x1
+#define DRA7XX_DEVICE_OFF_ENABLE_MASK (1 << 0)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_ABE_RECAL_EN_SHIFT 4
+#define DRA7XX_DPLL_ABE_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_ABE_RECAL_EN_MASK (1 << 4)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_ABE_RECAL_ST_SHIFT 4
+#define DRA7XX_DPLL_ABE_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_ABE_RECAL_ST_MASK (1 << 4)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_CORE_RECAL_EN_SHIFT 0
+#define DRA7XX_DPLL_CORE_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_CORE_RECAL_EN_MASK (1 << 0)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_CORE_RECAL_ST_SHIFT 0
+#define DRA7XX_DPLL_CORE_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_CORE_RECAL_ST_MASK (1 << 0)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_DDR_RECAL_EN_SHIFT 7
+#define DRA7XX_DPLL_DDR_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_DDR_RECAL_EN_MASK (1 << 7)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_DDR_RECAL_ST_SHIFT 7
+#define DRA7XX_DPLL_DDR_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_DDR_RECAL_ST_MASK (1 << 7)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_DPLL_DSP_RECAL_EN_SHIFT 11
+#define DRA7XX_DPLL_DSP_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_DSP_RECAL_EN_MASK (1 << 11)
+
+/* Renamed from DPLL_DSP_RECAL_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_DPLL_DSP_RECAL_EN_PRM_IRQENABLE_MPU_SHIFT 10
+#define DRA7XX_DPLL_DSP_RECAL_EN_PRM_IRQENABLE_MPU_WIDTH 0x1
+#define DRA7XX_DPLL_DSP_RECAL_EN_PRM_IRQENABLE_MPU_MASK (1 << 10)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_DSP_RECAL_ST_SHIFT 11
+#define DRA7XX_DPLL_DSP_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_DSP_RECAL_ST_MASK (1 << 11)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_DPLL_EVE_RECAL_EN_SHIFT 12
+#define DRA7XX_DPLL_EVE_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_EVE_RECAL_EN_MASK (1 << 12)
+
+/* Renamed from DPLL_EVE_RECAL_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_DPLL_EVE_RECAL_EN_PRM_IRQENABLE_MPU_SHIFT 11
+#define DRA7XX_DPLL_EVE_RECAL_EN_PRM_IRQENABLE_MPU_WIDTH 0x1
+#define DRA7XX_DPLL_EVE_RECAL_EN_PRM_IRQENABLE_MPU_MASK (1 << 11)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_EVE_RECAL_ST_SHIFT 12
+#define DRA7XX_DPLL_EVE_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_EVE_RECAL_ST_MASK (1 << 12)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_GMAC_RECAL_EN_SHIFT 5
+#define DRA7XX_DPLL_GMAC_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_GMAC_RECAL_EN_MASK (1 << 5)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_GMAC_RECAL_ST_SHIFT 5
+#define DRA7XX_DPLL_GMAC_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_GMAC_RECAL_ST_MASK (1 << 5)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_GPU_RECAL_EN_SHIFT 6
+#define DRA7XX_DPLL_GPU_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_GPU_RECAL_EN_MASK (1 << 6)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_GPU_RECAL_ST_SHIFT 6
+#define DRA7XX_DPLL_GPU_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_GPU_RECAL_ST_MASK (1 << 6)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_IVA_RECAL_EN_SHIFT 2
+#define DRA7XX_DPLL_IVA_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_IVA_RECAL_EN_MASK (1 << 2)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_IVA_RECAL_ST_SHIFT 2
+#define DRA7XX_DPLL_IVA_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_IVA_RECAL_ST_MASK (1 << 2)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_MPU_RECAL_EN_SHIFT 1
+#define DRA7XX_DPLL_MPU_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_MPU_RECAL_EN_MASK (1 << 1)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_MPU_RECAL_ST_SHIFT 1
+#define DRA7XX_DPLL_MPU_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_MPU_RECAL_ST_MASK (1 << 1)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_PER_RECAL_EN_SHIFT 3
+#define DRA7XX_DPLL_PER_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_PER_RECAL_EN_MASK (1 << 3)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_PER_RECAL_ST_SHIFT 3
+#define DRA7XX_DPLL_PER_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_PER_RECAL_ST_MASK (1 << 3)
+
+/* Used by PRM_IRQENABLE_DSP1 */
+#define DRA7XX_DPLL_USB_RECAL_EN_SHIFT 13
+#define DRA7XX_DPLL_USB_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_USB_RECAL_EN_MASK (1 << 13)
+
+/* Used by PM_DSP1_PWRSTCTRL */
+#define DRA7XX_DSP1_EDMA_ONSTATE_SHIFT 20
+#define DRA7XX_DSP1_EDMA_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP1_EDMA_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_DSP1_PWRSTST */
+#define DRA7XX_DSP1_EDMA_STATEST_SHIFT 8
+#define DRA7XX_DSP1_EDMA_STATEST_WIDTH 0x2
+#define DRA7XX_DSP1_EDMA_STATEST_MASK (0x3 << 8)
+
+/* Used by PM_DSP1_PWRSTCTRL */
+#define DRA7XX_DSP1_L1_ONSTATE_SHIFT 16
+#define DRA7XX_DSP1_L1_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP1_L1_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_DSP1_PWRSTST */
+#define DRA7XX_DSP1_L1_STATEST_SHIFT 4
+#define DRA7XX_DSP1_L1_STATEST_WIDTH 0x2
+#define DRA7XX_DSP1_L1_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_DSP1_PWRSTCTRL */
+#define DRA7XX_DSP1_L2_ONSTATE_SHIFT 18
+#define DRA7XX_DSP1_L2_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP1_L2_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_DSP1_PWRSTST */
+#define DRA7XX_DSP1_L2_STATEST_SHIFT 6
+#define DRA7XX_DSP1_L2_STATEST_WIDTH 0x2
+#define DRA7XX_DSP1_L2_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_DSP2_PWRSTCTRL */
+#define DRA7XX_DSP2_EDMA_ONSTATE_SHIFT 20
+#define DRA7XX_DSP2_EDMA_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP2_EDMA_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_DSP2_PWRSTST */
+#define DRA7XX_DSP2_EDMA_STATEST_SHIFT 8
+#define DRA7XX_DSP2_EDMA_STATEST_WIDTH 0x2
+#define DRA7XX_DSP2_EDMA_STATEST_MASK (0x3 << 8)
+
+/* Used by PM_DSP2_PWRSTCTRL */
+#define DRA7XX_DSP2_L1_ONSTATE_SHIFT 16
+#define DRA7XX_DSP2_L1_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP2_L1_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_DSP2_PWRSTST */
+#define DRA7XX_DSP2_L1_STATEST_SHIFT 4
+#define DRA7XX_DSP2_L1_STATEST_WIDTH 0x2
+#define DRA7XX_DSP2_L1_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_DSP2_PWRSTCTRL */
+#define DRA7XX_DSP2_L2_ONSTATE_SHIFT 18
+#define DRA7XX_DSP2_L2_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP2_L2_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_DSP2_PWRSTST */
+#define DRA7XX_DSP2_L2_STATEST_SHIFT 6
+#define DRA7XX_DSP2_L2_STATEST_WIDTH 0x2
+#define DRA7XX_DSP2_L2_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define DRA7XX_DSS_MEM_ONSTATE_SHIFT 16
+#define DRA7XX_DSS_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSS_MEM_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define DRA7XX_DSS_MEM_RETSTATE_SHIFT 8
+#define DRA7XX_DSS_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_DSS_MEM_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_DSS_PWRSTST */
+#define DRA7XX_DSS_MEM_STATEST_SHIFT 4
+#define DRA7XX_DSS_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_DSS_MEM_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define DRA7XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8
+#define DRA7XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1
+#define DRA7XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define DRA7XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9
+#define DRA7XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1
+#define DRA7XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
+
+/* Used by PM_EMU_PWRSTCTRL */
+#define DRA7XX_EMU_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EMU_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EMU_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EMU_PWRSTST */
+#define DRA7XX_EMU_BANK_STATEST_SHIFT 4
+#define DRA7XX_EMU_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EMU_BANK_STATEST_MASK (0x3 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP, PRM_SRAM_WKUP_SETUP
+ */
+#define DRA7XX_ENABLE_RTA_SHIFT 0
+#define DRA7XX_ENABLE_RTA_WIDTH 0x1
+#define DRA7XX_ENABLE_RTA_MASK (1 << 0)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC1_SHIFT 3
+#define DRA7XX_ENFUNC1_WIDTH 0x1
+#define DRA7XX_ENFUNC1_MASK (1 << 3)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC2_SHIFT 4
+#define DRA7XX_ENFUNC2_WIDTH 0x1
+#define DRA7XX_ENFUNC2_MASK (1 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC3_SHIFT 5
+#define DRA7XX_ENFUNC3_WIDTH 0x1
+#define DRA7XX_ENFUNC3_MASK (1 << 5)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC4_SHIFT 6
+#define DRA7XX_ENFUNC4_WIDTH 0x1
+#define DRA7XX_ENFUNC4_MASK (1 << 6)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC5_SHIFT 7
+#define DRA7XX_ENFUNC5_WIDTH 0x1
+#define DRA7XX_ENFUNC5_MASK (1 << 7)
+
+/* Used by PM_EVE1_PWRSTCTRL */
+#define DRA7XX_EVE1_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EVE1_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EVE1_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EVE1_PWRSTST */
+#define DRA7XX_EVE1_BANK_STATEST_SHIFT 4
+#define DRA7XX_EVE1_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EVE1_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_EVE2_PWRSTCTRL */
+#define DRA7XX_EVE2_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EVE2_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EVE2_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EVE2_PWRSTST */
+#define DRA7XX_EVE2_BANK_STATEST_SHIFT 4
+#define DRA7XX_EVE2_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EVE2_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_EVE3_PWRSTCTRL */
+#define DRA7XX_EVE3_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EVE3_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EVE3_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EVE3_PWRSTST */
+#define DRA7XX_EVE3_BANK_STATEST_SHIFT 4
+#define DRA7XX_EVE3_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EVE3_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_EVE4_PWRSTCTRL */
+#define DRA7XX_EVE4_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EVE4_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EVE4_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EVE4_PWRSTST */
+#define DRA7XX_EVE4_BANK_STATEST_SHIFT 4
+#define DRA7XX_EVE4_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EVE4_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_EXTERNAL_WARM_RST_SHIFT 5
+#define DRA7XX_EXTERNAL_WARM_RST_WIDTH 0x1
+#define DRA7XX_EXTERNAL_WARM_RST_MASK (1 << 5)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_FORCEWKUP_EN_SHIFT 10
+#define DRA7XX_FORCEWKUP_EN_WIDTH 0x1
+#define DRA7XX_FORCEWKUP_EN_MASK (1 << 10)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2
+ */
+#define DRA7XX_FORCEWKUP_ST_SHIFT 10
+#define DRA7XX_FORCEWKUP_ST_WIDTH 0x1
+#define DRA7XX_FORCEWKUP_ST_MASK (1 << 10)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_FUNC_SHIFT 16
+#define DRA7XX_FUNC_WIDTH 0xc
+#define DRA7XX_FUNC_MASK (0xfff << 16)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_GLOBAL_COLD_RST_SHIFT 0
+#define DRA7XX_GLOBAL_COLD_RST_WIDTH 0x1
+#define DRA7XX_GLOBAL_COLD_RST_MASK (1 << 0)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_GLOBAL_WARM_SW_RST_SHIFT 1
+#define DRA7XX_GLOBAL_WARM_SW_RST_WIDTH 0x1
+#define DRA7XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_GLOBAL_WUEN_SHIFT 16
+#define DRA7XX_GLOBAL_WUEN_WIDTH 0x1
+#define DRA7XX_GLOBAL_WUEN_MASK (1 << 16)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_GMAC_BANK_ONSTATE_SHIFT 18
+#define DRA7XX_GMAC_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_GMAC_BANK_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_GMAC_BANK_RETSTATE_SHIFT 10
+#define DRA7XX_GMAC_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_GMAC_BANK_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_GPU_PWRSTCTRL */
+#define DRA7XX_GPU_MEM_ONSTATE_SHIFT 16
+#define DRA7XX_GPU_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_GPU_MEM_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_GPU_PWRSTST */
+#define DRA7XX_GPU_MEM_STATEST_SHIFT 4
+#define DRA7XX_GPU_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_GPU_MEM_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_PSCON_COUNT */
+#define DRA7XX_HG_PONOUT_2_PGOODIN_TIME_SHIFT 16
+#define DRA7XX_HG_PONOUT_2_PGOODIN_TIME_WIDTH 0x8
+#define DRA7XX_HG_PONOUT_2_PGOODIN_TIME_MASK (0xff << 16)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_HWA_MEM_ONSTATE_SHIFT 16
+#define DRA7XX_HWA_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_HWA_MEM_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_HWA_MEM_RETSTATE_SHIFT 8
+#define DRA7XX_HWA_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_HWA_MEM_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_IVA_PWRSTST */
+#define DRA7XX_HWA_MEM_STATEST_SHIFT 4
+#define DRA7XX_HWA_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_HWA_MEM_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_ICEPICK_RST_SHIFT 9
+#define DRA7XX_ICEPICK_RST_WIDTH 0x1
+#define DRA7XX_ICEPICK_RST_MASK (1 << 9)
+
+/*
+ * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
+ * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST, PRM_VOLTST_MM,
+ * PRM_VOLTST_MPU
+ */
+#define DRA7XX_INTRANSITION_SHIFT 20
+#define DRA7XX_INTRANSITION_WIDTH 0x1
+#define DRA7XX_INTRANSITION_MASK (1 << 20)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_IO_EN_SHIFT 9
+#define DRA7XX_IO_EN_WIDTH 0x1
+#define DRA7XX_IO_EN_MASK (1 << 9)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_IO_ON_STATUS_SHIFT 5
+#define DRA7XX_IO_ON_STATUS_WIDTH 0x1
+#define DRA7XX_IO_ON_STATUS_MASK (1 << 5)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_IO_ST_SHIFT 9
+#define DRA7XX_IO_ST_WIDTH 0x1
+#define DRA7XX_IO_ST_MASK (1 << 9)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_IPU_L2RAM_ONSTATE_SHIFT 20
+#define DRA7XX_IPU_L2RAM_ONSTATE_WIDTH 0x2
+#define DRA7XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_IPU_L2RAM_RETSTATE_SHIFT 10
+#define DRA7XX_IPU_L2RAM_RETSTATE_WIDTH 0x1
+#define DRA7XX_IPU_L2RAM_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_IPU_L2RAM_STATEST_SHIFT 8
+#define DRA7XX_IPU_L2RAM_STATEST_WIDTH 0x2
+#define DRA7XX_IPU_L2RAM_STATEST_MASK (0x3 << 8)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_IPU_UNICACHE_ONSTATE_SHIFT 22
+#define DRA7XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2
+#define DRA7XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_IPU_UNICACHE_RETSTATE_SHIFT 11
+#define DRA7XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1
+#define DRA7XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_IPU_UNICACHE_STATEST_SHIFT 10
+#define DRA7XX_IPU_UNICACHE_STATEST_WIDTH 0x2
+#define DRA7XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_ISOCLK_OVERRIDE_SHIFT 0
+#define DRA7XX_ISOCLK_OVERRIDE_WIDTH 0x1
+#define DRA7XX_ISOCLK_OVERRIDE_MASK (1 << 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_ISOCLK_STATUS_SHIFT 1
+#define DRA7XX_ISOCLK_STATUS_WIDTH 0x1
+#define DRA7XX_ISOCLK_STATUS_MASK (1 << 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_ISOOVR_EXTEND_SHIFT 4
+#define DRA7XX_ISOOVR_EXTEND_WIDTH 0x1
+#define DRA7XX_ISOOVR_EXTEND_MASK (1 << 4)
+
+/* Used by PRM_IO_COUNT */
+#define DRA7XX_ISO_2_ON_TIME_SHIFT 0
+#define DRA7XX_ISO_2_ON_TIME_WIDTH 0x8
+#define DRA7XX_ISO_2_ON_TIME_MASK (0xff << 0)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_L3INIT_BANK1_ONSTATE_SHIFT 14
+#define DRA7XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2
+#define DRA7XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 14)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_L3INIT_BANK1_RETSTATE_SHIFT 8
+#define DRA7XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1
+#define DRA7XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define DRA7XX_L3INIT_BANK1_STATEST_SHIFT 4
+#define DRA7XX_L3INIT_BANK1_STATEST_WIDTH 0x2
+#define DRA7XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_L3INIT_BANK2_ONSTATE_SHIFT 16
+#define DRA7XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2
+#define DRA7XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_L3INIT_BANK2_RETSTATE_SHIFT 9
+#define DRA7XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1
+#define DRA7XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define DRA7XX_L3INIT_BANK2_STATEST_SHIFT 6
+#define DRA7XX_L3INIT_BANK2_STATEST_WIDTH 0x2
+#define DRA7XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define DRA7XX_L3INIT_GMAC_STATEST_SHIFT 8
+#define DRA7XX_L3INIT_GMAC_STATEST_WIDTH 0x2
+#define DRA7XX_L3INIT_GMAC_STATEST_MASK (0x3 << 8)
+
+/*
+ * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
+ * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST
+ */
+#define DRA7XX_LASTPOWERSTATEENTERED_SHIFT 24
+#define DRA7XX_LASTPOWERSTATEENTERED_WIDTH 0x2
+#define DRA7XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_LLI_RST_SHIFT 14
+#define DRA7XX_LLI_RST_WIDTH 0x1
+#define DRA7XX_LLI_RST_MASK (1 << 14)
+
+/*
+ * Used by PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_IPU_PWRSTCTRL,
+ * PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL,
+ * PM_VPE_PWRSTCTRL
+ */
+#define DRA7XX_LOGICRETSTATE_SHIFT 2
+#define DRA7XX_LOGICRETSTATE_WIDTH 0x1
+#define DRA7XX_LOGICRETSTATE_MASK (1 << 2)
+
+/*
+ * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
+ * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST
+ */
+#define DRA7XX_LOGICSTATEST_SHIFT 2
+#define DRA7XX_LOGICSTATEST_WIDTH 0x1
+#define DRA7XX_LOGICSTATEST_MASK (1 << 2)
+
+/*
+ * Used by RM_ATL_ATL_CONTEXT, RM_CAM_CSI1_CONTEXT, RM_CAM_CSI2_CONTEXT,
+ * RM_CAM_LVDSRX_CONTEXT, RM_CAM_VIP1_CONTEXT, RM_CAM_VIP2_CONTEXT,
+ * RM_CAM_VIP3_CONTEXT, RM_COREAON_DUMMY_MODULE1_CONTEXT,
+ * RM_COREAON_DUMMY_MODULE2_CONTEXT, RM_COREAON_DUMMY_MODULE3_CONTEXT,
+ * RM_COREAON_DUMMY_MODULE4_CONTEXT, RM_COREAON_SMARTREFLEX_CORE_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT, RM_COREAON_SMARTREFLEX_GPU_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT, RM_COREAON_SMARTREFLEX_MPU_CONTEXT,
+ * RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, RM_DSP1_DSP1_CONTEXT,
+ * RM_DSP2_DSP2_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_DSS_SDVENC_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
+ * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_DLL_CONTEXT,
+ * RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_EVE1_EVE1_CONTEXT,
+ * RM_EVE2_EVE2_CONTEXT, RM_EVE3_EVE3_CONTEXT, RM_EVE4_EVE4_CONTEXT,
+ * RM_GMAC_GMAC_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU1_IPU1_CONTEXT,
+ * RM_IPU2_IPU2_CONTEXT, RM_IPU_I2C5_CONTEXT, RM_IPU_MCASP1_CONTEXT,
+ * RM_IPU_TIMER5_CONTEXT, RM_IPU_TIMER6_CONTEXT, RM_IPU_TIMER7_CONTEXT,
+ * RM_IPU_TIMER8_CONTEXT, RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT,
+ * RM_L3INIT_IEEE1500_2_OCP_CONTEXT, RM_L3INIT_MLB_SS_CONTEXT,
+ * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
+ * RM_L3INSTR_L3_MAIN_2_CONTEXT, RM_L3INSTR_OCP_WP_NOC_CONTEXT,
+ * RM_L3MAIN1_L3_MAIN_1_CONTEXT, RM_L3MAIN1_OCMC_RAM1_CONTEXT,
+ * RM_L3MAIN1_OCMC_RAM2_CONTEXT, RM_L3MAIN1_OCMC_RAM3_CONTEXT,
+ * RM_L3MAIN1_OCMC_ROM_CONTEXT, RM_L3MAIN1_SPARE_CME_CONTEXT,
+ * RM_L3MAIN1_SPARE_HDMI_CONTEXT, RM_L3MAIN1_SPARE_ICM_CONTEXT,
+ * RM_L3MAIN1_SPARE_IVA2_CONTEXT, RM_L3MAIN1_SPARE_SATA2_CONTEXT,
+ * RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT, RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT,
+ * RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT, RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT,
+ * RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT, RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT,
+ * RM_L3MAIN1_VCP1_CONTEXT, RM_L3MAIN1_VCP2_CONTEXT,
+ * RM_L4CFG_IO_DELAY_BLOCK_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
+ * RM_L4CFG_OCP2SCP2_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
+ * RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT,
+ * RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT,
+ * RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT, RM_L4PER2_DCAN2_CONTEXT,
+ * RM_L4PER2_L4PER2_CONTEXT, RM_L4PER2_MCASP2_CONTEXT,
+ * RM_L4PER2_MCASP3_CONTEXT, RM_L4PER2_MCASP4_CONTEXT,
+ * RM_L4PER2_MCASP5_CONTEXT, RM_L4PER2_MCASP6_CONTEXT,
+ * RM_L4PER2_MCASP7_CONTEXT, RM_L4PER2_MCASP8_CONTEXT,
+ * RM_L4PER2_PRUSS1_CONTEXT, RM_L4PER2_PRUSS2_CONTEXT,
+ * RM_L4PER2_PWMSS1_CONTEXT, RM_L4PER2_PWMSS2_CONTEXT,
+ * RM_L4PER2_PWMSS3_CONTEXT, RM_L4PER2_QSPI_CONTEXT, RM_L4PER3_L4PER3_CONTEXT,
+ * RM_L4PER3_TIMER13_CONTEXT, RM_L4PER3_TIMER14_CONTEXT,
+ * RM_L4PER3_TIMER15_CONTEXT, RM_L4PER3_TIMER16_CONTEXT, RM_L4PER_ELM_CONTEXT,
+ * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT,
+ * RM_L4PER_I2C4_CONTEXT, RM_L4PER_L4PER1_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
+ * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
+ * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_TIMER10_CONTEXT,
+ * RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, RM_L4PER_TIMER3_CONTEXT,
+ * RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, RM_L4SEC_FPKA_CONTEXT,
+ * RM_MPU_MPU_CONTEXT, RM_RTC_RTCSS_CONTEXT, RM_VPE_VPE_CONTEXT,
+ * RM_WKUPAON_ADC_CONTEXT, RM_WKUPAON_COUNTER_32K_CONTEXT,
+ * RM_WKUPAON_DCAN1_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, RM_WKUPAON_KBD_CONTEXT,
+ * RM_WKUPAON_L4_WKUP_CONTEXT, RM_WKUPAON_SAR_RAM_CONTEXT,
+ * RM_WKUPAON_SPARE_SAFETY1_CONTEXT, RM_WKUPAON_SPARE_SAFETY2_CONTEXT,
+ * RM_WKUPAON_SPARE_SAFETY3_CONTEXT, RM_WKUPAON_SPARE_SAFETY4_CONTEXT,
+ * RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT, RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT,
+ * RM_WKUPAON_TIMER12_CONTEXT, RM_WKUPAON_TIMER1_CONTEXT,
+ * RM_WKUPAON_UART10_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
+ * RM_WKUPAON_WD_TIMER2_CONTEXT
+ */
+#define DRA7XX_LOSTCONTEXT_DFF_SHIFT 0
+#define DRA7XX_LOSTCONTEXT_DFF_WIDTH 0x1
+#define DRA7XX_LOSTCONTEXT_DFF_MASK (1 << 0)
+
+/*
+ * Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT,
+ * RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
+ * RM_IPU1_IPU1_CONTEXT, RM_IPU2_IPU2_CONTEXT, RM_IPU_UART6_CONTEXT,
+ * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS1_CONTEXT, RM_L3INIT_USB_OTG_SS2_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS3_CONTEXT, RM_L3INIT_USB_OTG_SS4_CONTEXT,
+ * RM_L3INSTR_L3_MAIN_2_CONTEXT, RM_L3INSTR_OCP_WP_NOC_CONTEXT,
+ * RM_L3MAIN1_GPMC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
+ * RM_L3MAIN1_MMU_EDMA_CONTEXT, RM_L3MAIN1_TPCC_CONTEXT,
+ * RM_L3MAIN1_TPTC1_CONTEXT, RM_L3MAIN1_TPTC2_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
+ * RM_L4CFG_MAILBOX10_CONTEXT, RM_L4CFG_MAILBOX11_CONTEXT,
+ * RM_L4CFG_MAILBOX12_CONTEXT, RM_L4CFG_MAILBOX13_CONTEXT,
+ * RM_L4CFG_MAILBOX1_CONTEXT, RM_L4CFG_MAILBOX2_CONTEXT,
+ * RM_L4CFG_MAILBOX3_CONTEXT, RM_L4CFG_MAILBOX4_CONTEXT,
+ * RM_L4CFG_MAILBOX5_CONTEXT, RM_L4CFG_MAILBOX6_CONTEXT,
+ * RM_L4CFG_MAILBOX7_CONTEXT, RM_L4CFG_MAILBOX8_CONTEXT,
+ * RM_L4CFG_MAILBOX9_CONTEXT, RM_L4CFG_SPINLOCK_CONTEXT,
+ * RM_L4PER2_L4PER2_CONTEXT, RM_L4PER2_UART7_CONTEXT, RM_L4PER2_UART8_CONTEXT,
+ * RM_L4PER2_UART9_CONTEXT, RM_L4PER3_L4PER3_CONTEXT, RM_L4PER_GPIO2_CONTEXT,
+ * RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT,
+ * RM_L4PER_GPIO6_CONTEXT, RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT,
+ * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4PER1_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ * RM_L4PER_UART5_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
+ * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
+ * RM_L4SEC_SHA2MD51_CONTEXT, RM_L4SEC_SHA2MD52_CONTEXT, RM_MPU_MPU_CONTEXT
+ */
+#define DRA7XX_LOSTCONTEXT_RFF_SHIFT 1
+#define DRA7XX_LOSTCONTEXT_RFF_WIDTH 0x1
+#define DRA7XX_LOSTCONTEXT_RFF_MASK (1 << 1)
+
+/* Used by RM_ATL_ATL_CONTEXT */
+#define DRA7XX_LOSTMEM_ATL_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_ATL_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_ATL_BANK_MASK (1 << 8)
+
+/* Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
+#define DRA7XX_LOSTMEM_CORE_NRET_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8)
+
+/*
+ * Used by RM_L3MAIN1_OCMC_RAM1_CONTEXT, RM_L3MAIN1_OCMC_RAM2_CONTEXT,
+ * RM_L3MAIN1_OCMC_RAM3_CONTEXT
+ */
+#define DRA7XX_LOSTMEM_CORE_OCMRAM_SHIFT 8
+#define DRA7XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
+
+/* Used by RM_L3MAIN1_OCMC_ROM_CONTEXT */
+#define DRA7XX_LOSTMEM_CORE_OCMROM_SHIFT 8
+#define DRA7XX_LOSTMEM_CORE_OCMROM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_CORE_OCMROM_MASK (1 << 8)
+
+/* Used by RM_DMA_DMA_SYSTEM_CONTEXT */
+#define DRA7XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
+
+/* Used by RM_L4PER2_DCAN2_CONTEXT */
+#define DRA7XX_LOSTMEM_DCAN_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_DCAN_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DCAN_BANK_MASK (1 << 8)
+
+/* Used by RM_WKUPAON_DCAN1_CONTEXT */
+#define DRA7XX_LOSTMEM_DCAN_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_DCAN_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DCAN_MEM_MASK (1 << 8)
+
+/* Used by RM_DSP1_DSP1_CONTEXT, RM_DSP2_DSP2_CONTEXT */
+#define DRA7XX_LOSTMEM_DSP_EDMA_SHIFT 10
+#define DRA7XX_LOSTMEM_DSP_EDMA_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DSP_EDMA_MASK (1 << 10)
+
+/* Used by RM_DSP1_DSP1_CONTEXT, RM_DSP2_DSP2_CONTEXT */
+#define DRA7XX_LOSTMEM_DSP_L1_SHIFT 8
+#define DRA7XX_LOSTMEM_DSP_L1_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DSP_L1_MASK (1 << 8)
+
+/* Used by RM_DSP1_DSP1_CONTEXT, RM_DSP2_DSP2_CONTEXT */
+#define DRA7XX_LOSTMEM_DSP_L2_SHIFT 9
+#define DRA7XX_LOSTMEM_DSP_L2_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DSP_L2_MASK (1 << 9)
+
+/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
+#define DRA7XX_LOSTMEM_DSS_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_DSS_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DSS_MEM_MASK (1 << 8)
+
+/* Used by RM_EMU_DEBUGSS_CONTEXT */
+#define DRA7XX_LOSTMEM_EMU_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_EMU_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_EMU_BANK_MASK (1 << 8)
+
+/*
+ * Used by RM_EVE1_EVE1_CONTEXT, RM_EVE2_EVE2_CONTEXT, RM_EVE3_EVE3_CONTEXT,
+ * RM_EVE4_EVE4_CONTEXT
+ */
+#define DRA7XX_LOSTMEM_EVE_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_EVE_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_EVE_BANK_MASK (1 << 8)
+
+/* Used by RM_GMAC_GMAC_CONTEXT */
+#define DRA7XX_LOSTMEM_GMAC_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_GMAC_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_GMAC_BANK_MASK (1 << 8)
+
+/* Used by RM_GPU_GPU_CONTEXT */
+#define DRA7XX_LOSTMEM_GPU_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_GPU_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_GPU_MEM_MASK (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define DRA7XX_LOSTMEM_HWA_MEM_SHIFT 10
+#define DRA7XX_LOSTMEM_HWA_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_HWA_MEM_MASK (1 << 10)
+
+/* Used by RM_IPU1_IPU1_CONTEXT, RM_IPU2_IPU2_CONTEXT */
+#define DRA7XX_LOSTMEM_IPU_L2RAM_SHIFT 9
+#define DRA7XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9)
+
+/* Used by RM_IPU1_IPU1_CONTEXT, RM_IPU2_IPU2_CONTEXT */
+#define DRA7XX_LOSTMEM_IPU_UNICACHE_SHIFT 8
+#define DRA7XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1
+#define DRA7XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8)
+
+/*
+ * Used by RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_USB_OTG_SS1_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS2_CONTEXT, RM_L3INIT_USB_OTG_SS3_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS4_CONTEXT
+ */
+#define DRA7XX_LOSTMEM_L3INIT_BANK1_SHIFT 8
+#define DRA7XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1
+#define DRA7XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
+
+/* Used by RM_L3INIT_MLB_SS_CONTEXT */
+#define DRA7XX_LOSTMEM_MLB_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_MLB_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_MLB_BANK_MASK (1 << 8)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define DRA7XX_LOSTMEM_MPU_L2_SHIFT 9
+#define DRA7XX_LOSTMEM_MPU_L2_WIDTH 0x1
+#define DRA7XX_LOSTMEM_MPU_L2_MASK (1 << 9)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define DRA7XX_LOSTMEM_MPU_RAM_SHIFT 10
+#define DRA7XX_LOSTMEM_MPU_RAM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_MPU_RAM_MASK (1 << 10)
+
+/* Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4SEC_FPKA_CONTEXT */
+#define DRA7XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
+
+/* Used by RM_L4PER2_PRUSS1_CONTEXT */
+#define DRA7XX_LOSTMEM_PRUSS1_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_PRUSS1_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_PRUSS1_BANK_MASK (1 << 8)
+
+/* Used by RM_L4PER2_PRUSS2_CONTEXT */
+#define DRA7XX_LOSTMEM_PRUSS2_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_PRUSS2_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_PRUSS2_BANK_MASK (1 << 8)
+
+/*
+ * Used by RM_IPU_UART6_CONTEXT, RM_L4PER2_UART7_CONTEXT,
+ * RM_L4PER2_UART8_CONTEXT, RM_L4PER2_UART9_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ * RM_L4PER_UART5_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT,
+ * RM_WKUPAON_UART10_CONTEXT
+ */
+#define DRA7XX_LOSTMEM_RETAINED_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
+
+/* Used by RM_IVA_SL2_CONTEXT */
+#define DRA7XX_LOSTMEM_SL2_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_SL2_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_SL2_MEM_MASK (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define DRA7XX_LOSTMEM_TCM1_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_TCM1_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_TCM1_MEM_MASK (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define DRA7XX_LOSTMEM_TCM2_MEM_SHIFT 9
+#define DRA7XX_LOSTMEM_TCM2_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_TCM2_MEM_MASK (1 << 9)
+
+/* Used by RM_L3MAIN1_TPCC_CONTEXT */
+#define DRA7XX_LOSTMEM_TPCC_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_TPCC_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_TPCC_BANK_MASK (1 << 8)
+
+/* Used by RM_L3MAIN1_TPTC1_CONTEXT, RM_L3MAIN1_TPTC2_CONTEXT */
+#define DRA7XX_LOSTMEM_TPTC_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_TPTC_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_TPTC_BANK_MASK (1 << 8)
+
+/* Used by RM_L3MAIN1_VCP1_CONTEXT, RM_L3MAIN1_VCP2_CONTEXT */
+#define DRA7XX_LOSTMEM_VCP_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_VCP_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_VCP_BANK_MASK (1 << 8)
+
+/* Used by RM_CAM_VIP1_CONTEXT, RM_CAM_VIP2_CONTEXT, RM_CAM_VIP3_CONTEXT */
+#define DRA7XX_LOSTMEM_VIP_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_VIP_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_VIP_BANK_MASK (1 << 8)
+
+/* Used by RM_VPE_VPE_CONTEXT */
+#define DRA7XX_LOSTMEM_VPE_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_VPE_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_VPE_BANK_MASK (1 << 8)
+
+/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
+#define DRA7XX_LOSTMEM_WKUP_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_WKUP_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_WKUP_BANK_MASK (1 << 8)
+
+/*
+ * Used by PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CUSTEFUSE_PWRSTCTRL,
+ * PM_DSP1_PWRSTCTRL, PM_DSP2_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EVE1_PWRSTCTRL,
+ * PM_EVE2_PWRSTCTRL, PM_EVE3_PWRSTCTRL, PM_EVE4_PWRSTCTRL, PM_GPU_PWRSTCTRL,
+ * PM_IPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_VPE_PWRSTCTRL
+ */
+#define DRA7XX_LOWPOWERSTATECHANGE_SHIFT 4
+#define DRA7XX_LOWPOWERSTATECHANGE_WIDTH 0x1
+#define DRA7XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define DRA7XX_MODEM_SHUTDOWN_IRQ_SHIFT 9
+#define DRA7XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1
+#define DRA7XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define DRA7XX_MODEM_WAKE_IRQ_SHIFT 8
+#define DRA7XX_MODEM_WAKE_IRQ_WIDTH 0x1
+#define DRA7XX_MODEM_WAKE_IRQ_MASK (1 << 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define DRA7XX_MPU_L2_ONSTATE_SHIFT 18
+#define DRA7XX_MPU_L2_ONSTATE_WIDTH 0x2
+#define DRA7XX_MPU_L2_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define DRA7XX_MPU_L2_RETSTATE_SHIFT 9
+#define DRA7XX_MPU_L2_RETSTATE_WIDTH 0x1
+#define DRA7XX_MPU_L2_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_MPU_PWRSTST */
+#define DRA7XX_MPU_L2_STATEST_SHIFT 6
+#define DRA7XX_MPU_L2_STATEST_WIDTH 0x2
+#define DRA7XX_MPU_L2_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define DRA7XX_MPU_RAM_ONSTATE_SHIFT 20
+#define DRA7XX_MPU_RAM_ONSTATE_WIDTH 0x2
+#define DRA7XX_MPU_RAM_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define DRA7XX_MPU_RAM_RETSTATE_SHIFT 10
+#define DRA7XX_MPU_RAM_RETSTATE_WIDTH 0x1
+#define DRA7XX_MPU_RAM_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_MPU_PWRSTST */
+#define DRA7XX_MPU_RAM_STATEST_SHIFT 8
+#define DRA7XX_MPU_RAM_STATEST_WIDTH 0x2
+#define DRA7XX_MPU_RAM_STATEST_MASK (0x3 << 8)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_MPU_SECURITY_VIOL_RST_SHIFT 2
+#define DRA7XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1
+#define DRA7XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_MPU_WDT_RST_SHIFT 3
+#define DRA7XX_MPU_WDT_RST_WIDTH 0x1
+#define DRA7XX_MPU_WDT_RST_MASK (1 << 3)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
+ * PRM_ABBLDO_MPU_SETUP
+ */
+#define DRA7XX_NOCAP_SHIFT 4
+#define DRA7XX_NOCAP_WIDTH 0x1
+#define DRA7XX_NOCAP_MASK (1 << 4)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define DRA7XX_NONRETAINED_BANK_ONSTATE_SHIFT 18
+#define DRA7XX_NONRETAINED_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define DRA7XX_NONRETAINED_BANK_RETSTATE_SHIFT 9
+#define DRA7XX_NONRETAINED_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_NONRETAINED_BANK_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_L4PER_PWRSTST */
+#define DRA7XX_NONRETAINED_BANK_STATEST_SHIFT 6
+#define DRA7XX_NONRETAINED_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_NONRETAINED_BANK_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_OCP_NRET_BANK_ONSTATE_SHIFT 24
+#define DRA7XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_OCP_NRET_BANK_RETSTATE_SHIFT 12
+#define DRA7XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_OCP_NRET_BANK_STATEST_SHIFT 12
+#define DRA7XX_OCP_NRET_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
+ * PRM_ABBLDO_MPU_CTRL
+ */
+#define DRA7XX_OPP_CHANGE_SHIFT 2
+#define DRA7XX_OPP_CHANGE_WIDTH 0x1
+#define DRA7XX_OPP_CHANGE_MASK (1 << 2)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
+ * PRM_ABBLDO_MPU_CTRL
+ */
+#define DRA7XX_OPP_SEL_SHIFT 0
+#define DRA7XX_OPP_SEL_WIDTH 0x2
+#define DRA7XX_OPP_SEL_MASK (0x3 << 0)
+
+/* Used by PRM_DEBUG_OUT */
+#define DRA7XX_OUTPUT_SHIFT 0
+#define DRA7XX_OUTPUT_WIDTH 0x20
+#define DRA7XX_OUTPUT_MASK (0xffffffff << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define DRA7XX_PCHARGECNT_VALUE_SHIFT 0
+#define DRA7XX_PCHARGECNT_VALUE_WIDTH 0x6
+#define DRA7XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
+
+/* Used by PRM_PSCON_COUNT */
+#define DRA7XX_PCHARGE_TIME_SHIFT 0
+#define DRA7XX_PCHARGE_TIME_WIDTH 0x8
+#define DRA7XX_PCHARGE_TIME_MASK (0xff << 0)
+
+/* Used by PM_IPU_PWRSTCTRL */
+#define DRA7XX_PERIPHMEM_ONSTATE_SHIFT 20
+#define DRA7XX_PERIPHMEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_IPU_PWRSTCTRL */
+#define DRA7XX_PERIPHMEM_RETSTATE_SHIFT 10
+#define DRA7XX_PERIPHMEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_PERIPHMEM_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_IPU_PWRSTST */
+#define DRA7XX_PERIPHMEM_STATEST_SHIFT 8
+#define DRA7XX_PERIPHMEM_STATEST_WIDTH 0x2
+#define DRA7XX_PERIPHMEM_STATEST_MASK (0x3 << 8)
+
+/* Used by PRM_PHASE1_CNDP */
+#define DRA7XX_PHASE1_CNDP_SHIFT 0
+#define DRA7XX_PHASE1_CNDP_WIDTH 0x20
+#define DRA7XX_PHASE1_CNDP_MASK (0xffffffff << 0)
+
+/* Used by PRM_PHASE2A_CNDP */
+#define DRA7XX_PHASE2A_CNDP_SHIFT 0
+#define DRA7XX_PHASE2A_CNDP_WIDTH 0x20
+#define DRA7XX_PHASE2A_CNDP_MASK (0xffffffff << 0)
+
+/* Used by PRM_PHASE2B_CNDP */
+#define DRA7XX_PHASE2B_CNDP_SHIFT 0
+#define DRA7XX_PHASE2B_CNDP_WIDTH 0x20
+#define DRA7XX_PHASE2B_CNDP_MASK (0xffffffff << 0)
+
+/* Used by PRM_PSCON_COUNT */
+#define DRA7XX_PONOUT_2_PGOODIN_TIME_SHIFT 8
+#define DRA7XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8
+#define DRA7XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
+
+/*
+ * Used by PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CUSTEFUSE_PWRSTCTRL,
+ * PM_DSP1_PWRSTCTRL, PM_DSP2_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL,
+ * PM_EVE1_PWRSTCTRL, PM_EVE2_PWRSTCTRL, PM_EVE3_PWRSTCTRL, PM_EVE4_PWRSTCTRL,
+ * PM_GPU_PWRSTCTRL, PM_IPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
+ * PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_VPE_PWRSTCTRL
+ */
+#define DRA7XX_POWERSTATE_SHIFT 0
+#define DRA7XX_POWERSTATE_WIDTH 0x2
+#define DRA7XX_POWERSTATE_MASK (0x3 << 0)
+
+/*
+ * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
+ * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST
+ */
+#define DRA7XX_POWERSTATEST_SHIFT 0
+#define DRA7XX_POWERSTATEST_WIDTH 0x2
+#define DRA7XX_POWERSTATEST_MASK (0x3 << 0)
+
+/* Used by PRM_PWRREQCTRL */
+#define DRA7XX_PWRREQ_COND_SHIFT 0
+#define DRA7XX_PWRREQ_COND_WIDTH 0x2
+#define DRA7XX_PWRREQ_COND_MASK (0x3 << 0)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define DRA7XX_RAMP_DOWN_COUNT_SHIFT 16
+#define DRA7XX_RAMP_DOWN_COUNT_WIDTH 0x6
+#define DRA7XX_RAMP_DOWN_COUNT_MASK (0x3f << 16)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define DRA7XX_RAMP_DOWN_PRESCAL_SHIFT 24
+#define DRA7XX_RAMP_DOWN_PRESCAL_WIDTH 0x2
+#define DRA7XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define DRA7XX_RAMP_UP_COUNT_SHIFT 0
+#define DRA7XX_RAMP_UP_COUNT_WIDTH 0x6
+#define DRA7XX_RAMP_UP_COUNT_MASK (0x3f << 0)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define DRA7XX_RAMP_UP_PRESCAL_SHIFT 8
+#define DRA7XX_RAMP_UP_PRESCAL_WIDTH 0x2
+#define DRA7XX_RAMP_UP_PRESCAL_MASK (0x3 << 8)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define DRA7XX_RETAINED_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_RETAINED_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_RETAINED_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define DRA7XX_RETAINED_BANK_RETSTATE_SHIFT 8
+#define DRA7XX_RETAINED_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_RETAINED_BANK_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_L4PER_PWRSTST */
+#define DRA7XX_RETAINED_BANK_STATEST_SHIFT 4
+#define DRA7XX_RETAINED_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_RETAINED_BANK_STATEST_MASK (0x3 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_DSPEVE_CTRL, PRM_SLDO_GPU_CTRL,
+ * PRM_SLDO_IVA_CTRL, PRM_SLDO_MPU_CTRL
+ */
+#define DRA7XX_RETMODE_ENABLE_SHIFT 0
+#define DRA7XX_RETMODE_ENABLE_WIDTH 0x1
+#define DRA7XX_RETMODE_ENABLE_MASK (1 << 0)
+
+/* Used by PRM_RSTTIME */
+#define DRA7XX_RSTTIME1_SHIFT 0
+#define DRA7XX_RSTTIME1_WIDTH 0xa
+#define DRA7XX_RSTTIME1_MASK (0x3ff << 0)
+
+/* Used by PRM_RSTTIME */
+#define DRA7XX_RSTTIME2_SHIFT 10
+#define DRA7XX_RSTTIME2_WIDTH 0x5
+#define DRA7XX_RSTTIME2_MASK (0x1f << 10)
+
+/* Used by RM_IPU1_RSTCTRL, RM_IPU1_RSTST, RM_IPU2_RSTCTRL, RM_IPU2_RSTST */
+#define DRA7XX_RST_CPU0_SHIFT 0
+#define DRA7XX_RST_CPU0_WIDTH 0x1
+#define DRA7XX_RST_CPU0_MASK (1 << 0)
+
+/* Used by RM_IPU1_RSTCTRL, RM_IPU1_RSTST, RM_IPU2_RSTCTRL, RM_IPU2_RSTST */
+#define DRA7XX_RST_CPU1_SHIFT 1
+#define DRA7XX_RST_CPU1_WIDTH 0x1
+#define DRA7XX_RST_CPU1_MASK (1 << 1)
+
+/* Used by RM_DSP1_RSTCTRL, RM_DSP1_RSTST */
+#define DRA7XX_RST_DSP1_SHIFT 1
+#define DRA7XX_RST_DSP1_WIDTH 0x1
+#define DRA7XX_RST_DSP1_MASK (1 << 1)
+
+/* Used by RM_DSP1_RSTST */
+#define DRA7XX_RST_DSP1_EMU_SHIFT 2
+#define DRA7XX_RST_DSP1_EMU_WIDTH 0x1
+#define DRA7XX_RST_DSP1_EMU_MASK (1 << 2)
+
+/* Used by RM_DSP1_RSTST */
+#define DRA7XX_RST_DSP1_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_DSP1_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_DSP1_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_DSP1_RSTCTRL, RM_DSP1_RSTST */
+#define DRA7XX_RST_DSP1_LRST_SHIFT 0
+#define DRA7XX_RST_DSP1_LRST_WIDTH 0x1
+#define DRA7XX_RST_DSP1_LRST_MASK (1 << 0)
+
+/* Used by RM_DSP2_RSTCTRL, RM_DSP2_RSTST */
+#define DRA7XX_RST_DSP2_SHIFT 1
+#define DRA7XX_RST_DSP2_WIDTH 0x1
+#define DRA7XX_RST_DSP2_MASK (1 << 1)
+
+/* Used by RM_DSP2_RSTST */
+#define DRA7XX_RST_DSP2_EMU_SHIFT 2
+#define DRA7XX_RST_DSP2_EMU_WIDTH 0x1
+#define DRA7XX_RST_DSP2_EMU_MASK (1 << 2)
+
+/* Used by RM_DSP2_RSTST */
+#define DRA7XX_RST_DSP2_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_DSP2_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_DSP2_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_DSP2_RSTCTRL, RM_DSP2_RSTST */
+#define DRA7XX_RST_DSP2_LRST_SHIFT 0
+#define DRA7XX_RST_DSP2_LRST_WIDTH 0x1
+#define DRA7XX_RST_DSP2_LRST_MASK (1 << 0)
+
+/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
+#define DRA7XX_RST_EMULATION_CPU0_SHIFT 3
+#define DRA7XX_RST_EMULATION_CPU0_WIDTH 0x1
+#define DRA7XX_RST_EMULATION_CPU0_MASK (1 << 3)
+
+/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
+#define DRA7XX_RST_EMULATION_CPU1_SHIFT 4
+#define DRA7XX_RST_EMULATION_CPU1_WIDTH 0x1
+#define DRA7XX_RST_EMULATION_CPU1_MASK (1 << 4)
+
+/* Used by RM_IVA_RSTST */
+#define DRA7XX_RST_EMULATION_SEQ1_SHIFT 3
+#define DRA7XX_RST_EMULATION_SEQ1_WIDTH 0x1
+#define DRA7XX_RST_EMULATION_SEQ1_MASK (1 << 3)
+
+/* Used by RM_IVA_RSTST */
+#define DRA7XX_RST_EMULATION_SEQ2_SHIFT 4
+#define DRA7XX_RST_EMULATION_SEQ2_WIDTH 0x1
+#define DRA7XX_RST_EMULATION_SEQ2_MASK (1 << 4)
+
+/* Used by RM_EVE1_RSTCTRL, RM_EVE1_RSTST */
+#define DRA7XX_RST_EVE1_SHIFT 1
+#define DRA7XX_RST_EVE1_WIDTH 0x1
+#define DRA7XX_RST_EVE1_MASK (1 << 1)
+
+/* Used by RM_EVE1_RSTST */
+#define DRA7XX_RST_EVE1_EMU_SHIFT 2
+#define DRA7XX_RST_EVE1_EMU_WIDTH 0x1
+#define DRA7XX_RST_EVE1_EMU_MASK (1 << 2)
+
+/* Used by RM_EVE1_RSTST */
+#define DRA7XX_RST_EVE1_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_EVE1_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_EVE1_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_EVE1_RSTCTRL, RM_EVE1_RSTST */
+#define DRA7XX_RST_EVE1_LRST_SHIFT 0
+#define DRA7XX_RST_EVE1_LRST_WIDTH 0x1
+#define DRA7XX_RST_EVE1_LRST_MASK (1 << 0)
+
+/* Used by RM_EVE2_RSTCTRL, RM_EVE2_RSTST */
+#define DRA7XX_RST_EVE2_SHIFT 1
+#define DRA7XX_RST_EVE2_WIDTH 0x1
+#define DRA7XX_RST_EVE2_MASK (1 << 1)
+
+/* Used by RM_EVE2_RSTST */
+#define DRA7XX_RST_EVE2_EMU_SHIFT 2
+#define DRA7XX_RST_EVE2_EMU_WIDTH 0x1
+#define DRA7XX_RST_EVE2_EMU_MASK (1 << 2)
+
+/* Used by RM_EVE2_RSTST */
+#define DRA7XX_RST_EVE2_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_EVE2_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_EVE2_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_EVE2_RSTCTRL, RM_EVE2_RSTST */
+#define DRA7XX_RST_EVE2_LRST_SHIFT 0
+#define DRA7XX_RST_EVE2_LRST_WIDTH 0x1
+#define DRA7XX_RST_EVE2_LRST_MASK (1 << 0)
+
+/* Used by RM_EVE3_RSTCTRL, RM_EVE3_RSTST */
+#define DRA7XX_RST_EVE3_SHIFT 1
+#define DRA7XX_RST_EVE3_WIDTH 0x1
+#define DRA7XX_RST_EVE3_MASK (1 << 1)
+
+/* Used by RM_EVE3_RSTST */
+#define DRA7XX_RST_EVE3_EMU_SHIFT 2
+#define DRA7XX_RST_EVE3_EMU_WIDTH 0x1
+#define DRA7XX_RST_EVE3_EMU_MASK (1 << 2)
+
+/* Used by RM_EVE3_RSTST */
+#define DRA7XX_RST_EVE3_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_EVE3_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_EVE3_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_EVE3_RSTCTRL, RM_EVE3_RSTST */
+#define DRA7XX_RST_EVE3_LRST_SHIFT 0
+#define DRA7XX_RST_EVE3_LRST_WIDTH 0x1
+#define DRA7XX_RST_EVE3_LRST_MASK (1 << 0)
+
+/* Used by RM_EVE4_RSTCTRL, RM_EVE4_RSTST */
+#define DRA7XX_RST_EVE4_SHIFT 1
+#define DRA7XX_RST_EVE4_WIDTH 0x1
+#define DRA7XX_RST_EVE4_MASK (1 << 1)
+
+/* Used by RM_EVE4_RSTST */
+#define DRA7XX_RST_EVE4_EMU_SHIFT 2
+#define DRA7XX_RST_EVE4_EMU_WIDTH 0x1
+#define DRA7XX_RST_EVE4_EMU_MASK (1 << 2)
+
+/* Used by RM_EVE4_RSTST */
+#define DRA7XX_RST_EVE4_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_EVE4_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_EVE4_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_EVE4_RSTCTRL, RM_EVE4_RSTST */
+#define DRA7XX_RST_EVE4_LRST_SHIFT 0
+#define DRA7XX_RST_EVE4_LRST_WIDTH 0x1
+#define DRA7XX_RST_EVE4_LRST_MASK (1 << 0)
+
+/* Used by PRM_RSTCTRL */
+#define DRA7XX_RST_GLOBAL_COLD_SW_SHIFT 1
+#define DRA7XX_RST_GLOBAL_COLD_SW_WIDTH 0x1
+#define DRA7XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
+
+/* Used by PRM_RSTCTRL */
+#define DRA7XX_RST_GLOBAL_WARM_SW_SHIFT 0
+#define DRA7XX_RST_GLOBAL_WARM_SW_WIDTH 0x1
+#define DRA7XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
+
+/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
+#define DRA7XX_RST_ICECRUSHER_CPU0_SHIFT 5
+#define DRA7XX_RST_ICECRUSHER_CPU0_WIDTH 0x1
+#define DRA7XX_RST_ICECRUSHER_CPU0_MASK (1 << 5)
+
+/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
+#define DRA7XX_RST_ICECRUSHER_CPU1_SHIFT 6
+#define DRA7XX_RST_ICECRUSHER_CPU1_WIDTH 0x1
+#define DRA7XX_RST_ICECRUSHER_CPU1_MASK (1 << 6)
+
+/* Used by RM_IVA_RSTST */
+#define DRA7XX_RST_ICECRUSHER_SEQ1_SHIFT 5
+#define DRA7XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1
+#define DRA7XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5)
+
+/* Used by RM_IVA_RSTST */
+#define DRA7XX_RST_ICECRUSHER_SEQ2_SHIFT 6
+#define DRA7XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1
+#define DRA7XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6)
+
+/* Used by RM_IPU1_RSTCTRL, RM_IPU1_RSTST, RM_IPU2_RSTCTRL, RM_IPU2_RSTST */
+#define DRA7XX_RST_IPU_SHIFT 2
+#define DRA7XX_RST_IPU_WIDTH 0x1
+#define DRA7XX_RST_IPU_MASK (1 << 2)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define DRA7XX_RST_LOGIC_SHIFT 2
+#define DRA7XX_RST_LOGIC_WIDTH 0x1
+#define DRA7XX_RST_LOGIC_MASK (1 << 2)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define DRA7XX_RST_SEQ1_SHIFT 0
+#define DRA7XX_RST_SEQ1_WIDTH 0x1
+#define DRA7XX_RST_SEQ1_MASK (1 << 0)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define DRA7XX_RST_SEQ2_SHIFT 1
+#define DRA7XX_RST_SEQ2_WIDTH 0x1
+#define DRA7XX_RST_SEQ2_MASK (1 << 1)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_R_RTL_SHIFT 11
+#define DRA7XX_R_RTL_WIDTH 0x5
+#define DRA7XX_R_RTL_MASK (0x1f << 11)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_SCHEME_SHIFT 30
+#define DRA7XX_SCHEME_WIDTH 0x2
+#define DRA7XX_SCHEME_MASK (0x3 << 30)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_SECURE_WDT_RST_SHIFT 4
+#define DRA7XX_SECURE_WDT_RST_WIDTH 0x1
+#define DRA7XX_SECURE_WDT_RST_MASK (1 << 4)
+
+/* Used by PRM_DEBUG_CFG1 */
+#define DRA7XX_PRM_SEL1_SHIFT 0
+#define DRA7XX_PRM_SEL1_WIDTH 0x9
+#define DRA7XX_PRM_SEL1_MASK (0x1ff << 0)
+
+/* Used by PRM_DEBUG_CFG2 */
+#define DRA7XX_PRM_SEL2_SHIFT 0
+#define DRA7XX_PRM_SEL2_WIDTH 0x9
+#define DRA7XX_PRM_SEL2_MASK (0x1ff << 0)
+
+/* Used by PRM_DEBUG_CFG3 */
+#define DRA7XX_PRM_SEL3_SHIFT 0
+#define DRA7XX_PRM_SEL3_WIDTH 0x9
+#define DRA7XX_PRM_SEL3_MASK (0x1ff << 0)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_SL2_MEM_ONSTATE_SHIFT 18
+#define DRA7XX_SL2_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_SL2_MEM_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_SL2_MEM_RETSTATE_SHIFT 9
+#define DRA7XX_SL2_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_SL2_MEM_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_IVA_PWRSTST */
+#define DRA7XX_SL2_MEM_STATEST_SHIFT 6
+#define DRA7XX_SL2_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_SL2_MEM_STATEST_MASK (0x3 << 6)
+
+/* Used by PRM_SRAM_COUNT */
+#define DRA7XX_SLPCNT_VALUE_SHIFT 16
+#define DRA7XX_SLPCNT_VALUE_WIDTH 0x8
+#define DRA7XX_SLPCNT_VALUE_MASK (0xff << 16)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
+ * PRM_ABBLDO_MPU_SETUP
+ */
+#define DRA7XX_SR2EN_SHIFT 0
+#define DRA7XX_SR2EN_WIDTH 0x1
+#define DRA7XX_SR2EN_MASK (1 << 0)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
+ * PRM_ABBLDO_MPU_CTRL
+ */
+#define DRA7XX_SR2_IN_TRANSITION_SHIFT 6
+#define DRA7XX_SR2_IN_TRANSITION_WIDTH 0x1
+#define DRA7XX_SR2_IN_TRANSITION_MASK (1 << 6)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
+ * PRM_ABBLDO_MPU_CTRL
+ */
+#define DRA7XX_SR2_STATUS_SHIFT 3
+#define DRA7XX_SR2_STATUS_WIDTH 0x2
+#define DRA7XX_SR2_STATUS_MASK (0x3 << 3)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
+ * PRM_ABBLDO_MPU_SETUP
+ */
+#define DRA7XX_SR2_WTCNT_VALUE_SHIFT 8
+#define DRA7XX_SR2_WTCNT_VALUE_WIDTH 0x8
+#define DRA7XX_SR2_WTCNT_VALUE_MASK (0xff << 8)
+
+/*
+ * Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_DSPEVE_CTRL, PRM_SLDO_GPU_CTRL,
+ * PRM_SLDO_IVA_CTRL, PRM_SLDO_MPU_CTRL
+ */
+#define DRA7XX_SRAMLDO_STATUS_SHIFT 8
+#define DRA7XX_SRAMLDO_STATUS_WIDTH 0x1
+#define DRA7XX_SRAMLDO_STATUS_MASK (1 << 8)
+
+/*
+ * Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_DSPEVE_CTRL, PRM_SLDO_GPU_CTRL,
+ * PRM_SLDO_IVA_CTRL, PRM_SLDO_MPU_CTRL
+ */
+#define DRA7XX_SRAM_IN_TRANSITION_SHIFT 9
+#define DRA7XX_SRAM_IN_TRANSITION_WIDTH 0x1
+#define DRA7XX_SRAM_IN_TRANSITION_MASK (1 << 9)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define DRA7XX_STABLE_COUNT_SHIFT 0
+#define DRA7XX_STABLE_COUNT_WIDTH 0x6
+#define DRA7XX_STABLE_COUNT_MASK (0x3f << 0)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define DRA7XX_STABLE_PRESCAL_SHIFT 8
+#define DRA7XX_STABLE_PRESCAL_WIDTH 0x2
+#define DRA7XX_STABLE_PRESCAL_MASK (0x3 << 8)
+
+/* Used by PRM_BANDGAP_SETUP */
+#define DRA7XX_STARTUP_COUNT_SHIFT 0
+#define DRA7XX_STARTUP_COUNT_WIDTH 0x8
+#define DRA7XX_STARTUP_COUNT_MASK (0xff << 0)
+
+/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+#define DRA7XX_STARTUP_COUNT_24_31_SHIFT 24
+#define DRA7XX_STARTUP_COUNT_24_31_WIDTH 0x8
+#define DRA7XX_STARTUP_COUNT_24_31_MASK (0xff << 24)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_TCM1_MEM_ONSTATE_SHIFT 20
+#define DRA7XX_TCM1_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_TCM1_MEM_RETSTATE_SHIFT 10
+#define DRA7XX_TCM1_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_TCM1_MEM_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_IVA_PWRSTST */
+#define DRA7XX_TCM1_MEM_STATEST_SHIFT 8
+#define DRA7XX_TCM1_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_TCM1_MEM_STATEST_MASK (0x3 << 8)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_TCM2_MEM_ONSTATE_SHIFT 22
+#define DRA7XX_TCM2_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_TCM2_MEM_RETSTATE_SHIFT 11
+#define DRA7XX_TCM2_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_TCM2_MEM_RETSTATE_MASK (1 << 11)
+
+/* Used by PM_IVA_PWRSTST */
+#define DRA7XX_TCM2_MEM_STATEST_SHIFT 10
+#define DRA7XX_TCM2_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_TCM2_MEM_STATEST_MASK (0x3 << 10)
+
+/* Used by PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU */
+#define DRA7XX_TRANSITION_EN_SHIFT 8
+#define DRA7XX_TRANSITION_EN_WIDTH 0x1
+#define DRA7XX_TRANSITION_EN_MASK (1 << 8)
+
+/* Used by PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU */
+#define DRA7XX_TRANSITION_ST_SHIFT 8
+#define DRA7XX_TRANSITION_ST_WIDTH 0x1
+#define DRA7XX_TRANSITION_ST_MASK (1 << 8)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_CORE_RST_SHIFT 13
+#define DRA7XX_TSHUT_CORE_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_CORE_RST_MASK (1 << 13)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_DSPEVE_RST_SHIFT 15
+#define DRA7XX_TSHUT_DSPEVE_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_DSPEVE_RST_MASK (1 << 15)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_IVA_RST_SHIFT 16
+#define DRA7XX_TSHUT_IVA_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_IVA_RST_MASK (1 << 16)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_MM_RST_SHIFT 12
+#define DRA7XX_TSHUT_MM_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_MM_RST_MASK (1 << 12)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_MPU_RST_SHIFT 11
+#define DRA7XX_TSHUT_MPU_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_MPU_RST_MASK (1 << 11)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_CORE_I2C_DISABLE_SHIFT 12
+#define DRA7XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1
+#define DRA7XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8
+#define DRA7XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1
+#define DRA7XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_MM_I2C_DISABLE_SHIFT 14
+#define DRA7XX_VDD_MM_I2C_DISABLE_WIDTH 0x1
+#define DRA7XX_VDD_MM_I2C_DISABLE_MASK (1 << 14)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_MM_PRESENCE_SHIFT 9
+#define DRA7XX_VDD_MM_PRESENCE_WIDTH 0x1
+#define DRA7XX_VDD_MM_PRESENCE_MASK (1 << 9)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_VDD_MM_VOLT_MGR_RST_SHIFT 7
+#define DRA7XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1
+#define DRA7XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_MPU_I2C_DISABLE_SHIFT 13
+#define DRA7XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1
+#define DRA7XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_MPU_PRESENCE_SHIFT 8
+#define DRA7XX_VDD_MPU_PRESENCE_WIDTH 0x1
+#define DRA7XX_VDD_MPU_PRESENCE_MASK (1 << 8)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6
+#define DRA7XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1
+#define DRA7XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
+
+/* Used by PM_CAM_PWRSTCTRL */
+#define DRA7XX_VIP_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_VIP_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_VIP_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_CAM_PWRSTST */
+#define DRA7XX_VIP_BANK_STATEST_SHIFT 4
+#define DRA7XX_VIP_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_VIP_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
+#define DRA7XX_VOLTSTATEST_SHIFT 0
+#define DRA7XX_VOLTSTATEST_WIDTH 0x2
+#define DRA7XX_VOLTSTATEST_MASK (0x3 << 0)
+
+/* Used by PM_VPE_PWRSTCTRL */
+#define DRA7XX_VPE_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_VPE_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_VPE_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_VPE_PWRSTCTRL */
+#define DRA7XX_VPE_BANK_RETSTATE_SHIFT 8
+#define DRA7XX_VPE_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_VPE_BANK_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_VPE_PWRSTST */
+#define DRA7XX_VPE_BANK_STATEST_SHIFT 4
+#define DRA7XX_VPE_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_VPE_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_SRAM_COUNT */
+#define DRA7XX_VSETUPCNT_VALUE_SHIFT 8
+#define DRA7XX_VSETUPCNT_VALUE_WIDTH 0x8
+#define DRA7XX_VSETUPCNT_VALUE_MASK (0xff << 8)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_ADC_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_ADC_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_ADC_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_ADC_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_ADC_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_ADC_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_ADC_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_ADC_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_ADC_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_DCAN1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_DCAN1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_DCAN1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_DCAN1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_DCAN1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_DCAN1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_DCAN1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_DCAN1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_DCAN1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_DCAN1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_DCAN2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_DCAN2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_DCAN2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_DCAN2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_DCAN2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_DCAN2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_DCAN2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_DCAN2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_DCAN2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_DCAN2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_SDMA_MASK (1 << 3)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_DISPC_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_DSP1_MASK (1 << 2)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_DISPC_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_DSP2_MASK (1 << 5)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_DISPC_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_EVE1_MASK (1 << 6)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_DISPC_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_EVE2_MASK (1 << 7)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_DISPC_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_EVE3_MASK (1 << 8)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_DISPC_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_EVE4_MASK (1 << 9)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_DISPC_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_IPU1_MASK (1 << 4)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_DISPC_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_IPU2_MASK (1 << 1)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_DISPC_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_MPU_MASK (1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_DSI1_A_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_DSP1_MASK (1 << 12)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_DSI1_A_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_DSP2_MASK (1 << 15)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_DSI1_A_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_EVE1_MASK (1 << 16)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_DSI1_A_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_EVE2_MASK (1 << 17)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_DSI1_A_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_EVE3_MASK (1 << 18)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_DSI1_A_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_EVE4_MASK (1 << 19)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_DSI1_A_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_IPU1_MASK (1 << 14)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_DSI1_A_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_IPU2_MASK (1 << 11)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 10)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 13)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_DSP1_SHIFT 22
+#define DRA7XX_WKUPDEP_DSI1_B_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_DSP1_MASK (1 << 22)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_DSP2_SHIFT 25
+#define DRA7XX_WKUPDEP_DSI1_B_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_DSP2_MASK (1 << 25)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_EVE1_SHIFT 26
+#define DRA7XX_WKUPDEP_DSI1_B_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_EVE1_MASK (1 << 26)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_EVE2_SHIFT 27
+#define DRA7XX_WKUPDEP_DSI1_B_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_EVE2_MASK (1 << 27)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_EVE3_SHIFT 28
+#define DRA7XX_WKUPDEP_DSI1_B_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_EVE3_MASK (1 << 28)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_EVE4_SHIFT 29
+#define DRA7XX_WKUPDEP_DSI1_B_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_EVE4_MASK (1 << 29)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_IPU1_SHIFT 24
+#define DRA7XX_WKUPDEP_DSI1_B_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_IPU1_MASK (1 << 24)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_IPU2_SHIFT 21
+#define DRA7XX_WKUPDEP_DSI1_B_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_IPU2_MASK (1 << 21)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_MPU_SHIFT 20
+#define DRA7XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 20)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_SDMA_SHIFT 23
+#define DRA7XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 23)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_DSI1_C_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_DSP1_MASK (1 << 12)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_DSI1_C_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_DSP2_MASK (1 << 15)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_DSI1_C_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_EVE1_MASK (1 << 16)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_DSI1_C_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_EVE2_MASK (1 << 17)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_DSI1_C_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_EVE3_MASK (1 << 18)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_DSI1_C_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_EVE4_MASK (1 << 19)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_DSI1_C_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_IPU1_MASK (1 << 14)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_DSI1_C_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_IPU2_MASK (1 << 11)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 10)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 13)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_EVE1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_DSP1_MASK (1 << 2)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_EVE1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_DSP2_MASK (1 << 5)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_EVE1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_EVE2_MASK (1 << 7)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_EVE1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_EVE3_MASK (1 << 8)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_EVE1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_EVE4_MASK (1 << 9)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_EVE1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_IPU1_MASK (1 << 4)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_EVE1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_IPU2_MASK (1 << 1)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_EVE1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_MPU_MASK (1 << 0)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_EVE1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_SDMA_MASK (1 << 3)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_EVE2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_DSP1_MASK (1 << 2)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_EVE2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_DSP2_MASK (1 << 5)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_EVE2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_EVE1_MASK (1 << 6)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_EVE2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_EVE3_MASK (1 << 8)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_EVE2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_EVE4_MASK (1 << 9)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_EVE2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_IPU1_MASK (1 << 4)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_EVE2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_IPU2_MASK (1 << 1)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_EVE2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_MPU_MASK (1 << 0)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_EVE2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_SDMA_MASK (1 << 3)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_EVE3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_DSP1_MASK (1 << 2)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_EVE3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_DSP2_MASK (1 << 5)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_EVE3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_EVE1_MASK (1 << 6)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_EVE3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_EVE2_MASK (1 << 7)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_EVE3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_EVE4_MASK (1 << 9)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_EVE3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_IPU1_MASK (1 << 4)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_EVE3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_IPU2_MASK (1 << 1)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_EVE3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_MPU_MASK (1 << 0)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_EVE3_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_SDMA_MASK (1 << 3)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_EVE4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_DSP1_MASK (1 << 2)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_EVE4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_DSP2_MASK (1 << 5)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_EVE4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_EVE1_MASK (1 << 6)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_EVE4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_EVE2_MASK (1 << 7)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_EVE4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_EVE3_MASK (1 << 8)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_EVE4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_IPU1_MASK (1 << 4)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_EVE4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_IPU2_MASK (1 << 1)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_EVE4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_MPU_MASK (1 << 0)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_EVE4_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_SDMA_MASK (1 << 3)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP1_SHIFT 22
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP1_MASK (1 << 22)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP2_SHIFT 25
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP2_MASK (1 << 25)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 23
+#define DRA7XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 23)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C5_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_KBD_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_KBD_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_KBD_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_KBD_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_KBD_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_KBD_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_KBD_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_KBD_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_KBD_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP1_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP2_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP3_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP4_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP5_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP6_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP7_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP8_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCSPI1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCSPI1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCSPI1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCSPI1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCSPI1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCSPI1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCSPI1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCSPI1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCSPI2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCSPI2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCSPI2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCSPI2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCSPI2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCSPI2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCSPI2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCSPI2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCSPI3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCSPI3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCSPI3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCSPI3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCSPI3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCSPI3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCSPI3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCSPI3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCSPI4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCSPI4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCSPI4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCSPI4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCSPI4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCSPI4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCSPI4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCSPI4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MMC1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MMC1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MMC1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MMC1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MMC1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MMC1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MMC1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MMC1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MMC1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MMC2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MMC2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MMC2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MMC2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MMC2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MMC2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MMC2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MMC2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MMC2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MMC3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MMC3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MMC3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MMC3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MMC3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MMC3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MMC3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MMC3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MMC3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MMC4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MMC4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MMC4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MMC4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MMC4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MMC4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MMC4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MMC4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MMC4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_OCMC_RAM1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_OCMC_RAM2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_OCMC_RAM3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_QSPI_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_QSPI_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_QSPI_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_QSPI_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_QSPI_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_QSPI_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_QSPI_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_QSPI_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_QSPI_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_MPU_MASK (1 << 0)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_RTC_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_RTC_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SATA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SATA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SATA_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SATA_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SATA_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SATA_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SATA_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SATA_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SATA_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_MASK (1 << 3)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER10_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER10_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER10_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER10_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER10_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER10_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER10_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER10_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER11_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER11_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER11_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER11_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER11_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER11_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER11_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER11_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER12_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER12_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER12_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER12_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER12_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER12_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER12_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER12_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER13_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER13_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER13_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER13_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER13_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER13_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER13_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER13_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER13_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER14_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER14_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER14_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER14_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER14_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER14_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER14_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER14_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER14_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER15_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER15_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER15_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER15_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER15_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER15_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER15_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER15_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER15_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER16_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER16_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER16_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER16_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER16_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER16_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER16_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER16_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER16_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER5_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER5_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER5_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER5_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER5_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER5_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER5_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER5_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER6_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER6_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER6_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER6_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER6_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER6_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER6_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER6_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER7_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER7_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER7_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER7_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER7_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER7_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER7_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER7_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER8_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER8_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER8_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER8_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER8_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER8_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER8_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER8_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER9_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER9_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER9_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER9_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER9_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER9_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER9_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER9_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TPCC_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TPCC_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TPCC_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TPCC_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TPCC_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TPCC_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TPCC_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TPCC_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TPCC_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TPTC1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TPTC1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TPTC1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TPTC1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TPTC1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TPTC1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TPTC1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TPTC1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TPTC1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TPTC2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TPTC2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TPTC2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TPTC2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TPTC2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TPTC2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TPTC2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TPTC2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TPTC2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART10_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART10_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART10_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART10_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART10_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART10_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART10_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART10_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART10_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART10_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART3_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART4_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART5_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART5_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART5_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART5_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART5_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART5_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART5_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART5_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART5_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART5_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_SDMA_MASK (1 << 3)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART6_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART6_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART6_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART6_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART6_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART6_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART6_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART6_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART6_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART6_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART7_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART7_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART7_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART7_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART7_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART7_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART7_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART7_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART7_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART7_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART8_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART8_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART8_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART8_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART8_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART8_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART8_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART8_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART8_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART8_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART9_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART9_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART9_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART9_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART9_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART9_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART9_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART9_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART9_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART9_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_SDMA_MASK (1 << 3)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_MPU_MASK (1 << 0)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_VIP1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_DSP1_MASK (1 << 2)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_VIP1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_DSP2_MASK (1 << 5)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_VIP1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_EVE1_MASK (1 << 6)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_VIP1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_EVE2_MASK (1 << 7)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_VIP1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_EVE3_MASK (1 << 8)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_VIP1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_EVE4_MASK (1 << 9)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_VIP1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_IPU1_MASK (1 << 4)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_VIP1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_IPU2_MASK (1 << 1)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_VIP1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_MPU_MASK (1 << 0)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_VIP2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_DSP1_MASK (1 << 2)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_VIP2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_DSP2_MASK (1 << 5)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_VIP2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_EVE1_MASK (1 << 6)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_VIP2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_EVE2_MASK (1 << 7)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_VIP2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_EVE3_MASK (1 << 8)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_VIP2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_EVE4_MASK (1 << 9)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_VIP2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_IPU1_MASK (1 << 4)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_VIP2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_IPU2_MASK (1 << 1)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_VIP2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_MPU_MASK (1 << 0)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_VIP3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_DSP1_MASK (1 << 2)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_VIP3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_DSP2_MASK (1 << 5)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_VIP3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_EVE1_MASK (1 << 6)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_VIP3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_EVE2_MASK (1 << 7)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_VIP3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_EVE3_MASK (1 << 8)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_VIP3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_EVE4_MASK (1 << 9)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_VIP3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_IPU1_MASK (1 << 4)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_VIP3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_IPU2_MASK (1 << 1)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_VIP3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_MPU_MASK (1 << 0)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_VPE_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_DSP1_MASK (1 << 2)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_VPE_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_DSP2_MASK (1 << 5)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_VPE_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_EVE1_MASK (1 << 6)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_VPE_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_EVE2_MASK (1 << 7)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_VPE_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_EVE3_MASK (1 << 8)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_VPE_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_EVE4_MASK (1 << 9)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_VPE_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_IPU1_MASK (1 << 4)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_VPE_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_IPU2_MASK (1 << 1)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_VPE_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_WD_TIMER1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_WUCLK_CTRL_SHIFT 8
+#define DRA7XX_WUCLK_CTRL_WIDTH 0x1
+#define DRA7XX_WUCLK_CTRL_MASK (1 << 8)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_WUCLK_STATUS_SHIFT 9
+#define DRA7XX_WUCLK_STATUS_WIDTH 0x1
+#define DRA7XX_WUCLK_STATUS_MASK (1 << 9)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_X_MAJOR_SHIFT 8
+#define DRA7XX_X_MAJOR_WIDTH 0x3
+#define DRA7XX_X_MAJOR_MASK (0x7 << 8)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_Y_MINOR_SHIFT 0
+#define DRA7XX_Y_MINOR_WIDTH 0x6
+#define DRA7XX_Y_MINOR_MASK (0x3f << 0)
+#endif
index cb24b26f36e9d256090e82541a4e8ba3c67123a1..637b38a89e0dcb5510f4ceebcadb914e1ffa7cdc 100644 (file)
return 0;
}
+static int omap4_check_vcvp(void)
+{
+ if (soc_is_dra7xx())
+ return 0;
+
+ /* All others have VC/VP */
+ return 1;
+}
+
struct pwrdm_ops omap4_pwrdm_operations = {
.pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
.pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
.pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
.pwrdm_wait_transition = omap4_pwrdm_wait_transition,
+ .pwrdm_has_voltdm = omap4_check_vcvp,
};
/*
int __init omap44xx_prm_init(void)
{
- if (!cpu_is_omap44xx() && !soc_is_omap54xx())
+ if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
return 0;
return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
--- /dev/null
@@ -0,0 +1,690 @@
+/*
+ * DRA7xx PRM instance offset macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+#define DRA7XX_PRM_BASE 0x4ae06000
+
+#define DRA7XX_PRM_REGADDR(inst, reg) \
+ OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
+#define DRA7XX_PRM_CKGEN_INST 0x0100
+#define DRA7XX_PRM_MPU_INST 0x0300
+#define DRA7XX_PRM_DSP1_INST 0x0400
+#define DRA7XX_PRM_IPU_INST 0x0500
+#define DRA7XX_PRM_COREAON_INST 0x0628
+#define DRA7XX_PRM_CORE_INST 0x0700
+#define DRA7XX_PRM_IVA_INST 0x0f00
+#define DRA7XX_PRM_CAM_INST 0x1000
+#define DRA7XX_PRM_DSS_INST 0x1100
+#define DRA7XX_PRM_GPU_INST 0x1200
+#define DRA7XX_PRM_L3INIT_INST 0x1300
+#define DRA7XX_PRM_L4PER_INST 0x1400
+#define DRA7XX_PRM_CUSTEFUSE_INST 0x1600
+#define DRA7XX_PRM_WKUPAON_INST 0x1724
+#define DRA7XX_PRM_WKUPAON_CM_INST 0x1800
+#define DRA7XX_PRM_EMU_INST 0x1900
+#define DRA7XX_PRM_EMU_CM_INST 0x1a00
+#define DRA7XX_PRM_DSP2_INST 0x1b00
+#define DRA7XX_PRM_EVE1_INST 0x1b40
+#define DRA7XX_PRM_EVE2_INST 0x1b80
+#define DRA7XX_PRM_EVE3_INST 0x1bc0
+#define DRA7XX_PRM_EVE4_INST 0x1c00
+#define DRA7XX_PRM_RTC_INST 0x1c60
+#define DRA7XX_PRM_VPE_INST 0x1c80
+#define DRA7XX_PRM_DEVICE_INST 0x1d00
+#define DRA7XX_PRM_INSTR_INST 0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
+#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define DRA7XX_REVISION_PRM_OFFSET 0x0000
+#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
+#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
+#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
+#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
+#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020
+#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028
+#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030
+#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038
+#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040)
+#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044
+#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048
+#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c
+#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050
+#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054
+#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058
+#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c
+#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060
+#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064
+#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068
+#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c
+#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070
+#define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4
+#define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8
+#define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec
+#define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4
+
+/* PRM.CKGEN_PRM register offsets */
+#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000
+#define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
+#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
+#define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008)
+#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
+#define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c)
+#define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010
+#define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
+#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014
+#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014)
+#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018
+#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018)
+#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c
+#define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c)
+#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020
+#define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020)
+#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024
+#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024)
+#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028
+#define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028)
+#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c
+#define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c)
+#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030
+#define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030)
+#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034
+#define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034)
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038)
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040)
+#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044
+#define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044)
+#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048
+#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048)
+#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c
+#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c)
+#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050
+#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050)
+#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054
+#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054)
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058)
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c)
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060)
+#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064
+#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064)
+#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068
+#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068)
+#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c
+#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c)
+#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070
+#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070)
+#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074
+#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074)
+#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078
+#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078)
+#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080
+#define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080)
+#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084
+#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084)
+#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088
+#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088)
+#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c
+#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c)
+#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090
+#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090)
+#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094
+#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094)
+#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098
+#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098)
+#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c
+#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c)
+#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0
+#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0)
+#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4
+#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4)
+#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8
+#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8)
+#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac
+#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac)
+#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0
+#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0)
+#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4
+#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4)
+#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8
+#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8)
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc)
+#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0
+#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0)
+#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4
+#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4)
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8)
+#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc
+#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc)
+#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0
+#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0)
+#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4
+#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4)
+#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8
+#define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8)
+#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc
+#define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc)
+#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0
+#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)
+
+/* PRM.MPU_PRM register offsets */
+#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
+
+/* PRM.DSP1_PRM register offsets */
+#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024
+
+/* PRM.IPU_PRM register offsets */
+#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024
+#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054
+#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058
+#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c
+#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060
+#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064
+#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068
+#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c
+#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070
+#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074
+#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078
+#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c
+#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080
+#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084
+
+/* PRM.COREAON_PRM register offsets */
+#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000
+#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004
+#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010
+#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014
+#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030
+#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034
+#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040
+#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044
+#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054
+#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084
+#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094
+#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4
+#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4
+
+/* PRM.CORE_PRM register offsets */
+#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
+#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c
+#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064
+#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c
+#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070
+#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074
+#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078
+#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c
+#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080
+#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084
+#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c
+#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094
+#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c
+#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4
+#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac
+#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4
+#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc
+#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210
+#define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214
+#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224
+#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
+#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
+#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
+#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
+#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
+#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
+#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524
+#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
+#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
+#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634
+#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
+#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
+#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c
+#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654
+#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c
+#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664
+#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c
+#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674
+#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c
+#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684
+#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c
+#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694
+#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c
+#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc
+#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4
+#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724
+#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
+#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
+
+/* PRM.IVA_PRM register offsets */
+#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
+#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
+
+/* PRM.CAM_PRM register offsets */
+#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004
+#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024
+#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028
+#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c
+#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030
+#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034
+#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c
+#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044
+#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c
+
+/* PRM.DSS_PRM register offsets */
+#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004
+#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
+#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028
+#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
+#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c
+
+/* PRM.GPU_PRM register offsets */
+#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
+
+/* PRM.L3INIT_PRM register offsets */
+#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
+#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
+#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
+#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
+#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
+#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040
+#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044
+#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048
+#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c
+#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054
+#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c
+#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
+#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
+#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
+#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
+#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
+#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
+#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0
+#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4
+
+/* PRM.L4PER_PRM register offsets */
+#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c
+#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014
+#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c
+#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024
+#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028
+#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c
+#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030
+#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034
+#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038
+#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c
+#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040
+#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044
+#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048
+#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c
+#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054
+#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
+#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
+#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
+#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
+#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
+#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
+#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
+#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
+#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
+#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
+#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
+#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
+#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094
+#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c
+#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
+#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
+#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
+#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
+#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
+#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
+#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
+#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
+#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0
+#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4
+#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8
+#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc
+#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0
+#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4
+#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8
+#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc
+#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
+#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
+#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
+#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
+#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
+#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
+#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
+#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
+#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110
+#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114
+#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118
+#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c
+#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120
+#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124
+#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128
+#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c
+#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130
+#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134
+#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138
+#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c
+#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
+#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
+#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
+#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
+#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
+#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
+#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
+#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
+#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160
+#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164
+#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168
+#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c
+#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170
+#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174
+#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178
+#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c
+#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180
+#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184
+#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188
+#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c
+#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190
+#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194
+#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198
+#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c
+#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
+#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
+#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
+#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc
+#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
+#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
+#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0
+#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4
+#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc
+#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0
+#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4
+#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8
+#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec
+#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0
+#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4
+#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc
+
+/* PRM.CUSTEFUSE_PRM register offsets */
+#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
+
+/* PRM.WKUPAON_PRM register offsets */
+#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000
+#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004
+#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008
+#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c
+#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010
+#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014
+#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018
+#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c
+#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020
+#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024
+#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028
+#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030
+#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040
+#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054
+#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058
+#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c
+#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060
+#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064
+#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068
+#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c
+#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8
+#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0
+#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8
+
+/* PRM.WKUPAON_CM register offsets */
+#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020)
+#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028)
+#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030)
+#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
+#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038)
+#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040)
+#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
+#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048)
+#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050)
+#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
+#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060)
+#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078)
+#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080
+#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080)
+#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088)
+#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
+#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090)
+#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
+#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098)
+#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8)
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0)
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8)
+
+/* PRM.EMU_PRM register offsets */
+#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
+
+/* PRM.EMU_CM register offsets */
+#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004
+#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004)
+#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c
+#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c)
+
+/* PRM.DSP2_PRM register offsets */
+#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024
+
+/* PRM.EVE1_PRM register offsets */
+#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014
+#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024
+
+/* PRM.EVE2_PRM register offsets */
+#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014
+#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024
+
+/* PRM.EVE3_PRM register offsets */
+#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014
+#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024
+
+/* PRM.EVE4_PRM register offsets */
+#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014
+#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024
+
+/* PRM.RTC_PRM register offsets */
+#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000
+#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004
+
+/* PRM.VPE_PRM register offsets */
+#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004
+#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024
+
+/* PRM.DEVICE_PRM register offsets */
+#define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000
+#define DRA7XX_PRM_RSTST_OFFSET 0x0004
+#define DRA7XX_PRM_RSTTIME_OFFSET 0x0008
+#define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c
+#define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010
+#define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014
+#define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018
+#define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c
+#define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020
+#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
+#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
+#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
+#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
+#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
+#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
+#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
+#define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc
+#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
+#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
+#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
+#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
+#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
+#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4
+#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8
+#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
+#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
+#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4
+#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8
+#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
+#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
+#define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
+#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
+#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
+#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
+#define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110
+#define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114
+#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118
+#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c
+#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120
+#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124
+#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128
+#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c
+#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130
+#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134
+
+/* Function prototypes */
+#ifndef __ASSEMBLER__
+
+extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+
+#endif
+#endif
index 430fb1db14c255e1af193333c4bd0116399decc9..66a994bd006794bce7b35361acd204ef16719f0c 100644 (file)
#include "prcm-common.h"
#include "prm44xx.h"
#include "prm54xx.h"
+#include "prm7xx.h"
#include "prminst44xx.h"
#include "prm-regbits-44xx.h"
#include "prcm44xx.h"
{
u32 v;
s16 dev_inst = cpu_is_omap44xx() ? OMAP4430_PRM_DEVICE_INST :
- OMAP54XX_PRM_DEVICE_INST;
+ (soc_is_omap54xx() ?
+ OMAP54XX_PRM_DEVICE_INST :
+ DRA7XX_PRM_DEVICE_INST);
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
dev_inst,
index 037e69108662505e0b7c5e130aa15bdef9ff20eb..591a26ef9823819b10bc571f5ce2c5c8d8968240 100644 (file)
static LIST_HEAD(uart_list);
static u8 num_uarts;
static u8 console_uart_id = -1;
-static u8 no_console_suspend;
static u8 uart_debug;
#define DEFAULT_RXDMA_POLLRATE 1 /* RX DMA polling rate (us) */
uart_name, uart->num);
}
- if (cmdline_find_option("no_console_suspend"))
- no_console_suspend = true;
-
/*
* omap-uart can be used for earlyprintk logs
* So if omap-uart is used as console then prevent
return;
}
- if ((console_uart_id == bdata->id) && no_console_suspend)
- omap_device_disable_idle_on_suspend(pdev);
-
oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
if (console_uart_id == bdata->id) {
index eb03e28636d06a9d8815d24d899f5a1897734b00..872401c5cf08708e4caeb522b16d4145b5817a87 100644 (file)
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
* Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
# endif
#endif
+#ifdef CONFIG_SOC_DRA7XX
+# ifdef OMAP_NAME
+# undef MULTI_OMAP2
+# define MULTI_OMAP2
+# else
+# define OMAP_NAME DRA7XX
+# endif
+#endif
/*
* Omap device type i.e. EMU/HS/TST/GP/BAD
*/
* cpu_is_omap446x(): True for OMAP4460
* cpu_is_omap447x(): True for OMAP4470
* soc_is_omap543x(): True for OMAP5430, OMAP5432
+ * soc_is_dra75x(): True for DRA752
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
return (GET_TI_CLASS == (id)) ? 1 : 0; \
}
+#define IS_DRA_CLASS(class, id) \
+static inline int is_dra ##class(void) \
+{ \
+ return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
+}
+
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
#define IS_OMAP_SUBCLASS(subclass, id) \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
+#define IS_DRA_SUBCLASS(subclass, id) \
+static inline int is_dra ##subclass(void) \
+{ \
+ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
+}
+
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
IS_AM_CLASS(35xx, 0x35)
IS_OMAP_CLASS(54xx, 0x54)
+
+IS_DRA_CLASS(7xx, 0x7)
+
IS_AM_CLASS(33xx, 0x33)
IS_TI_CLASS(81xx, 0x81)
IS_OMAP_SUBCLASS(447x, 0x447)
IS_OMAP_SUBCLASS(543x, 0x543)
+IS_DRA_SUBCLASS(75x, 0x75)
+IS_DRA_SUBCLASS(74x, 0x74)
+
IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
#define cpu_is_omap447x() 0
#define soc_is_omap54xx() 0
#define soc_is_omap543x() 0
+#define soc_is_dra7xx() 0
+#define soc_is_dra75x() 0
#if defined(MULTI_OMAP2)
# if defined(CONFIG_ARCH_OMAP2)
# define soc_is_omap543x() is_omap543x()
#endif
+# if defined(CONFIG_SOC_DRA7XX)
+# undef soc_is_dra7xx
+# undef soc_is_dra75x
+# define soc_is_dra7xx() is_dra7xx()
+# define soc_is_dra75x() is_dra75x()
+#endif
+
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024
#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
+#define DRA7XX_CLASS 0x07000007
+#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
+
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
void omap5xxx_check_revision(void);
void omap3xxx_check_features(void);
void ti81xx_check_features(void);
+void am33xx_check_features(void);
void omap4xxx_check_features(void);
+void dra7xx_check_revision(void);
/*
* Runtime detection of OMAP3 features
index 6c50e4c7fca3b521a03af718c884663283a6b20e..8d40e8eb3bdaa3fd7131116b5611b47f4c82bcda 100644 (file)
omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */
omap_sram_size -= OMAP5_SRAM_HS_RESERVE;
omap_sram_start += OMAP5_SRAM_HS_RESERVE;
+ } else if (soc_is_dra7xx()) {
+ omap_sram_start = OMAP4_SRAM_START_PA;
+ omap_sram_size = DRA7XX_SRAM_SIZE; /* 512KB */
+ /*
+ * Fix me:
+ * The reservation size might change based on
+ * the PPA requirements.
+ */
+ omap_sram_size -= OMAP5_SRAM_HS_RESERVE;
+ omap_sram_start += OMAP5_SRAM_HS_RESERVE;
} else {
omap_sram_start = OMAP2_SRAM_PUB_PA;
omap_sram_size = 0x800; /* 2K */
omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */
omap_sram_size -= OMAP5_SRAM_GP_RESERVE;
omap_sram_start += OMAP5_SRAM_GP_RESERVE;
+ } else if (soc_is_dra7xx()) {
+ omap_sram_start = OMAP4_SRAM_START_PA;
+ omap_sram_size = DRA7XX_SRAM_SIZE; /* 512KB */
+ omap_sram_size -= OMAP5_SRAM_GP_RESERVE;
+ omap_sram_start += OMAP5_SRAM_GP_RESERVE;
} else {
omap_sram_start = OMAP2_SRAM_PA;
if (cpu_is_omap242x())
index 6476c38b3da93e792994d03ff9aa661e6aa75343..e19ec2ee2f5d3ef8aac9933d0903443b30c9be2e 100644 (file)
#define OMAP4_SRAM_SIZE (SZ_64K - SZ_8K)
/* OMAP5 has 128K */
#define OMAP5_SRAM_SIZE SZ_128K
+
+/* DRA7XX has 512K */
+#define DRA7XX_SRAM_SIZE SZ_512K
+
/* 16K GP, 52K HS(default) for secure world */
#define OMAP4_SRAM_GP_RESERVE SZ_16K
#ifdef CONFIG_OMAP4_HS_SECURE_SRAM_SIZE
index 286e18661487a7fa460d869ffb8ad70b7299294c..c6e1adc4681203fb7b8baafdc3327287bccf4667 100644 (file)
OMAP_SYS_TIMER(4, local);
#endif /* CONFIG_ARCH_OMAP4 */
-#ifdef CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
2, OMAP5_MPU_SOURCE);
static void __init omap5_realtime_timer_init(void)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 1e49d901f2c9212d665848a13c7d2099f5a8d3a9..0320495efc4d6ac6a3d49d3d96b6fcd9f3f0185f 100644 (file)
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
/* Fast UART1 on U335 only */
-#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
+#define U300_UART1_BASE (U300_FAST_PER_PHYS_BASE+0x7000)
/*
* SLOW peripherals
index dd3d59122cc374c80ad487ad57bc3f5fbc580325..48bc3c0a87ce321cc2e37c257bf217dc085307e6 100644 (file)
outer_cache.inv_range = feroceon_l2_inv_range;
outer_cache.clean_range = feroceon_l2_clean_range;
outer_cache.flush_range = feroceon_l2_flush_range;
+ outer_cache.inv_all = l2_inv_all;
enable_l2();
index 2c3b9421ab5eca938dfe9289fc39472259ada3c1..2556cf1c2da1c8f40c09edbe7d43b7c0286f355f 100644 (file)
/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
.globl cpu_arm920_suspend_size
.equ cpu_arm920_suspend_size, 4 * 3
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_arm920_do_suspend)
stmfd sp!, {r4 - r6, lr}
mrc p15, 0, r4, c13, c0, 0 @ PID
index f1803f7e29728460965675b6722a978d0cc33dcd..344c8a548cc0ef95aea9653d883b26c629f016dd 100644 (file)
/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
.globl cpu_arm926_suspend_size
.equ cpu_arm926_suspend_size, 4 * 3
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_arm926_do_suspend)
stmfd sp!, {r4 - r6, lr}
mrc p15, 0, r4, c13, c0, 0 @ PID
index 82f9cdc751d6421d01bcb4eca3de51dd211f1868..0b60dd3d742a1d909e4ffdf8d5162cd052754098 100644 (file)
.globl cpu_mohawk_suspend_size
.equ cpu_mohawk_suspend_size, 4 * 6
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_mohawk_do_suspend)
stmfd sp!, {r4 - r9, lr}
mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
index 3aa0da11fd8473376405d6fe57b76b777ca1cf93..d92dfd081429294200875ddedfbd6beb4fd98735 100644 (file)
.globl cpu_sa1100_suspend_size
.equ cpu_sa1100_suspend_size, 4 * 3
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_sa1100_do_suspend)
stmfd sp!, {r4 - r6, lr}
mrc p15, 0, r4, c3, c0, 0 @ domain ID
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 09c5233f4dfc81993312734e1ce434b92c131553..d222215b6fe8c0f68a70af5c95974c5e91f15cfa 100644 (file)
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
.globl cpu_v6_suspend_size
.equ cpu_v6_suspend_size, 4 * 6
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v6_do_suspend)
stmfd sp!, {r4 - r9, lr}
mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
index eb93d6487f3598fcb0cc6e92c0f3e23faa36fb11..e8efd83b6f252f00b85b29eb45d24bbd4919d4ae 100644 (file)
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
.globl cpu_xsc3_suspend_size
.equ cpu_xsc3_suspend_size, 4 * 6
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_xsc3_do_suspend)
stmfd sp!, {r4 - r9, lr}
mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
index 25510361aa181e7200d6f69a64d41ff6b8f8a8a6..e766f889bfd6d1b4159c6724a975468dbba56892 100644 (file)
.globl cpu_xscale_suspend_size
.equ cpu_xscale_suspend_size, 4 * 6
-#ifdef CONFIG_PM_SLEEP
+#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_xscale_do_suspend)
stmfd sp!, {r4 - r9, lr}
mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
index 23d429bbf73b708c083b12530ce52d2d64e8bc1c..5d6975084fb862672893bc36ade9eefb4d377333 100644 (file)
select TI_PRIV_EDMA
select USE_OF
help
- "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
+ "Systems based on OMAP2, OMAP3, OMAP4, OMAP5 or DRA7XX"
endchoice
This timer saves power compared to the OMAP_MPU_TIMER, and has
support for no tick during idle. The 32KHz timer provides less
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
- currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
+ currently only available for OMAP16XX, 24XX, 34XX, OMAP4/5 and DRA7XX.
On OMAP2PLUS this value is only used for CONFIG_HZ and
CLOCK_TICK_RATE compile time calculation.
index 7a32976fa2a3644af886006478aa791cf1f3779f..01b20a2074e9231a69b94544082c0e9693660caf 100644 (file)
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
xen_init_IRQ();
if (request_percpu_irq(xen_events_irq, xen_arm_callback,
- "events", xen_vcpu)) {
+ "events", &xen_vcpu)) {
pr_err("Error requesting IRQ %d\n", xen_events_irq);
return -EINVAL;
}
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index afadae6682ed8b867f6165b0e92860f0f0cc566d..0782eaf491363c5bdd08673dfe57a65fae48b89c 100644 (file)
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
#define VM_FAULT_BADACCESS 0x020000
#define ESR_WRITE (1 << 6)
+#define ESR_CM (1 << 8)
#define ESR_LNX_EXEC (1 << 24)
/*
struct task_struct *tsk;
struct mm_struct *mm;
int fault, sig, code;
- int write = esr & ESR_WRITE;
+ bool write = (esr & ESR_WRITE) && !(esr & ESR_CM);
unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
(write ? FAULT_FLAG_WRITE : 0);
index 0421498d666b979b992446fe83603325786f2e03..97918204f7958eb3ddeab58890970c37f9a9e2fe 100644 (file)
CONFIG_USB_CDC_COMPOSITE=m
CONFIG_MMC=y
CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_ATMELMCI_DMA=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_ATMEL_PWM=m
index 3befab966827bacb4339247637e27d39333a7b1b..65de4431108c837334dc07facfc578fb815d55cd 100644 (file)
CONFIG_LOGO=y
CONFIG_MMC=y
CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_ATMELMCI_DMA=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_ATMEL_PWM=y
index d2bf1fd5e44f5970caf455acdddc671fc0dee192..76acbcd5c06090e25cd35e77b3afbd5c16f7c0ae 100644 (file)
return -EFAULT;
{
- register unsigned long r8 __asm ("r8");
+ register unsigned long r8 __asm ("r8") = 0;
unsigned long prev;
__asm__ __volatile__(
" mf;; \n"
- " mov %0=r0 \n"
" mov ar.ccv=%4;; \n"
"[1:] cmpxchg4.acq %1=[%2],%3,ar.ccv \n"
" .xdata4 \"__ex_table\", 1b-., 2f-. \n"
"[2:]"
- : "=r" (r8), "=r" (prev)
+ : "+r" (r8), "=&r" (prev)
: "r" (uaddr), "r" (newval),
"rO" ((long) (unsigned) oldval)
: "memory");
index 43f96ab18fa0d2754ff5f79374c02e785ec24347..8c709616871626f175164a5f237bfa0cec1af2d9 100644 (file)
extern int cpe_vector;
extern int ia64_cpe_irq;
extern void ia64_mca_init(void);
+extern void ia64_mca_irq_init(void);
extern void ia64_mca_cpu_init(void *);
extern void ia64_os_mca_dispatch(void);
extern void ia64_os_mca_dispatch_end(void);
diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c
index ad69606613eb6d336a6f73af5f6c45eb2c936eb1..f2c41828113050c19f0f09ce6d97beb733ebcd3e 100644 (file)
--- a/arch/ia64/kernel/irq.c
+++ b/arch/ia64/kernel/irq.c
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
+#include <asm/mca.h>
+
/*
* 'what should we do if we get a hw irq event on an illegal vector'.
* each architecture has to answer this themselves.
#endif /* CONFIG_SMP */
+int __init arch_early_irq_init(void)
+{
+ ia64_mca_irq_init();
+ return 0;
+}
+
#ifdef CONFIG_HOTPLUG_CPU
unsigned int vectors_in_migration[NR_IRQS];
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index 65bf9cd390443c3574e8d4da5a175c566928b535..d7396dbb07bb40598c2a7de3b26ffc34bf5de8ca 100644 (file)
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
printk(KERN_INFO "MCA related initialization done\n");
}
+
/*
- * ia64_mca_late_init
- *
- * Opportunity to setup things that require initialization later
- * than ia64_mca_init. Setup a timer to poll for CPEs if the
- * platform doesn't support an interrupt driven mechanism.
- *
- * Inputs : None
- * Outputs : Status
+ * These pieces cannot be done in ia64_mca_init() because it is called before
+ * early_irq_init() which would wipe out our percpu irq registrations. But we
+ * cannot leave them until ia64_mca_late_init() because by then all the other
+ * processors have been brought online and have set their own CMC vectors to
+ * point at a non-existant action. Called from arch_early_irq_init().
*/
-static int __init
-ia64_mca_late_init(void)
+void __init ia64_mca_irq_init(void)
{
- if (!mca_init)
- return 0;
-
/*
* Configure the CMCI/P vector and handler. Interrupts for CMC are
* per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
/* Setup the CPEI/P handler */
register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
#endif
+}
+
+/*
+ * ia64_mca_late_init
+ *
+ * Opportunity to setup things that require initialization later
+ * than ia64_mca_init. Setup a timer to poll for CPEs if the
+ * platform doesn't support an interrupt driven mechanism.
+ *
+ * Inputs : None
+ * Outputs : Status
+ */
+static int __init
+ia64_mca_late_init(void)
+{
+ if (!mca_init)
+ return 0;
register_hotcpu_notifier(&mca_cpu_notifier);
diff --git a/arch/ia64/kvm/vtlb.c b/arch/ia64/kvm/vtlb.c
index 4332f7ee5203f27179db08b5a95d372c6509e681..a7869f8f49a6604cd550750766250aeb0d04756c 100644 (file)
--- a/arch/ia64/kvm/vtlb.c
+++ b/arch/ia64/kvm/vtlb.c
"srlz.d;;"
"ssm psr.i;;"
"srlz.d;;"
- : "=r"(ret) : "r"(iha), "r"(pte):"memory");
+ : "=&r"(ret) : "r"(iha), "r"(pte) : "memory");
return ret;
}
index dbaec94046dab06348eb688887b73e2513e3b666..21bff32ca854519aa8129bfd10f274812954e4de 100644 (file)
#define PAGE_SHIFT 16
#endif
#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK (~(PAGE_SIZE - 1))
+#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
#define HPAGE_SHIFT (PAGE_SHIFT + PAGE_SHIFT - 3)
index 51fb00a20d7ea4a02304b43cf14a3a1593ef8350..4f440a65f6e1060e6d8e37a9f7ad492624425da6 100644 (file)
#define PPC_INST_MFSPR_DSCR_MASK 0xfc1fffff
#define PPC_INST_MTSPR_DSCR 0x7c1103a6
#define PPC_INST_MTSPR_DSCR_MASK 0xfc1fffff
+#define PPC_INST_MFSPR_DSCR_USER 0x7c0302a6
+#define PPC_INST_MFSPR_DSCR_USER_MASK 0xfc1fffff
+#define PPC_INST_MTSPR_DSCR_USER 0x7c0303a6
+#define PPC_INST_MTSPR_DSCR_USER_MASK 0xfc1fffff
#define PPC_INST_SLBFEE 0x7c0007a7
#define PPC_INST_STRING 0x7c00042a
index 57cf14065aecfd261269e21b428d8aba4f4856f4..0c0fc7b559a59401c45b232feba274a4fcd6a1f2 100644 (file)
mflr r11
mfmsr r3
rldicl. r0,r3,4,63
+ mtlr r11
beqlr
li r0,0
mtspr SPRN_LPID,r0
index 3d990d3bd8baf5923d019208f7782d42e7f8a458..e0822a36192a88a1f630a1f6647a22e6799a35de 100644 (file)
/* Clear _TIF_EMULATE_STACK_STORE flag */
lis r11,_TIF_EMULATE_STACK_STORE@h
addi r5,r9,TI_FLAGS
- ldarx r4,0,r5
+0: ldarx r4,0,r5
andc r4,r4,r11
stdcx. r4,0,r5
bne- 0b
index 3684cbdd87926cf3ff4437c283629f933c36c081..bb1107597140633d8b11d55e4909a0e6bb3416a1 100644 (file)
_MASKABLE_RELON_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV, SOFTEN_TEST_HV)
FTR_SECTION_ELSE
_MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD, SOFTEN_TEST_PR)
- ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_206)
+ ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
STD_RELON_EXCEPTION_PSERIES(0x4600, 0x600, alignment)
STD_RELON_EXCEPTION_PSERIES(0x4700, 0x700, program_check)
STD_RELON_EXCEPTION_PSERIES(0x4800, 0x800, fp_unavailable)
index 116f0868695bc65a689d0759f9391247dc14eed3..1a63febf5edddd263ee4f3cbc603ed87ab184204 100644 (file)
sync
addi r5,r5,8
addi r6,r6,8
+ isync
blr
.align 8
index 32518401af68d274be52d52cf9249505496d07a9..6686794c963901ead0ab8fe4adf17f9e79f7a92d 100644 (file)
#ifdef CONFIG_PPC64
/* Emulate the mfspr rD, DSCR. */
- if (((instword & PPC_INST_MFSPR_DSCR_MASK) == PPC_INST_MFSPR_DSCR) &&
+ if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
+ PPC_INST_MFSPR_DSCR_USER) ||
+ ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
+ PPC_INST_MFSPR_DSCR)) &&
cpu_has_feature(CPU_FTR_DSCR)) {
PPC_WARN_EMULATED(mfdscr, regs);
rd = (instword >> 21) & 0x1f;
return 0;
}
/* Emulate the mtspr DSCR, rD. */
- if (((instword & PPC_INST_MTSPR_DSCR_MASK) == PPC_INST_MTSPR_DSCR) &&
+ if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
+ PPC_INST_MTSPR_DSCR_USER) ||
+ ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
+ PPC_INST_MTSPR_DSCR)) &&
cpu_has_feature(CPU_FTR_DSCR)) {
PPC_WARN_EMULATED(mtdscr, regs);
rd = (instword >> 21) & 0x1f;
index 1f89d26e65fb72534e130ed755bfe3874740316f..2f4baa074b2ebf0bf9cfe497055afbe9460ec4a5 100644 (file)
{
}
+static DEFINE_PER_CPU(struct kvm_vcpu *, last_vcpu_on_cpu);
+
void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
{
struct kvmppc_vcpu_e500 *vcpu_e500 = to_e500(vcpu);
mtspr(SPRN_GDEAR, vcpu->arch.shared->dar);
mtspr(SPRN_GESR, vcpu->arch.shared->esr);
- if (vcpu->arch.oldpir != mfspr(SPRN_PIR))
+ if (vcpu->arch.oldpir != mfspr(SPRN_PIR) ||
+ __get_cpu_var(last_vcpu_on_cpu) != vcpu) {
kvmppc_e500_tlbil_all(vcpu_e500);
+ __get_cpu_var(last_vcpu_on_cpu) = vcpu;
+ }
kvmppc_load_guest_fp(vcpu);
}
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index bba87ca2b4d78a1a8fbedd70e6122d583d365d79..6a252c468d6809361400fcc0ac2784cfcd08fc21 100644 (file)
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
int distance = LOCAL_DISTANCE;
if (!form1_affinity)
- return distance;
+ return ((a == b) ? LOCAL_DISTANCE : REMOTE_DISTANCE);
for (i = 0; i < distance_ref_points_depth; i++) {
if (distance_lookup_table[a][i] == distance_lookup_table[b][i])
index dba1ce235da59e23172cd5d6474d9ce4a72900ac..506dc9f9fbe318b5a5d76ac80d97b0d327db82c4 100644 (file)
if (!inode)
goto out;
+ inode->i_ino = get_next_ino();
inode->i_mode = mode;
inode->i_uid = current_fsuid();
inode->i_gid = current_fsgid();
index 27cb32185ce1d950e5a6097198a1864a69e6594b..379d96e2105ea1d60f79a4cd881593a188a61c01 100644 (file)
#define ioremap_nocache(addr, size) ioremap(addr, size)
#define ioremap_wc ioremap_nocache
-/* TODO: s390 cannot support io_remap_pfn_range... */
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
- remap_pfn_range(vma, vaddr, pfn, size, prot)
-
static inline void __iomem *ioremap(unsigned long offset, unsigned long size)
{
return (void __iomem *) offset;
index 098adbb62660be234d4d2ed5171d5c0615027f31..1532d7f33381867ca750688142478ebeac53e926 100644 (file)
(((unsigned long)(vaddr)) &zero_page_mask))))
#define __HAVE_COLOR_ZERO_PAGE
+/* TODO: s390 cannot support io_remap_pfn_range... */
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
+ remap_pfn_range(vma, vaddr, pfn, size, prot)
+
#endif /* !__ASSEMBLY__ */
/*
index 08fcce90316b36654dea14af5525a94a0cded6e8..7619f2f792aff549905ca49d1a70b3cd7514979c 100644 (file)
return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot);
}
+#include <asm/tlbflush.h>
#include <asm-generic/pgtable.h>
/* We provide our own get_unmapped_area to cope with VA holes and
index cad36f56fa03e6605797c4dca13f5127048b47d7..c7de3323819c5389a8c1855f09aa542cd67f4d41 100644 (file)
* and 2 stores in this critical code path. -DaveM
*/
#define switch_to(prev, next, last) \
-do { flush_tlb_pending(); \
- save_and_clear_fpu(); \
+do { save_and_clear_fpu(); \
/* If you are tempted to conditionalize the following */ \
/* so that ASI is only written if it changes, think again. */ \
__asm__ __volatile__("wr %%g0, %0, %%asi" \
index 2ef463494153a65adec7c7a59a37c0095fda2649..f0d6a9700f4c8351e20be4743d9782c590b9e016 100644 (file)
struct tlb_batch {
struct mm_struct *mm;
unsigned long tlb_nr;
+ unsigned long active;
unsigned long vaddrs[TLB_BATCH_NR];
};
extern void flush_tsb_kernel_range(unsigned long start, unsigned long end);
extern void flush_tsb_user(struct tlb_batch *tb);
+extern void flush_tsb_user_page(struct mm_struct *mm, unsigned long vaddr);
/* TLB flush operations. */
-extern void flush_tlb_pending(void);
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+}
+
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+ unsigned long vmaddr)
+{
+}
+
+static inline void flush_tlb_range(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end)
+{
+}
+
+#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
-#define flush_tlb_range(vma,start,end) \
- do { (void)(start); flush_tlb_pending(); } while (0)
-#define flush_tlb_page(vma,addr) flush_tlb_pending()
-#define flush_tlb_mm(mm) flush_tlb_pending()
+extern void flush_tlb_pending(void);
+extern void arch_enter_lazy_mmu_mode(void);
+extern void arch_leave_lazy_mmu_mode(void);
+#define arch_flush_lazy_mmu_mode() do {} while (0)
/* Local cpu only. */
extern void __flush_tlb_all(void);
-
+extern void __flush_tlb_page(unsigned long context, unsigned long vaddr);
extern void __flush_tlb_kernel_range(unsigned long start, unsigned long end);
#ifndef CONFIG_SMP
__flush_tlb_kernel_range(start,end); \
} while (0)
+static inline void global_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
+{
+ __flush_tlb_page(CTX_HWBITS(mm->context), vaddr);
+}
+
#else /* CONFIG_SMP */
extern void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end);
+extern void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr);
#define flush_tlb_kernel_range(start, end) \
do { flush_tsb_kernel_range(start,end); \
smp_flush_tlb_kernel_range(start, end); \
} while (0)
+#define global_flush_tlb_page(mm, vaddr) \
+ smp_flush_tlb_page(mm, vaddr)
+
#endif /* ! CONFIG_SMP */
#endif /* _SPARC64_TLBFLUSH_H */
index 537eb66abd0654054aef7402ffaf857ad3971a85..ca64d2a86ec03e4189b88367906456e99de77a14 100644 (file)
}
extern unsigned long xcall_flush_tlb_mm;
-extern unsigned long xcall_flush_tlb_pending;
+extern unsigned long xcall_flush_tlb_page;
extern unsigned long xcall_flush_tlb_kernel_range;
extern unsigned long xcall_fetch_glob_regs;
extern unsigned long xcall_fetch_glob_pmu;
put_cpu();
}
+struct tlb_pending_info {
+ unsigned long ctx;
+ unsigned long nr;
+ unsigned long *vaddrs;
+};
+
+static void tlb_pending_func(void *info)
+{
+ struct tlb_pending_info *t = info;
+
+ __flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
+}
+
void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
{
u32 ctx = CTX_HWBITS(mm->context);
+ struct tlb_pending_info info;
int cpu = get_cpu();
+ info.ctx = ctx;
+ info.nr = nr;
+ info.vaddrs = vaddrs;
+
if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
else
- smp_cross_call_masked(&xcall_flush_tlb_pending,
- ctx, nr, (unsigned long) vaddrs,
- mm_cpumask(mm));
+ smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
+ &info, 1);
__flush_tlb_pending(ctx, nr, vaddrs);
put_cpu();
}
+void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
+{
+ unsigned long context = CTX_HWBITS(mm->context);
+ int cpu = get_cpu();
+
+ if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
+ cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
+ else
+ smp_cross_call_masked(&xcall_flush_tlb_page,
+ context, vaddr, 0,
+ mm_cpumask(mm));
+ __flush_tlb_page(context, vaddr);
+
+ put_cpu();
+}
+
void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
{
start &= PAGE_MASK;
diff --git a/arch/sparc/mm/tlb.c b/arch/sparc/mm/tlb.c
index ba6ae7ffdc2c9d5d1e3bbbb8d2af3b68a2f2572e..83d89bcb44afcace24b757b02ce5305c1e762afe 100644 (file)
--- a/arch/sparc/mm/tlb.c
+++ b/arch/sparc/mm/tlb.c
void flush_tlb_pending(void)
{
struct tlb_batch *tb = &get_cpu_var(tlb_batch);
+ struct mm_struct *mm = tb->mm;
- if (tb->tlb_nr) {
- flush_tsb_user(tb);
+ if (!tb->tlb_nr)
+ goto out;
- if (CTX_VALID(tb->mm->context)) {
+ flush_tsb_user(tb);
+
+ if (CTX_VALID(mm->context)) {
+ if (tb->tlb_nr == 1) {
+ global_flush_tlb_page(mm, tb->vaddrs[0]);
+ } else {
#ifdef CONFIG_SMP
smp_flush_tlb_pending(tb->mm, tb->tlb_nr,
&tb->vaddrs[0]);
tb->tlb_nr, &tb->vaddrs[0]);
#endif
}
- tb->tlb_nr = 0;
}
+ tb->tlb_nr = 0;
+
+out:
put_cpu_var(tlb_batch);
}
+void arch_enter_lazy_mmu_mode(void)
+{
+ struct tlb_batch *tb = &__get_cpu_var(tlb_batch);
+
+ tb->active = 1;
+}
+
+void arch_leave_lazy_mmu_mode(void)
+{
+ struct tlb_batch *tb = &__get_cpu_var(tlb_batch);
+
+ if (tb->tlb_nr)
+ flush_tlb_pending();
+ tb->active = 0;
+}
+
static void tlb_batch_add_one(struct mm_struct *mm, unsigned long vaddr,
bool exec)
{
nr = 0;
}
+ if (!tb->active) {
+ global_flush_tlb_page(mm, vaddr);
+ flush_tsb_user_page(mm, vaddr);
+ goto out;
+ }
+
if (nr == 0)
tb->mm = mm;
if (nr >= TLB_BATCH_NR)
flush_tlb_pending();
+out:
put_cpu_var(tlb_batch);
}
diff --git a/arch/sparc/mm/tsb.c b/arch/sparc/mm/tsb.c
index 428982b9becfe267b33ad2745efb36b5dc861a11..2cc3bce5ee914a158a16960c4ece028cc959b83a 100644 (file)
--- a/arch/sparc/mm/tsb.c
+++ b/arch/sparc/mm/tsb.c
#include <linux/preempt.h>
#include <linux/slab.h>
#include <asm/page.h>
-#include <asm/tlbflush.h>
-#include <asm/tlb.h>
-#include <asm/mmu_context.h>
#include <asm/pgtable.h>
+#include <asm/mmu_context.h>
#include <asm/tsb.h>
+#include <asm/tlb.h>
#include <asm/oplib.h>
extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
}
}
-static void __flush_tsb_one(struct tlb_batch *tb, unsigned long hash_shift,
- unsigned long tsb, unsigned long nentries)
+static void __flush_tsb_one_entry(unsigned long tsb, unsigned long v,
+ unsigned long hash_shift,
+ unsigned long nentries)
{
- unsigned long i;
+ unsigned long tag, ent, hash;
- for (i = 0; i < tb->tlb_nr; i++) {
- unsigned long v = tb->vaddrs[i];
- unsigned long tag, ent, hash;
+ v &= ~0x1UL;
+ hash = tsb_hash(v, hash_shift, nentries);
+ ent = tsb + (hash * sizeof(struct tsb));
+ tag = (v >> 22UL);
- v &= ~0x1UL;
+ tsb_flush(ent, tag);
+}
- hash = tsb_hash(v, hash_shift, nentries);
- ent = tsb + (hash * sizeof(struct tsb));
- tag = (v >> 22UL);
+static void __flush_tsb_one(struct tlb_batch *tb, unsigned long hash_shift,
+ unsigned long tsb, unsigned long nentries)
+{
+ unsigned long i;
- tsb_flush(ent, tag);
- }
+ for (i = 0; i < tb->tlb_nr; i++)
+ __flush_tsb_one_entry(tsb, tb->vaddrs[i], hash_shift, nentries);
}
void flush_tsb_user(struct tlb_batch *tb)
spin_unlock_irqrestore(&mm->context.lock, flags);
}
+void flush_tsb_user_page(struct mm_struct *mm, unsigned long vaddr)
+{
+ unsigned long nentries, base, flags;
+
+ spin_lock_irqsave(&mm->context.lock, flags);
+
+ base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb;
+ nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries;
+ if (tlb_type == cheetah_plus || tlb_type == hypervisor)
+ base = __pa(base);
+ __flush_tsb_one_entry(base, vaddr, PAGE_SHIFT, nentries);
+
+#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
+ if (mm->context.tsb_block[MM_TSB_HUGE].tsb) {
+ base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb;
+ nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries;
+ if (tlb_type == cheetah_plus || tlb_type == hypervisor)
+ base = __pa(base);
+ __flush_tsb_one_entry(base, vaddr, HPAGE_SHIFT, nentries);
+ }
+#endif
+ spin_unlock_irqrestore(&mm->context.lock, flags);
+}
+
#define HV_PGSZ_IDX_BASE HV_PGSZ_IDX_8K
#define HV_PGSZ_MASK_BASE HV_PGSZ_MASK_8K
diff --git a/arch/sparc/mm/ultra.S b/arch/sparc/mm/ultra.S
index f8e13d421fcbf415dd49a50bc2ed4aaf2b3b6494..29b96081e19c1bda232f6dfd1e20e3e1fa58cfb7 100644 (file)
--- a/arch/sparc/mm/ultra.S
+++ b/arch/sparc/mm/ultra.S
nop
nop
+ .align 32
+ .globl __flush_tlb_page
+__flush_tlb_page: /* 22 insns */
+ /* %o0 = context, %o1 = vaddr */
+ rdpr %pstate, %g7
+ andn %g7, PSTATE_IE, %g2
+ wrpr %g2, %pstate
+ mov SECONDARY_CONTEXT, %o4
+ ldxa [%o4] ASI_DMMU, %g2
+ stxa %o0, [%o4] ASI_DMMU
+ andcc %o1, 1, %g0
+ andn %o1, 1, %o3
+ be,pn %icc, 1f
+ or %o3, 0x10, %o3
+ stxa %g0, [%o3] ASI_IMMU_DEMAP
+1: stxa %g0, [%o3] ASI_DMMU_DEMAP
+ membar #Sync
+ stxa %g2, [%o4] ASI_DMMU
+ sethi %hi(KERNBASE), %o4
+ flush %o4
+ retl
+ wrpr %g7, 0x0, %pstate
+ nop
+ nop
+ nop
+ nop
+
.align 32
.globl __flush_tlb_pending
__flush_tlb_pending: /* 26 insns */
retl
wrpr %g7, 0x0, %pstate
+__cheetah_flush_tlb_page: /* 22 insns */
+ /* %o0 = context, %o1 = vaddr */
+ rdpr %pstate, %g7
+ andn %g7, PSTATE_IE, %g2
+ wrpr %g2, 0x0, %pstate
+ wrpr %g0, 1, %tl
+ mov PRIMARY_CONTEXT, %o4
+ ldxa [%o4] ASI_DMMU, %g2
+ srlx %g2, CTX_PGSZ1_NUC_SHIFT, %o3
+ sllx %o3, CTX_PGSZ1_NUC_SHIFT, %o3
+ or %o0, %o3, %o0 /* Preserve nucleus page size fields */
+ stxa %o0, [%o4] ASI_DMMU
+ andcc %o1, 1, %g0
+ be,pn %icc, 1f
+ andn %o1, 1, %o3
+ stxa %g0, [%o3] ASI_IMMU_DEMAP
+1: stxa %g0, [%o3] ASI_DMMU_DEMAP
+ membar #Sync
+ stxa %g2, [%o4] ASI_DMMU
+ sethi %hi(KERNBASE), %o4
+ flush %o4
+ wrpr %g0, 0, %tl
+ retl
+ wrpr %g7, 0x0, %pstate
+
__cheetah_flush_tlb_pending: /* 27 insns */
/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
rdpr %pstate, %g7
retl
nop
+__hypervisor_flush_tlb_page: /* 11 insns */
+ /* %o0 = context, %o1 = vaddr */
+ mov %o0, %g2
+ mov %o1, %o0 /* ARG0: vaddr + IMMU-bit */
+ mov %g2, %o1 /* ARG1: mmu context */
+ mov HV_MMU_ALL, %o2 /* ARG2: flags */
+ srlx %o0, PAGE_SHIFT, %o0
+ sllx %o0, PAGE_SHIFT, %o0
+ ta HV_MMU_UNMAP_ADDR_TRAP
+ brnz,pn %o0, __hypervisor_tlb_tl0_error
+ mov HV_MMU_UNMAP_ADDR_TRAP, %o1
+ retl
+ nop
+
__hypervisor_flush_tlb_pending: /* 16 insns */
/* %o0 = context, %o1 = nr, %o2 = vaddrs[] */
sllx %o1, 3, %g1
call tlb_patch_one
mov 19, %o2
+ sethi %hi(__flush_tlb_page), %o0
+ or %o0, %lo(__flush_tlb_page), %o0
+ sethi %hi(__cheetah_flush_tlb_page), %o1
+ or %o1, %lo(__cheetah_flush_tlb_page), %o1
+ call tlb_patch_one
+ mov 22, %o2
+
sethi %hi(__flush_tlb_pending), %o0
or %o0, %lo(__flush_tlb_pending), %o0
sethi %hi(__cheetah_flush_tlb_pending), %o1
nop
nop
- .globl xcall_flush_tlb_pending
-xcall_flush_tlb_pending: /* 21 insns */
- /* %g5=context, %g1=nr, %g7=vaddrs[] */
- sllx %g1, 3, %g1
+ .globl xcall_flush_tlb_page
+xcall_flush_tlb_page: /* 17 insns */
+ /* %g5=context, %g1=vaddr */
mov PRIMARY_CONTEXT, %g4
ldxa [%g4] ASI_DMMU, %g2
srlx %g2, CTX_PGSZ1_NUC_SHIFT, %g4
or %g5, %g4, %g5
mov PRIMARY_CONTEXT, %g4
stxa %g5, [%g4] ASI_DMMU
-1: sub %g1, (1 << 3), %g1
- ldx [%g7 + %g1], %g5
- andcc %g5, 0x1, %g0
+ andcc %g1, 0x1, %g0
be,pn %icc, 2f
-
- andn %g5, 0x1, %g5
+ andn %g1, 0x1, %g5
stxa %g0, [%g5] ASI_IMMU_DEMAP
2: stxa %g0, [%g5] ASI_DMMU_DEMAP
membar #Sync
- brnz,pt %g1, 1b
- nop
stxa %g2, [%g4] ASI_DMMU
retry
nop
+ nop
.globl xcall_flush_tlb_kernel_range
xcall_flush_tlb_kernel_range: /* 25 insns */
membar #Sync
retry
- .globl __hypervisor_xcall_flush_tlb_pending
-__hypervisor_xcall_flush_tlb_pending: /* 21 insns */
- /* %g5=ctx, %g1=nr, %g7=vaddrs[], %g2,%g3,%g4,g6=scratch */
- sllx %g1, 3, %g1
+ .globl __hypervisor_xcall_flush_tlb_page
+__hypervisor_xcall_flush_tlb_page: /* 17 insns */
+ /* %g5=ctx, %g1=vaddr */
mov %o0, %g2
mov %o1, %g3
mov %o2, %g4
-1: sub %g1, (1 << 3), %g1
- ldx [%g7 + %g1], %o0 /* ARG0: virtual address */
+ mov %g1, %o0 /* ARG0: virtual address */
mov %g5, %o1 /* ARG1: mmu context */
mov HV_MMU_ALL, %o2 /* ARG2: flags */
srlx %o0, PAGE_SHIFT, %o0
mov HV_MMU_UNMAP_ADDR_TRAP, %g6
brnz,a,pn %o0, __hypervisor_tlb_xcall_error
mov %o0, %g5
- brnz,pt %g1, 1b
- nop
mov %g2, %o0
mov %g3, %o1
mov %g4, %o2
call tlb_patch_one
mov 10, %o2
+ sethi %hi(__flush_tlb_page), %o0
+ or %o0, %lo(__flush_tlb_page), %o0
+ sethi %hi(__hypervisor_flush_tlb_page), %o1
+ or %o1, %lo(__hypervisor_flush_tlb_page), %o1
+ call tlb_patch_one
+ mov 11, %o2
+
sethi %hi(__flush_tlb_pending), %o0
or %o0, %lo(__flush_tlb_pending), %o0
sethi %hi(__hypervisor_flush_tlb_pending), %o1
call tlb_patch_one
mov 21, %o2
- sethi %hi(xcall_flush_tlb_pending), %o0
- or %o0, %lo(xcall_flush_tlb_pending), %o0
- sethi %hi(__hypervisor_xcall_flush_tlb_pending), %o1
- or %o1, %lo(__hypervisor_xcall_flush_tlb_pending), %o1
+ sethi %hi(xcall_flush_tlb_page), %o0
+ or %o0, %lo(xcall_flush_tlb_page), %o0
+ sethi %hi(__hypervisor_xcall_flush_tlb_page), %o1
+ or %o1, %lo(__hypervisor_xcall_flush_tlb_page), %o1
call tlb_patch_one
- mov 21, %o2
+ mov 17, %o2
sethi %hi(xcall_flush_tlb_kernel_range), %o0
or %o0, %lo(xcall_flush_tlb_kernel_range), %o0
index 93c6d39237ac3753c1f1e7600351192715829a90..b0f7d3937ebbc86d73f3b54df0224a9177281f83 100644 (file)
* SOFTWARE.
*/
+#include <asm/inst.h>
+
## ISCSI CRC 32 Implementation with crc32 and pclmulqdq Instruction
.macro LABEL prefix n
movdqa (bufp), %xmm0 # 2 consts: K1:K2
movq crc_init, %xmm1 # CRC for block 1
- pclmulqdq $0x00,%xmm0,%xmm1 # Multiply by K2
+ PCLMULQDQ 0x00,%xmm0,%xmm1 # Multiply by K2
movq crc1, %xmm2 # CRC for block 2
- pclmulqdq $0x10, %xmm0, %xmm2 # Multiply by K1
+ PCLMULQDQ 0x10, %xmm0, %xmm2 # Multiply by K1
pxor %xmm2,%xmm1
movq %xmm1, %rax
index dc87b65e9c3a065b51c908bd9c964134718a5b94..85039f97f2d81e8879769f270299c6d4bf569cf4 100644 (file)
gpa_t time;
struct pvclock_vcpu_time_info hv_clock;
unsigned int hw_tsc_khz;
- unsigned int time_offset;
- struct page *time_page;
+ struct gfn_to_hva_cache pv_time;
+ bool pv_time_enabled;
/* set guest stopped flag in pvclock flags field */
bool pvclock_set_guest_stopped_request;
index 4914e94ad6e86a9565420dcac8d014ff679ab6fa..70602f81f052042195475f44f58978e6893b518c 100644 (file)
};
static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
- INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
- INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
+ INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
+ INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
+ EVENT_EXTRA_END
+};
+
+static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
+ INTEL_EVENT_EXTRA_REG(0xb7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
+ INTEL_EVENT_EXTRA_REG(0xbb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
EVENT_EXTRA_END
};
x86_pmu.event_constraints = intel_snb_event_constraints;
x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
- x86_pmu.extra_regs = intel_snb_extra_regs;
+ if (boot_cpu_data.x86_model == 45)
+ x86_pmu.extra_regs = intel_snbep_extra_regs;
+ else
+ x86_pmu.extra_regs = intel_snb_extra_regs;
/* all extra regs are per-cpu when HT is on */
x86_pmu.er_flags |= ERF_HAS_RSP_1;
x86_pmu.er_flags |= ERF_NO_HT_SHARING;
x86_pmu.event_constraints = intel_snb_event_constraints;
x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
- x86_pmu.extra_regs = intel_snb_extra_regs;
+ if (boot_cpu_data.x86_model == 62)
+ x86_pmu.extra_regs = intel_snbep_extra_regs;
+ else
+ x86_pmu.extra_regs = intel_snb_extra_regs;
/* all extra regs are per-cpu when HT is on */
x86_pmu.er_flags |= ERF_HAS_RSP_1;
x86_pmu.er_flags |= ERF_NO_HT_SHARING;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index da02e9cc3754b4a2c1a37c1edb44865143f7f723..d978353c939bba235a29e76fda02d1f8eb97f84a 100644 (file)
* - in case there is no HW filter
* - in case the HW filter has errata or limitations
*/
-static void intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
+static int intel_pmu_setup_sw_lbr_filter(struct perf_event *event)
{
u64 br_type = event->attr.branch_sample_type;
int mask = 0;
if (br_type & PERF_SAMPLE_BRANCH_USER)
mask |= X86_BR_USER;
- if (br_type & PERF_SAMPLE_BRANCH_KERNEL)
+ if (br_type & PERF_SAMPLE_BRANCH_KERNEL) {
+ if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN))
+ return -EACCES;
mask |= X86_BR_KERNEL;
+ }
/* we ignore BRANCH_HV here */
* be used by fixup code for some CPU
*/
event->hw.branch_reg.reg = mask;
+
+ return 0;
}
/*
/*
* setup SW LBR filter
*/
- intel_pmu_setup_sw_lbr_filter(event);
+ ret = intel_pmu_setup_sw_lbr_filter(event);
+ if (ret)
+ return ret;
/*
* setup HW LBR filter, if any
return X86_BR_NONE;
addr = buf;
- } else
- addr = (void *)from;
+ } else {
+ /*
+ * The LBR logs any address in the IP, even if the IP just
+ * faulted. This means userspace can control the from address.
+ * Ensure we don't blindy read any address by validating it is
+ * a known text address.
+ */
+ if (kernel_text_address(from))
+ addr = (void *)from;
+ else
+ return X86_BR_NONE;
+ }
/*
* decoder needs to know the ABI especially
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore.c b/arch/x86/kernel/cpu/perf_event_intel_uncore.c
index b43200dbfe7e179d65386f0dfb3b4afd3f33bf36..3e091f04487c89c9f977044dc7477bcd3ffc17d4 100644 (file)
static int __init uncore_type_init(struct intel_uncore_type *type)
{
struct intel_uncore_pmu *pmus;
- struct attribute_group *events_group;
+ struct attribute_group *attr_group;
struct attribute **attrs;
int i, j;
while (type->event_descs[i].attr.attr.name)
i++;
- events_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
- sizeof(*events_group), GFP_KERNEL);
- if (!events_group)
+ attr_group = kzalloc(sizeof(struct attribute *) * (i + 1) +
+ sizeof(*attr_group), GFP_KERNEL);
+ if (!attr_group)
goto fail;
- attrs = (struct attribute **)(events_group + 1);
- events_group->name = "events";
- events_group->attrs = attrs;
+ attrs = (struct attribute **)(attr_group + 1);
+ attr_group->name = "events";
+ attr_group->attrs = attrs;
for (j = 0; j < i; j++)
attrs[j] = &type->event_descs[j].attr.attr;
- type->events_group = events_group;
+ type->events_group = attr_group;
}
type->pmu_group = &uncore_pmu_attr_group;
msr_uncores = nhm_msr_uncores;
break;
case 42: /* Sandy Bridge */
+ case 58: /* Ivy Bridge */
if (snb_uncore_cbox.num_boxes > max_cores)
snb_uncore_cbox.num_boxes = max_cores;
msr_uncores = snb_msr_uncores;
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index e4595f10591071c4af181bc0a16a2bf2d901a30f..84b778962c661ce3a00f6c333038d4fa328628a2 100644 (file)
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
u64 arch_irq_stat(void)
{
u64 sum = atomic_read(&irq_err_count);
-
-#ifdef CONFIG_X86_IO_APIC
- sum += atomic_read(&irq_mis_count);
-#endif
return sum;
}
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index a27e763711087df9e095f440b7e6aaf76cfeff5b..d330b3c619f8f2abc903ad8605a9d36ed20ea110 100644 (file)
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
break;
case OpMem8:
ctxt->memop.bytes = 1;
+ if (ctxt->memop.type == OP_REG) {
+ ctxt->memop.addr.reg = decode_register(ctxt, ctxt->modrm_rm, 1);
+ fetch_register_operand(&ctxt->memop);
+ }
goto mem_common;
case OpMem16:
ctxt->memop.bytes = 2;
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 9392f527f107490b9fc8d036f971994c3823b31d..a2f492c33e08db4c6be7aa9dbbee10257167e1d2 100644 (file)
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
if (!pv_eoi_enabled(vcpu))
return 0;
return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
- addr);
+ addr, sizeof(u8));
}
void kvm_lapic_init(void)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index c243b81e3c74b56bb69d7d26e692ac4181d73320..9a51121a06ee6c47c44461f1eeb00885b0090205 100644 (file)
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
unsigned long flags, this_tsc_khz;
struct kvm_vcpu_arch *vcpu = &v->arch;
struct kvm_arch *ka = &v->kvm->arch;
- void *shared_kaddr;
s64 kernel_ns, max_kernel_ns;
u64 tsc_timestamp, host_tsc;
- struct pvclock_vcpu_time_info *guest_hv_clock;
+ struct pvclock_vcpu_time_info guest_hv_clock;
u8 pvclock_flags;
bool use_master_clock;
local_irq_restore(flags);
- if (!vcpu->time_page)
+ if (!vcpu->pv_time_enabled)
return 0;
/*
*/
vcpu->hv_clock.version += 2;
- shared_kaddr = kmap_atomic(vcpu->time_page);
-
- guest_hv_clock = shared_kaddr + vcpu->time_offset;
+ if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
+ &guest_hv_clock, sizeof(guest_hv_clock))))
+ return 0;
/* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
- pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
+ pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
if (vcpu->pvclock_set_guest_stopped_request) {
pvclock_flags |= PVCLOCK_GUEST_STOPPED;
vcpu->hv_clock.flags = pvclock_flags;
- memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
- sizeof(vcpu->hv_clock));
-
- kunmap_atomic(shared_kaddr);
-
- mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
+ kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
+ &vcpu->hv_clock,
+ sizeof(vcpu->hv_clock));
return 0;
}
return 0;
}
- if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
+ if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
+ sizeof(u32)))
return 1;
vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
static void kvmclock_reset(struct kvm_vcpu *vcpu)
{
- if (vcpu->arch.time_page) {
- kvm_release_page_dirty(vcpu->arch.time_page);
- vcpu->arch.time_page = NULL;
- }
+ vcpu->arch.pv_time_enabled = false;
}
static void accumulate_steal_time(struct kvm_vcpu *vcpu)
break;
case MSR_KVM_SYSTEM_TIME_NEW:
case MSR_KVM_SYSTEM_TIME: {
+ u64 gpa_offset;
kvmclock_reset(vcpu);
vcpu->arch.time = data;
if (!(data & 1))
break;
- /* ...but clean it before doing the actual write */
- vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
-
- vcpu->arch.time_page =
- gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
+ gpa_offset = data & ~(PAGE_MASK | 1);
- if (is_error_page(vcpu->arch.time_page))
- vcpu->arch.time_page = NULL;
+ if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
+ &vcpu->arch.pv_time, data & ~1ULL,
+ sizeof(struct pvclock_vcpu_time_info)))
+ vcpu->arch.pv_time_enabled = false;
+ else
+ vcpu->arch.pv_time_enabled = true;
break;
}
return 1;
if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
- data & KVM_STEAL_VALID_BITS))
+ data & KVM_STEAL_VALID_BITS,
+ sizeof(struct kvm_steal_time)))
return 1;
vcpu->arch.st.msr_val = data;
*/
static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
{
- if (!vcpu->arch.time_page)
+ if (!vcpu->arch.pv_time_enabled)
return -EINVAL;
vcpu->arch.pvclock_set_guest_stopped_request = true;
kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
goto fail_free_wbinvd_dirty_mask;
vcpu->arch.ia32_tsc_adjust_msr = 0x0;
+ vcpu->arch.pv_time_enabled = false;
kvm_async_pf_hash_reset(vcpu);
kvm_pmu_init(vcpu);
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index d7aea41563b372437eb227a499259be23d755564..7d7a36d645d3e492f17c71ac31c76252aeabd207 100644 (file)
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
int i;
unsigned long puds = 0, pmds = 0, ptes = 0, tables;
unsigned long start = 0, good_end;
+ unsigned long pgd_extra = 0;
phys_addr_t base;
for (i = 0; i < nr_range; i++) {
unsigned long range, extra;
+ if ((mr[i].end >> PGDIR_SHIFT) - (mr[i].start >> PGDIR_SHIFT))
+ pgd_extra++;
+
range = mr[i].end - mr[i].start;
puds += (range + PUD_SIZE - 1) >> PUD_SHIFT;
tables = roundup(puds * sizeof(pud_t), PAGE_SIZE);
tables += roundup(pmds * sizeof(pmd_t), PAGE_SIZE);
tables += roundup(ptes * sizeof(pte_t), PAGE_SIZE);
+ tables += (pgd_extra * PAGE_SIZE);
#ifdef CONFIG_X86_32
/* for fixmap */
index 226200384983c26ccecec932910fbf402c912687..08c6511bf1ba4d5f8f2a80b863ffddf1f706fc3b 100644 (file)
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
switch (action) {
case CPU_UP_PREPARE:
xen_vcpu_setup(cpu);
- if (xen_have_vector_callback)
+ if (xen_have_vector_callback) {
xen_init_lock_cpu(cpu);
+ if (xen_feature(XENFEAT_hvm_safe_pvclock))
+ xen_setup_timer(cpu);
+ }
break;
default:
break;
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 34bc4cee8887b2c2d974c99ca81b78577f719ff9..48d7b2cf92d905c921e436cd98d1b219c5b69224 100644 (file)
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
unbind_from_irqhandler(per_cpu(xen_debug_irq, cpu), NULL);
unbind_from_irqhandler(per_cpu(xen_callfuncsingle_irq, cpu), NULL);
unbind_from_irqhandler(per_cpu(xen_irq_work, cpu), NULL);
+ xen_uninit_lock_cpu(cpu);
+ xen_teardown_timer(cpu);
native_cpu_die(cpu);
}
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 0296a95225017912cec06b9794683e62b20a5382..054cc01bb849acbb7c9cc9a98e0484c3f1b308ff 100644 (file)
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
{
int cpu = smp_processor_id();
xen_setup_runstate_info(cpu);
- xen_setup_timer(cpu);
+ /*
+ * xen_setup_timer(cpu) - snprintf is bad in atomic context. Hence
+ * doing it xen_hvm_cpu_notify (which gets called by smp_init during
+ * early bootup and also during CPU hotplug events).
+ */
xen_setup_cpu_clockevents();
}
diff --git a/crypto/algif_hash.c b/crypto/algif_hash.c
index ef5356cd280a54c086e4f8ff964245e38748a391..0262210cad386bde9b75f45d823c730920a54756 100644 (file)
--- a/crypto/algif_hash.c
+++ b/crypto/algif_hash.c
else if (len < ds)
msg->msg_flags |= MSG_TRUNC;
+ msg->msg_namelen = 0;
+
lock_sock(sk);
if (ctx->more) {
ctx->more = 0;
index 6a6dfc062d2a47f04449fbb0e1c3f3852be337dc..a1c4f0a555832089129eb77be3680aea03856148 100644 (file)
--- a/crypto/algif_skcipher.c
+++ b/crypto/algif_skcipher.c
long copied = 0;
lock_sock(sk);
+ msg->msg_namelen = 0;
for (iov = msg->msg_iov, iovlen = msg->msg_iovlen; iovlen > 0;
iovlen--, iov++) {
unsigned long seglen = iov->iov_len;
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
index bd22f8667eed65e3889e61dcc357d85f5f3d1239..299996603160b464b23aab69396f7b10c9713a72 100644 (file)
--- a/drivers/acpi/osl.c
+++ b/drivers/acpi/osl.c
* Both memblock_reserve and e820_add_region (via arch_reserve_mem_area)
* works fine.
*/
- memblock_reserve(acpi_tables_addr, acpi_tables_addr + all_tables_size);
+ memblock_reserve(acpi_tables_addr, all_tables_size);
arch_reserve_mem_area(acpi_tables_addr, all_tables_size);
p = early_ioremap(acpi_tables_addr, all_tables_size);
index eb737981c077b317cc04ea13636214ed5fc18c98..77c9a9249eccf116276edd706b9464ec6b750c31 100644 (file)
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
*control &= OSC_PCI_CONTROL_MASKS;
capbuf[OSC_CONTROL_TYPE] = *control | root->osc_control_set;
} else {
- /* Run _OSC query for all possible controls. */
- capbuf[OSC_CONTROL_TYPE] = OSC_PCI_CONTROL_MASKS;
+ /* Run _OSC query only with existing controls. */
+ capbuf[OSC_CONTROL_TYPE] = root->osc_control_set;
}
status = acpi_pci_run_osc(root->device->handle, capbuf, &result);
diff --git a/drivers/acpi/thermal.c b/drivers/acpi/thermal.c
index 506fbd4b5733b5f1751d8c23521aaa398447e33d..25246e80fc4204d845091539e3a923678cba27a3 100644 (file)
--- a/drivers/acpi/thermal.c
+++ b/drivers/acpi/thermal.c
return -EINVAL;
if (type == THERMAL_TRIP_ACTIVE) {
- /* aggressive active cooling */
- *trend = THERMAL_TREND_RAISING;
- return 0;
+ unsigned long trip_temp;
+ unsigned long temp = KELVIN_TO_MILLICELSIUS(tz->temperature,
+ tz->kelvin_offset);
+ if (thermal_get_trip_temp(thermal, trip, &trip_temp))
+ return -EINVAL;
+
+ if (temp > trip_temp) {
+ *trend = THERMAL_TREND_RAISING;
+ return 0;
+ } else {
+ /* Fall back on default trend */
+ return -EINVAL;
+ }
}
/*
index ef01ac07502e54625cbf02b7ae7ff11322f5c245..cc8aa9e0782da89bfff4e7d3795c572092d059d4 100644 (file)
if (ap->flags & ATA_FLAG_ACPI_SATA)
return NULL;
- return acpi_get_child(DEVICE_ACPI_HANDLE(ap->host->dev), ap->port_no);
+ return ap->scsi_host ?
+ DEVICE_ACPI_HANDLE(&ap->scsi_host->shost_gendev) : NULL;
}
EXPORT_SYMBOL(ata_ap_acpi_handle);
}
}
-/**
- * ata_acpi_gtm - execute _GTM
- * @ap: target ATA port
- * @gtm: out parameter for _GTM result
- *
- * Evaluate _GTM and store the result in @gtm.
- *
- * LOCKING:
- * EH context.
- *
- * RETURNS:
- * 0 on success, -ENOENT if _GTM doesn't exist, -errno on failure.
- */
-int ata_acpi_gtm(struct ata_port *ap, struct ata_acpi_gtm *gtm)
+static int __ata_acpi_gtm(struct ata_port *ap, acpi_handle handle,
+ struct ata_acpi_gtm *gtm)
{
struct acpi_buffer output = { .length = ACPI_ALLOCATE_BUFFER };
union acpi_object *out_obj;
acpi_status status;
int rc = 0;
- status = acpi_evaluate_object(ata_ap_acpi_handle(ap), "_GTM", NULL,
- &output);
+ status = acpi_evaluate_object(handle, "_GTM", NULL, &output);
rc = -ENOENT;
if (status == AE_NOT_FOUND)
return rc;
}
+/**
+ * ata_acpi_gtm - execute _GTM
+ * @ap: target ATA port
+ * @gtm: out parameter for _GTM result
+ *
+ * Evaluate _GTM and store the result in @gtm.
+ *
+ * LOCKING:
+ * EH context.
+ *
+ * RETURNS:
+ * 0 on success, -ENOENT if _GTM doesn't exist, -errno on failure.
+ */
+int ata_acpi_gtm(struct ata_port *ap, struct ata_acpi_gtm *gtm)
+{
+ if (ata_ap_acpi_handle(ap))
+ return __ata_acpi_gtm(ap, ata_ap_acpi_handle(ap), gtm);
+ else
+ return -EINVAL;
+}
+
EXPORT_SYMBOL_GPL(ata_acpi_gtm);
/**
if (!*handle)
return -ENODEV;
- if (ata_acpi_gtm(ap, &ap->__acpi_init_gtm) == 0)
+ if (__ata_acpi_gtm(ap, *handle, &ap->__acpi_init_gtm) == 0)
ap->pflags |= ATA_PFLAG_INIT_GTM_VALID;
return 0;
index 5dba77ccaa0b9e89badebcad04b2525c7d5e9add..b1a664a8f55d21737049eaa430c32d8beb4fb2aa 100644 (file)
};
static struct scsi_host_template ahci_highbank_platform_sht = {
- AHCI_SHT("highbank-ahci"),
+ AHCI_SHT("sata_highbank"),
};
static const struct of_device_id ahci_of_match[] = {
diff --git a/drivers/char/hpet.c b/drivers/char/hpet.c
index fe6d4be4829600d9c6e44078f95ddb65b84ba957..615d2624ad3104bc3833bbc9c247e093efa8690d 100644 (file)
--- a/drivers/char/hpet.c
+++ b/drivers/char/hpet.c
struct hpet_dev *devp;
unsigned long addr;
- if (((vma->vm_end - vma->vm_start) != PAGE_SIZE) || vma->vm_pgoff)
- return -EINVAL;
-
devp = file->private_data;
addr = devp->hd_hpets->hp_hpet_phys;
if (addr & (PAGE_SIZE - 1))
return -ENOSYS;
- vma->vm_flags |= VM_IO;
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-
- if (io_remap_pfn_range(vma, vma->vm_start, addr >> PAGE_SHIFT,
- PAGE_SIZE, vma->vm_page_prot)) {
- printk(KERN_ERR "%s: io_remap_pfn_range failed\n",
- __func__);
- return -EAGAIN;
- }
-
- return 0;
+ return vm_iomap_memory(vma, addr, PAGE_SIZE);
#else
return -ENOSYS;
#endif
diff --git a/drivers/char/tpm/tpm.c b/drivers/char/tpm/tpm.c
index 93211df52aab7cef9ad9615e42a7b9d36dea4d6f..ba780b74bda1ad4bbf08ef7e869e5614f00800d6 100644 (file)
--- a/drivers/char/tpm/tpm.c
+++ b/drivers/char/tpm/tpm.c
{
struct tpm_chip *chip = dev_get_drvdata(dev);
struct tpm_cmd_t cmd;
- int rc;
+ int rc, try;
u8 dummy_hash[TPM_DIGEST_SIZE] = { 0 };
}
/* now do the actual savestate */
- cmd.header.in = savestate_header;
- rc = transmit_cmd(chip, &cmd, SAVESTATE_RESULT_SIZE,
- "sending savestate before suspend");
+ for (try = 0; try < TPM_RETRY; try++) {
+ cmd.header.in = savestate_header;
+ rc = transmit_cmd(chip, &cmd, SAVESTATE_RESULT_SIZE, NULL);
+
+ /*
+ * If the TPM indicates that it is too busy to respond to
+ * this command then retry before giving up. It can take
+ * several seconds for this TPM to be ready.
+ *
+ * This can happen if the TPM has already been sent the
+ * SaveState command before the driver has loaded. TCG 1.2
+ * specification states that any communication after SaveState
+ * may cause the TPM to invalidate previously saved state.
+ */
+ if (rc != TPM_WARN_RETRY)
+ break;
+ msleep(TPM_TIMEOUT_RETRY);
+ }
+
+ if (rc)
+ dev_err(chip->dev,
+ "Error (%d) sending savestate before suspend\n", rc);
+ else if (try > 0)
+ dev_warn(chip->dev, "TPM savestate took %dms\n",
+ try * TPM_TIMEOUT_RETRY);
+
return rc;
}
EXPORT_SYMBOL_GPL(tpm_pm_suspend);
diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h
index 8ef7649a50aa7d31f32360ea81ad0668cf041065..9c12a52ede7991218404de5fbecc3e72c63e45d5 100644 (file)
--- a/drivers/char/tpm/tpm.h
+++ b/drivers/char/tpm/tpm.h
TPM_MINOR = 224, /* officially assigned */
TPM_BUFSIZE = 4096,
TPM_NUM_DEVICES = 256,
+ TPM_RETRY = 50, /* 5 seconds */
};
enum tpm_timeout {
TPM_TIMEOUT = 5, /* msecs */
+ TPM_TIMEOUT_RETRY = 100 /* msecs */
};
/* TPM addresses */
TPM_ADDR = 0x4E,
};
+#define TPM_WARN_RETRY 0x800
#define TPM_WARN_DOING_SELFTEST 0x802
#define TPM_ERR_DEACTIVATED 0x6
#define TPM_ERR_DISABLED 0x7
index dae0667032531a1570012ab4cf994abc66778428..ef4fbc4b0075390572fa3ee3758f56ccc9350951 100644 (file)
cpu_dev = &pdev->dev;
cpu_dev->of_node = np;
+ cpu_reg = devm_regulator_get(cpu_dev, "cpu0");
+ if (IS_ERR(cpu_reg)) {
+ /*
+ * If cpu0 regulator supply node is present, but regulator is
+ * not yet registered, we should try defering probe.
+ */
+ if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
+ dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
+ return -EPROBE_DEFER;
+ }
+ pr_err("failed to get cpu0 regulator: %ld\n", PTR_ERR(cpu_reg));
+ cpu_reg = NULL;
+ }
+
cpu_clk = devm_clk_get(cpu_dev, NULL);
if (IS_ERR(cpu_clk)) {
ret = PTR_ERR(cpu_clk);
goto out_put_node;
}
- cpu_reg = devm_regulator_get(cpu_dev, "cpu0");
- if (IS_ERR(cpu_reg)) {
- pr_warn("failed to get cpu0 regulator\n");
- cpu_reg = NULL;
- }
-
ret = of_init_opp_table(cpu_dev);
if (ret) {
pr_err("failed to init OPP table: %d\n", ret);
index 0ca1ca71157f2b7320e418d13deceeb63965c030..c9303edc932411a6edd1c6a142656070979312f6 100644 (file)
};
/* possible dynamic channel ce_count attribute files */
-DEVICE_CHANNEL(ch0_ce_count, S_IRUGO | S_IWUSR,
+DEVICE_CHANNEL(ch0_ce_count, S_IRUGO,
channel_ce_count_show, NULL, 0);
-DEVICE_CHANNEL(ch1_ce_count, S_IRUGO | S_IWUSR,
+DEVICE_CHANNEL(ch1_ce_count, S_IRUGO,
channel_ce_count_show, NULL, 1);
-DEVICE_CHANNEL(ch2_ce_count, S_IRUGO | S_IWUSR,
+DEVICE_CHANNEL(ch2_ce_count, S_IRUGO,
channel_ce_count_show, NULL, 2);
-DEVICE_CHANNEL(ch3_ce_count, S_IRUGO | S_IWUSR,
+DEVICE_CHANNEL(ch3_ce_count, S_IRUGO,
channel_ce_count_show, NULL, 3);
-DEVICE_CHANNEL(ch4_ce_count, S_IRUGO | S_IWUSR,
+DEVICE_CHANNEL(ch4_ce_count, S_IRUGO,
channel_ce_count_show, NULL, 4);
-DEVICE_CHANNEL(ch5_ce_count, S_IRUGO | S_IWUSR,
+DEVICE_CHANNEL(ch5_ce_count, S_IRUGO,
channel_ce_count_show, NULL, 5);
/* Total possible dynamic ce_count attribute file table */
index a19b7457a726e4c4f6a2c48a9c8c9a52e370dcff..a9e81d8f35e24aa656106b424680e8c4cc6c2915 100644 (file)
/*-------------------------------------------------------------------------*/
+struct pcf857x_platform_data *of_gpio_pcf857x(struct device *dev)
+{
+ struct pcf857x_platform_data *pdata;
+ int r;
+
+ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return NULL;
+
+ pdata->gpio_base = -1;
+
+ r = of_property_read_u32(dev->of_node, "n_latch", &pdata->n_latch);
+ if (r) {
+ dev_dbg(dev, "couldn't find n-latch, use default\n");
+ pdata->n_latch = ~0;
+ }
+
+ return pdata;
+}
+
static int pcf857x_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
struct pcf857x_platform_data *pdata;
+ struct device_node *node;
struct pcf857x *gpio;
int status;
pdata = client->dev.platform_data;
- if (!pdata) {
+ node = client->dev.of_node;
+
+ if (!pdata && node)
+ pdata = of_gpio_pcf857x(&client->dev);
+
+ if (!pdata)
dev_dbg(&client->dev, "no platform data\n");
- }
/* Allocate, initialize, and register this gpio_chip. */
gpio = kzalloc(sizeof *gpio, GFP_KERNEL);
return status;
}
+static const struct of_device_id pcf857x_dt_ids[] = {
+ { .compatible = "ti,pcf8574", },
+ { .compatible = "ti,pcf8574a", },
+ { .compatible = "ti,pca8574", },
+ { .compatible = "ti,pca9670", },
+ { .compatible = "ti,pca9672", },
+ { .compatible = "ti,pca9674", },
+ { .compatible = "ti,pcf8575", },
+ { .compatible = "ti,pca8575", },
+ { .compatible = "ti,pca9671", },
+ { .compatible = "ti,pca9673", },
+ { .compatible = "ti,pca9675", },
+ { .compatible = "ti,max7328", },
+ { .compatible = "ti,max7329", },
+ { }
+};
+
+MODULE_DEVICE_TABLE(of, pcf857x_dt_ids);
+
static struct i2c_driver pcf857x_driver = {
.driver = {
- .name = "pcf857x",
- .owner = THIS_MODULE,
+ .name = "pcf857x",
+ .owner = THIS_MODULE,
+ .of_match_table = pcf857x_dt_ids,
},
.probe = pcf857x_probe,
.remove = pcf857x_remove,
index 983201b450f16cae63154442cbb3059866ad29f5..898e9fa2a6072a19039fc3c1e94465e567870323 100644 (file)
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
source "drivers/gpu/drm/shmobile/Kconfig"
source "drivers/gpu/drm/tegra/Kconfig"
+
+source "drivers/gpu/drm/omapdrm/Kconfig"
index 6f58c81cfcbcb073065bf29889c9bfce73cde2ae..b6b43cbc18e45dd056b0c09fde2ce55e6e1f50f5 100644 (file)
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
obj-$(CONFIG_DRM_AST) += ast/
obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
obj-$(CONFIG_DRM_TEGRA) += tegra/
+obj-$(CONFIG_DRM_OMAP) += omapdrm/
obj-y += i2c/
index 5ccf984f063acf484a365ce9f62caca95fd093c2..cac9c9a4fe70886e60c825cd6826fa1f94e757d6 100644 (file)
void *sysram;
int size;
struct ttm_bo_kmap_obj mapping;
+ int x1, y1, x2, y2; /* dirty rect */
+ spinlock_t dirty_lock;
};
#define to_ast_crtc(x) container_of(x, struct ast_crtc, base)
index d9ec77959dff1b01b9be38825e344a4a78212d31..9138678e7ea1420d9422d592310fdef19cd68157 100644 (file)
int bpp = (afbdev->afb.base.bits_per_pixel + 7)/8;
int ret;
bool unmap = false;
+ bool store_for_later = false;
+ int x2, y2;
+ unsigned long flags;
obj = afbdev->afb.obj;
bo = gem_to_ast_bo(obj);
+ /*
+ * try and reserve the BO, if we fail with busy
+ * then the BO is being moved and we should
+ * store up the damage until later.
+ */
ret = ast_bo_reserve(bo, true);
if (ret) {
- DRM_ERROR("failed to reserve fb bo\n");
+ if (ret != -EBUSY)
+ return;
+
+ store_for_later = true;
+ }
+
+ x2 = x + width - 1;
+ y2 = y + height - 1;
+ spin_lock_irqsave(&afbdev->dirty_lock, flags);
+
+ if (afbdev->y1 < y)
+ y = afbdev->y1;
+ if (afbdev->y2 > y2)
+ y2 = afbdev->y2;
+ if (afbdev->x1 < x)
+ x = afbdev->x1;
+ if (afbdev->x2 > x2)
+ x2 = afbdev->x2;
+
+ if (store_for_later) {
+ afbdev->x1 = x;
+ afbdev->x2 = x2;
+ afbdev->y1 = y;
+ afbdev->y2 = y2;
+ spin_unlock_irqrestore(&afbdev->dirty_lock, flags);
return;
}
+ afbdev->x1 = afbdev->y1 = INT_MAX;
+ afbdev->x2 = afbdev->y2 = 0;
+ spin_unlock_irqrestore(&afbdev->dirty_lock, flags);
+
if (!bo->kmap.virtual) {
ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
if (ret) {
}
unmap = true;
}
- for (i = y; i < y + height; i++) {
+ for (i = y; i <= y2; i++) {
/* assume equal stride for now */
src_offset = dst_offset = i * afbdev->afb.base.pitches[0] + (x * bpp);
- memcpy_toio(bo->kmap.virtual + src_offset, afbdev->sysram + src_offset, width * bpp);
+ memcpy_toio(bo->kmap.virtual + src_offset, afbdev->sysram + src_offset, (x2 - x + 1) * bpp);
}
if (unmap)
ast->fbdev = afbdev;
afbdev->helper.funcs = &ast_fb_helper_funcs;
+ spin_lock_init(&afbdev->dirty_lock);
ret = drm_fb_helper_init(dev, &afbdev->helper,
1, 1);
if (ret) {
index 3602731a6112244aa59f6a8b91eec87d0f8adbf8..09da3393c527188f85a5e5f42316c502788e1a93 100644 (file)
ret = ttm_bo_reserve(&bo->bo, true, no_wait, false, 0);
if (ret) {
- if (ret != -ERESTARTSYS)
+ if (ret != -ERESTARTSYS && ret != -EBUSY)
DRM_ERROR("reserve failed %p\n", bo);
return ret;
}
index 6e0cc724e5a23635c8f82fbf72b40b442caf42ef..7ca05959688748a436eb27ae7215ec106dd220d2 100644 (file)
struct list_head fbdev_list;
void *sysram;
int size;
+ int x1, y1, x2, y2; /* dirty rect */
+ spinlock_t dirty_lock;
};
struct cirrus_bo {
index 6c6b4c87d309ca03d9372aff618e2f6cf7e923a7..1e64d6f067b73aa473fa45ada951a101f8f9b954 100644 (file)
int bpp = (afbdev->gfb.base.bits_per_pixel + 7)/8;
int ret;
bool unmap = false;
+ bool store_for_later = false;
+ int x2, y2;
+ unsigned long flags;
obj = afbdev->gfb.obj;
bo = gem_to_cirrus_bo(obj);
+ /*
+ * try and reserve the BO, if we fail with busy
+ * then the BO is being moved and we should
+ * store up the damage until later.
+ */
ret = cirrus_bo_reserve(bo, true);
if (ret) {
- DRM_ERROR("failed to reserve fb bo\n");
+ if (ret != -EBUSY)
+ return;
+ store_for_later = true;
+ }
+
+ x2 = x + width - 1;
+ y2 = y + height - 1;
+ spin_lock_irqsave(&afbdev->dirty_lock, flags);
+
+ if (afbdev->y1 < y)
+ y = afbdev->y1;
+ if (afbdev->y2 > y2)
+ y2 = afbdev->y2;
+ if (afbdev->x1 < x)
+ x = afbdev->x1;
+ if (afbdev->x2 > x2)
+ x2 = afbdev->x2;
+
+ if (store_for_later) {
+ afbdev->x1 = x;
+ afbdev->x2 = x2;
+ afbdev->y1 = y;
+ afbdev->y2 = y2;
+ spin_unlock_irqrestore(&afbdev->dirty_lock, flags);
return;
}
+ afbdev->x1 = afbdev->y1 = INT_MAX;
+ afbdev->x2 = afbdev->y2 = 0;
+ spin_unlock_irqrestore(&afbdev->dirty_lock, flags);
+
if (!bo->kmap.virtual) {
ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
if (ret) {
cdev->mode_info.gfbdev = gfbdev;
gfbdev->helper.funcs = &cirrus_fb_helper_funcs;
+ spin_lock_init(&gfbdev->dirty_lock);
ret = drm_fb_helper_init(cdev->dev, &gfbdev->helper,
cdev->num_crtc, CIRRUSFB_CONN_LIMIT);
index 1413a26e490527ea69dea371bb3bbc25d92020e2..2ed8cfc740c9fa1845d86edcd876644b69302f82 100644 (file)
ret = ttm_bo_reserve(&bo->bo, true, no_wait, false, 0);
if (ret) {
- if (ret != -ERESTARTSYS)
+ if (ret != -ERESTARTSYS && ret != -EBUSY)
DRM_ERROR("reserve failed %p\n", bo);
return ret;
}
index 24efae464e2c4660a99daabbc7735e8b9d2ec2d6..539bae92ace6eb68c475b3dbf901e0b5782fe5b8 100644 (file)
drm_gem_remove_prime_handles(struct drm_gem_object *obj, struct drm_file *filp)
{
if (obj->import_attach) {
- drm_prime_remove_imported_buf_handle(&filp->prime,
+ drm_prime_remove_buf_handle(&filp->prime,
obj->import_attach->dmabuf);
}
if (obj->export_dma_buf) {
- drm_prime_remove_imported_buf_handle(&filp->prime,
+ drm_prime_remove_buf_handle(&filp->prime,
obj->export_dma_buf);
}
}
index 7f125738f44e78dc37439fe13b9bc0868e9d4baf..4f6439d7b39fa8a0fb80adb51094b304bdcbac61 100644 (file)
struct dma_buf *dma_buf;
uint32_t handle;
};
+static int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf, uint32_t handle);
int drm_gem_prime_handle_to_fd(struct drm_device *dev,
struct drm_file *file_priv, uint32_t handle, uint32_t flags,
{
struct drm_gem_object *obj;
void *buf;
- int ret;
+ int ret = 0;
+ struct dma_buf *dmabuf;
obj = drm_gem_object_lookup(dev, file_priv, handle);
if (!obj)
mutex_lock(&file_priv->prime.lock);
/* re-export the original imported object */
if (obj->import_attach) {
- get_dma_buf(obj->import_attach->dmabuf);
- *prime_fd = dma_buf_fd(obj->import_attach->dmabuf, flags);
- drm_gem_object_unreference_unlocked(obj);
- mutex_unlock(&file_priv->prime.lock);
- return 0;
+ dmabuf = obj->import_attach->dmabuf;
+ goto out_have_obj;
}
if (obj->export_dma_buf) {
- get_dma_buf(obj->export_dma_buf);
- *prime_fd = dma_buf_fd(obj->export_dma_buf, flags);
- drm_gem_object_unreference_unlocked(obj);
- } else {
- buf = dev->driver->gem_prime_export(dev, obj, flags);
- if (IS_ERR(buf)) {
- /* normally the created dma-buf takes ownership of the ref,
- * but if that fails then drop the ref
- */
- drm_gem_object_unreference_unlocked(obj);
- mutex_unlock(&file_priv->prime.lock);
- return PTR_ERR(buf);
- }
- obj->export_dma_buf = buf;
- *prime_fd = dma_buf_fd(buf, flags);
+ dmabuf = obj->export_dma_buf;
+ goto out_have_obj;
}
+
+ buf = dev->driver->gem_prime_export(dev, obj, flags);
+ if (IS_ERR(buf)) {
+ /* normally the created dma-buf takes ownership of the ref,
+ * but if that fails then drop the ref
+ */
+ ret = PTR_ERR(buf);
+ goto out;
+ }
+ obj->export_dma_buf = buf;
+
/* if we've exported this buffer the cheat and add it to the import list
* so we get the correct handle back
*/
- ret = drm_prime_add_imported_buf_handle(&file_priv->prime,
- obj->export_dma_buf, handle);
- if (ret) {
- drm_gem_object_unreference_unlocked(obj);
- mutex_unlock(&file_priv->prime.lock);
- return ret;
- }
+ ret = drm_prime_add_buf_handle(&file_priv->prime,
+ obj->export_dma_buf, handle);
+ if (ret)
+ goto out;
+ *prime_fd = dma_buf_fd(buf, flags);
mutex_unlock(&file_priv->prime.lock);
return 0;
+
+out_have_obj:
+ get_dma_buf(dmabuf);
+ *prime_fd = dma_buf_fd(dmabuf, flags);
+out:
+ drm_gem_object_unreference_unlocked(obj);
+ mutex_unlock(&file_priv->prime.lock);
+ return ret;
}
EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
mutex_lock(&file_priv->prime.lock);
- ret = drm_prime_lookup_imported_buf_handle(&file_priv->prime,
+ ret = drm_prime_lookup_buf_handle(&file_priv->prime,
dma_buf, handle);
if (!ret) {
ret = 0;
if (ret)
goto out_put;
- ret = drm_prime_add_imported_buf_handle(&file_priv->prime,
+ ret = drm_prime_add_buf_handle(&file_priv->prime,
dma_buf, *handle);
if (ret)
goto fail;
}
EXPORT_SYMBOL(drm_prime_destroy_file_private);
-int drm_prime_add_imported_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf, uint32_t handle)
+static int drm_prime_add_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf, uint32_t handle)
{
struct drm_prime_member *member;
@@ -315,14 +318,14 @@ int drm_prime_add_imported_buf_handle(struct drm_prime_file_private *prime_fpriv
if (!member)
return -ENOMEM;
+ get_dma_buf(dma_buf);
member->dma_buf = dma_buf;
member->handle = handle;
list_add(&member->entry, &prime_fpriv->head);
return 0;
}
-EXPORT_SYMBOL(drm_prime_add_imported_buf_handle);
-int drm_prime_lookup_imported_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf, uint32_t *handle)
+int drm_prime_lookup_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf, uint32_t *handle)
{
struct drm_prime_member *member;
@@ -334,19 +337,20 @@ int drm_prime_lookup_imported_buf_handle(struct drm_prime_file_private *prime_fp
}
return -ENOENT;
}
-EXPORT_SYMBOL(drm_prime_lookup_imported_buf_handle);
+EXPORT_SYMBOL(drm_prime_lookup_buf_handle);
-void drm_prime_remove_imported_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf)
+void drm_prime_remove_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf)
{
struct drm_prime_member *member, *safe;
mutex_lock(&prime_fpriv->lock);
list_for_each_entry_safe(member, safe, &prime_fpriv->head, entry) {
if (member->dma_buf == dma_buf) {
+ dma_buf_put(dma_buf);
list_del(&member->entry);
kfree(member);
}
}
mutex_unlock(&prime_fpriv->lock);
}
-EXPORT_SYMBOL(drm_prime_remove_imported_buf_handle);
+EXPORT_SYMBOL(drm_prime_remove_buf_handle);
index 8652cdf3f03f9d3dcb74d952be4d85d822223d83..029eccf3013784ccb588c0bc139c917533417d9e 100644 (file)
vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
- if (vdc_stat & _PSB_PIPE_EVENT_FLAG)
+ if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
dsp_int = 1;
/* FIXME: Handle Medfield
index 7339a4b89d5fcdfa53923892e66093d3dbeadb7e..e78419f1f4196e77a6c1b653623914db59d8e726 100644 (file)
unsigned int int_crt_support:1;
unsigned int lvds_use_ssc:1;
unsigned int display_clock_mode:1;
+ unsigned int fdi_rx_polarity_inverted:1;
int lvds_ssc_freq;
unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
unsigned int lvds_val; /* used for checking LVDS channel mode */
unsigned long gtt_start;
unsigned long gtt_mappable_end;
unsigned long gtt_end;
+ unsigned long stolen_base; /* limited to low memory (32-bit) */
struct io_mapping *gtt_mapping;
phys_addr_t gtt_base_addr;
index de45b60516e61cbc376ffb2caebf1636fdf774dc..3b9d18b9e92e23ee9bdabf049471953b447150ae 100644 (file)
return fence - dev_priv->fence_regs;
}
+static void i915_gem_write_fence__ipi(void *data)
+{
+ wbinvd();
+}
+
static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
struct drm_i915_fence_reg *fence,
bool enable)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
- int reg = fence_number(dev_priv, fence);
-
- i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
+ struct drm_device *dev = obj->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int fence_reg = fence_number(dev_priv, fence);
+
+ /* In order to fully serialize access to the fenced region and
+ * the update to the fence register we need to take extreme
+ * measures on SNB+. In theory, the write to the fence register
+ * flushes all memory transactions before, and coupled with the
+ * mb() placed around the register write we serialise all memory
+ * operations with respect to the changes in the tiler. Yet, on
+ * SNB+ we need to take a step further and emit an explicit wbinvd()
+ * on each processor in order to manually flush all memory
+ * transactions before updating the fence register.
+ */
+ if (HAS_LLC(obj->base.dev))
+ on_each_cpu(i915_gem_write_fence__ipi, NULL, 1);
+ i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL);
if (enable) {
- obj->fence_reg = reg;
+ obj->fence_reg = fence_reg;
fence->obj = obj;
list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
} else {
index a3f06bcad551d844c1e3649fee266466a04ff759..d8ac0a3a17434ac2d69a625f941b910019bf2353 100644 (file)
return ERR_PTR(-ENOMEM);
}
+ if (INTEL_INFO(dev)->gen >= 7) {
+ ret = i915_gem_object_set_cache_level(ctx->obj,
+ I915_CACHE_LLC_MLC);
+ if (ret)
+ goto err_out;
+ }
+
/* The ring associated with the context object is handled by the normal
* object tracking code. We give an initial ring value simple to pass an
* assertion in the context switch code.
index 8e91083b126ffd32a65d7d36165525a9ef37e1a0..be24312cd32fd55157ebc03a7a52ef67d305bbac 100644 (file)
* for is a boon.
*/
-#define PTE_ADDRESS_MASK 0xfffff000
-#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
-#define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
-#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
-#define PTE_MAPPING_TYPE_CACHED (3 << 1)
-#define PTE_MAPPING_TYPE_MASK (3 << 1)
-#define PTE_VALID (1 << 0)
-
-/**
- * i915_stolen_to_phys - take an offset into stolen memory and turn it into
- * a physical one
- * @dev: drm device
- * @offset: address to translate
- *
- * Some chip functions require allocations from stolen space and need the
- * physical address of the memory in question.
- */
-static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
+static unsigned long i915_stolen_to_physical(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
struct pci_dev *pdev = dev_priv->bridge_dev;
u32 base;
-#if 0
/* On the machines I have tested the Graphics Base of Stolen Memory
- * is unreliable, so compute the base by subtracting the stolen memory
- * from the Top of Low Usable DRAM which is where the BIOS places
- * the graphics stolen memory.
+ * is unreliable, so on those compute the base by subtracting the
+ * stolen memory from the Top of Low Usable DRAM which is where the
+ * BIOS places the graphics stolen memory.
+ *
+ * On gen2, the layout is slightly different with the Graphics Segment
+ * immediately following Top of Memory (or Top of Usable DRAM). Note
+ * it appears that TOUD is only reported by 865g, so we just use the
+ * top of memory as determined by the e820 probe.
+ *
+ * XXX gen2 requires an unavailable symbol and 945gm fails with
+ * its value of TOLUD.
*/
- if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
- /* top 32bits are reserved = 0 */
+ base = 0;
+ if (INTEL_INFO(dev)->gen >= 6) {
+ /* Read Base Data of Stolen Memory Register (BDSM) directly.
+ * Note that there is also a MCHBAR miror at 0x1080c0 or
+ * we could use device 2:0x5c instead.
+ */
+ pci_read_config_dword(pdev, 0xB0, &base);
+ base &= ~4095; /* lower bits used for locking register */
+ } else if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
+ /* Read Graphics Base of Stolen Memory directly */
pci_read_config_dword(pdev, 0xA4, &base);
- } else {
- /* XXX presume 8xx is the same as i915 */
- pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
- }
-#else
- if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
- u16 val;
- pci_read_config_word(pdev, 0xb0, &val);
- base = val >> 4 << 20;
- } else {
+#if 0
+ } else if (IS_GEN3(dev)) {
u8 val;
+ /* Stolen is immediately below Top of Low Usable DRAM */
pci_read_config_byte(pdev, 0x9c, &val);
base = val >> 3 << 27;
- }
- base -= dev_priv->mm.gtt->stolen_size;
+ base -= dev_priv->mm.gtt->stolen_size;
+ } else {
+ /* Stolen is immediately above Top of Memory */
+ base = max_low_pfn_mapped << PAGE_SHIFT;
#endif
+ }
- return base + offset;
+ return base;
}
static void i915_warn_stolen(struct drm_device *dev)
if (!compressed_fb)
goto err;
- cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
+ cfb_base = dev_priv->mm.stolen_base + compressed_fb->start;
if (!cfb_base)
goto err_fb;
if (!compressed_llb)
goto err_fb;
- ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
+ ll_base = dev_priv->mm.stolen_base + compressed_llb->start;
if (!ll_base)
goto err_llb;
}
}
DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
- cfb_base, ll_base, size >> 20);
+ (long)cfb_base, (long)ll_base, size >> 20);
return;
err_llb:
struct drm_i915_private *dev_priv = dev->dev_private;
unsigned long prealloc_size = dev_priv->mm.gtt->stolen_size;
+ dev_priv->mm.stolen_base = i915_stolen_to_physical(dev);
+ if (dev_priv->mm.stolen_base == 0)
+ return 0;
+
+ DRM_DEBUG_KMS("found %d bytes of stolen memory at %08lx\n",
+ dev_priv->mm.gtt->stolen_size, dev_priv->mm.stolen_base);
+
/* Basic memrange allocator for stolen space */
drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
index 2bfd05a5da275ab339c04426c043215d4c6e8ddf..ce70f0ac1c7316a11082fbebeb3932046f48064d 100644 (file)
#define _TRANSB_CHICKEN2 0xf1064
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
-
+#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
#define SOUTH_CHICKEN1 0xc2000
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
index 55ffba1f5818d933227c0ea5344afb491da295a9..bd833918c492bdb305d8632ba319b8364a7e292c 100644 (file)
dev_priv->lvds_ssc_freq =
intel_bios_ssc_frequency(dev, general->ssc_freq);
dev_priv->display_clock_mode = general->display_clock_mode;
- DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d\n",
+ dev_priv->fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted;
+ DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n",
dev_priv->int_tv_support,
dev_priv->int_crt_support,
dev_priv->lvds_use_ssc,
dev_priv->lvds_ssc_freq,
- dev_priv->display_clock_mode);
+ dev_priv->display_clock_mode,
+ dev_priv->fdi_rx_polarity_inverted);
}
}
index 36e57f9343735644d7c8e0079f06d86ca22499f7..e088d6f0956a87a239cf94ab31983359d0993f70 100644 (file)
/* bits 3 */
u8 disable_smooth_vision:1;
u8 single_dvi:1;
- u8 rsvd9:6; /* finish byte */
+ u8 rsvd9:1;
+ u8 fdi_rx_polarity_inverted:1;
+ u8 rsvd10:4; /* finish byte */
/* bits 4 */
u8 legacy_monitor_detect;
index d3f834a56ab33f99b98799db87c70201e37bca5d..faeaebc719ad5442a3f37e6c62e4d695d698f7d1 100644 (file)
@@ -7732,22 +7732,25 @@ intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
if (crtc->enabled)
*prepare_pipes |= 1 << intel_crtc->pipe;
- /* We only support modeset on one single crtc, hence we need to do that
- * only for the passed in crtc iff we change anything else than just
- * disable crtcs.
- *
- * This is actually not true, to be fully compatible with the old crtc
- * helper we automatically disable _any_ output (i.e. doesn't need to be
- * connected to the crtc we're modesetting on) if it's disconnected.
- * Which is a rather nutty api (since changed the output configuration
- * without userspace's explicit request can lead to confusion), but
- * alas. Hence we currently need to modeset on all pipes we prepare. */
+ /*
+ * For simplicity do a full modeset on any pipe where the output routing
+ * changed. We could be more clever, but that would require us to be
+ * more careful with calling the relevant encoder->mode_set functions.
+ */
if (*prepare_pipes)
*modeset_pipes = *prepare_pipes;
/* ... and mask these out. */
*modeset_pipes &= ~(*disable_pipes);
*prepare_pipes &= ~(*disable_pipes);
+
+ /*
+ * HACK: We don't (yet) fully support global modesets. intel_set_config
+ * obies this rule, but the modeset restore mode of
+ * intel_modeset_setup_hw_state does not.
+ */
+ *modeset_pipes &= 1 << intel_crtc->pipe;
+ *prepare_pipes &= 1 << intel_crtc->pipe;
}
static bool intel_crtc_in_use(struct drm_crtc *crtc)
/* flush any delayed tasks or pending work */
flush_scheduled_work();
+ /* destroy backlight, if any, before the connectors */
+ intel_panel_destroy_backlight(dev);
+
drm_mode_config_cleanup(dev);
}
index 73ce6e903be6e6c9192f508e346322417a263740..cbe1ec3d07bd8a0a8bb8e1cdf8718a72b975d6b9 100644 (file)
static void
intel_dp_destroy(struct drm_connector *connector)
{
- struct drm_device *dev = connector->dev;
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_connector *intel_connector = to_intel_connector(connector);
if (!IS_ERR_OR_NULL(intel_connector->edid))
kfree(intel_connector->edid);
- if (is_edp(intel_dp)) {
- intel_panel_destroy_backlight(dev);
+ if (is_edp(intel_dp))
intel_panel_fini(&intel_connector->panel);
- }
drm_sysfs_connector_remove(connector);
drm_connector_cleanup(connector);
index 15da99533e5b627eb493c69745b399a8b2439e36..ba96e0406cce4f0c7a519636244334d0bca7c68f 100644 (file)
const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
struct i2c_adapter *i2c;
int gpio;
+ bool dvoinit;
/* Allow the I2C driver info to specify the GPIO to be used in
* special cases, but otherwise default to what's defined
i2c = intel_gmbus_get_adapter(dev_priv, gpio);
intel_dvo->dev = *dvo;
- if (!dvo->dev_ops->init(&intel_dvo->dev, i2c))
+
+ /* GMBUS NAK handling seems to be unstable, hence let the
+ * transmitter detection run in bit banging mode for now.
+ */
+ intel_gmbus_force_bit(i2c, true);
+
+ dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
+
+ intel_gmbus_force_bit(i2c, false);
+
+ if (!dvoinit)
continue;
intel_encoder->type = INTEL_OUTPUT_DVO;
index 17aee74258ad4dfa43083e431fc3f0b224aa4ec4..8b383a61a957a545fb0a07727ae3852013d5908d 100644 (file)
if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
kfree(lvds_connector->base.edid);
- intel_panel_destroy_backlight(connector->dev);
intel_panel_fini(&lvds_connector->base.panel);
drm_sysfs_connector_remove(connector);
DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
},
},
+ {
+ .callback = intel_no_lvds_dmi_callback,
+ .ident = "Fujitsu Esprimo Q900",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
+ DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
+ },
+ },
{ } /* terminating entry */
};
index bee8cb6108a7d44883286ef4b35bb6d7f8713a0f..94d895b665d5d7400b32cb17ad46333505ce004a 100644 (file)
intel_panel_init_backlight(dev);
+ if (WARN_ON(dev_priv->backlight))
+ return -ENODEV;
+
memset(&props, 0, sizeof(props));
props.type = BACKLIGHT_RAW;
props.max_brightness = _intel_panel_get_max_backlight(dev);
void intel_panel_destroy_backlight(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
- if (dev_priv->backlight)
+ if (dev_priv->backlight) {
backlight_device_unregister(dev_priv->backlight);
+ dev_priv->backlight = NULL;
+ }
}
#else
int intel_panel_setup_backlight(struct drm_connector *connector)
index dde0dedfc9c47835ba7d52d36be4494242f6772d..253bcf3bcc02de2108fe8c2d36d0d1f6640130f6 100644 (file)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe;
+ uint32_t val;
/*
* On Ibex Peak and Cougar Point, we need to disable clock
/* The below fixes the weird display corruption, a few pixels shifted
* downward, on (only) LVDS of some HP laptops with IVY.
*/
- for_each_pipe(pipe)
- I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
+ for_each_pipe(pipe) {
+ val = TRANS_CHICKEN2_TIMING_OVERRIDE;
+ if (dev_priv->fdi_rx_polarity_inverted)
+ val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
+ I915_WRITE(TRANS_CHICKEN2(pipe), val);
+ }
/* WADP0ClockGatingDisable */
for_each_pipe(pipe) {
I915_WRITE(TRANS_CHICKEN1(pipe),
index c275bf0fa36db86a09d861a7e17457c2c103dd4e..506c331281d70fc830ecef817a50e2ce19aba088 100644 (file)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
+ u16 active_outputs;
u32 tmp;
tmp = I915_READ(intel_sdvo->sdvo_reg);
+ intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
- if (!(tmp & SDVO_ENABLE))
+ if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
return false;
if (HAS_PCH_CPT(dev))
@@ -2704,7 +2706,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
struct intel_sdvo *intel_sdvo;
u32 hotplug_mask;
int i;
-
intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
if (!intel_sdvo)
return false;
index 5ea5033eae0a4109d9230dd663508273da0bfd7c..a657709aefd63b4da5c1ba34c643b6cc8b751a49 100644 (file)
void *sysram;
int size;
struct ttm_bo_kmap_obj mapping;
+ int x1, y1, x2, y2; /* dirty rect */
+ spinlock_t dirty_lock;
};
struct mga_crtc {
index 2f486481d79ad01db9c786a44103d7ef4062ad5c..41eefc4473bfc327513b2d98bbd591efee2e1227 100644 (file)
int bpp = (mfbdev->mfb.base.bits_per_pixel + 7)/8;
int ret;
bool unmap = false;
+ bool store_for_later = false;
+ int x2, y2;
+ unsigned long flags;
obj = mfbdev->mfb.obj;
bo = gem_to_mga_bo(obj);
+ /*
+ * try and reserve the BO, if we fail with busy
+ * then the BO is being moved and we should
+ * store up the damage until later.
+ */
ret = mgag200_bo_reserve(bo, true);
if (ret) {
- DRM_ERROR("failed to reserve fb bo\n");
+ if (ret != -EBUSY)
+ return;
+
+ store_for_later = true;
+ }
+
+ x2 = x + width - 1;
+ y2 = y + height - 1;
+ spin_lock_irqsave(&mfbdev->dirty_lock, flags);
+
+ if (mfbdev->y1 < y)
+ y = mfbdev->y1;
+ if (mfbdev->y2 > y2)
+ y2 = mfbdev->y2;
+ if (mfbdev->x1 < x)
+ x = mfbdev->x1;
+ if (mfbdev->x2 > x2)
+ x2 = mfbdev->x2;
+
+ if (store_for_later) {
+ mfbdev->x1 = x;
+ mfbdev->x2 = x2;
+ mfbdev->y1 = y;
+ mfbdev->y2 = y2;
+ spin_unlock_irqrestore(&mfbdev->dirty_lock, flags);
return;
}
+ mfbdev->x1 = mfbdev->y1 = INT_MAX;
+ mfbdev->x2 = mfbdev->y2 = 0;
+ spin_unlock_irqrestore(&mfbdev->dirty_lock, flags);
+
if (!bo->kmap.virtual) {
ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
if (ret) {
}
unmap = true;
}
- for (i = y; i < y + height; i++) {
+ for (i = y; i <= y2; i++) {
/* assume equal stride for now */
src_offset = dst_offset = i * mfbdev->mfb.base.pitches[0] + (x * bpp);
- memcpy_toio(bo->kmap.virtual + src_offset, mfbdev->sysram + src_offset, width * bpp);
+ memcpy_toio(bo->kmap.virtual + src_offset, mfbdev->sysram + src_offset, (x2 - x + 1) * bpp);
}
if (unmap)
mdev->mfbdev = mfbdev;
mfbdev->helper.funcs = &mga_fb_helper_funcs;
+ spin_lock_init(&mfbdev->dirty_lock);
ret = drm_fb_helper_init(mdev->dev, &mfbdev->helper,
mdev->num_crtc, MGAG200FB_CONN_LIMIT);
index 8fc9d920194556344f49c540abf361a43271309f..401c9891d3a8b7cfdf37ed4f40e1a5c5e79b050f 100644 (file)
ret = ttm_bo_reserve(&bo->bo, true, no_wait, false, 0);
if (ret) {
- if (ret != -ERESTARTSYS)
- DRM_ERROR("reserve failed %p\n", bo);
+ if (ret != -ERESTARTSYS && ret != -EBUSY)
+ DRM_ERROR("reserve failed %p %d\n", bo, ret);
return ret;
}
return 0;
similarity index 100%
rename from drivers/staging/omapdrm/Kconfig
rename to drivers/gpu/drm/omapdrm/Kconfig
rename from drivers/staging/omapdrm/Kconfig
rename to drivers/gpu/drm/omapdrm/Kconfig
similarity index 100%
rename from drivers/staging/omapdrm/Makefile
rename to drivers/gpu/drm/omapdrm/Makefile
rename from drivers/staging/omapdrm/Makefile
rename to drivers/gpu/drm/omapdrm/Makefile
diff --git a/drivers/gpu/drm/omapdrm/TODO b/drivers/gpu/drm/omapdrm/TODO
--- /dev/null
@@ -0,0 +1,23 @@
+TODO
+. Where should we do eviction (detatch_pages())? We aren't necessarily
+ accessing the pages via a GART, so maybe we need some other threshold
+ to put a cap on the # of pages that can be pin'd.
+ . Use mm_shrinker to trigger unpinning pages.
+ . This is mainly theoretical since most of these devices don't actually
+ have swap or harddrive.
+. GEM/shmem backed pages can have existing mappings (kernel linear map,
+ etc..), which isn't really ideal.
+. Revisit GEM sync object infrastructure.. TTM has some framework for this
+ already. Possibly this could be refactored out and made more common?
+ There should be some way to do this with less wheel-reinvention.
+ . This can be handled by the dma-buf fence/reservation stuff when it
+ lands
+
+Userspace:
+. git://anongit.freedesktop.org/xorg/driver/xf86-video-omap
+
+Currently tested on
+. OMAP3530 beagleboard
+. OMAP4430 pandaboard
+. OMAP4460 pandaboard
+. OMAP5432 uEVM
similarity index 99%
rename from drivers/staging/omapdrm/omap_connector.c
rename to drivers/gpu/drm/omapdrm/omap_connector.c
index 4cc9ee733c5fb4a80c656ad978ca6a349e07b8dc..44284fd981fc0824b3bd5c6b6e0d583c03d5f72a 100644 (file)
rename from drivers/staging/omapdrm/omap_connector.c
rename to drivers/gpu/drm/omapdrm/omap_connector.c
index 4cc9ee733c5fb4a80c656ad978ca6a349e07b8dc..44284fd981fc0824b3bd5c6b6e0d583c03d5f72a 100644 (file)
/*
- * drivers/staging/omapdrm/omap_connector.c
+ * drivers/gpu/drm/omapdrm/omap_connector.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
similarity index 98%
rename from drivers/staging/omapdrm/omap_crtc.c
rename to drivers/gpu/drm/omapdrm/omap_crtc.c
index 5c6ed6040eff572a384659561e1fdbaf427c883c..9b0bff29d3997d8c4b1fe7624f62c676dd2eb522 100644 (file)
rename from drivers/staging/omapdrm/omap_crtc.c
rename to drivers/gpu/drm/omapdrm/omap_crtc.c
index 5c6ed6040eff572a384659561e1fdbaf427c883c..9b0bff29d3997d8c4b1fe7624f62c676dd2eb522 100644 (file)
/*
- * drivers/staging/omapdrm/omap_crtc.c
+ * drivers/gpu/drm/omapdrm/omap_crtc.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
struct work_struct page_flip_work;
};
+uint32_t pipe2vbl(struct drm_crtc *crtc)
+{
+ struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
+
+ return dispc_mgr_get_vsync_irq(omap_crtc->channel);
+}
+
/*
* Manager-ops, callbacks from output when they need to configure
* the upstream part of the video pipe.
omap_crtc->apply.pre_apply = omap_crtc_pre_apply;
omap_crtc->apply.post_apply = omap_crtc_post_apply;
- omap_crtc->apply_irq.irqmask = pipe2vbl(id);
+ omap_crtc->channel = channel;
+ omap_crtc->plane = plane;
+ omap_crtc->plane->crtc = crtc;
+ omap_crtc->name = channel_names[channel];
+ omap_crtc->pipe = id;
+
+ omap_crtc->apply_irq.irqmask = pipe2vbl(crtc);
omap_crtc->apply_irq.irq = omap_crtc_apply_irq;
omap_crtc->error_irq.irqmask =
omap_crtc->error_irq.irq = omap_crtc_error_irq;
omap_irq_register(dev, &omap_crtc->error_irq);
- omap_crtc->channel = channel;
- omap_crtc->plane = plane;
- omap_crtc->plane->crtc = crtc;
- omap_crtc->name = channel_names[channel];
- omap_crtc->pipe = id;
-
/* temporary: */
omap_crtc->mgr.id = channel;
similarity index 98%
rename from drivers/staging/omapdrm/omap_debugfs.c
rename to drivers/gpu/drm/omapdrm/omap_debugfs.c
index 2f122e00b51da07ad7c29e7c4f868ad2bb4ce7b7..7b5c6402acfba18524760955cc9f0b79f7901469 100644 (file)
rename from drivers/staging/omapdrm/omap_debugfs.c
rename to drivers/gpu/drm/omapdrm/omap_debugfs.c
index 2f122e00b51da07ad7c29e7c4f868ad2bb4ce7b7..7b5c6402acfba18524760955cc9f0b79f7901469 100644 (file)
/*
- * drivers/staging/omapdrm/omap_debugfs.c
+ * drivers/gpu/drm/omapdrm/omap_debugfs.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob.clark@linaro.org>
similarity index 100%
rename from drivers/staging/omapdrm/omap_dmm_priv.h
rename to drivers/gpu/drm/omapdrm/omap_dmm_priv.h
rename from drivers/staging/omapdrm/omap_dmm_priv.h
rename to drivers/gpu/drm/omapdrm/omap_dmm_priv.h
similarity index 99%
rename from drivers/staging/omapdrm/omap_dmm_tiler.c
rename to drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
index 9e43ae2372770e179219b737be2820bc86f2ec85..fdf8e98fcf36d959b59051f9bb9c35fb51c183ad 100644 (file)
rename from drivers/staging/omapdrm/omap_dmm_tiler.c
rename to drivers/gpu/drm/omapdrm/omap_dmm_tiler.c
index 9e43ae2372770e179219b737be2820bc86f2ec85..fdf8e98fcf36d959b59051f9bb9c35fb51c183ad 100644 (file)
};
#endif
+#if defined(CONFIG_OF)
+static const struct of_device_id dmm_of_match[] = {
+ {
+ .compatible = "ti,omap4-dmm",
+ },
+ {
+ .compatible = "ti,omap5-dmm",
+ },
+ {},
+};
+#else
+#define dmm_of_match NULL
+#endif
+
struct platform_driver omap_dmm_driver = {
.probe = omap_dmm_probe,
.remove = omap_dmm_remove,
.driver = {
.owner = THIS_MODULE,
.name = DMM_DRIVER_NAME,
+ .of_match_table = dmm_of_match,
#ifdef CONFIG_PM
.pm = &omap_dmm_pm_ops,
#endif
similarity index 100%
rename from drivers/staging/omapdrm/omap_dmm_tiler.h
rename to drivers/gpu/drm/omapdrm/omap_dmm_tiler.h
rename from drivers/staging/omapdrm/omap_dmm_tiler.h
rename to drivers/gpu/drm/omapdrm/omap_dmm_tiler.h
similarity index 81%
rename from drivers/staging/omapdrm/omap_drv.c
rename to drivers/gpu/drm/omapdrm/omap_drv.c
index d246f8543d2ee20b8fe5df7a9386d969da1dba95..fa38267a46f05bd232c179f6c322c57d074f29c3 100644 (file)
rename from drivers/staging/omapdrm/omap_drv.c
rename to drivers/gpu/drm/omapdrm/omap_drv.c
index d246f8543d2ee20b8fe5df7a9386d969da1dba95..fa38267a46f05bd232c179f6c322c57d074f29c3 100644 (file)
/*
- * drivers/staging/omapdrm/omap_drv.c
+ * drivers/gpu/drm/omapdrm/omap_drv.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
}
}
+static bool channel_used(struct drm_device *dev, enum omap_channel channel)
+{
+ struct omap_drm_private *priv = dev->dev_private;
+ int i;
+
+ for (i = 0; i < priv->num_crtcs; i++) {
+ struct drm_crtc *crtc = priv->crtcs[i];
+
+ if (omap_crtc_channel(crtc) == channel)
+ return true;
+ }
+
+ return false;
+}
+
static int omap_modeset_init(struct drm_device *dev)
{
struct omap_drm_private *priv = dev->dev_private;
struct omap_dss_device *dssdev = NULL;
int num_ovls = dss_feat_get_num_ovls();
- int id;
+ int num_mgrs = dss_feat_get_num_mgrs();
+ int num_crtcs;
+ int i, id = 0;
drm_mode_config_init(dev);
omap_drm_irq_install(dev);
/*
- * Create private planes and CRTCs for the last NUM_CRTCs overlay
- * plus manager:
+ * We usually don't want to create a CRTC for each manager, at least
+ * not until we have a way to expose private planes to userspace.
+ * Otherwise there would not be enough video pipes left for drm planes.
+ * We use the num_crtc argument to limit the number of crtcs we create.
*/
- for (id = 0; id < min(num_crtc, num_ovls); id++) {
- struct drm_plane *plane;
- struct drm_crtc *crtc;
-
- plane = omap_plane_init(dev, id, true);
- crtc = omap_crtc_init(dev, plane, pipe2chan(id), id);
+ num_crtcs = min3(num_crtc, num_mgrs, num_ovls);
- BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs));
- priv->crtcs[id] = crtc;
- priv->num_crtcs++;
-
- priv->planes[id] = plane;
- priv->num_planes++;
- }
-
- /*
- * Create normal planes for the remaining overlays:
- */
- for (; id < num_ovls; id++) {
- struct drm_plane *plane = omap_plane_init(dev, id, false);
-
- BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes));
- priv->planes[priv->num_planes++] = plane;
- }
+ dssdev = NULL;
for_each_dss_dev(dssdev) {
struct drm_connector *connector;
struct drm_encoder *encoder;
+ enum omap_channel channel;
if (!dssdev->driver) {
dev_warn(dev->dev, "%s has no driver.. skipping it\n",
dssdev->name);
- return 0;
+ continue;
}
if (!(dssdev->driver->get_timings ||
dev_warn(dev->dev, "%s driver does not support "
"get_timings or read_edid.. skipping it!\n",
dssdev->name);
- return 0;
+ continue;
}
encoder = omap_encoder_init(dev, dssdev);
drm_mode_connector_attach_encoder(connector, encoder);
+ /*
+ * if we have reached the limit of the crtcs we are allowed to
+ * create, let's not try to look for a crtc for this
+ * panel/encoder and onwards, we will, of course, populate the
+ * the possible_crtcs field for all the encoders with the final
+ * set of crtcs we create
+ */
+ if (id == num_crtcs)
+ continue;
+
+ /*
+ * get the recommended DISPC channel for this encoder. For now,
+ * we only try to get create a crtc out of the recommended, the
+ * other possible channels to which the encoder can connect are
+ * not considered.
+ */
+ channel = dssdev->type == OMAP_DISPLAY_TYPE_HDMI ?
+ OMAP_DSS_CHANNEL_DIGIT :
+ OMAP_DSS_CHANNEL_LCD;
+
+ /*
+ * if this channel hasn't already been taken by a previously
+ * allocated crtc, we create a new crtc for it
+ */
+ if (!channel_used(dev, channel)) {
+ struct drm_plane *plane;
+ struct drm_crtc *crtc;
+
+ plane = omap_plane_init(dev, id, true);
+ crtc = omap_crtc_init(dev, plane, channel, id);
+
+ BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs));
+ priv->crtcs[id] = crtc;
+ priv->num_crtcs++;
+
+ priv->planes[id] = plane;
+ priv->num_planes++;
+
+ id++;
+ }
+ }
+
+ /*
+ * we have allocated crtcs according to the need of the panels/encoders,
+ * adding more crtcs here if needed
+ */
+ for (; id < num_crtcs; id++) {
+
+ /* find a free manager for this crtc */
+ for (i = 0; i < num_mgrs; i++) {
+ if (!channel_used(dev, i)) {
+ struct drm_plane *plane;
+ struct drm_crtc *crtc;
+
+ plane = omap_plane_init(dev, id, true);
+ crtc = omap_crtc_init(dev, plane, i, id);
+
+ BUG_ON(priv->num_crtcs >=
+ ARRAY_SIZE(priv->crtcs));
+
+ priv->crtcs[id] = crtc;
+ priv->num_crtcs++;
+
+ priv->planes[id] = plane;
+ priv->num_planes++;
+
+ break;
+ } else {
+ continue;
+ }
+ }
+
+ if (i == num_mgrs) {
+ /* this shouldn't really happen */
+ dev_err(dev->dev, "no managers left for crtc\n");
+ return -ENOMEM;
+ }
+ }
+
+ /*
+ * Create normal planes for the remaining overlays:
+ */
+ for (; id < num_ovls; id++) {
+ struct drm_plane *plane = omap_plane_init(dev, id, false);
+
+ BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes));
+ priv->planes[priv->num_planes++] = plane;
+ }
+
+ for (i = 0; i < priv->num_encoders; i++) {
+ struct drm_encoder *encoder = priv->encoders[i];
+ struct omap_dss_device *dssdev =
+ omap_encoder_get_dssdev(encoder);
+
/* figure out which crtc's we can connect the encoder to: */
encoder->possible_crtcs = 0;
for (id = 0; id < priv->num_crtcs; id++) {
- enum omap_dss_output_id supported_outputs =
- dss_feat_get_supported_outputs(pipe2chan(id));
+ struct drm_crtc *crtc = priv->crtcs[id];
+ enum omap_channel crtc_channel;
+ enum omap_dss_output_id supported_outputs;
+
+ crtc_channel = omap_crtc_channel(crtc);
+ supported_outputs =
+ dss_feat_get_supported_outputs(crtc_channel);
+
if (supported_outputs & dssdev->output->id)
encoder->possible_crtcs |= (1 << id);
}
}
+ DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
+ priv->num_planes, priv->num_crtcs, priv->num_encoders,
+ priv->num_connectors);
+
dev->mode_config.min_width = 32;
dev->mode_config.min_height = 32;
similarity index 91%
rename from drivers/staging/omapdrm/omap_drv.h
rename to drivers/gpu/drm/omapdrm/omap_drv.h
index f921027e7500efb8de4fc350f330ec34ea552044..215a20dd340cc8984ddffad32b0c7c42010d06c1 100644 (file)
rename from drivers/staging/omapdrm/omap_drv.h
rename to drivers/gpu/drm/omapdrm/omap_drv.h
index f921027e7500efb8de4fc350f330ec34ea552044..215a20dd340cc8984ddffad32b0c7c42010d06c1 100644 (file)
/*
- * drivers/staging/omapdrm/omap_drv.h
+ * drivers/gpu/drm/omapdrm/omap_drv.h
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
#include <linux/types.h>
#include <drm/drmP.h>
#include <drm/drm_crtc_helper.h>
+#include <drm/omap_drm.h>
#include <linux/platform_data/omap_drm.h>
-#include "omap_drm.h"
#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
int omap_gem_resume(struct device *dev);
#endif
-int omap_irq_enable_vblank(struct drm_device *dev, int crtc);
-void omap_irq_disable_vblank(struct drm_device *dev, int crtc);
+int omap_irq_enable_vblank(struct drm_device *dev, int crtc_id);
+void omap_irq_disable_vblank(struct drm_device *dev, int crtc_id);
irqreturn_t omap_irq_handler(DRM_IRQ_ARGS);
void omap_irq_preinstall(struct drm_device *dev);
int omap_irq_postinstall(struct drm_device *dev);
return ALIGN(pitch, 8 * bytespp);
}
-static inline enum omap_channel pipe2chan(int pipe)
-{
- int num_mgrs = dss_feat_get_num_mgrs();
-
- /*
- * We usually don't want to create a CRTC for each manager,
- * at least not until we have a way to expose private planes
- * to userspace. Otherwise there would not be enough video
- * pipes left for drm planes. The higher #'d managers tend
- * to have more features so start in reverse order.
- */
- return num_mgrs - pipe - 1;
-}
-
/* map crtc to vblank mask */
-static inline uint32_t pipe2vbl(int crtc)
-{
- enum omap_channel channel = pipe2chan(crtc);
- return dispc_mgr_get_vsync_irq(channel);
-}
-
-static inline int crtc2pipe(struct drm_device *dev, struct drm_crtc *crtc)
-{
- struct omap_drm_private *priv = dev->dev_private;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(priv->crtcs); i++)
- if (priv->crtcs[i] == crtc)
- return i;
-
- BUG(); /* bogus CRTC ptr */
- return -1;
-}
+uint32_t pipe2vbl(struct drm_crtc *crtc);
+struct omap_dss_device *omap_encoder_get_dssdev(struct drm_encoder *encoder);
/* should these be made into common util helpers?
*/
similarity index 95%
rename from drivers/staging/omapdrm/omap_encoder.c
rename to drivers/gpu/drm/omapdrm/omap_encoder.c
index e053160d2db38c9fd6d77bea4971e22635ef18ad..c2aabe05152eb486a17345134155aa7efdac3a77 100644 (file)
rename from drivers/staging/omapdrm/omap_encoder.c
rename to drivers/gpu/drm/omapdrm/omap_encoder.c
index e053160d2db38c9fd6d77bea4971e22635ef18ad..c2aabe05152eb486a17345134155aa7efdac3a77 100644 (file)
/*
- * drivers/staging/omapdrm/omap_encoder.c
+ * drivers/gpu/drm/omapdrm/omap_encoder.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
struct omap_dss_device *dssdev;
};
+struct omap_dss_device *omap_encoder_get_dssdev(struct drm_encoder *encoder)
+{
+ struct omap_encoder *omap_encoder = to_omap_encoder(encoder);
+
+ return omap_encoder->dssdev;
+}
+
static void omap_encoder_destroy(struct drm_encoder *encoder)
{
struct omap_encoder *omap_encoder = to_omap_encoder(encoder);
similarity index 99%
rename from drivers/staging/omapdrm/omap_fb.c
rename to drivers/gpu/drm/omapdrm/omap_fb.c
index 09028e9c1093e247476d4be7fa7684395bede40f..66b8404d87e7cc694ad6bc254fa302a93c659cca 100644 (file)
rename from drivers/staging/omapdrm/omap_fb.c
rename to drivers/gpu/drm/omapdrm/omap_fb.c
index 09028e9c1093e247476d4be7fa7684395bede40f..66b8404d87e7cc694ad6bc254fa302a93c659cca 100644 (file)
/*
- * drivers/staging/omapdrm/omap_fb.c
+ * drivers/gpu/drm/omapdrm/omap_fb.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
similarity index 99%
rename from drivers/staging/omapdrm/omap_fbdev.c
rename to drivers/gpu/drm/omapdrm/omap_fbdev.c
index 8a027bb77d97c8c3fe04a6e0398c8e74aced86ae..5fbb0faeda06f56746f1dcd9e643b2200806171a 100644 (file)
rename from drivers/staging/omapdrm/omap_fbdev.c
rename to drivers/gpu/drm/omapdrm/omap_fbdev.c
index 8a027bb77d97c8c3fe04a6e0398c8e74aced86ae..5fbb0faeda06f56746f1dcd9e643b2200806171a 100644 (file)
/*
- * drivers/staging/omapdrm/omap_fbdev.c
+ * drivers/gpu/drm/omapdrm/omap_fbdev.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
similarity index 99%
rename from drivers/staging/omapdrm/omap_gem.c
rename to drivers/gpu/drm/omapdrm/omap_gem.c
index 08f1e292ed201c57a65bddf67e84de6695a5bf0a..ba8e8d6c42a000e8a561fde8bb4c00cd37997530 100644 (file)
rename from drivers/staging/omapdrm/omap_gem.c
rename to drivers/gpu/drm/omapdrm/omap_gem.c
index 08f1e292ed201c57a65bddf67e84de6695a5bf0a..ba8e8d6c42a000e8a561fde8bb4c00cd37997530 100644 (file)
/*
- * drivers/staging/omapdrm/omap_gem.c
+ * drivers/gpu/drm/omapdrm/omap_gem.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob.clark@linaro.org>
similarity index 99%
rename from drivers/staging/omapdrm/omap_gem_dmabuf.c
rename to drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c
index b6c5b5c6c8c53dbd39e84baa91cd43e1b81ebfb7..ed8d83675330979c7c2f3583c2e2b041d7b4a435 100644 (file)
rename from drivers/staging/omapdrm/omap_gem_dmabuf.c
rename to drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c
index b6c5b5c6c8c53dbd39e84baa91cd43e1b81ebfb7..ed8d83675330979c7c2f3583c2e2b041d7b4a435 100644 (file)
/*
- * drivers/staging/omapdrm/omap_gem_dmabuf.c
+ * drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob.clark@linaro.org>
diff --git a/drivers/staging/omapdrm/omap_gem_helpers.c b/drivers/gpu/drm/omapdrm/omap_gem_helpers.c
similarity index 98%
rename from drivers/staging/omapdrm/omap_gem_helpers.c
rename to drivers/gpu/drm/omapdrm/omap_gem_helpers.c
index ffb8cceaeb465d0c3d3d4ba60606328a353ba152..e4a66a35fc6a9315bdd1bdbb64f77871d0ff58d4 100644 (file)
rename from drivers/staging/omapdrm/omap_gem_helpers.c
rename to drivers/gpu/drm/omapdrm/omap_gem_helpers.c
index ffb8cceaeb465d0c3d3d4ba60606328a353ba152..e4a66a35fc6a9315bdd1bdbb64f77871d0ff58d4 100644 (file)
/*
- * drivers/staging/omapdrm/omap_gem_helpers.c
+ * drivers/gpu/drm/omapdrm/omap_gem_helpers.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob.clark@linaro.org>
similarity index 94%
rename from drivers/staging/omapdrm/omap_irq.c
rename to drivers/gpu/drm/omapdrm/omap_irq.c
index 2629ba7be6c86de53861534d15fbdec02d5f4bda..9263db117ff8ae937dbf743ac0e8a267264d95a4 100644 (file)
rename from drivers/staging/omapdrm/omap_irq.c
rename to drivers/gpu/drm/omapdrm/omap_irq.c
index 2629ba7be6c86de53861534d15fbdec02d5f4bda..9263db117ff8ae937dbf743ac0e8a267264d95a4 100644 (file)
/*
- * drivers/staging/omapdrm/omap_irq.c
+ * drivers/gpu/drm/omapdrm/omap_irq.c
*
* Copyright (C) 2012 Texas Instruments
* Author: Rob Clark <rob.clark@linaro.org>
* Zero on success, appropriate errno if the given @crtc's vblank
* interrupt cannot be enabled.
*/
-int omap_irq_enable_vblank(struct drm_device *dev, int crtc)
+int omap_irq_enable_vblank(struct drm_device *dev, int crtc_id)
{
struct omap_drm_private *priv = dev->dev_private;
+ struct drm_crtc *crtc = priv->crtcs[crtc_id];
unsigned long flags;
- DBG("dev=%p, crtc=%d", dev, crtc);
+ DBG("dev=%p, crtc=%d", dev, crtc_id);
dispc_runtime_get();
spin_lock_irqsave(&list_lock, flags);
* a hardware vblank counter, this routine should be a no-op, since
* interrupts will have to stay on to keep the count accurate.
*/
-void omap_irq_disable_vblank(struct drm_device *dev, int crtc)
+void omap_irq_disable_vblank(struct drm_device *dev, int crtc_id)
{
struct omap_drm_private *priv = dev->dev_private;
+ struct drm_crtc *crtc = priv->crtcs[crtc_id];
unsigned long flags;
- DBG("dev=%p, crtc=%d", dev, crtc);
+ DBG("dev=%p, crtc=%d", dev, crtc_id);
dispc_runtime_get();
spin_lock_irqsave(&list_lock, flags);
VERB("irqs: %08x", irqstatus);
- for (id = 0; id < priv->num_crtcs; id++)
- if (irqstatus & pipe2vbl(id))
+ for (id = 0; id < priv->num_crtcs; id++) {
+ struct drm_crtc *crtc = priv->crtcs[id];
+
+ if (irqstatus & pipe2vbl(crtc))
drm_handle_vblank(dev, id);
+ }
spin_lock_irqsave(&list_lock, flags);
list_for_each_entry_safe(handler, n, &priv->irq_list, node) {
similarity index 98%
rename from drivers/staging/omapdrm/omap_plane.c
rename to drivers/gpu/drm/omapdrm/omap_plane.c
index bb989d7f026dcafd62f1aba1f5d1877ea34d3d9b..b9a94907f78596a6de268c4a4cb804191322fbf3 100644 (file)
rename from drivers/staging/omapdrm/omap_plane.c
rename to drivers/gpu/drm/omapdrm/omap_plane.c
index bb989d7f026dcafd62f1aba1f5d1877ea34d3d9b..b9a94907f78596a6de268c4a4cb804191322fbf3 100644 (file)
/*
- * drivers/staging/omapdrm/omap_plane.c
+ * drivers/gpu/drm/omapdrm/omap_plane.c
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob.clark@linaro.org>
{
struct omap_plane *omap_plane = to_omap_plane(plane);
omap_plane->enabled = true;
+
+ if (plane->fb)
+ drm_framebuffer_unreference(plane->fb);
+
+ drm_framebuffer_reference(fb);
+
return omap_plane_mode_set(plane, crtc, fb,
crtc_x, crtc_y, crtc_w, crtc_h,
src_x, src_y, src_w, src_h,
similarity index 100%
rename from drivers/staging/omapdrm/sita.c
rename to drivers/gpu/drm/omapdrm/sita.c
rename from drivers/staging/omapdrm/sita.c
rename to drivers/gpu/drm/omapdrm/sita.c
similarity index 100%
rename from drivers/staging/omapdrm/tcm-sita.h
rename to drivers/gpu/drm/omapdrm/tcm-sita.h
rename from drivers/staging/omapdrm/tcm-sita.h
rename to drivers/gpu/drm/omapdrm/tcm-sita.h
similarity index 100%
rename from drivers/staging/omapdrm/tcm.h
rename to drivers/gpu/drm/omapdrm/tcm.h
rename from drivers/staging/omapdrm/tcm.h
rename to drivers/gpu/drm/omapdrm/tcm.h
index 5ce9bf51a8de680c1658e0dd26491e16f8f77511..43672b6f7cfd1c9dc29eb6a31e0c91adb68a5f47 100644 (file)
firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset);
DRM_DEBUG("atom firmware requested %08x %dkb\n",
- firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware,
- firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb);
+ le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware),
+ le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb));
- usage_bytes = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb * 1024;
+ usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024;
}
ctx->scratch_size_bytes = 0;
if (usage_bytes == 0)
index 21a892c6ab9c85929bc781bb116071ae66e8ad23..6d6fdb3ba0d07d859b8c0fba223c0fe8193b1e46 100644 (file)
/* use frac fb div on APUs */
if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
+ /* use frac fb div on RS780/RS880 */
+ if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
+ radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
} else {
index 1b0a4eca922a8d0e0399451cc7eeeadd9cbb590e..90dc470766206e14f606fdbdf44c86021fa0dba8 100644 (file)
}
}
+static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
+{
+ if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
+ return true;
+ else
+ return false;
+}
+
+static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
+{
+ u32 pos1, pos2;
+
+ pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
+ pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
+
+ if (pos1 != pos2)
+ return true;
+ else
+ return false;
+}
+
/**
* dce4_wait_for_vblank - vblank wait asic callback.
*
*/
void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
{
- int i;
+ unsigned i = 0;
if (crtc >= rdev->num_crtc)
return;
- if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
- for (i = 0; i < rdev->usec_timeout; i++) {
- if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
+ if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
+ return;
+
+ /* depending on when we hit vblank, we may be close to active; if so,
+ * wait for another frame.
+ */
+ while (dce4_is_in_vblank(rdev, crtc)) {
+ if (i++ % 100 == 0) {
+ if (!dce4_is_counter_moving(rdev, crtc))
break;
- udelay(1);
}
- for (i = 0; i < rdev->usec_timeout; i++) {
- if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
+ }
+
+ while (!dce4_is_in_vblank(rdev, crtc)) {
+ if (i++ % 100 == 0) {
+ if (!dce4_is_counter_moving(rdev, crtc))
break;
- udelay(1);
}
}
}
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+
+ if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
+ connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
+ /* don't try to enable hpd on eDP or LVDS avoid breaking the
+ * aux dp channel on imac and help (but not completely fix)
+ * https://bugzilla.redhat.com/show_bug.cgi?id=726143
+ * also avoid interrupt storms during dpms.
+ */
+ continue;
+ }
switch (radeon_connector->hpd.hpd) {
case RADEON_HPD_1:
WREG32(DC_HPD1_CONTROL, tmp);
@@ -1325,17 +1363,16 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
radeon_wait_for_vblank(rdev, i);
- tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
- WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
}
} else {
tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
radeon_wait_for_vblank(rdev, i);
- tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
}
@@ -1347,6 +1384,15 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
break;
udelay(1);
}
+
+ /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+ tmp &= ~EVERGREEN_CRTC_MASTER_EN;
+ WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
+ WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ save->crtc_enabled[i] = false;
+ /* ***** */
} else {
save->crtc_enabled[i] = false;
}
@@ -1364,6 +1410,22 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
}
/* wait for the MC to settle */
udelay(100);
+
+ /* lock double buffered regs */
+ for (i = 0; i < rdev->num_crtc; i++) {
+ if (save->crtc_enabled[i]) {
+ tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
+ if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
+ tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
+ WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
+ }
+ tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+ if (!(tmp & 1)) {
+ tmp |= 1;
+ WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+ }
+ }
+ }
}
void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -1385,6 +1447,33 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
+ /* unlock regs and wait for update */
+ for (i = 0; i < rdev->num_crtc; i++) {
+ if (save->crtc_enabled[i]) {
+ tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
+ if ((tmp & 0x3) != 0) {
+ tmp &= ~0x3;
+ WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
+ }
+ tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
+ if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
+ tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
+ WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
+ }
+ tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+ if (tmp & 1) {
+ tmp &= ~1;
+ WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+ }
+ for (j = 0; j < rdev->usec_timeout; j++) {
+ tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
+ if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
+ break;
+ udelay(1);
+ }
+ }
+ }
+
/* unblackout the MC */
tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
tmp &= ~BLACKOUT_MODE_MASK;
index 034f4c22e5db7ffdd6735540c80b0769def8b324..3e9773aea7fe56861a708fb6a9d9f88ee49db067 100644 (file)
#define EVERGREEN_CRTC_STATUS_POSITION 0x6e90
#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
+#define EVERGREEN_MASTER_UPDATE_LOCK 0x6ef4
+#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0
#define EVERGREEN_DC_GPIO_HPD_A 0x64b4
index b64e55dac7571672a6a734dddc1f591646abfde1..10e1bd112709b6aa1295ddbb8648426437b86042 100644 (file)
(rdev->pdev->device == 0x990F) ||
(rdev->pdev->device == 0x9910) ||
(rdev->pdev->device == 0x9917) ||
- (rdev->pdev->device == 0x9999)) {
+ (rdev->pdev->device == 0x9999) ||
+ (rdev->pdev->device == 0x999C)) {
rdev->config.cayman.max_simds_per_se = 6;
rdev->config.cayman.max_backends_per_se = 2;
} else if ((rdev->pdev->device == 0x9903) ||
(rdev->pdev->device == 0x990D) ||
(rdev->pdev->device == 0x990E) ||
(rdev->pdev->device == 0x9913) ||
- (rdev->pdev->device == 0x9918)) {
+ (rdev->pdev->device == 0x9918) ||
+ (rdev->pdev->device == 0x999D)) {
rdev->config.cayman.max_simds_per_se = 4;
rdev->config.cayman.max_backends_per_se = 2;
} else if ((rdev->pdev->device == 0x9919) ||
WREG32(GB_ADDR_CONFIG, gb_addr_config);
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+ if (ASIC_IS_DCE6(rdev))
+ WREG32(DMIF_ADDR_CALC, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
index 48e5022ee921d33081f86de17d8ab6b0520ea037..e045f8cbcd4f4ac1ebf24149cfff274614acaa95 100644 (file)
#define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
#define DMIF_ADDR_CONFIG 0xBD4
+
+/* DCE6 only */
+#define DMIF_ADDR_CALC 0xC00
+
#define SRBM_GFX_CNTL 0x0E44
#define RINGID(x) (((x) & 0x3) << 0)
#define VMID(x) (((x) & 0x7) << 0)
index 8ff7cac222dce7ccba37e5318adea5773571cd6f..62719ecfef632f55cdd393117df93f50b39e68fa 100644 (file)
* and others in some cases.
*/
+static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
+{
+ if (crtc == 0) {
+ if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
+ return true;
+ else
+ return false;
+ } else {
+ if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
+ return true;
+ else
+ return false;
+ }
+}
+
+static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
+{
+ u32 vline1, vline2;
+
+ if (crtc == 0) {
+ vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
+ vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
+ } else {
+ vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
+ vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
+ }
+ if (vline1 != vline2)
+ return true;
+ else
+ return false;
+}
+
/**
* r100_wait_for_vblank - vblank wait asic callback.
*
*/
void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
{
- int i;
+ unsigned i = 0;
if (crtc >= rdev->num_crtc)
return;
if (crtc == 0) {
- if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
- for (i = 0; i < rdev->usec_timeout; i++) {
- if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
- break;
- udelay(1);
- }
- for (i = 0; i < rdev->usec_timeout; i++) {
- if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
- break;
- udelay(1);
- }
- }
+ if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
+ return;
} else {
- if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
- for (i = 0; i < rdev->usec_timeout; i++) {
- if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
- break;
- udelay(1);
- }
- for (i = 0; i < rdev->usec_timeout; i++) {
- if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
- break;
- udelay(1);
- }
+ if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
+ return;
+ }
+
+ /* depending on when we hit vblank, we may be close to active; if so,
+ * wait for another frame.
+ */
+ while (r100_is_in_vblank(rdev, crtc)) {
+ if (i++ % 100 == 0) {
+ if (!r100_is_counter_moving(rdev, crtc))
+ break;
+ }
+ }
+
+ while (!r100_is_in_vblank(rdev, crtc)) {
+ if (i++ % 100 == 0) {
+ if (!r100_is_counter_moving(rdev, crtc))
+ break;
}
}
}
index ec576aaafb7347b74f5f223f31a0273ffb8215fe..8ec2376d47c1bdceee4ef9b870e1bc0b7f63c9e3 100644 (file)
#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
+#define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0
#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
+#define AVIVO_D1CRTC_UPDATE_LOCK 0x60e8
/* master controls */
#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
index 95970ec47c45f674bc80b712faedd95caaf11e81..d89a1f83309f6b090b270be088e09121dec10465 100644 (file)
offset = dig->afmt->offset;
/* Older chipsets require setting HDMI and routing manually */
- if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
+ if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) {
hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE;
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
/* Older chipsets not handled by AtomBIOS */
- if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
+ if (ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE3(rdev)) {
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
WREG32_P(AVIVO_TMDSA_CNTL, 0,
index f22eb5713528e6e83037c3950360261932cb9273..96168ef4ab19e9d81dc401ae8b783d64b0f261bf 100644 (file)
num_modes = power_info->info.ucNumOfPowerModeEntries;
if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
+ if (num_modes == 0)
+ return state_index;
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) * num_modes, GFP_KERNEL);
if (!rdev->pm.power_state)
return state_index;
power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
+ if (power_info->pplib.ucNumStates == 0)
+ return state_index;
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
power_info->pplib.ucNumStates, GFP_KERNEL);
if (!rdev->pm.power_state)
int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
u16 data_offset;
u8 frev, crev;
+ u8 *power_state_offset;
if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
&frev, &crev, &data_offset))
non_clock_info_array = (struct _NonClockInfoArray *)
(mode_info->atom_context->bios + data_offset +
le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
+ if (state_array->ucNumEntries == 0)
+ return state_index;
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state) *
state_array->ucNumEntries, GFP_KERNEL);
if (!rdev->pm.power_state)
return state_index;
+ power_state_offset = (u8 *)state_array->states;
for (i = 0; i < state_array->ucNumEntries; i++) {
mode_index = 0;
- power_state = (union pplib_power_state *)&state_array->states[i];
- /* XXX this might be an inagua bug... */
- non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
+ power_state = (union pplib_power_state *)power_state_offset;
+ non_clock_array_index = power_state->v2.nonClockInfoIndex;
non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
&non_clock_info_array->nonClockInfo[non_clock_array_index];
rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
if (power_state->v2.ucNumDPMLevels) {
for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
clock_array_index = power_state->v2.clockInfoIndex[j];
- /* XXX this might be an inagua bug... */
- if (clock_array_index >= clock_info_array->ucNumEntries)
- continue;
clock_info = (union pplib_clock_info *)
&clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
valid = radeon_atombios_parse_pplib_clock_info(rdev,
non_clock_info);
state_index++;
}
+ power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
}
/* if multiple clock modes, mark the lowest as no display */
for (i = 0; i < state_index; i++) {
default:
break;
}
- } else {
+ }
+
+ if (state_index == 0) {
rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
if (rdev->pm.power_state) {
rdev->pm.power_state[0].clock_info =
index 9c312f9afb68cf5bc1faafce0e9ba39818987715..bc36922d05f1b199d860bb54fcc59fdae2038770 100644 (file)
if (rdev == NULL)
return 0;
+ if (rdev->rmmio == NULL)
+ goto done_free;
radeon_acpi_fini(rdev);
radeon_modeset_fini(rdev);
radeon_device_fini(rdev);
+
+done_free:
kfree(rdev);
dev->dev_private = NULL;
return 0;
index 338fd6a74e8715e8db2335a90043242870e094f6..788c64cb4b47e95ef66edbc1d5fcbbefb01c2e95 100644 (file)
struct radeon_device *rdev = dev->dev_private;
seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
- seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
+ /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
+ if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
+ seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
+ else
+ seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
if (rdev->asic->pm.get_memory_clock)
seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
index cd72062d5a9134bd596c8a6388b78fd45bb02425..8adc5b5541fe11f4ce0d0cb44bd0a205c782526a 100644 (file)
radeon_semaphore_free(rdev, &ib->semaphore, NULL);
}
/* if we can't remember our last VM flush then flush now! */
- if (ib->vm && !ib->vm->last_flush) {
+ /* XXX figure out why we have to flush for every IB */
+ if (ib->vm /*&& !ib->vm->last_flush*/) {
radeon_ring_vm_flush(rdev, ib->ring, ib->vm);
}
if (const_ib) {
index 5a0fc74c2ba68c61d93779ec10d3164ee59087c4..46fa1b07c5602388581bed64cc9bc5ea6065a35c 100644 (file)
AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
};
+static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
+{
+ if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
+ return true;
+ else
+ return false;
+}
+
+static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
+{
+ u32 pos1, pos2;
+
+ pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
+ pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
+
+ if (pos1 != pos2)
+ return true;
+ else
+ return false;
+}
+
+/**
+ * avivo_wait_for_vblank - vblank wait asic callback.
+ *
+ * @rdev: radeon_device pointer
+ * @crtc: crtc to wait for vblank on
+ *
+ * Wait for vblank on the requested crtc (r5xx-r7xx).
+ */
void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
{
- int i;
+ unsigned i = 0;
if (crtc >= rdev->num_crtc)
return;
- if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) {
- for (i = 0; i < rdev->usec_timeout; i++) {
- if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK))
+ if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
+ return;
+
+ /* depending on when we hit vblank, we may be close to active; if so,
+ * wait for another frame.
+ */
+ while (avivo_is_in_vblank(rdev, crtc)) {
+ if (i++ % 100 == 0) {
+ if (!avivo_is_counter_moving(rdev, crtc))
break;
- udelay(1);
}
- for (i = 0; i < rdev->usec_timeout; i++) {
- if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
+ }
+
+ while (!avivo_is_in_vblank(rdev, crtc)) {
+ if (i++ % 100 == 0) {
+ if (!avivo_is_counter_moving(rdev, crtc))
break;
- udelay(1);
}
}
}
index 435ed35513643b868907716b9b4a231de4d0a58c..ffcba730c57cb3172a4084d696d1cc70e9ec0adf 100644 (file)
tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
radeon_wait_for_vblank(rdev, i);
+ WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
+ WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
}
/* wait for the next frame */
frame_count = radeon_get_vblank_counter(rdev, i);
break;
udelay(1);
}
+
+ /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
+ WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+ tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
+ tmp &= ~AVIVO_CRTC_EN;
+ WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
+ WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+ save->crtc_enabled[i] = false;
+ /* ***** */
} else {
save->crtc_enabled[i] = false;
}
}
/* wait for the MC to settle */
udelay(100);
+
+ /* lock double buffered regs */
+ for (i = 0; i < rdev->num_crtc; i++) {
+ if (save->crtc_enabled[i]) {
+ tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
+ if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
+ tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
+ WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
+ }
+ tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+ if (!(tmp & 1)) {
+ tmp |= 1;
+ WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+ }
+ }
+ }
}
void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
/* update crtc base addresses */
for (i = 0; i < rdev->num_crtc; i++) {
if (rdev->family >= CHIP_RV770) {
- if (i == 1) {
+ if (i == 0) {
WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
upper_32_bits(rdev->mc.vram_start));
WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
}
WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
+ /* unlock regs and wait for update */
+ for (i = 0; i < rdev->num_crtc; i++) {
+ if (save->crtc_enabled[i]) {
+ tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
+ if ((tmp & 0x3) != 0) {
+ tmp &= ~0x3;
+ WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
+ }
+ tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
+ if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
+ tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
+ WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
+ }
+ tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
+ if (tmp & 1) {
+ tmp &= ~1;
+ WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
+ }
+ for (j = 0; j < rdev->usec_timeout; j++) {
+ tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
+ if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
+ break;
+ udelay(1);
+ }
+ }
+ }
+
if (rdev->family >= CHIP_R600) {
/* unblackout the MC */
if (rdev->family >= CHIP_RV770)
index dd007214dfffdd8edc178e25e2445e5fcc18c3e2..40d766edc30174bce3bc8d6139f1fb88f6158539 100644 (file)
u32 data = INSTANCE_BROADCAST_WRITES;
if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
- data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
+ data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
else if (se_num == 0xffffffff)
data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
else if (sh_num == 0xffffffff)
WREG32(GB_ADDR_CONFIG, gb_addr_config);
WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
+ WREG32(DMIF_ADDR_CALC, gb_addr_config);
WREG32(HDP_ADDR_CONFIG, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
index c056aae814f090693a4eb445d83d3ca2be30efd7..e9a01f025dcd2545659ce157d39911bb81329073 100644 (file)
#define DMIF_ADDR_CONFIG 0xBD4
+#define DMIF_ADDR_CALC 0xC00
+
#define SRBM_STATUS 0xE50
#define SRBM_SOFT_RESET 0x0E60
index f042f6da0ace57cb60d0da99ef6bdb554db0d8b5..fd7d66dd2e1482a45c63a44e3607d9f8ae1fd670 100644 (file)
/* last message in transfer -> STOP */
data |= XIIC_TX_DYN_STOP_MASK;
dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__);
-
- xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
- } else
- xiic_setreg8(i2c, XIIC_DTR_REG_OFFSET, data);
+ }
+ xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data);
}
}
index cd030e100c395416e4043ad6659f7030266b9b7e..ee20c0c967652b8c3469da3000e8ed43e267665e 100644 (file)
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/platform_device.h>
-#include <linux/io.h>
#include <linux/iio/iio.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/iio/machine.h>
+#include <linux/iio/driver.h>
+#include <linux/regmap.h>
+#include <linux/io.h>
#include <linux/mfd/ti_am335x_tscadc.h>
#include <linux/platform_data/ti_am335x_adc.h>
struct tiadc_device {
struct ti_tscadc_dev *mfd_tscadc;
int channels;
+ char *buf;
+ struct iio_map *map;
};
static unsigned int tiadc_readl(struct tiadc_device *adc, unsigned int reg)
{
- return readl(adc->mfd_tscadc->tscadc_base + reg);
+ unsigned int val;
+
+ val = (unsigned int)-1;
+ regmap_read(adc->mfd_tscadc->regmap_tscadc, reg, &val);
+ return val;
}
static void tiadc_writel(struct tiadc_device *adc, unsigned int reg,
unsigned int val)
{
- writel(val, adc->mfd_tscadc->tscadc_base + reg);
+ regmap_write(adc->mfd_tscadc->regmap_tscadc, reg, val);
}
static void tiadc_step_config(struct tiadc_device *adc_dev)
tiadc_writel(adc_dev, REG_SE, STPENB_STEPENB);
}
-static int tiadc_channel_init(struct iio_dev *indio_dev, int channels)
+static int tiadc_channel_init(struct iio_dev *indio_dev,
+ struct tiadc_device *adc_dev)
{
struct iio_chan_spec *chan_array;
- int i;
-
- indio_dev->num_channels = channels;
- chan_array = kcalloc(indio_dev->num_channels,
- sizeof(struct iio_chan_spec), GFP_KERNEL);
+ struct iio_chan_spec *chan;
+ char *s;
+ int i, len, size, ret;
+ int channels = adc_dev->channels;
+ size = channels * (sizeof(struct iio_chan_spec) + 6);
+ chan_array = kzalloc(size, GFP_KERNEL);
if (chan_array == NULL)
return -ENOMEM;
- for (i = 0; i < (indio_dev->num_channels); i++) {
- struct iio_chan_spec *chan = chan_array + i;
+ /* buffer space is after the array */
+ s = (char *)(chan_array + channels);
+ chan = chan_array;
+ for (i = 0; i < channels; i++, chan++, s += len + 1) {
+
+ len = sprintf(s, "AIN%d", i);
+
chan->type = IIO_VOLTAGE;
chan->indexed = 1;
chan->channel = i;
- chan->info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT;
+ chan->datasheet_name = s;
+ chan->scan_type.sign = 'u';
+ chan->scan_type.realbits = 12;
+ chan->scan_type.storagebits = 32;
+ chan->scan_type.shift = 0;
}
indio_dev->channels = chan_array;
+ indio_dev->num_channels = channels;
+
+ size = (channels + 1) * sizeof(struct iio_map);
+ adc_dev->map = kzalloc(size, GFP_KERNEL);
+ if (adc_dev->map == NULL) {
+ kfree(chan_array);
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < indio_dev->num_channels; i++) {
+ adc_dev->map[i].adc_channel_label = chan_array[i].datasheet_name;
+ adc_dev->map[i].consumer_dev_name = "any";
+ adc_dev->map[i].consumer_channel = chan_array[i].datasheet_name;
+ }
+ adc_dev->map[i].adc_channel_label = NULL;
+ adc_dev->map[i].consumer_dev_name = NULL;
+ adc_dev->map[i].consumer_channel = NULL;
+
+ ret = iio_map_array_register(indio_dev, adc_dev->map);
+ if (ret != 0) {
+ kfree(adc_dev->map);
+ kfree(chan_array);
+ return -ENOMEM;
+ }
return indio_dev->num_channels;
}
struct iio_dev *indio_dev;
struct tiadc_device *adc_dev;
struct ti_tscadc_dev *tscadc_dev = pdev->dev.platform_data;
- struct mfd_tscadc_board *pdata;
+ struct mfd_tscadc_board *pdata = tscadc_dev->dev->platform_data;
+ struct device_node *node = tscadc_dev->dev->of_node;
int err;
+ u32 val32;
- pdata = tscadc_dev->dev->platform_data;
- if (!pdata || !pdata->adc_init) {
+ if (!pdata && !node) {
dev_err(&pdev->dev, "Could not find platform data\n");
return -EINVAL;
}
adc_dev = iio_priv(indio_dev);
adc_dev->mfd_tscadc = tscadc_dev;
- adc_dev->channels = pdata->adc_init->adc_channels;
+
+ if (pdata)
+ adc_dev->channels = pdata->adc_init->adc_channels;
+ else {
+ node = of_get_child_by_name(node, "adc");
+ if (!node)
+ return -EINVAL;
+ else {
+ err = of_property_read_u32(node,
+ "ti,adc-channels", &val32);
+ if (err < 0)
+ goto err_free_device;
+ else
+ adc_dev->channels = val32;
+ }
+ }
indio_dev->dev.parent = &pdev->dev;
indio_dev->name = dev_name(&pdev->dev);
tiadc_step_config(adc_dev);
- err = tiadc_channel_init(indio_dev, adc_dev->channels);
+ err = tiadc_channel_init(indio_dev, adc_dev);
if (err < 0)
goto err_free_device;
platform_set_drvdata(pdev, indio_dev);
+ dev_info(&pdev->dev, "Initialized\n");
+
return 0;
err_free_channels:
index 05bfe53bff647b8e47ed1d6ef361734ce69b4e8e..892cd872733c4ccbfd9c803c227a71965c812033 100644 (file)
return 0;
}
+static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
+{
+ int ret = -ENOSYS;
+ if (user)
+ ret = alloc_oc_sq(rdev, sq);
+ if (ret)
+ ret = alloc_host_sq(rdev, sq);
+ return ret;
+}
+
static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
struct c4iw_dev_ucontext *uctx)
{
goto free_sw_rq;
}
- if (user) {
- ret = alloc_oc_sq(rdev, &wq->sq);
- if (ret)
- goto free_hwaddr;
-
- ret = alloc_host_sq(rdev, &wq->sq);
- if (ret)
- goto free_sq;
- } else
- ret = alloc_host_sq(rdev, &wq->sq);
- if (ret)
- goto free_hwaddr;
+ ret = alloc_sq(rdev, &wq->sq, user);
+ if (ret)
+ goto free_hwaddr;
memset(wq->sq.queue, 0, wq->sq.memsize);
dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
index 51e7b87827a45ff0bd1c5335d2dc7b7b0ce70d8a..4fcf72f488d07fff9e201b03affc4f0bc4852aee 100644 (file)
#include <linux/io.h>
#include <linux/input/ti_am335x_tsc.h>
#include <linux/delay.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
#include <linux/mfd/ti_am335x_tscadc.h>
#define ADCFSM_STEPID 0x10
#define SEQ_SETTLE 275
#define MAX_12BIT ((1 << 12) - 1)
+#define TSCADC_DELTA_X 15
+#define TSCADC_DELTA_Y 15
+
+/*
+ * Refer to function regbit_map() to
+ * map the values in the matrix.
+ */
+static int config[4][4] = {
+ {1, 0, 1, 0},
+ {2, 3, 2, 3},
+ {4, 5, 4, 5},
+ {0, 6, 0, 6}
+};
struct titsc {
struct input_dev *input;
unsigned int irq;
unsigned int wires;
unsigned int x_plate_resistance;
+ unsigned int enable_bits;
+ unsigned int bckup_x;
+ unsigned int bckup_y;
bool pen_down;
int steps_to_configure;
+ int config_inp[20];
+ int bit_xp, bit_xn, bit_yp, bit_yn;
+ int inp_xp, inp_xn, inp_yp, inp_yn;
};
static unsigned int titsc_readl(struct titsc *ts, unsigned int reg)
{
- return readl(ts->mfd_tscadc->tscadc_base + reg);
+ unsigned int val;
+
+ val = (unsigned int)-1;
+ regmap_read(ts->mfd_tscadc->regmap_tscadc, reg, &val);
+ return val;
}
static void titsc_writel(struct titsc *tsc, unsigned int reg,
unsigned int val)
{
- writel(val, tsc->mfd_tscadc->tscadc_base + reg);
+ regmap_write(tsc->mfd_tscadc->regmap_tscadc, reg, val);
+}
+
+/*
+ * Each of the analog lines are mapped
+ * with one or two register bits,
+ * which can be either pulled high/low
+ * depending on the value to be read.
+ */
+static int regbit_map(int val)
+{
+ int map_bits = 0;
+
+ switch (val) {
+ case 1:
+ map_bits = XPP;
+ break;
+ case 2:
+ map_bits = XNP;
+ break;
+ case 3:
+ map_bits = XNN;
+ break;
+ case 4:
+ map_bits = YPP;
+ break;
+ case 5:
+ map_bits = YPN;
+ break;
+ case 6:
+ map_bits = YNN;
+ break;
+ }
+
+ return map_bits;
+}
+
+static int titsc_config_wires(struct titsc *ts_dev)
+{
+ int analog_line[10], wire_order[10];
+ int i, temp_bits, err;
+
+ for (i = 0; i < 4; i++) {
+ /*
+ * Get the order in which TSC wires are attached
+ * w.r.t. each of the analog input lines on the EVM.
+ */
+ analog_line[i] = ts_dev->config_inp[i] & 0xF0;
+ analog_line[i] = analog_line[i] >> 4;
+
+ wire_order[i] = ts_dev->config_inp[i] & 0x0F;
+ }
+
+ for (i = 0; i < 4; i++) {
+ switch (wire_order[i]) {
+ case 0:
+ temp_bits = config[analog_line[i]][0];
+ if (temp_bits == 0) {
+ err = -EINVAL;
+ goto ret;
+ } else {
+ ts_dev->bit_xp = regbit_map(temp_bits);
+ ts_dev->inp_xp = analog_line[i];
+ break;
+ }
+ case 1:
+ temp_bits = config[analog_line[i]][1];
+ if (temp_bits == 0) {
+ err = -EINVAL;
+ goto ret;
+ } else {
+ ts_dev->bit_xn = regbit_map(temp_bits);
+ ts_dev->inp_xn = analog_line[i];
+ break;
+ }
+ case 2:
+ temp_bits = config[analog_line[i]][2];
+ if (temp_bits == 0) {
+ err = -EINVAL;
+ goto ret;
+ } else {
+ ts_dev->bit_yp = regbit_map(temp_bits);
+ ts_dev->inp_yp = analog_line[i];
+ break;
+ }
+ case 3:
+ temp_bits = config[analog_line[i]][3];
+ if (temp_bits == 0) {
+ err = -EINVAL;
+ goto ret;
+ } else {
+ ts_dev->bit_yn = regbit_map(temp_bits);
+ ts_dev->inp_yn = analog_line[i];
+ break;
+ }
+ }
+ }
+
+ return 0;
+
+ret:
+ return err;
}
static void titsc_step_config(struct titsc *ts_dev)
{
unsigned int config;
+ unsigned int stepenable = 0;
int i, total_steps;
/* Configure the Step registers */
total_steps = 2 * ts_dev->steps_to_configure;
config = STEPCONFIG_MODE_HWSYNC |
- STEPCONFIG_AVG_16 | STEPCONFIG_XPP;
+ STEPCONFIG_AVG_16 | ts_dev->bit_xp;
switch (ts_dev->wires) {
case 4:
- config |= STEPCONFIG_INP_AN2 | STEPCONFIG_XNN;
+ config |= STEPCONFIG_INP(ts_dev->inp_yp) | ts_dev->bit_xn;
break;
case 5:
- config |= STEPCONFIG_YNN |
- STEPCONFIG_INP_AN4 | STEPCONFIG_XNN |
- STEPCONFIG_YPP;
+ config |= ts_dev->bit_yn |
+ STEPCONFIG_INP_AN4 | ts_dev->bit_xn |
+ ts_dev->bit_yp;
break;
case 8:
- config |= STEPCONFIG_INP_AN2 | STEPCONFIG_XNN;
+ config |= STEPCONFIG_INP(ts_dev->inp_yp) | ts_dev->bit_xn;
break;
}
config = 0;
config = STEPCONFIG_MODE_HWSYNC |
- STEPCONFIG_AVG_16 | STEPCONFIG_YNN |
+ STEPCONFIG_AVG_16 | ts_dev->bit_yn |
STEPCONFIG_INM_ADCREFM | STEPCONFIG_FIFO1;
switch (ts_dev->wires) {
case 4:
- config |= STEPCONFIG_YPP;
+ config |= ts_dev->bit_yp | STEPCONFIG_INP(ts_dev->inp_xp);
break;
case 5:
- config |= STEPCONFIG_XPP | STEPCONFIG_INP_AN4 |
- STEPCONFIG_XNP | STEPCONFIG_YPN;
+ config |= ts_dev->bit_xp | STEPCONFIG_INP_AN4 |
+ ts_dev->bit_xn | ts_dev->bit_yp;
break;
case 8:
- config |= STEPCONFIG_YPP;
+ config |= ts_dev->bit_yp | STEPCONFIG_INP(ts_dev->inp_xp);
break;
}
config = 0;
/* Charge step configuration */
- config = STEPCONFIG_XPP | STEPCONFIG_YNN |
+ config = ts_dev->bit_xp | ts_dev->bit_yn |
STEPCHARGE_RFP_XPUL | STEPCHARGE_RFM_XNUR |
- STEPCHARGE_INM_AN1 | STEPCHARGE_INP_AN1;
+ STEPCHARGE_INM_AN1 | STEPCHARGE_INP(ts_dev->inp_yp);
titsc_writel(ts_dev, REG_CHARGECONFIG, config);
titsc_writel(ts_dev, REG_CHARGEDELAY, CHARGEDLY_OPENDLY);
config = 0;
/* Configure to calculate pressure */
config = STEPCONFIG_MODE_HWSYNC |
- STEPCONFIG_AVG_16 | STEPCONFIG_YPP |
- STEPCONFIG_XNN | STEPCONFIG_INM_ADCREFM;
+ STEPCONFIG_AVG_16 | ts_dev->bit_yp |
+ ts_dev->bit_xn | STEPCONFIG_INM_ADCREFM |
+ STEPCONFIG_INP(ts_dev->inp_xp);
titsc_writel(ts_dev, REG_STEPCONFIG(total_steps + 1), config);
titsc_writel(ts_dev, REG_STEPDELAY(total_steps + 1),
STEPCONFIG_OPENDLY);
- config |= STEPCONFIG_INP_AN3 | STEPCONFIG_FIFO1;
+ config |= STEPCONFIG_INP(ts_dev->inp_yn) | STEPCONFIG_FIFO1;
titsc_writel(ts_dev, REG_STEPCONFIG(total_steps + 2), config);
titsc_writel(ts_dev, REG_STEPDELAY(total_steps + 2),
STEPCONFIG_OPENDLY);
- titsc_writel(ts_dev, REG_SE, STPENB_STEPENB_TC);
+ for (i = 0; i <= (total_steps + 2); i++)
+ stepenable |= 1 << i;
+ ts_dev->enable_bits = stepenable;
+
+ titsc_writel(ts_dev, REG_SE, ts_dev->enable_bits);
}
static void titsc_read_coordinates(struct titsc *ts_dev,
unsigned int x = 0, y = 0;
unsigned int z1, z2, z;
unsigned int fsm;
- unsigned int fifo1count, fifo0count;
+ unsigned int diffx = 0, diffy = 0;
int i;
status = titsc_readl(ts_dev, REG_IRQSTATUS);
if (status & IRQENB_FIFO0THRES) {
titsc_read_coordinates(ts_dev, &x, &y);
+ diffx = abs(x - (ts_dev->bckup_x));
+ diffy = abs(y - (ts_dev->bckup_y));
+ ts_dev->bckup_x = x;
+ ts_dev->bckup_y = y;
+
z1 = titsc_readl(ts_dev, REG_FIFO0) & 0xfff;
z2 = titsc_readl(ts_dev, REG_FIFO1) & 0xfff;
- fifo1count = titsc_readl(ts_dev, REG_FIFO1CNT);
- for (i = 0; i < fifo1count; i++)
- titsc_readl(ts_dev, REG_FIFO1);
-
- fifo0count = titsc_readl(ts_dev, REG_FIFO0CNT);
- for (i = 0; i < fifo0count; i++)
- titsc_readl(ts_dev, REG_FIFO0);
-
if (ts_dev->pen_down && z1 != 0 && z2 != 0) {
/*
* Calculate pressure using formula
z /= z1;
z = (z + 2047) >> 12;
- if (z <= MAX_12BIT) {
+ if ((diffx < TSCADC_DELTA_X) &&
+ (diffy < TSCADC_DELTA_Y) && (z <= MAX_12BIT)) {
input_report_abs(input_dev, ABS_X, x);
input_report_abs(input_dev, ABS_Y, y);
input_report_abs(input_dev, ABS_PRESSURE, z);
fsm = titsc_readl(ts_dev, REG_ADCFSM);
if (fsm == ADCFSM_STEPID) {
ts_dev->pen_down = false;
+ ts_dev->bckup_x = 0;
+ ts_dev->bckup_y = 0;
input_report_key(input_dev, BTN_TOUCH, 0);
input_report_abs(input_dev, ABS_PRESSURE, 0);
input_sync(input_dev);
titsc_writel(ts_dev, REG_IRQSTATUS, irqclr);
- titsc_writel(ts_dev, REG_SE, STPENB_STEPENB_TC);
+ titsc_writel(ts_dev, REG_SE, ts_dev->enable_bits);
return IRQ_HANDLED;
}
+static int titsc_parse_dt(struct ti_tscadc_dev *tscadc_dev,
+ struct titsc *ts_dev)
+{
+ struct device_node *node = tscadc_dev->dev->of_node;
+ int err, i;
+ u32 val32, wires_conf[4];
+
+ if (!node)
+ return -EINVAL;
+ else {
+ node = of_get_child_by_name(node, "tsc");
+ if (!node)
+ return -EINVAL;
+ else {
+ err = of_property_read_u32(node, "ti,wires", &val32);
+ if (err < 0)
+ goto error_ret;
+ else
+ ts_dev->wires = val32;
+
+ err = of_property_read_u32(node,
+ "ti,x-plate-resistance", &val32);
+ if (err < 0)
+ goto error_ret;
+ else
+ ts_dev->x_plate_resistance = val32;
+
+ err = of_property_read_u32(node,
+ "ti,steps-to-configure", &val32);
+ if (err < 0)
+ goto error_ret;
+ else
+ ts_dev->steps_to_configure = val32;
+
+ err = of_property_read_u32_array(node, "ti,wire-config",
+ wires_conf, ARRAY_SIZE(wires_conf));
+ if (err < 0)
+ goto error_ret;
+ else {
+ for (i = 0; i < ARRAY_SIZE(wires_conf); i++)
+ ts_dev->config_inp[i] = wires_conf[i];
+ }
+ }
+ }
+ return 0;
+
+error_ret:
+ return err;
+}
+
+static int titsc_parse_pdata(struct ti_tscadc_dev *tscadc_dev,
+ struct titsc *ts_dev)
+{
+ struct mfd_tscadc_board *pdata = tscadc_dev->dev->platform_data;
+
+ if (!pdata)
+ return -EINVAL;
+
+ ts_dev->wires = pdata->tsc_init->wires;
+ ts_dev->x_plate_resistance =
+ pdata->tsc_init->x_plate_resistance;
+ ts_dev->steps_to_configure =
+ pdata->tsc_init->steps_to_configure;
+ memcpy(ts_dev->config_inp, pdata->tsc_init->wire_config,
+ sizeof(pdata->tsc_init->wire_config));
+ return 0;
+}
+
/*
* The functions for inserting/removing driver as a module.
*/
struct titsc *ts_dev;
struct input_dev *input_dev;
struct ti_tscadc_dev *tscadc_dev = pdev->dev.platform_data;
- struct mfd_tscadc_board *pdata;
int err;
- pdata = tscadc_dev->dev->platform_data;
-
- if (!pdata) {
- dev_err(&pdev->dev, "Could not find platform data\n");
- return -EINVAL;
- }
-
/* Allocate memory for device */
ts_dev = kzalloc(sizeof(struct titsc), GFP_KERNEL);
input_dev = input_allocate_device();
ts_dev->mfd_tscadc = tscadc_dev;
ts_dev->input = input_dev;
ts_dev->irq = tscadc_dev->irq;
- ts_dev->wires = pdata->tsc_init->wires;
- ts_dev->x_plate_resistance = pdata->tsc_init->x_plate_resistance;
- ts_dev->steps_to_configure = pdata->tsc_init->steps_to_configure;
+
+ if (tscadc_dev->dev->platform_data)
+ err = titsc_parse_pdata(tscadc_dev, ts_dev);
+ else
+ err = titsc_parse_dt(tscadc_dev, ts_dev);
+
+ if (err) {
+ dev_err(&pdev->dev, "Could not find platform data\n");
+ err = -EINVAL;
+ goto err_free_mem;
+ }
err = request_irq(ts_dev->irq, titsc_irq,
0, pdev->dev.driver->name, ts_dev);
}
titsc_writel(ts_dev, REG_IRQENABLE, IRQENB_FIFO0THRES);
+ err = titsc_config_wires(ts_dev);
+ if (err) {
+ dev_err(&pdev->dev, "wrong i/p wire configuration\n");
+ goto err_free_irq;
+ }
titsc_step_config(ts_dev);
titsc_writel(ts_dev, REG_FIFO0THR, ts_dev->steps_to_configure);
/* register to the input system */
err = input_register_device(input_dev);
- if (err)
+ if (err) {
+ dev_err(&pdev->dev, "Failed to register input device\n");
goto err_free_irq;
+ }
platform_set_drvdata(pdev, ts_dev);
+
+ dev_info(&pdev->dev, "Initialized OK\n");
+
return 0;
err_free_irq:
0x00);
titsc_writel(ts_dev, REG_IRQCLR, IRQENB_HW_PEN);
}
+ titsc_config_wires(ts_dev);
titsc_step_config(ts_dev);
titsc_writel(ts_dev, REG_FIFO0THR,
ts_dev->steps_to_configure);
index 4647b50b249ca2a0ab8abbbf5f58adff70ed037b..4c867f47b53c2d97069811bdf57e13d2e647850c 100644 (file)
if (!table)
goto out;
+ /* Initialize table spin-lock */
+ spin_lock_init(&table->lock);
+
if (ioapic)
/* Keep the first 32 indexes free for IOAPIC interrupts */
table->min_index = 32;
diff --git a/drivers/md/md.c b/drivers/md/md.c
index f363135144f62fe4ea9cdb4abf4ad5b6bdcf80cf..0411bdef94a27cdf7a55689db340dd7faaf8afa2 100644 (file)
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -1564,8 +1564,8 @@ static int super_1_load(struct md_rdev *rdev, struct md_rdev *refdev, int minor_
sector, count, 1) == 0)
return -EINVAL;
}
- } else if (sb->bblog_offset == 0)
- rdev->badblocks.shift = -1;
+ } else if (sb->bblog_offset != 0)
+ rdev->badblocks.shift = 0;
if (!refdev) {
ret = 1;
* be used - I wonder if that matters
*/
rdev->badblocks.count = 0;
- rdev->badblocks.shift = 0;
+ rdev->badblocks.shift = -1; /* disabled until explicitly enabled */
rdev->badblocks.page = kmalloc(PAGE_SIZE, GFP_KERNEL);
seqlock_init(&rdev->badblocks.lock);
if (rdev->badblocks.page == NULL)
@@ -3293,9 +3293,6 @@ static struct md_rdev *md_import_device(dev_t newdev, int super_format, int supe
goto abort_free;
}
}
- if (super_format == -1)
- /* hot-add for 0.90, or non-persistent: so no badblocks */
- rdev->badblocks.shift = -1;
return rdev;
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index 75b1f898792cd2377bf3268801389d63d0ae5411..6af167f810900507184f291738647b45b890d1e3 100644 (file)
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
while (bio) { /* submit pending writes */
struct bio *next = bio->bi_next;
bio->bi_next = NULL;
- generic_make_request(bio);
+ if (unlikely((bio->bi_rw & REQ_DISCARD) &&
+ !blk_queue_discard(bdev_get_queue(bio->bi_bdev))))
+ /* Just ignore it */
+ bio_endio(bio, 0);
+ else
+ generic_make_request(bio);
bio = next;
}
kfree(plug);
const unsigned long do_flush_fua = (bio->bi_rw & (REQ_FLUSH | REQ_FUA));
const unsigned long do_discard = (bio->bi_rw
& (REQ_DISCARD | REQ_SECURE));
+ const unsigned long do_same = (bio->bi_rw & REQ_WRITE_SAME);
struct md_rdev *blocked_rdev;
struct blk_plug_cb *cb;
struct raid1_plug_cb *plug = NULL;
conf->mirrors[i].rdev->data_offset);
mbio->bi_bdev = conf->mirrors[i].rdev->bdev;
mbio->bi_end_io = raid1_end_write_request;
- mbio->bi_rw = WRITE | do_flush_fua | do_sync | do_discard;
+ mbio->bi_rw =
+ WRITE | do_flush_fua | do_sync | do_discard | do_same;
mbio->bi_private = r1_bio;
atomic_inc(&r1_bio->remaining);
if (IS_ERR(conf))
return PTR_ERR(conf);
+ if (mddev->queue)
+ blk_queue_max_write_same_sectors(mddev->queue,
+ mddev->chunk_sectors);
rdev_for_each(rdev, mddev) {
if (!mddev->gendisk)
continue;
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 8d925dc7882805b81631c1c5ee76bc869e6445b9..61ab219e2d392841579f4ebd6b444c4887200f8f 100644 (file)
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
while (bio) { /* submit pending writes */
struct bio *next = bio->bi_next;
bio->bi_next = NULL;
- generic_make_request(bio);
+ if (unlikely((bio->bi_rw & REQ_DISCARD) &&
+ !blk_queue_discard(bdev_get_queue(bio->bi_bdev))))
+ /* Just ignore it */
+ bio_endio(bio, 0);
+ else
+ generic_make_request(bio);
bio = next;
}
kfree(plug);
const unsigned long do_fua = (bio->bi_rw & REQ_FUA);
const unsigned long do_discard = (bio->bi_rw
& (REQ_DISCARD | REQ_SECURE));
+ const unsigned long do_same = (bio->bi_rw & REQ_WRITE_SAME);
unsigned long flags;
struct md_rdev *blocked_rdev;
struct blk_plug_cb *cb;
rdev));
mbio->bi_bdev = rdev->bdev;
mbio->bi_end_io = raid10_end_write_request;
- mbio->bi_rw = WRITE | do_sync | do_fua | do_discard;
+ mbio->bi_rw =
+ WRITE | do_sync | do_fua | do_discard | do_same;
mbio->bi_private = r10_bio;
atomic_inc(&r10_bio->remaining);
r10_bio, rdev));
mbio->bi_bdev = rdev->bdev;
mbio->bi_end_io = raid10_end_write_request;
- mbio->bi_rw = WRITE | do_sync | do_fua | do_discard;
+ mbio->bi_rw =
+ WRITE | do_sync | do_fua | do_discard | do_same;
mbio->bi_private = r10_bio;
atomic_inc(&r10_bio->remaining);
if (mddev->queue) {
blk_queue_max_discard_sectors(mddev->queue,
mddev->chunk_sectors);
+ blk_queue_max_write_same_sectors(mddev->queue,
+ mddev->chunk_sectors);
blk_queue_io_min(mddev->queue, chunk_size);
if (conf->geo.raid_disks % conf->geo.near_copies)
blk_queue_io_opt(mddev->queue, chunk_size * conf->geo.raid_disks);
diff --git a/drivers/mfd/adp5520.c b/drivers/mfd/adp5520.c
index 210dd038bb5a464f36b9c234f4087c42271deebe..6b40e0cde9658a07ed99c5d9ac19fc7ab82da859 100644 (file)
--- a/drivers/mfd/adp5520.c
+++ b/drivers/mfd/adp5520.c
struct blocking_notifier_head notifier_list;
int irq;
unsigned long id;
+ uint8_t mode;
};
static int __adp5520_read(struct i2c_client *client,
struct i2c_client *client = to_i2c_client(dev);
struct adp5520_chip *chip = dev_get_drvdata(&client->dev);
- adp5520_clr_bits(chip->dev, ADP5520_MODE_STATUS, ADP5520_nSTNBY);
+ adp5520_read(chip->dev, ADP5520_MODE_STATUS, &chip->mode);
+ /* All other bits are W1C */
+ chip->mode &= ADP5520_BL_EN | ADP5520_DIM_EN | ADP5520_nSTNBY;
+ adp5520_write(chip->dev, ADP5520_MODE_STATUS, 0);
return 0;
}
struct i2c_client *client = to_i2c_client(dev);
struct adp5520_chip *chip = dev_get_drvdata(&client->dev);
- adp5520_set_bits(chip->dev, ADP5520_MODE_STATUS, ADP5520_nSTNBY);
+ adp5520_write(chip->dev, ADP5520_MODE_STATUS, chip->mode);
return 0;
}
#endif
diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c
index b077bedda03ef18d211c6d30446ac6fc1679d61d..ddaad028d5ef84bddb1fba9cabfe21b44342736f 100644 (file)
--- a/drivers/mfd/palmas.c
+++ b/drivers/mfd/palmas.c
PALMAS_USB_ID,
};
+static struct resource palmas_rtc_resources[] = {
+ {
+ .start = PALMAS_RTC_ALARM_IRQ,
+ .end = PALMAS_RTC_ALARM_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
static const struct mfd_cell palmas_children[] = {
{
.name = "palmas-pmic",
{
.name = "palmas-rtc",
.id = PALMAS_RTC_ID,
+ .resources = &palmas_rtc_resources[0],
+ .num_resources = ARRAY_SIZE(palmas_rtc_resources),
},
{
.name = "palmas-pwrbutton",
}
};
+static const struct mfd_cell tps659038_children[] = {
+ {
+ .name = "tps659038-pmic",
+ .id = PALMAS_PMIC_ID,
+ },
+ {
+ .name = "tps659038-gpio",
+ .id = PALMAS_GPIO_ID,
+ },
+ {
+ .name = "tps659038-leds",
+ .id = PALMAS_LEDS_ID,
+ },
+ {
+ .name = "tps659038-wdt",
+ .id = PALMAS_WDT_ID,
+ },
+ {
+ .name = "tps659038-rtc",
+ .id = PALMAS_RTC_ID,
+ },
+ {
+ .name = "tps659038-pwrbutton",
+ .id = PALMAS_PWRBUTTON_ID,
+ },
+ {
+ .name = "tps659038-gpadc",
+ .id = PALMAS_GPADC_ID,
+ },
+ {
+ .name = "tps659038-resource",
+ .id = PALMAS_RESOURCE_ID,
+ },
+ {
+ .name = "tps659038-clk",
+ .id = PALMAS_CLK_ID,
+ },
+ {
+ .name = "tps659038-pwm",
+ .id = PALMAS_PWM_ID,
+ }
+};
+
static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
{
.reg_bits = 8,
return ret;
}
+static struct palmas_pmic_data palmas_data = {
+ .irq_chip = &palmas_irq_chip,
+ .regmap_config = palmas_regmap_config,
+ .mfd_cell = palmas_children,
+ .id = TWL6035,
+ .has_usb = 1,
+};
+
+static struct palmas_pmic_data tps659038_data = {
+ .irq_chip = &palmas_irq_chip,
+ .regmap_config = palmas_regmap_config,
+ .mfd_cell = tps659038_children,
+ .id = TPS659038,
+ .has_usb = 0,
+};
+
+static const struct of_device_id of_palmas_match_tbl[] = {
+ {
+ .compatible = "ti,palmas",
+ .data = &palmas_data,
+ },
+ {
+ .compatible = "ti,tps659038",
+ .data = &tps659038_data,
+ },
+ { },
+};
+
static int palmas_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
unsigned int reg, addr;
int slave;
struct mfd_cell *children;
+ const struct of_device_id *match;
+ const struct palmas_pmic_data *pmic_data;
pdata = dev_get_platdata(&i2c->dev);
i2c_set_clientdata(i2c, palmas);
palmas->dev = &i2c->dev;
- palmas->id = id->driver_data;
+ palmas->palmas_id = id->driver_data;
palmas->irq = i2c->irq;
+ match = of_match_device(of_match_ptr(of_palmas_match_tbl), &i2c->dev);
+
+ if (match) {
+ pmic_data = match->data;
+ palmas->palmas_id = pmic_data->id;
+ } else {
+ return -ENODATA;
+ }
+
for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
if (i == 0)
palmas->i2c_clients[i] = i2c;
}
}
palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
- &palmas_regmap_config[i]);
+ pmic_data->regmap_config + i);
if (IS_ERR(palmas->regmap[i])) {
ret = PTR_ERR(palmas->regmap[i]);
dev_err(palmas->dev,
}
}
- /* Change IRQ into clear on read mode for efficiency */
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
- reg = PALMAS_INT_CTRL_INT_CLEAR;
+ /* Avoid irq requesting for TOS659038 as the IRQ line
+ is only connected to a test point */
+ if (palmas->palmas_id != TPS659038) {
+ /* Change IRQ into clear on read mode for efficiency */
+ slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
+ addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
+ PALMAS_INT_CTRL);
+ reg = PALMAS_INT_CTRL_INT_CLEAR;
- regmap_write(palmas->regmap[slave], addr, reg);
+ regmap_write(palmas->regmap[slave], addr, reg);
- ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
- IRQF_ONESHOT, 0, &palmas_irq_chip,
- &palmas->irq_data);
- if (ret < 0)
- goto err;
+ ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
+ IRQF_ONESHOT, 0, pmic_data->irq_chip,
+ &palmas->irq_data);
+ if (ret < 0)
+ goto err;
+ }
slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
return ret;
}
+ /*
+ * For now all PMICs belonging to palmas family are assumed to get the
+ * same childern as PALMAS
+ */
children = kmemdup(palmas_children, sizeof(palmas_children),
GFP_KERNEL);
if (!children) {
children[PALMAS_RESOURCE_ID].pdata_size =
sizeof(*pdata->resource_pdata);
- children[PALMAS_USB_ID].platform_data = pdata->usb_pdata;
- children[PALMAS_USB_ID].pdata_size = sizeof(*pdata->usb_pdata);
+ /* TPS659038 does not have USB */
+ if (pmic_data->has_usb) {
+ children[PALMAS_USB_ID].platform_data = pdata->usb_pdata;
+ children[PALMAS_USB_ID].pdata_size = sizeof(*pdata->usb_pdata);
+ }
children[PALMAS_CLK_ID].platform_data = pdata->clk_pdata;
children[PALMAS_CLK_ID].pdata_size = sizeof(*pdata->clk_pdata);
ret = mfd_add_devices(palmas->dev, -1,
children, ARRAY_SIZE(palmas_children),
- NULL, regmap_irq_chip_get_base(palmas->irq_data),
- NULL);
+ NULL, 0,
+ regmap_irq_get_domain(palmas->irq_data));
kfree(children);
}
static const struct i2c_device_id palmas_i2c_id[] = {
- { "palmas", },
- { "twl6035", },
- { "twl6037", },
- { "tps65913", },
+ { "palmas", TWL6035},
+ { "twl6035", TWL6035},
+ { "twl6037", TWL6037},
+ { "tps65913", TPS65913},
+ { "tps659038", TPS659038},
{ /* end */ }
};
MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
-static struct of_device_id of_palmas_match_tbl[] = {
- { .compatible = "ti,palmas", },
- { /* end */ }
-};
-
static struct i2c_driver palmas_i2c_driver = {
.driver = {
.name = "palmas",
index e9f3fb510b44f965795bc87f56c26bffeefe2078..e28a31d56ce8f985f3cb4532e93617cfbe38460e 100644 (file)
#include <linux/regmap.h>
#include <linux/mfd/core.h>
#include <linux/pm_runtime.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/mfd/ti_am335x_tscadc.h>
#include <linux/input/ti_am335x_tsc.h>
{
unsigned int val;
+ val = (unsigned int)-1;
regmap_read(tsadc->regmap_tscadc, reg, &val);
return val;
}
struct resource *res;
struct clk *clk;
struct mfd_tscadc_board *pdata = pdev->dev.platform_data;
+ struct device_node *node = pdev->dev.of_node;
struct mfd_cell *cell;
int err, ctrl;
int clk_value, clock_rate;
- int tsc_wires, adc_channels = 0, total_channels;
+ int tsc_wires = 0, adc_channels = 0, total_channels;
- if (!pdata) {
+ if (!pdata && !pdev->dev.of_node) {
dev_err(&pdev->dev, "Could not find platform data\n");
return -EINVAL;
}
- if (pdata->adc_init)
- adc_channels = pdata->adc_init->adc_channels;
+ if (pdev->dev.platform_data) {
+ if (pdata->tsc_init)
+ tsc_wires = pdata->tsc_init->wires;
+
+ if (pdata->adc_init)
+ adc_channels = pdata->adc_init->adc_channels;
+ } else {
+ node = of_get_child_by_name(pdev->dev.of_node, "tsc");
+ of_property_read_u32(node, "ti,wires", &tsc_wires);
+
+ node = of_get_child_by_name(pdev->dev.of_node, "adc");
+ of_property_read_u32(node, "ti,adc-channels", &adc_channels);
+ }
- tsc_wires = pdata->tsc_init->wires;
total_channels = tsc_wires + adc_channels;
if (total_channels > 8) {
ctrl |= CNTRLREG_TSCSSENB;
tscadc_writel(tscadc, REG_CTRL, ctrl);
+ tscadc->used_cells = 0;
+ tscadc->tsc_cell = -1;
+ tscadc->adc_cell = -1;
+
/* TSC Cell */
- cell = &tscadc->cells[TSC_CELL];
- cell->name = "tsc";
- cell->platform_data = tscadc;
- cell->pdata_size = sizeof(*tscadc);
+ if (tsc_wires > 0) {
+ tscadc->tsc_cell = tscadc->used_cells;
+ cell = &tscadc->cells[tscadc->used_cells++];
+ cell->name = "tsc";
+ cell->platform_data = tscadc;
+ cell->pdata_size = sizeof(*tscadc);
+ }
/* ADC Cell */
- cell = &tscadc->cells[ADC_CELL];
- cell->name = "tiadc";
- cell->platform_data = tscadc;
- cell->pdata_size = sizeof(*tscadc);
+ if (adc_channels > 0) {
+ tscadc->adc_cell = tscadc->used_cells;
+ cell = &tscadc->cells[tscadc->used_cells++];
+ cell->name = "tiadc";
+ cell->platform_data = tscadc;
+ cell->pdata_size = sizeof(*tscadc);
+ }
err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
- TSCADC_CELLS, NULL, 0, NULL);
+ tscadc->used_cells, NULL, 0, NULL);
if (err < 0)
goto err_disable_clk;
device_init_wakeup(&pdev->dev, true);
platform_set_drvdata(pdev, tscadc);
+ dev_info(&pdev->dev, "Initialized OK.\n");
+
return 0;
err_disable_clk:
#define TSCADC_PM_OPS NULL
#endif
+static const struct of_device_id ti_tscadc_dt_ids[] = {
+ { .compatible = "ti,ti-tscadc", },
+ { }
+};
+
static struct platform_driver ti_tscadc_driver = {
.driver = {
.name = "ti_tscadc",
.owner = THIS_MODULE,
.pm = TSCADC_PM_OPS,
+ .of_match_table = of_match_ptr(ti_tscadc_dt_ids),
},
.probe = ti_tscadc_probe,
.remove = ti_tscadc_remove,
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 089e8ea34812516612000faab9ec79d530cf8f51..2743b7d3309d54f4b13245a1fe17cf7c948d5a70 100644 (file)
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT];
card->ext_csd.raw_trim_mult =
ext_csd[EXT_CSD_TRIM_MULT];
+ card->ext_csd.raw_partition_support = ext_csd[EXT_CSD_PARTITION_SUPPORT];
if (card->ext_csd.rev >= 4) {
/*
* Enhanced area feature support -- check whether the eMMC
* card has the Enhanced area enabled. If so, export enhanced
* area offset and size to user by adding sysfs interface.
*/
- card->ext_csd.raw_partition_support = ext_csd[EXT_CSD_PARTITION_SUPPORT];
if ((ext_csd[EXT_CSD_PARTITION_SUPPORT] & 0x2) &&
(ext_csd[EXT_CSD_PARTITION_ATTRIBUTE] & 0x1)) {
hc_erase_grp_sz =
index 8d13c6594520094c82f054628b1086bfe5cc7bec..009dabded17916788e5e75a4d15132c3f23c96dd 100644 (file)
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
If unsure, say N.
-config MMC_ATMELMCI_DMA
- bool "Atmel MCI DMA support"
- depends on MMC_ATMELMCI && (AVR32 || ARCH_AT91SAM9G45) && DMA_ENGINE
- help
- Say Y here to have the Atmel MCI driver use a DMA engine to
- do data transfers and thus increase the throughput and
- reduce the CPU utilization.
-
- If unsure, say N.
-
config MMC_MSM
tristate "Qualcomm SDCC Controller Support"
depends on MMC && ARCH_MSM
index 722af1de7967e77d50aee58588052249f356b50d..e75774f72606487573cd3ee1817040b460bd11fb 100644 (file)
void __iomem *regs;
struct scatterlist *sg;
+ unsigned int sg_len;
unsigned int pio_offset;
unsigned int *buffer;
unsigned int buf_size;
data->error = -EINPROGRESS;
host->sg = data->sg;
+ host->sg_len = data->sg_len;
host->data = data;
host->data_chan = NULL;
if (offset == sg->length) {
flush_dcache_page(sg_page(sg));
host->sg = sg = sg_next(sg);
- if (!sg)
+ host->sg_len--;
+ if (!sg || !host->sg_len)
goto done;
offset = 0;
flush_dcache_page(sg_page(sg));
host->sg = sg = sg_next(sg);
- if (!sg)
+ host->sg_len--;
+ if (!sg || !host->sg_len)
goto done;
offset = 4 - remaining;
nbytes += 4;
if (offset == sg->length) {
host->sg = sg = sg_next(sg);
- if (!sg)
+ host->sg_len--;
+ if (!sg || !host->sg_len)
goto done;
offset = 0;
nbytes += remaining;
host->sg = sg = sg_next(sg);
- if (!sg) {
+ host->sg_len--;
+ if (!sg || !host->sg_len) {
atmci_writel(host, ATMCI_TDR, value);
goto done;
}
atmci_readl(host, ATMCI_SR);
clk_disable(host->mck);
-#ifdef CONFIG_MMC_ATMELMCI_DMA
if (host->dma.chan)
dma_release_channel(host->dma.chan);
-#endif
free_irq(platform_get_irq(pdev, 0), host);
iounmap(host->regs);
diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c
index 82c06165d3d27351f3cebf9966b513b6669e96bf..6e3d6dc6a833bfa9f0d75b8f8e93999864f3f92e 100644 (file)
--- a/drivers/mtd/mtdchar.c
+++ b/drivers/mtd/mtdchar.c
struct mtd_file_info *mfi = file->private_data;
struct mtd_info *mtd = mfi->mtd;
struct map_info *map = mtd->priv;
- resource_size_t start, off;
- unsigned long len, vma_len;
/* This is broken because it assumes the MTD device is map-based
and that mtd->priv is a valid struct map_info. It should be
replaced with something that uses the mtd_get_unmapped_area()
operation properly. */
if (0 /*mtd->type == MTD_RAM || mtd->type == MTD_ROM*/) {
- off = get_vm_offset(vma);
- start = map->phys;
- len = PAGE_ALIGN((start & ~PAGE_MASK) + map->size);
- start &= PAGE_MASK;
- vma_len = get_vm_size(vma);
-
- /* Overflow in off+len? */
- if (vma_len + off < off)
- return -EINVAL;
- /* Does it fit in the mapping? */
- if (vma_len + off > len)
- return -EINVAL;
-
- off += start;
- /* Did that overflow? */
- if (off < start)
- return -EINVAL;
- if (set_vm_offset(vma, off) < 0)
- return -EINVAL;
- vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP;
-
#ifdef pgprot_noncached
- if (file->f_flags & O_DSYNC || off >= __pa(high_memory))
+ if (file->f_flags & O_DSYNC || map->phys >= __pa(high_memory))
vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
#endif
- if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
- vma->vm_end - vma->vm_start,
- vma->vm_page_prot))
- return -EAGAIN;
-
- return 0;
+ return vm_iomap_memory(vma, map->phys, map->size);
}
return -ENOSYS;
#else
index 27cdf1f5e604336632617e047ee97eee7704d596..045dc533a4d0601979ab5694b1d36f2b8d740d7b 100644 (file)
write_unlock_bh(&bond->lock);
err_close:
+ slave_dev->priv_flags &= ~IFF_BONDING;
dev_close(slave_dev);
err_unset_master:
*/
static int bond_xmit_hash_policy_l23(struct sk_buff *skb, int count)
{
- struct ethhdr *data = (struct ethhdr *)skb->data;
- struct iphdr *iph;
- struct ipv6hdr *ipv6h;
+ const struct ethhdr *data;
+ const struct iphdr *iph;
+ const struct ipv6hdr *ipv6h;
u32 v6hash;
- __be32 *s, *d;
+ const __be32 *s, *d;
if (skb->protocol == htons(ETH_P_IP) &&
- skb_network_header_len(skb) >= sizeof(*iph)) {
+ pskb_network_may_pull(skb, sizeof(*iph))) {
iph = ip_hdr(skb);
+ data = (struct ethhdr *)skb->data;
return ((ntohl(iph->saddr ^ iph->daddr) & 0xffff) ^
(data->h_dest[5] ^ data->h_source[5])) % count;
} else if (skb->protocol == htons(ETH_P_IPV6) &&
- skb_network_header_len(skb) >= sizeof(*ipv6h)) {
+ pskb_network_may_pull(skb, sizeof(*ipv6h))) {
ipv6h = ipv6_hdr(skb);
+ data = (struct ethhdr *)skb->data;
s = &ipv6h->saddr.s6_addr32[0];
d = &ipv6h->daddr.s6_addr32[0];
v6hash = (s[1] ^ d[1]) ^ (s[2] ^ d[2]) ^ (s[3] ^ d[3]);
static int bond_xmit_hash_policy_l34(struct sk_buff *skb, int count)
{
u32 layer4_xor = 0;
- struct iphdr *iph;
- struct ipv6hdr *ipv6h;
- __be32 *s, *d;
- __be16 *layer4hdr;
+ const struct iphdr *iph;
+ const struct ipv6hdr *ipv6h;
+ const __be32 *s, *d;
+ const __be16 *l4 = NULL;
+ __be16 _l4[2];
+ int noff = skb_network_offset(skb);
+ int poff;
if (skb->protocol == htons(ETH_P_IP) &&
- skb_network_header_len(skb) >= sizeof(*iph)) {
+ pskb_may_pull(skb, noff + sizeof(*iph))) {
iph = ip_hdr(skb);
- if (!ip_is_fragment(iph) &&
- (iph->protocol == IPPROTO_TCP ||
- iph->protocol == IPPROTO_UDP) &&
- (skb_headlen(skb) - skb_network_offset(skb) >=
- iph->ihl * sizeof(u32) + sizeof(*layer4hdr) * 2)) {
- layer4hdr = (__be16 *)((u32 *)iph + iph->ihl);
- layer4_xor = ntohs(*layer4hdr ^ *(layer4hdr + 1));
+ poff = proto_ports_offset(iph->protocol);
+
+ if (!ip_is_fragment(iph) && poff >= 0) {
+ l4 = skb_header_pointer(skb, noff + (iph->ihl << 2) + poff,
+ sizeof(_l4), &_l4);
+ if (l4)
+ layer4_xor = ntohs(l4[0] ^ l4[1]);
}
return (layer4_xor ^
((ntohl(iph->saddr ^ iph->daddr)) & 0xffff)) % count;
} else if (skb->protocol == htons(ETH_P_IPV6) &&
- skb_network_header_len(skb) >= sizeof(*ipv6h)) {
+ pskb_may_pull(skb, noff + sizeof(*ipv6h))) {
ipv6h = ipv6_hdr(skb);
- if ((ipv6h->nexthdr == IPPROTO_TCP ||
- ipv6h->nexthdr == IPPROTO_UDP) &&
- (skb_headlen(skb) - skb_network_offset(skb) >=
- sizeof(*ipv6h) + sizeof(*layer4hdr) * 2)) {
- layer4hdr = (__be16 *)(ipv6h + 1);
- layer4_xor = ntohs(*layer4hdr ^ *(layer4hdr + 1));
+ poff = proto_ports_offset(ipv6h->nexthdr);
+ if (poff >= 0) {
+ l4 = skb_header_pointer(skb, noff + sizeof(*ipv6h) + poff,
+ sizeof(_l4), &_l4);
+ if (l4)
+ layer4_xor = ntohs(l4[0] ^ l4[1]);
}
s = &ipv6h->saddr.s6_addr32[0];
d = &ipv6h->daddr.s6_addr32[0];
static void __net_exit bond_net_exit(struct net *net)
{
struct bond_net *bn = net_generic(net, bond_net_id);
+ struct bonding *bond, *tmp_bond;
+ LIST_HEAD(list);
bond_destroy_sysfs(bn);
bond_destroy_proc_dir(bn);
+
+ /* Kill off any bonds created after unregistering bond rtnl ops */
+ rtnl_lock();
+ list_for_each_entry_safe(bond, tmp_bond, &bn->dev_list, bond_list)
+ unregister_netdevice_queue(bond->dev, &list);
+ unregister_netdevice_many(&list);
+ rtnl_unlock();
}
static struct pernet_operations bond_net_ops = {
index 5eaf47b8e37bc4427a7004b1199da5dee8d7bccc..42b6d6971a64345a11ba9176fb47369eb083d2b9 100644 (file)
struct mcp251x_priv *priv = netdev_priv(net);
struct spi_device *spi = priv->spi;
struct mcp251x_platform_data *pdata = spi->dev.platform_data;
+ unsigned long flags;
int ret;
ret = open_candev(net);
priv->tx_skb = NULL;
priv->tx_len = 0;
+ flags = IRQF_ONESHOT;
+ if (pdata->irq_flags)
+ flags |= pdata->irq_flags;
+ else
+ flags |= IRQF_TRIGGER_FALLING;
+
ret = request_threaded_irq(spi->irq, NULL, mcp251x_can_ist,
- pdata->irq_flags ? pdata->irq_flags : IRQF_TRIGGER_FALLING,
- DEVICE_NAME, priv);
+ flags, DEVICE_NAME, priv);
if (ret) {
dev_err(&spi->dev, "failed to acquire irq %d\n", spi->irq);
if (pdata->transceiver_enable)
diff --git a/drivers/net/can/sja1000/sja1000_of_platform.c b/drivers/net/can/sja1000/sja1000_of_platform.c
index 6433b81256cdafd1cfe35fcc1a37d0a378411f59..8e0c4a0019397f61af74d44da1b60ca0c61032d2 100644 (file)
struct net_device *dev;
struct sja1000_priv *priv;
struct resource res;
- const u32 *prop;
- int err, irq, res_size, prop_size;
+ u32 prop;
+ int err, irq, res_size;
void __iomem *base;
err = of_address_to_resource(np, 0, &res);
priv->read_reg = sja1000_ofp_read_reg;
priv->write_reg = sja1000_ofp_write_reg;
- prop = of_get_property(np, "nxp,external-clock-frequency", &prop_size);
- if (prop && (prop_size == sizeof(u32)))
- priv->can.clock.freq = *prop / 2;
+ err = of_property_read_u32(np, "nxp,external-clock-frequency", &prop);
+ if (!err)
+ priv->can.clock.freq = prop / 2;
else
priv->can.clock.freq = SJA1000_OFP_CAN_CLOCK; /* default */
- prop = of_get_property(np, "nxp,tx-output-mode", &prop_size);
- if (prop && (prop_size == sizeof(u32)))
- priv->ocr |= *prop & OCR_MODE_MASK;
+ err = of_property_read_u32(np, "nxp,tx-output-mode", &prop);
+ if (!err)
+ priv->ocr |= prop & OCR_MODE_MASK;
else
priv->ocr |= OCR_MODE_NORMAL; /* default */
- prop = of_get_property(np, "nxp,tx-output-config", &prop_size);
- if (prop && (prop_size == sizeof(u32)))
- priv->ocr |= (*prop << OCR_TX_SHIFT) & OCR_TX_MASK;
+ err = of_property_read_u32(np, "nxp,tx-output-config", &prop);
+ if (!err)
+ priv->ocr |= (prop << OCR_TX_SHIFT) & OCR_TX_MASK;
else
priv->ocr |= OCR_TX0_PULLDOWN; /* default */
- prop = of_get_property(np, "nxp,clock-out-frequency", &prop_size);
- if (prop && (prop_size == sizeof(u32)) && *prop) {
- u32 divider = priv->can.clock.freq * 2 / *prop;
+ err = of_property_read_u32(np, "nxp,clock-out-frequency", &prop);
+ if (!err && prop) {
+ u32 divider = priv->can.clock.freq * 2 / prop;
if (divider > 1)
priv->cdr |= divider / 2 - 1;
priv->cdr |= CDR_CLK_OFF; /* default */
}
- prop = of_get_property(np, "nxp,no-comparator-bypass", NULL);
- if (!prop)
+ if (!of_property_read_bool(np, "nxp,no-comparator-bypass"))
priv->cdr |= CDR_CBP; /* default */
priv->irq_flags = IRQF_SHARED;
diff --git a/drivers/net/ethernet/atheros/atl1e/atl1e.h b/drivers/net/ethernet/atheros/atl1e/atl1e.h
index edfdf6b950e73ad82f8c1e3749a973c113237bb7..b5fd934585e9f9f14595f60a2ec2e069cd2bed35 100644 (file)
/* how about 0x2000 */
#define MAX_TX_BUF_LEN 0x2000
#define MAX_TX_BUF_SHIFT 13
-/*#define MAX_TX_BUF_LEN 0x3000 */
+#define MAX_TSO_SEG_SIZE 0x3c00
/* rrs word 1 bit 0:31 */
#define RRS_RX_CSUM_MASK 0xFFFF
diff --git a/drivers/net/ethernet/atheros/atl1e/atl1e_main.c b/drivers/net/ethernet/atheros/atl1e/atl1e_main.c
index 35faab799637e7160ba0a0c9a65abce644651e66..ca33b28ad47254ec9df56822658b3dde60fb8a3f 100644 (file)
INIT_WORK(&adapter->reset_task, atl1e_reset_task);
INIT_WORK(&adapter->link_chg_task, atl1e_link_chg_task);
+ netif_set_gso_max_size(netdev, MAX_TSO_SEG_SIZE);
err = register_netdev(netdev);
if (err) {
netdev_err(netdev, "register netdevice failed\n");
index 8a5253c1d764040cb169dd1789c1a2f028fbb5dd..6917998ba0ec4748cf3bd0dee2754f62ad16ee33 100644 (file)
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
{PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
+ {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
{PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
{PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
}
if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_57765_AX) {
- u32 grc_mode = tr32(GRC_MODE);
+ u32 grc_mode;
+
+ /* Fix transmit hangs */
+ val = tr32(TG3_CPMU_PADRNG_CTL);
+ val |= TG3_CPMU_PADRNG_CTL_RDIV2;
+ tw32(TG3_CPMU_PADRNG_CTL, val);
+
+ grc_mode = tr32(GRC_MODE);
/* Access the lower 1K of DL PCIE block registers. */
val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
if (tg3_flag(tp, PCI_EXPRESS))
rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766) {
+ tp->dma_limit = 0;
+ if (tp->dev->mtu <= ETH_DATA_LEN) {
+ rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
+ tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
+ }
+ }
+
if (tg3_flag(tp, HW_TSO_1) ||
tg3_flag(tp, HW_TSO_2) ||
tg3_flag(tp, HW_TSO_3))
index d330e81f5793ad47e8f6257d3e08c728719c9651..6f9b74ce377e4270a801c6a1513efab9a3065a53 100644 (file)
#define CPMU_MUTEX_GNT_DRIVER 0x00001000
#define TG3_CPMU_PHY_STRAP 0x00003664
#define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
+#define TG3_CPMU_PADRNG_CTL 0x00003668
+#define TG3_CPMU_PADRNG_CTL_RDIV2 0x00040000
/* 0x3664 --> 0x36b0 unused */
#define TG3_CPMU_EEE_MODE 0x000036b0
diff --git a/drivers/net/ethernet/freescale/gianfar_ptp.c b/drivers/net/ethernet/freescale/gianfar_ptp.c
index 2e5daee0438a55891072595400d643bd8ad1340b..a3f8a2551f2dc0f86a06356be9c9e2cc16d7f71e 100644 (file)
#define DRIVER "gianfar_ptp"
#define DEFAULT_CKSEL 1
-#define N_ALARM 1 /* first alarm is used internally to reset fipers */
#define N_EXT_TS 2
#define REG_SIZE sizeof(struct gianfar_ptp_registers)
.owner = THIS_MODULE,
.name = "gianfar clock",
.max_adj = 512000,
- .n_alarm = N_ALARM,
+ .n_alarm = 0,
.n_ext_ts = N_EXT_TS,
.n_per_out = 0,
.pps = 1,
index f2fdbb79837eafcc7baf00d070efb48251bd1f7a..82c63ac9b9ec288aa4c34d38e19b83ccf6d3def3 100644 (file)
static int ibmveth_probe(struct vio_dev *dev, const struct vio_device_id *id)
{
- int rc, i;
+ int rc, i, mac_len;
struct net_device *netdev;
struct ibmveth_adapter *adapter;
unsigned char *mac_addr_p;
@@ -1336,11 +1336,19 @@ static int ibmveth_probe(struct vio_dev *dev, const struct vio_device_id *id)
dev->unit_address);
mac_addr_p = (unsigned char *)vio_get_attribute(dev, VETH_MAC_ADDR,
- NULL);
+ &mac_len);
if (!mac_addr_p) {
dev_err(&dev->dev, "Can't find VETH_MAC_ADDR attribute\n");
return -EINVAL;
}
+ /* Workaround for old/broken pHyp */
+ if (mac_len == 8)
+ mac_addr_p += 2;
+ else if (mac_len != 6) {
+ dev_err(&dev->dev, "VETH_MAC_ADDR attribute wrong len %d\n",
+ mac_len);
+ return -EINVAL;
+ }
mcastFilterSize_p = (unsigned int *)vio_get_attribute(dev,
VETH_MCAST_FILTER_SIZE, NULL);
@@ -1365,17 +1373,6 @@ static int ibmveth_probe(struct vio_dev *dev, const struct vio_device_id *id)
netif_napi_add(netdev, &adapter->napi, ibmveth_poll, 16);
- /*
- * Some older boxes running PHYP non-natively have an OF that returns
- * a 8-byte local-mac-address field (and the first 2 bytes have to be
- * ignored) while newer boxes' OF return a 6-byte field. Note that
- * IEEE 1275 specifies that local-mac-address must be a 6-byte field.
- * The RPA doc specifies that the first byte must be 10b, so we'll
- * just look for it to solve this 8 vs. 6 byte field issue
- */
- if ((*mac_addr_p & 0x3) != 0x02)
- mac_addr_p += 2;
-
adapter->mac_addr = 0;
memcpy(&adapter->mac_addr, mac_addr_p, 6);
diff --git a/drivers/net/ethernet/intel/e1000e/ethtool.c b/drivers/net/ethernet/intel/e1000e/ethtool.c
index fd4772a2691c510fb83e5e2c9b9211c55f116465..522fb102e2b1d5ece7b7b6ae41ceb0c74418298f 100644 (file)
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/vmalloc.h>
+#include <linux/pm_runtime.h>
#include "e1000.h"
}
}
+static int e1000e_ethtool_begin(struct net_device *netdev)
+{
+ return pm_runtime_get_sync(netdev->dev.parent);
+}
+
+static void e1000e_ethtool_complete(struct net_device *netdev)
+{
+ pm_runtime_put_sync(netdev->dev.parent);
+}
+
static const struct ethtool_ops e1000_ethtool_ops = {
+ .begin = e1000e_ethtool_begin,
+ .complete = e1000e_ethtool_complete,
.get_settings = e1000_get_settings,
.set_settings = e1000_set_settings,
.get_drvinfo = e1000_get_drvinfo,
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index 1f93880e3f436bf2ccab0324e60e9ce5dc5cf74f..8692ecac536f824d72e22c5cdbf5de5c1f96d284 100644 (file)
netif_start_queue(netdev);
adapter->idle_check = true;
+ hw->mac.get_link_status = true;
pm_runtime_put(&pdev->dev);
/* fire a link status change interrupt to start the watchdog */
(adapter->hw.phy.media_type == e1000_media_type_copper)) {
int ret_val;
+ pm_runtime_get_sync(&adapter->pdev->dev);
ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
if (ret_val)
e_warn("Error reading PHY register\n");
+ pm_runtime_put_sync(&adapter->pdev->dev);
} else {
/* Do not read PHY registers if link is not up
* Set values to typical power-on defaults
return retval;
}
-static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
- bool runtime)
+static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
{
struct net_device *netdev = pci_get_drvdata(pdev);
struct e1000_adapter *adapter = netdev_priv(netdev);
}
e1000e_reset_interrupt_capability(adapter);
- retval = pci_save_state(pdev);
- if (retval)
- return retval;
-
status = er32(STATUS);
if (status & E1000_STATUS_LU)
wufc &= ~E1000_WUFC_LNKC;
ew32(WUFC, 0);
}
- *enable_wake = !!wufc;
-
- /* make sure adapter isn't asleep if manageability is enabled */
- if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
- (hw->mac.ops.check_mng_mode(hw)))
- *enable_wake = true;
-
if (adapter->hw.phy.type == e1000_phy_igp_3)
e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
pci_clear_master(pdev);
- return 0;
-}
-
-static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
-{
- if (sleep && wake) {
- pci_prepare_to_sleep(pdev);
- return;
- }
-
- pci_wake_from_d3(pdev, wake);
- pci_set_power_state(pdev, PCI_D3hot);
-}
-
-static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
- bool wake)
-{
- struct net_device *netdev = pci_get_drvdata(pdev);
- struct e1000_adapter *adapter = netdev_priv(netdev);
-
/* The pci-e switch on some quad port adapters will report a
* correctable error when the MAC transitions from D0 to D3. To
* prevent this we need to mask off the correctable errors on the
pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
(devctl & ~PCI_EXP_DEVCTL_CERE));
- e1000_power_off(pdev, sleep, wake);
+ pci_save_state(pdev);
+ pci_prepare_to_sleep(pdev);
pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
- } else {
- e1000_power_off(pdev, sleep, wake);
}
+
+ return 0;
}
#ifdef CONFIG_PCIEASPM
if (aspm_disable_flag)
e1000e_disable_aspm(pdev, aspm_disable_flag);
- pci_set_power_state(pdev, PCI_D0);
- pci_restore_state(pdev);
- pci_save_state(pdev);
+ pci_set_master(pdev);
e1000e_set_interrupt_capability(adapter);
if (netif_running(netdev)) {
static int e1000_suspend(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
- int retval;
- bool wake;
-
- retval = __e1000_shutdown(pdev, &wake, false);
- if (!retval)
- e1000_complete_shutdown(pdev, true, wake);
- return retval;
+ return __e1000_shutdown(pdev, false);
}
static int e1000_resume(struct device *dev)
struct net_device *netdev = pci_get_drvdata(pdev);
struct e1000_adapter *adapter = netdev_priv(netdev);
- if (e1000e_pm_ready(adapter)) {
- bool wake;
-
- __e1000_shutdown(pdev, &wake, true);
- }
+ if (!e1000e_pm_ready(adapter))
+ return 0;
- return 0;
+ return __e1000_shutdown(pdev, true);
}
static int e1000_idle(struct device *dev)
static void e1000_shutdown(struct pci_dev *pdev)
{
- bool wake = false;
-
- __e1000_shutdown(pdev, &wake, false);
-
- if (system_state == SYSTEM_POWER_OFF)
- e1000_complete_shutdown(pdev, false, wake);
+ __e1000_shutdown(pdev, false);
}
#ifdef CONFIG_NET_POLL_CONTROLLER
"Cannot re-enable PCI device after reset.\n");
result = PCI_ERS_RESULT_DISCONNECT;
} else {
- pci_set_master(pdev);
pdev->state_saved = true;
pci_restore_state(pdev);
+ pci_set_master(pdev);
pci_enable_wake(pdev, PCI_D3hot, 0);
pci_enable_wake(pdev, PCI_D3cold, 0);
@@ -6341,7 +6297,11 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
/* initialize the wol settings based on the eeprom settings */
adapter->wol = adapter->eeprom_wol;
- device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
+
+ /* make sure adapter isn't asleep if manageability is enabled */
+ if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
+ (hw->mac.ops.check_mng_mode(hw)))
+ device_wakeup_enable(&pdev->dev);
/* save off EEPROM version number */
e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 0d03d387c3324a1dff48798da92243371d5bf40f..911956e5328112378de27852747b66744e05cfc1 100644 (file)
* with the write to EICR.
*/
eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
+
+ /* The lower 16bits of the EICR register are for the queue interrupts
+ * which should be masked here in order to not accidently clear them if
+ * the bits are high when ixgbe_msix_other is called. There is a race
+ * condition otherwise which results in possible performance loss
+ * especially if the ixgbe_msix_other interrupt is triggering
+ * consistently (as it would when PPS is turned on for the X540 device)
+ */
+ eicr &= 0xFFFF0000;
+
IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
if (eicr & IXGBE_EICR_LSC)
index edfba9370922f54632f96440d394772a9da9054b..434e33c527df102adf5052854bc92d816588b4ba 100644 (file)
config MVMDIO
tristate "Marvell MDIO interface support"
+ select PHYLIB
---help---
This driver supports the MDIO interface found in the network
interface units of the Marvell EBU SoCs (Kirkwood, Orion5x,
config MVNETA
tristate "Marvell Armada 370/XP network interface support"
depends on MACH_ARMADA_370_XP
- select PHYLIB
select MVMDIO
---help---
This driver supports the network interface units in the
index b6025c305e1086e5a45beeac14cf10a93b41c0fe..84b312ead2655ea10d994530b06c978677e90b1e 100644 (file)
static int txq_number = 8;
static int rxq_def;
-static int txq_def;
#define MVNETA_DRIVER_NAME "mvneta"
#define MVNETA_DRIVER_VERSION "1.0"
static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
{
struct mvneta_port *pp = netdev_priv(dev);
- struct mvneta_tx_queue *txq = &pp->txqs[txq_def];
+ u16 txq_id = skb_get_queue_mapping(skb);
+ struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
struct mvneta_tx_desc *tx_desc;
struct netdev_queue *nq;
int frags = 0;
goto out;
frags = skb_shinfo(skb)->nr_frags + 1;
- nq = netdev_get_tx_queue(dev, txq_def);
+ nq = netdev_get_tx_queue(dev, txq_id);
/* Get a descriptor for the first part of the packet */
tx_desc = mvneta_txq_next_desc_get(txq);
return -EINVAL;
}
- dev = alloc_etherdev_mq(sizeof(struct mvneta_port), 8);
+ dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
if (!dev)
return -ENOMEM;
module_param(txq_number, int, S_IRUGO);
module_param(rxq_def, int, S_IRUGO);
-module_param(txq_def, int, S_IRUGO);
index 2d849da4c5666466f0994c1168edb60296f0b807..2d56d7160a2385c1bf235a4fde9d6123a4b12479 100644 (file)
goto err_stop_0;
}
+ /* 8168evl does not automatically pad to minimum length. */
+ if (unlikely(tp->mac_version == RTL_GIGA_MAC_VER_34 &&
+ skb->len < ETH_ZLEN)) {
+ if (skb_padto(skb, ETH_ZLEN))
+ goto err_update_stats;
+ skb_put(skb, ETH_ZLEN - skb->len);
+ }
+
if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
goto err_stop_0;
rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
err_dma_0:
dev_kfree_skb(skb);
+err_update_stats:
dev->stats.tx_dropped++;
return NETDEV_TX_OK;
index 16c842997291483eb12306d9ccf0a638772f18f0..6bd91676d2cbb9a46b43108ae1fa994d4fca84f9 100644 (file)
@@ -134,7 +134,7 @@ static struct sk_buff *cdc_mbim_tx_fixup(struct usbnet *dev, struct sk_buff *skb
goto error;
if (skb) {
- if (skb->len <= sizeof(ETH_HLEN))
+ if (skb->len <= ETH_HLEN)
goto error;
/* mapping VLANs to MBIM sessions:
diff --git a/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar9580_1p0_initvals.h
index 28fd99203f6447e4d3545b0fd12b920733ffc10c..bdee2ed67219b6e1c56a0f03a6a28391ba3283aa 100644 (file)
{0x00008258, 0x00000000},
{0x0000825c, 0x40000000},
{0x00008260, 0x00080922},
- {0x00008264, 0x9bc00010},
+ {0x00008264, 0x9d400010},
{0x00008268, 0xffffffff},
{0x0000826c, 0x0000ffff},
{0x00008270, 0x00000000},
diff --git a/drivers/net/wireless/ath/ath9k/htc_drv_init.c b/drivers/net/wireless/ath/ath9k/htc_drv_init.c
index e5d7958ab9485a617c60f520d2981b38b50cb7eb..2a99733db849540152a85094dff7100fd8f6434b 100644 (file)
* required version.
*/
if (priv->fw_version_major != MAJOR_VERSION_REQ ||
- priv->fw_version_minor != MINOR_VERSION_REQ) {
+ priv->fw_version_minor < MINOR_VERSION_REQ) {
dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
return -EINVAL;
index e8486c1e091af2f2db2a23827dc612315398751b..b70f220bc4b378e626a59752fca5bce965456340 100644 (file)
#endif
#ifdef CONFIG_B43_SSB
case B43_BUS_SSB:
- /* FIXME */
+ ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
+ avoid);
break;
#endif
}
diff --git a/drivers/net/wireless/iwlwifi/dvm/debugfs.c b/drivers/net/wireless/iwlwifi/dvm/debugfs.c
index 20806cae11b72a50eee5525e3384613ad3c3181f..81d4071130c17787dc134fe2cc337ecc946ea111 100644 (file)
size_t count, loff_t *ppos)
{
struct iwl_priv *priv = file->private_data;
- char *buf;
- int pos = 0;
- ssize_t ret = -ENOMEM;
+ char *buf = NULL;
+ ssize_t ret;
- ret = pos = iwl_dump_nic_event_log(priv, true, &buf, true);
- if (buf) {
- ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
- kfree(buf);
- }
+ ret = iwl_dump_nic_event_log(priv, true, &buf, true);
+ if (ret < 0)
+ goto err;
+ ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
+err:
+ kfree(buf);
return ret;
}
index ab768045696b48598ba91f889a22c87403f73c21..4748e1d4298e8c5418599efbbcb2feb165b56351 100644 (file)
void iwl_restore_stations(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
{
struct iwl_addsta_cmd sta_cmd;
+ static const struct iwl_link_quality_cmd zero_lq = {};
struct iwl_link_quality_cmd lq;
int i;
bool found = false;
else
memcpy(&lq, priv->stations[i].lq,
sizeof(struct iwl_link_quality_cmd));
- send_lq = true;
+
+ if (!memcmp(&lq, &zero_lq, sizeof(lq)))
+ send_lq = true;
}
spin_unlock_bh(&priv->sta_lock);
ret = iwl_send_add_sta(priv, &sta_cmd, CMD_SYNC);
index fb07aa361bc1ae33299d0aaef2ba3992cd644d66..9da65cccb20d30b218a4d3f79af25cd54a1baa58 100644 (file)
if (pdev) {
pci_iounmap(pdev, card->pci_mmap);
pci_iounmap(pdev, card->pci_mmap1);
-
- pci_release_regions(pdev);
pci_disable_device(pdev);
+ pci_release_region(pdev, 2);
+ pci_release_region(pdev, 0);
pci_set_drvdata(pdev, NULL);
}
}
index a658b4bc7da2fea78f2160b97907f20d547abde5..92849e5cf65746a9e108187c5d6acceeec694dcb 100644 (file)
if (!rt2x00_rt(rt2x00dev, RT5390) &&
!rt2x00_rt(rt2x00dev, RT5392)) {
+ u8 min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
+
rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
if (rt2x00_rt(rt2x00dev, RT3070) ||
&rt2x00dev->cap_flags))
rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
}
- rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
- drv_data->txmixer_gain_24g);
+ if (drv_data->txmixer_gain_24g >= min_gain) {
+ rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
+ drv_data->txmixer_gain_24g);
+ }
rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
}
index f79cbcd3944bf5e61e76a96022331a665e63f93e..8c1ecc555b54fb663cb536cc4be7b82a9fa48e3d 100644 (file)
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
goto Fixup;
}
+ pci_dev->state_saved = false;
if (pm->suspend) {
pci_power_t prev = pci_dev->current_state;
int error;
return 0;
}
+ pci_dev->state_saved = false;
if (pm->freeze) {
int error;
goto Fixup;
}
+ pci_dev->state_saved = false;
if (pm->poweroff) {
int error;
if (!pm || !pm->runtime_suspend)
return -ENOSYS;
+ pci_dev->state_saved = false;
pci_dev->no_d3cold = false;
error = pm->runtime_suspend(dev);
suspend_report_result(pm->runtime_suspend, error);
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 5cb5820fae40147a29c79913cd1ebadcbfba1348..d1b4e000c2c41f6f0b17bae17d051852711610aa 100644 (file)
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -651,15 +651,11 @@ static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
error = platform_pci_set_power_state(dev, state);
if (!error)
pci_update_current_state(dev, state);
- /* Fall back to PCI_D0 if native PM is not supported */
- if (!dev->pm_cap)
- dev->current_state = PCI_D0;
- } else {
+ } else
error = -ENODEV;
- /* Fall back to PCI_D0 if native PM is not supported */
- if (!dev->pm_cap)
- dev->current_state = PCI_D0;
- }
+
+ if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
+ dev->current_state = PCI_D0;
return error;
}
index 5c32e880bcb24315b4b2db260294106765eb4240..398949f4b052193a04f22f9081dc3c88598ad1a8 100644 (file)
},
};
-module_platform_driver(pcs_driver);
+static int __init pcs_init(void)
+{
+ return platform_driver_register(&pcs_driver);
+}
+arch_initcall(pcs_init);
+
+static void __exit pcs_exit(void)
+{
+ platform_driver_unregister(&pcs_driver);
+}
+module_exit(pcs_exit);
MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
index 83b21d9d5cf900e3e9ddde7ea4784fb6c6202c64..0c644e7d6b5ad87d689bd50d23efb230d4badf8c 100644 (file)
--- a/drivers/pwm/pwm-spear.c
+++ b/drivers/pwm/pwm-spear.c
u32 val;
rc = clk_enable(pc->clk);
- if (!rc)
+ if (rc)
return rc;
val = spear_pwm_readl(pc, pwm->hwpwm, PWMCR);
pc->chip.npwm = NUM_PWM;
ret = clk_prepare(pc->clk);
- if (!ret)
+ if (ret)
return ret;
if (of_device_is_compatible(np, "st,spear1340-pwm")) {
ret = clk_enable(pc->clk);
- if (!ret) {
+ if (ret) {
clk_unprepare(pc->clk);
return ret;
}
index 551a22b075387a0641d37ff9dc1a34e25b65ee9d..acfd69f7e719f1ce3dd7df118843f64839eff84b 100644 (file)
This driver provides support for the voltage regulators on the
AS3711 PMIC
+config REGULATOR_TIAVSCLASS0
+ tristate "Adaptive Voltage Scaling class 0 support for TI SoCs"
+ depends on ARCH_OMAP2PLUS
+ help
+ AVS is a power management technique which finely controls the
+ operating voltage of a device in order to optimize (i.e. reduce)
+ its power consumption.
+ At a given operating point, the voltage is adapted depending on
+ static factors (chip manufacturing process) and this adapted
+ voltage is made available in an efuse offset.
+ AVS is also called SmartReflex on OMAP devices.
+
+ Say Y here to enable Adaptive Voltage Scaling class 0 support.
+
endif
index b802b0c7fb02d7d7bb3bf3c1fa72b95aed899ce4..0ae7c64895c3c59a02ed9f1d949b94c3f6c08d7a 100644 (file)
obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
+obj-$(CONFIG_REGULATOR_TIAVSCLASS0) += ti-avs-class0-regulator.o
ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
index 5a0f54a1b8bdc147ef78a3fe73e8e73427bdcbaa..1a10eeabaa485a212a45b30eb311d0620575f34f 100644 (file)
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
return "";
}
+static void regulator_lock(struct regulator_dev *rdev)
+{
+ struct regulator_dev *locking_rdev = rdev;
+
+ while (locking_rdev->supply)
+ locking_rdev = locking_rdev->supply->rdev;
+
+ if (!mutex_trylock(&locking_rdev->mutex)) {
+ if (locking_rdev->lock_owner == current) {
+ locking_rdev->lock_count++;
+ dev_dbg(&locking_rdev->dev,
+ "Is locked. locking %s (ref=%u)\n",
+ rdev_get_name(rdev),
+ locking_rdev->lock_count);
+ return;
+ }
+ mutex_lock(&locking_rdev->mutex);
+ }
+
+ WARN_ON_ONCE(locking_rdev->lock_owner != NULL);
+ WARN_ON_ONCE(locking_rdev->lock_count != 0);
+
+ locking_rdev->lock_count = 1;
+ locking_rdev->lock_owner = current;
+ dev_dbg(&locking_rdev->dev, "Is locked. locking %s\n",
+ rdev_get_name(rdev));
+}
+
+static void regulator_unlock(struct regulator_dev *rdev)
+{
+ struct regulator_dev *locking_rdev = rdev;
+
+ while (locking_rdev->supply)
+ locking_rdev = locking_rdev->supply->rdev;
+
+ dev_dbg(&locking_rdev->dev, "Is unlocked. unlocking %s (ref=%u)\n",
+ rdev_get_name(rdev), locking_rdev->lock_count);
+
+ if (--locking_rdev->lock_count)
+ return;
+
+ locking_rdev->lock_owner = NULL;
+ mutex_unlock(&locking_rdev->mutex);
+}
+
/**
* of_get_regulator - get a regulator device node based on supply name
* @dev: Device pointer for the consumer (of regulator) device
struct regulator_dev *rdev = dev_get_drvdata(dev);
ssize_t ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = sprintf(buf, "%d\n", _regulator_get_voltage(rdev));
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
struct regulator_dev *rdev = dev_get_drvdata(dev);
ssize_t ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = regulator_print_state(buf, _regulator_is_enabled(rdev));
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
struct regulator *regulator;
int uA = 0;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
list_for_each_entry(regulator, &rdev->consumer_list, list)
uA += regulator->uA_load;
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return sprintf(buf, "%d\n", uA);
}
static DEVICE_ATTR(requested_microamps, 0444, regulator_total_uA_show, NULL);
if (regulator == NULL)
return NULL;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
regulator->rdev = rdev;
list_add(®ulator->list, &rdev->consumer_list);
_regulator_is_enabled(rdev))
regulator->always_on = true;
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return regulator;
overflow_err:
list_del(®ulator->list);
kfree(regulator);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return NULL;
}
struct regulator_dev *rdev;
struct regulator *regulator = ERR_PTR(-EPROBE_DEFER);
const char *devname = NULL;
- int ret;
+ int ret = 0;
if (id == NULL) {
pr_err("get() with no identifier\n");
if (rdev)
goto found;
+ /*
+ * If we have return value from dev_lookup fail, we do not expect to
+ * succeed, so, quit with appropriate error value
+ */
+ if (ret) {
+ regulator = ERR_PTR(ret);
+ goto out;
+ }
+
if (board_wants_dummy_regulator) {
rdev = dummy_regulator_rdev;
goto found;
return ret;
}
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = _regulator_enable(rdev);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (ret != 0 && rdev->supply)
regulator_disable(rdev->supply);
if (regulator->always_on)
return 0;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = _regulator_disable(rdev);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (ret == 0 && rdev->supply)
regulator_disable(rdev->supply);
struct regulator_dev *rdev = regulator->rdev;
int ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
regulator->uA_load = 0;
ret = _regulator_force_disable(regulator->rdev);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (rdev->supply)
while (rdev->open_count--)
disable_work.work);
int count, i, ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
BUG_ON(!rdev->deferred_disables);
rdev_err(rdev, "Deferred disable failed: %d\n", ret);
}
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (rdev->supply) {
for (i = 0; i < count; i++) {
if (!ms)
return regulator_disable(regulator);
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
rdev->deferred_disables++;
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
ret = schedule_delayed_work(&rdev->disable_work,
msecs_to_jiffies(ms));
if (regulator->always_on)
return 1;
- mutex_lock(®ulator->rdev->mutex);
+ regulator_lock(regulator->rdev);
ret = _regulator_is_enabled(regulator->rdev);
- mutex_unlock(®ulator->rdev->mutex);
+ regulator_unlock(regulator->rdev);
return ret;
}
if (!ops->list_voltage || selector >= rdev->desc->n_voltages)
return -EINVAL;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = ops->list_voltage(rdev, selector);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (ret > 0) {
if (ret < rdev->constraints->min_uV)
@@ -2295,7 +2349,7 @@ int regulator_set_voltage(struct regulator *regulator, int min_uV, int max_uV)
struct regulator_dev *rdev = regulator->rdev;
int ret = 0;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* If we're setting the same range as last time the change
* should be a noop (some cpufreq implementations use the same
@@ -2325,7 +2379,7 @@ int regulator_set_voltage(struct regulator *regulator, int min_uV, int max_uV)
ret = _regulator_do_set_voltage(rdev, min_uV, max_uV);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_set_voltage);
struct regulator_dev *rdev = regulator->rdev;
int ret, min_uV, max_uV;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
if (!rdev->desc->ops->set_voltage &&
!rdev->desc->ops->set_voltage_sel) {
ret = _regulator_do_set_voltage(rdev, min_uV, max_uV);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_sync_voltage);
{
int ret;
- mutex_lock(®ulator->rdev->mutex);
+ regulator_lock(regulator->rdev);
ret = _regulator_get_voltage(regulator->rdev);
- mutex_unlock(®ulator->rdev->mutex);
+ regulator_unlock(regulator->rdev);
return ret;
}
struct regulator_dev *rdev = regulator->rdev;
int ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* sanity check */
if (!rdev->desc->ops->set_current_limit) {
ret = rdev->desc->ops->set_current_limit(rdev, min_uA, max_uA);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_set_current_limit);
{
int ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* sanity check */
if (!rdev->desc->ops->get_current_limit) {
ret = rdev->desc->ops->get_current_limit(rdev);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
int ret;
int regulator_curr_mode;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* sanity check */
if (!rdev->desc->ops->set_mode) {
ret = rdev->desc->ops->set_mode(rdev, mode);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_set_mode);
{
int ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* sanity check */
if (!rdev->desc->ops->get_mode) {
ret = rdev->desc->ops->get_mode(rdev);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
if (rdev->supply)
input_uV = regulator_get_voltage(rdev->supply);
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/*
* first check to see if we can set modes at all, otherwise just
}
ret = mode;
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_set_optimum_mode);
!(rdev->constraints->valid_ops_mask & REGULATOR_CHANGE_BYPASS))
return 0;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
if (enable && !regulator->bypass) {
rdev->bypass_count++;
if (ret == 0)
regulator->bypass = enable;
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
mutex_lock(®ulator_list_mutex);
list_for_each_entry(rdev, ®ulator_list, list) {
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = suspend_prepare(rdev, state);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (ret < 0) {
rdev_err(rdev, "failed to prepare\n");
list_for_each_entry(rdev, ®ulator_list, list) {
struct regulator_ops *ops = rdev->desc->ops;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
if ((rdev->use_count > 0 || rdev->constraints->always_on) &&
ops->enable) {
error = ops->enable(rdev);
ret = error;
}
unlock:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
}
mutex_unlock(®ulator_list_mutex);
return ret;
if (!ops->disable || (c && c->always_on))
continue;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
if (rdev->use_count)
goto unlock;
}
unlock:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
}
mutex_unlock(®ulator_list_mutex);
index c6ca8e1a5c65944cbdf1d276d04a65ab7811a816..d59faabe13bec1a2309dc9ef73c2289846ca1d03 100644 (file)
case PALMAS_REG_SMPS457:
if (!pmic->smps457)
continue;
+ case PALMAS_REG_SMPS10:
+ if (palmas->palmas_id == TPS659038)
+ continue;
}
/* Initialise sleep/init values from platform data */
switch (id) {
case PALMAS_REG_SMPS10:
+
pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
pmic->desc[id].ops = &palmas_ops_smps10;
pmic->desc[id].vsel_reg =
static struct of_device_id of_palmas_match_tbl[] = {
{ .compatible = "ti,palmas-pmic", },
+ { .compatible = "ti,tps659038-pmic", },
{ /* end */ }
};
diff --git a/drivers/regulator/ti-avs-class0-regulator.c b/drivers/regulator/ti-avs-class0-regulator.c
--- /dev/null
@@ -0,0 +1,349 @@
+/*
+ * Texas Instrument SmartReflex AVS Class 0 driver
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Nishanth Menon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": %s(): " fmt, __func__
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+/**
+ * struct tiavs_class0_data - class data for the regulator instance
+ * @desc: regulator descriptor
+ * @reg: regulator that will actually set the voltage
+ * @volt_set_table: voltage to set data table
+ * @current_idx: current index
+ * @voltage_tolerance: % tolerance for voltage(optional)
+ */
+struct tiavs_class0_data {
+ struct regulator_desc desc;
+ struct regulator *reg;
+ unsigned int *volt_set_table;
+ int current_idx;
+ u32 voltage_tolerance;
+};
+
+/**
+ * tiavs_class0_set_voltage_sel() - set voltage
+ * @rdev: regulator device
+ * @sel: set voltage corresponding to selector
+ *
+ * This searches for a best case match and uses the child regulator to set
+ * appropriate voltage
+ *
+ * Return: -ENODEV if no proper regulator data/-EINVAL if no match,bad efuse
+ * else returns regulator set result
+ */
+static int tiavs_class0_set_voltage_sel(struct regulator_dev *rdev,
+ unsigned sel)
+{
+ struct tiavs_class0_data *data = rdev_get_drvdata(rdev);
+ const struct regulator_desc *desc = rdev->desc;
+ struct regulator *reg;
+ int vset, ret, tol;
+
+ if (!data) {
+ pr_err("No regulator drvdata\n");
+ return -ENODEV;
+ }
+
+ reg = data->reg;
+ if (!reg) {
+ pr_err("No regulator\n");
+ return -ENODEV;
+ }
+
+ if (!desc->n_voltages || !data->volt_set_table) {
+ pr_err("No valid voltage table entries?\n");
+ return -EINVAL;
+ }
+
+ if (sel >= desc->n_voltages) {
+ pr_err("sel(%d) > max voltage table entries(%d)\n", sel,
+ desc->n_voltages);
+ return -EINVAL;
+ }
+
+ vset = data->volt_set_table[sel];
+
+ /* Adjust for % tolerance needed */
+ tol = DIV_ROUND_UP(vset * data->voltage_tolerance, 100);
+ ret = regulator_set_voltage_tol(reg, vset, tol);
+ if (!ret)
+ data->current_idx = sel;
+
+ return ret;
+}
+
+/**
+ * tiavs_class0_get_voltage_sel() - Get voltage selector
+ * @rdev: regulator device
+ *
+ * Return: -ENODEV if no proper regulator data/-EINVAL if no data,
+ * else returns current index.
+ */
+static int tiavs_class0_get_voltage_sel(struct regulator_dev *rdev)
+{
+ const struct regulator_desc *desc = rdev->desc;
+ struct tiavs_class0_data *data = rdev_get_drvdata(rdev);
+
+ if (!data) {
+ pr_err("No regulator drvdata\n");
+ return -ENODEV;
+ }
+
+ if (!desc->n_voltages || !data->volt_set_table) {
+ pr_err("No valid voltage table entries?\n");
+ return -EINVAL;
+ }
+
+ if (data->current_idx > desc->n_voltages) {
+ pr_err("Corrupted data structure?? idx(%d) > n_voltages(%d)\n",
+ data->current_idx, desc->n_voltages);
+ return -EINVAL;
+ }
+
+ return data->current_idx;
+}
+
+static struct regulator_ops tiavs_class0_ops = {
+ .list_voltage = regulator_list_voltage_table,
+
+ .set_voltage_sel = tiavs_class0_set_voltage_sel,
+ .get_voltage_sel = tiavs_class0_get_voltage_sel,
+
+};
+
+static const struct of_device_id tiavs_class0_of_match[] = {
+ {.compatible = "ti,avsclass0",},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, tiavs_class0_of_match);
+
+/**
+ * tiavs_class0_probe() - AVS class 0 probe
+ * @pdev: matching platform device
+ *
+ * We support only device tree provided data here. Once we find a regulator,
+ * efuse offsets, we pick up the efuse register voltages store them per
+ * instance.
+ *
+ * Return: if everything goes through, we return 0, else corresponding error
+ * value is returned.
+ */
+static int tiavs_class0_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct device_node *np = pdev->dev.of_node;
+ struct property *prop;
+ struct resource *res;
+ struct regulator *reg;
+ struct regulator_init_data *initdata = NULL;
+ struct regulator_config config = { };
+ struct regulation_constraints *c;
+ struct regulator_dev *rdev;
+ struct regulator_desc *desc;
+ struct tiavs_class0_data *data;
+ void __iomem *base;
+ const __be32 *val;
+ unsigned int *volt_table;
+ bool efuse_is_uV = false;
+ int proplen, i, ret;
+ int reg_v, min_uV = INT_MAX, max_uV = 0;
+ int best_val = INT_MAX, choice = -EINVAL;
+
+ match = of_match_device(tiavs_class0_of_match, &pdev->dev);
+ if (match)
+ initdata = of_get_regulator_init_data(&pdev->dev, np);
+ if (!initdata) {
+ dev_err(&pdev->dev, "No proper OF?\n");
+ return -ENODEV;
+ }
+
+ /* look for avs-supply */
+ reg = devm_regulator_get(&pdev->dev, "avs");
+ if (IS_ERR(reg)) {
+ ret = PTR_ERR(reg);
+ reg = NULL;
+ dev_err(&pdev->dev, "avs_class0 regulator not available(%d)\n",
+ ret);
+ return ret;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ dev_err(&pdev->dev, "No memory to alloc data!\n");
+ return -ENOMEM;
+ }
+ data->reg = reg;
+
+ desc = &data->desc;
+ desc->name = dev_name(&pdev->dev);
+ desc->owner = THIS_MODULE;
+ desc->type = REGULATOR_VOLTAGE;
+ desc->ops = &tiavs_class0_ops;
+
+ /* pick up optional properties */
+ of_property_read_u32(np, "voltage-tolerance", &data->voltage_tolerance);
+ efuse_is_uV = of_property_read_bool(np,
+ "ti,avsclass0-microvolt-values");
+
+ /* pick up Efuse based voltages */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get IO resource\n");
+ return -ENODEV;
+ }
+
+ base = devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res));
+ if (!base) {
+ dev_err(&pdev->dev, "Unable to map Efuse registers\n");
+ return -ENOMEM;
+ }
+
+ /* Fetch efuse-settings. */
+ prop = of_find_property(np, "efuse-settings", NULL);
+ if (!prop) {
+ dev_err(&pdev->dev, "No 'efuse-settings' property found\n");
+ return -EINVAL;
+ }
+
+ proplen = prop->length / sizeof(int);
+
+ data->volt_set_table =
+ devm_kzalloc(&pdev->dev, sizeof(unsigned int) * (proplen / 2),
+ GFP_KERNEL);
+ if (!data->volt_set_table) {
+ dev_err(&pdev->dev, "Unable to Allocate voltage set table\n");
+ return -ENOMEM;
+ }
+
+ volt_table =
+ devm_kzalloc(&pdev->dev, sizeof(unsigned int) * (proplen / 2),
+ GFP_KERNEL);
+ if (!volt_table) {
+ dev_err(&pdev->dev,
+ "Unable to Allocate voltage lookup table\n");
+ return -ENOMEM;
+ }
+
+ val = prop->value;
+ for (i = 0; i < proplen / 2; i++) {
+ u32 efuse_offset;
+
+ volt_table[i] = be32_to_cpup(val++);
+ efuse_offset = be32_to_cpup(val++);
+
+ data->volt_set_table[i] = efuse_is_uV ?
+ readl(base + efuse_offset) :
+ readw(base + efuse_offset) * 1000;
+
+ /* Find min/max for the voltage sets */
+ if (min_uV > volt_table[i])
+ min_uV = volt_table[i];
+ if (max_uV < volt_table[i])
+ max_uV = volt_table[i];
+
+ dev_dbg(&pdev->dev, "[%d] efuse=0x%08x volt_table=%d vset=%d\n",
+ i, efuse_offset, volt_table[i],
+ data->volt_set_table[i]);
+ }
+ desc->n_voltages = i;
+ desc->volt_table = volt_table;
+
+ /* Search for a best match voltage */
+ reg_v = regulator_get_voltage(reg);
+ if (reg_v < 0) {
+ dev_err(&pdev->dev, "Regulator error %d for get_voltage!\n",
+ reg_v);
+ return reg_v;
+ }
+
+ for (i = 0; i < desc->n_voltages; i++)
+ if (data->volt_set_table[i] < best_val &&
+ data->volt_set_table[i] >= reg_v) {
+ best_val = data->volt_set_table[i];
+ choice = i;
+ }
+
+ if (choice == -EINVAL) {
+ dev_err(&pdev->dev, "No match regulator V=%d\n", reg_v);
+ return -EINVAL;
+ }
+ data->current_idx = choice;
+
+ /*
+ * Constrain board-specific capabilities according to what
+ * this driver can actually do.
+ */
+ c = &initdata->constraints;
+ if (desc->n_voltages > 1)
+ c->valid_ops_mask |= REGULATOR_CHANGE_VOLTAGE;
+ c->always_on = true;
+
+ c->min_uV = min_uV;
+ c->max_uV = max_uV;
+
+ config.dev = &pdev->dev;
+ config.init_data = initdata;
+ config.driver_data = data;
+ config.of_node = pdev->dev.of_node;
+
+ rdev = regulator_register(desc, &config);
+ if (IS_ERR(rdev)) {
+ dev_err(&pdev->dev, "can't register %s, %ld\n",
+ desc->name, PTR_ERR(rdev));
+ return PTR_ERR(rdev);
+ }
+ platform_set_drvdata(pdev, rdev);
+
+ return 0;
+}
+
+static int tiavs_class0_remove(struct platform_device *pdev)
+{
+ struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+ regulator_unregister(rdev);
+ return 0;
+}
+
+MODULE_ALIAS("platform:tiavs_class0");
+
+static struct platform_driver tiavs_class0_driver = {
+ .probe = tiavs_class0_probe,
+ .remove = tiavs_class0_remove,
+ .driver = {
+ .name = "tiavs_class0",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(tiavs_class0_of_match),
+ },
+};
+module_platform_driver(tiavs_class0_driver);
+
+MODULE_DESCRIPTION("TI SmartReflex AVS class 0 regulator driver");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index f62eab30143817ac008a52b788843d1fbb180a47..f11f746f7a3507bece3c126ce95d4cb73c306029 100644 (file)
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
This driver can also be built as a module. If so, the module
will be called rtc-x1205.
+config RTC_DRV_PALMAS
+ tristate "TI Palmas RTC driver"
+ depends on MFD_PALMAS
+ help
+ If you say yes here you get support for the RTC of TI PALMA series PMIC
+ chips.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-palma.
+
config RTC_DRV_PCF8523
tristate "NXP PCF8523"
help
This driver can also be built as a module. If so, the module
will be called rtc-rv3029c2.
-config RTC_DRV_PALMAS
- tristate "Palmas RTC"
- help
- If you say yes here you get support for the RTC on the Palmas
- series of PMICs from TI.
-
endif # I2C
comment "SPI RTC drivers"
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index 16630aa87f45d181d37576fa2e71576196f1da53..1c77423cff00b5c4abe297c0a4af6db40cf5e9b5 100644 (file)
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
mask = RTC_IRQMASK;
tmp &= ~mask;
CMOS_WRITE(tmp, RTC_CONTROL);
+ hpet_mask_rtc_irq_bit(mask);
- /* shut down hpet emulation - we don't need it for alarm */
- hpet_mask_rtc_irq_bit(RTC_PIE|RTC_AIE|RTC_UIE);
cmos_checkintr(cmos, tmp);
}
spin_unlock_irq(&rtc_lock);
rtc_update_irq(cmos->rtc, 1, mask);
tmp &= ~RTC_AIE;
hpet_mask_rtc_irq_bit(RTC_AIE);
+ hpet_rtc_timer_init();
} while (mask & RTC_AIE);
spin_unlock_irq(&rtc_lock);
}
index 116a3002ce189ad72339dcd7617cdbd5cfc720d7..a7d5175d29a98f03ff74538e94d4168a80cc3efb 100644 (file)
--- a/drivers/rtc/rtc-palmas.c
+++ b/drivers/rtc/rtc-palmas.c
/*
- * Palmas Real Time Clock interface
+ * rtc-palmas.c -- Palmas Real Time Clock driver.
+
+ * RTC driver for TI Palma series devices like TPS65913,
+ * TPS65914 power management IC.
*
- * Copyright (C) 2012 Texas Instruments
- * Author: Graeme Gregory <gg@slimlogic.co.uk>
+ * Copyright (c) 2012, NVIDIA Corporation.
*
- * Based on rtc-twl.c
- * Copyright (C) 2007 MontaVista Software, Inc
- * Author: Alexandre Rusev <source@mvista.com>
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
*
- * Based on original TI driver twl4030-rtc.c
- * Copyright (C) 2006 Texas Instruments, Inc.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
*
- * Based on rtc-omap.c
- * Copyright (C) 2003 MontaVista Software, Inc.
- * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
- * Copyright (C) 2006 David Brownell
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
*/
-#include <linux/kernel.h>
+#include <linux/bcd.h>
#include <linux/errno.h>
#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mfd/palmas.h>
#include <linux/module.h>
-#include <linux/types.h>
#include <linux/rtc.h>
-#include <linux/bcd.h>
+#include <linux/types.h>
#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/slab.h>
-#include <linux/mfd/palmas.h>
-
-#define ALL_TIME_REGS 6
+#include <linux/pm.h>
struct palmas_rtc {
- struct palmas *palmas;
- struct device *dev;
- struct rtc_device *rtc;
- unsigned int irq_bits;
- int irq;
+ struct rtc_device *rtc;
+ struct device *dev;
+ unsigned int irq;
};
-static int palmas_rtc_read(struct palmas *palmas, unsigned int reg,
- unsigned int *dest)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RTC_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RTC_BASE, reg);
-
- return regmap_read(palmas->regmap[slave], addr, dest);
-}
-
-static int palmas_rtc_write(struct palmas *palmas, unsigned int reg,
- unsigned int data)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RTC_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RTC_BASE, reg);
-
- return regmap_write(palmas->regmap[slave], addr, data);
-}
-
-static int palmas_rtc_read_block(struct palmas *palmas, unsigned int reg,
- u8 *dest, size_t count)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RTC_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RTC_BASE, reg);
-
- return regmap_bulk_read(palmas->regmap[slave], addr, dest, count);
-}
-
-static int palmas_rtc_write_block(struct palmas *palmas, unsigned int reg,
- u8 *src, size_t count)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RTC_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RTC_BASE, reg);
-
- return regmap_raw_write(palmas->regmap[slave], addr, src, count);
-}
+/* Total number of RTC registers needed to set time*/
+#define PALMAS_NUM_TIME_REGS (PALMAS_YEARS_REG - PALMAS_SECONDS_REG + 1)
-static int palmas_rtc_setbits(struct palmas *palmas, unsigned int reg,
- unsigned int data)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RESOURCE_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, reg);
-
- return regmap_update_bits(palmas->regmap[slave], addr, data, data);
-}
-
-static int palmas_rtc_clrbits(struct palmas *palmas, unsigned int reg,
- unsigned int data)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RESOURCE_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, reg);
-
- return regmap_update_bits(palmas->regmap[slave], addr, data, 0);
-}
-
-/*
- * Gets current TWL RTC time and date parameters.
- *
- * The RTC's time/alarm representation is not what gmtime(3) requires
- * Linux to use:
- *
- * - Months are 1..12 vs Linux 0-11
- * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
- */
static int palmas_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned char rtc_data[ALL_TIME_REGS];
+ unsigned char rtc_data[PALMAS_NUM_TIME_REGS];
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
int ret;
- ret = palmas_rtc_setbits(palmas, PALMAS_RTC_CTRL_REG,
- PALMAS_RTC_CTRL_REG_GET_TIME);
+ /* Copy RTC counting registers to static registers or latches */
+ ret = palmas_update_bits(palmas, PALMAS_RTC_BASE, PALMAS_RTC_CTRL_REG,
+ PALMAS_RTC_CTRL_REG_GET_TIME, PALMAS_RTC_CTRL_REG_GET_TIME);
if (ret < 0) {
- dev_err(dev, "Failed to update RTC_CTRL %d\n", ret);
- goto out;
+ dev_err(dev, "RTC CTRL reg update failed, err: %d\n", ret);
+ return ret;
}
- ret = palmas_rtc_read_block(palmas,PALMAS_SECONDS_REG, rtc_data,
- ALL_TIME_REGS);
-
+ ret = palmas_bulk_read(palmas, PALMAS_RTC_BASE, PALMAS_SECONDS_REG,
+ rtc_data, PALMAS_NUM_TIME_REGS);
if (ret < 0) {
- dev_err(dev, "Failed to read time block %d\n", ret);
- goto out;
+ dev_err(dev, "RTC_SECONDS reg read failed, err = %d\n", ret);
+ return ret;
}
tm->tm_sec = bcd2bin(rtc_data[0]);
tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
tm->tm_year = bcd2bin(rtc_data[5]) + 100;
- ret = palmas_rtc_clrbits(palmas, PALMAS_RTC_CTRL_REG,
- PALMAS_RTC_CTRL_REG_GET_TIME);
- if (ret < 0)
- dev_err(dev, "Failed to update RTC_CTRL %d\n", ret);
-
-out:
return ret;
}
static int palmas_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned char rtc_data[ALL_TIME_REGS];
+ unsigned char rtc_data[PALMAS_NUM_TIME_REGS];
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
int ret;
rtc_data[0] = bin2bcd(tm->tm_sec);
rtc_data[4] = bin2bcd(tm->tm_mon + 1);
rtc_data[5] = bin2bcd(tm->tm_year - 100);
- /* Stop RTC while updating the TC registers */
- ret = palmas_rtc_clrbits(palmas, PALMAS_RTC_CTRL_REG,
- PALMAS_RTC_CTRL_REG_STOP_RTC);
+ /* Stop RTC while updating the RTC time registers */
+ ret = palmas_update_bits(palmas, PALMAS_RTC_BASE, PALMAS_RTC_CTRL_REG,
+ PALMAS_RTC_CTRL_REG_STOP_RTC, 0);
if (ret < 0) {
- dev_err(dev, "Failed to stop RTC %d\n", ret);
- goto out;
+ dev_err(dev, "RTC stop failed, err = %d\n", ret);
+ return ret;
}
- /* update all the time registers in one shot */
- ret = palmas_rtc_write_block(palmas, PALMAS_SECONDS_REG, rtc_data,
- ALL_TIME_REGS);
+ ret = palmas_bulk_write(palmas, PALMAS_RTC_BASE, PALMAS_SECONDS_REG,
+ rtc_data, PALMAS_NUM_TIME_REGS);
if (ret < 0) {
- dev_err(dev, "Failed to write time block %d\n", ret);
- goto out;
+ dev_err(dev, "RTC_SECONDS reg write failed, err = %d\n", ret);
+ return ret;
}
/* Start back RTC */
- ret = palmas_rtc_setbits(palmas, PALMAS_RTC_CTRL_REG,
- PALMAS_RTC_CTRL_REG_STOP_RTC);
- if (ret < 0) {
- dev_err(dev, "Failed to start RTC %d\n", ret);
- goto out;
- }
-
-out:
+ ret = palmas_update_bits(palmas, PALMAS_RTC_BASE, PALMAS_RTC_CTRL_REG,
+ PALMAS_RTC_CTRL_REG_STOP_RTC, PALMAS_RTC_CTRL_REG_STOP_RTC);
+ if (ret < 0)
+ dev_err(dev, "RTC start failed, err = %d\n", ret);
return ret;
}
static int palmas_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- int ret;
-
- if (enabled) {
- ret = palmas_rtc_setbits(palmas, PALMAS_RTC_INTERRUPTS_REG,
- PALMAS_RTC_INTERRUPTS_REG_IT_ALARM);
- if (ret)
- dev_err(palmas_rtc->dev,
- "failed to set RTC alarm IRQ %d\n", ret);
-
- palmas_rtc->irq_bits |= PALMAS_RTC_INTERRUPTS_REG_IT_ALARM;
- } else {
- ret = palmas_rtc_clrbits(palmas, PALMAS_RTC_INTERRUPTS_REG,
- PALMAS_RTC_INTERRUPTS_REG_IT_ALARM);
- if (ret)
- dev_err(palmas_rtc->dev,
- "failed to clear RTC alarm IRQ %d\n", ret);
-
- palmas_rtc->irq_bits &= ~PALMAS_RTC_INTERRUPTS_REG_IT_ALARM;
- }
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
+ u8 val;
- return ret;
+ val = enabled ? PALMAS_RTC_INTERRUPTS_REG_IT_ALARM : 0;
+ return palmas_write(palmas, PALMAS_RTC_BASE,
+ PALMAS_RTC_INTERRUPTS_REG, val);
}
-/*
- * Gets current TWL RTC alarm time.
- */
static int palmas_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned char rtc_data[ALL_TIME_REGS];
+ unsigned char alarm_data[PALMAS_NUM_TIME_REGS];
+ u32 int_val;
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
int ret;
- ret = palmas_rtc_read_block(palmas, PALMAS_ALARM_SECONDS_REG, rtc_data,
- ALL_TIME_REGS);
+ ret = palmas_bulk_read(palmas, PALMAS_RTC_BASE,
+ PALMAS_ALARM_SECONDS_REG,
+ alarm_data, PALMAS_NUM_TIME_REGS);
if (ret < 0) {
- dev_err(dev, "Failed to read alarm block %d\n", ret);
- goto out;
+ dev_err(dev, "RTC_ALARM_SECONDS read failed, err = %d\n", ret);
+ return ret;
}
- /* some of these fields may be wildcard/"match all" */
- alm->time.tm_sec = bcd2bin(rtc_data[0]);
- alm->time.tm_min = bcd2bin(rtc_data[1]);
- alm->time.tm_hour = bcd2bin(rtc_data[2]);
- alm->time.tm_mday = bcd2bin(rtc_data[3]);
- alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
- alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
+ alm->time.tm_sec = bcd2bin(alarm_data[0]);
+ alm->time.tm_min = bcd2bin(alarm_data[1]);
+ alm->time.tm_hour = bcd2bin(alarm_data[2]);
+ alm->time.tm_mday = bcd2bin(alarm_data[3]);
+ alm->time.tm_mon = bcd2bin(alarm_data[4]) - 1;
+ alm->time.tm_year = bcd2bin(alarm_data[5]) + 100;
- /* report cached alarm enable state */
- if (palmas_rtc->irq_bits & PALMAS_RTC_INTERRUPTS_REG_IT_ALARM)
- alm->enabled = 1;
+ ret = palmas_read(palmas, PALMAS_RTC_BASE, PALMAS_RTC_INTERRUPTS_REG,
+ &int_val);
+ if (ret < 0) {
+ dev_err(dev, "RTC_INTERRUPTS reg read failed, err = %d\n", ret);
+ return ret;
+ }
-out:
+ if (int_val & PALMAS_RTC_INTERRUPTS_REG_IT_ALARM)
+ alm->enabled = 1;
return ret;
}
static int palmas_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned char alarm_data[ALL_TIME_REGS];
+ unsigned char alarm_data[PALMAS_NUM_TIME_REGS];
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
int ret;
ret = palmas_rtc_alarm_irq_enable(dev, 0);
- if (ret)
- goto out;
+ if (ret < 0) {
+ dev_err(dev, "Disable RTC alarm failed\n");
+ return ret;
+ }
alarm_data[0] = bin2bcd(alm->time.tm_sec);
alarm_data[1] = bin2bcd(alm->time.tm_min);
alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
- /* update all the alarm registers in one shot */
- ret = palmas_rtc_write_block(palmas, PALMAS_ALARM_SECONDS_REG,
- alarm_data, ALL_TIME_REGS);
- if (ret) {
- dev_err(dev, "Failed to write alarm block %d\n", ret);
- goto out;
+ ret = palmas_bulk_write(palmas, PALMAS_RTC_BASE,
+ PALMAS_ALARM_SECONDS_REG, alarm_data, PALMAS_NUM_TIME_REGS);
+ if (ret < 0) {
+ dev_err(dev, "ALARM_SECONDS_REG write failed, err = %d\n", ret);
+ return ret;
}
- if (alm->enabled) {
+ if (alm->enabled)
ret = palmas_rtc_alarm_irq_enable(dev, 1);
- }
-
-out:
return ret;
}
-static irqreturn_t palmas_rtc_interrupt(int irq, void *rtc)
+static int palmas_clear_interrupts(struct device *dev)
{
- struct palmas_rtc *palmas_rtc = rtc;
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned long events = 0;
- int ret = IRQ_NONE;
- int res;
- unsigned int rd_reg;
-
- res = palmas_rtc_read(palmas, PALMAS_RTC_STATUS_REG, &rd_reg);
- if (res) {
- dev_err(palmas_rtc->dev, "Failed to read IRQ sts %d\n, res",
- res);
- goto out;
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
+ unsigned int rtc_reg;
+ int ret;
+
+ ret = palmas_read(palmas, PALMAS_RTC_BASE, PALMAS_RTC_STATUS_REG,
+ &rtc_reg);
+ if (ret < 0) {
+ dev_err(dev, "RTC_STATUS read failed, err = %d\n", ret);
+ return ret;
}
- /*
- * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
- * only one (ALARM or RTC) interrupt source may be enabled
- * at time, we also could check our results
- * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
- */
- if (rd_reg & PALMAS_RTC_STATUS_REG_ALARM)
- events |= RTC_IRQF | RTC_AF;
- else
- events |= RTC_IRQF | RTC_UF;
-
- res = palmas_rtc_write(palmas, PALMAS_RTC_STATUS_REG,
- rd_reg | PALMAS_RTC_STATUS_REG_ALARM);
- if (res) {
- dev_err(palmas_rtc->dev, "Failed to clear IRQ sts %d\n, res",
- res);
- goto out;
+ ret = palmas_write(palmas, PALMAS_RTC_BASE, PALMAS_RTC_STATUS_REG,
+ rtc_reg);
+ if (ret < 0) {
+ dev_err(dev, "RTC_STATUS write failed, err = %d\n", ret);
+ return ret;
}
+ return 0;
+}
- /* Notify RTC core on event */
- rtc_update_irq(rtc, 1, events);
+static irqreturn_t palmas_rtc_interrupt(int irq, void *context)
+{
+ struct palmas_rtc *palmas_rtc = context;
+ struct device *dev = palmas_rtc->dev;
+ int ret;
- ret = IRQ_HANDLED;
-out:
- return ret;
+ ret = palmas_clear_interrupts(dev);
+ if (ret < 0) {
+ dev_err(dev, "RTC interrupt clear failed, err = %d\n", ret);
+ return IRQ_NONE;
+ }
+
+ rtc_update_irq(palmas_rtc->rtc, 1, RTC_IRQF | RTC_AF);
+ return IRQ_HANDLED;
}
-static struct rtc_class_ops twl_rtc_ops = {
+static struct rtc_class_ops palmas_rtc_ops = {
.read_time = palmas_rtc_read_time,
.set_time = palmas_rtc_set_time,
.read_alarm = palmas_rtc_read_alarm,
.alarm_irq_enable = palmas_rtc_alarm_irq_enable,
};
-/*----------------------------------------------------------------------*/
-
static int palmas_rtc_probe(struct platform_device *pdev)
{
struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
- struct palmas_rtc *palmas_rtc;
- struct rtc_device *rtc;
- int ret = -EINVAL;
- int irq;
- unsigned int rd_reg;
-
- ret = palmas_rtc_read(palmas, PALMAS_RTC_STATUS_REG, &rd_reg);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to read RTC status %d\n", rd_reg);
- goto out1;
- }
-
- palmas_rtc = kzalloc(sizeof(*palmas_rtc), GFP_KERNEL);
- if (!palmas_rtc) {
- ret = -ENOMEM;
- goto out1;
- }
-
- if (rd_reg & PALMAS_RTC_STATUS_REG_POWER_UP)
- dev_warn(&pdev->dev, "Power up reset detected\n");
+ struct palmas_rtc *palmas_rtc = NULL;
+ int ret;
- if (rd_reg & PALMAS_RTC_STATUS_REG_ALARM)
- dev_warn(&pdev->dev, "Pending Alarm interrupt detected\n");
+ palmas_rtc = devm_kzalloc(&pdev->dev, sizeof(struct palmas_rtc),
+ GFP_KERNEL);
+ if (!palmas_rtc)
+ return -ENOMEM;
- /* Clear RTC Power up reset and pending alarm interrupts */
- ret = palmas_rtc_write(palmas, PALMAS_RTC_STATUS_REG, rd_reg);
+ /* Clear pending interrupts */
+ ret = palmas_clear_interrupts(&pdev->dev);
if (ret < 0) {
- dev_err(&pdev->dev, "Failed to read RTC status %d\n", ret);
- goto out2;
+ dev_err(&pdev->dev, "clear RTC int failed, err = %d\n", ret);
+ return ret;
}
- /* Check RTC module status, Enable if it is off */
- ret = palmas_rtc_read(palmas, PALMAS_RTC_CTRL_REG, &rd_reg);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to read RTC ctrl %d\n", ret);
- goto out2;
- }
-
- if (!(rd_reg & PALMAS_RTC_CTRL_REG_STOP_RTC)) {
- dev_info(&pdev->dev, "Enabling Palmas RTC\n");
- rd_reg = PALMAS_RTC_CTRL_REG_STOP_RTC;
- ret = palmas_rtc_write(palmas, PALMAS_RTC_CTRL_REG, rd_reg);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to write RTC ctrl %d\n",
- ret);
- goto out2;
- }
- }
+ palmas_rtc->dev = &pdev->dev;
+ platform_set_drvdata(pdev, palmas_rtc);
- /* init cached IRQ enable bits */
- ret = palmas_rtc_read(palmas, PALMAS_RTC_INTERRUPTS_REG,
- &palmas_rtc->irq_bits);
+ /* Start RTC */
+ ret = palmas_update_bits(palmas, PALMAS_RTC_BASE, PALMAS_RTC_CTRL_REG,
+ PALMAS_RTC_CTRL_REG_STOP_RTC,
+ PALMAS_RTC_CTRL_REG_STOP_RTC);
if (ret < 0) {
- dev_err(&pdev->dev, "Failed to cache IRQ bits %d\n", ret);
- goto out2;
+ dev_err(&pdev->dev, "RTC_CTRL write failed, err = %d\n", ret);
+ return ret;
}
- palmas_rtc->palmas = palmas;
- palmas_rtc->dev = &pdev->dev;
- platform_set_drvdata(pdev, palmas_rtc);
-
- device_init_wakeup(&pdev->dev, 1);
+ palmas_rtc->irq = regmap_irq_get_virq(palmas->irq_data,
+ PALMAS_RTC_ALARM_IRQ);
- rtc = rtc_device_register(pdev->name,
- &pdev->dev, &twl_rtc_ops, THIS_MODULE);
- if (IS_ERR(rtc)) {
- ret = PTR_ERR(rtc);
- dev_err(&pdev->dev, "can't register RTC device, err %d\n",
- ret);
- goto out2;
+ palmas_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
+ &palmas_rtc_ops, THIS_MODULE);
+ if (IS_ERR(palmas_rtc->rtc)) {
+ ret = PTR_ERR(palmas_rtc->rtc);
+ dev_err(&pdev->dev, "RTC register failed, err = %d\n", ret);
+ return ret;
}
- irq = regmap_irq_get_virq(palmas->irq_data, PALMAS_RTC_ALARM_IRQ);
- ret = request_threaded_irq(irq, NULL, palmas_rtc_interrupt,
- IRQF_TRIGGER_RISING,
- dev_name(&pdev->dev), palmas_rtc);
+ ret = request_threaded_irq(palmas_rtc->irq, NULL,
+ palmas_rtc_interrupt,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT |
+ IRQF_EARLY_RESUME,
+ dev_name(&pdev->dev), palmas_rtc);
if (ret < 0) {
- dev_err(&pdev->dev, "IRQ is not free\n");
- goto out3;
+ dev_err(&pdev->dev, "IRQ request failed, err = %d\n", ret);
+ rtc_device_unregister(palmas_rtc->rtc);
+ return ret;
}
- palmas_rtc->irq = irq;
-
+ device_set_wakeup_capable(&pdev->dev, 1);
return 0;
-
-out3:
- rtc_device_unregister(rtc);
-out2:
- kfree(palmas_rtc);
-out1:
- return ret;
}
-/*
- * Disable all TWL RTC module interrupts.
- * Sets status flag to free.
- */
static int palmas_rtc_remove(struct platform_device *pdev)
{
struct palmas_rtc *palmas_rtc = platform_get_drvdata(pdev);
- struct rtc_device *rtc = palmas_rtc->rtc;
palmas_rtc_alarm_irq_enable(&pdev->dev, 0);
-
free_irq(palmas_rtc->irq, palmas_rtc);
- rtc_device_unregister(rtc);
- kfree(palmas_rtc);
+ rtc_device_unregister(palmas_rtc->rtc);
+ return 0;
+}
+#ifdef CONFIG_PM_SLEEP
+static int palmas_rtc_suspend(struct device *dev)
+{
+ struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ enable_irq_wake(palmas_rtc->irq);
+ return 0;
+}
+
+static int palmas_rtc_resume(struct device *dev)
+{
+ struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ disable_irq_wake(palmas_rtc->irq);
return 0;
}
+#endif
+
+static const struct dev_pm_ops palmas_rtc_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(palmas_rtc_suspend, palmas_rtc_resume)
+};
static struct of_device_id of_palmas_match_tbl[] = {
+ { .compatible = "ti,twl6035-rtc", },
+ { .compatible = "ti,twl6036-rtc", },
+ { .compatible = "ti,twl6037-rtc", },
+ { .compatible = "ti,tps65913-rtc", },
+ { .compatible = "ti,tps65914-rtc", },
+ { .compatible = "ti,tps80032-rtc", },
{ .compatible = "ti,palmas-rtc", },
+ { .compatible = "ti,palmas-charger-rtc", },
{ /* end */ },
};
static struct platform_driver palmas_rtc_driver = {
- .probe = palmas_rtc_probe,
- .remove = palmas_rtc_remove,
- .driver = {
- .owner = THIS_MODULE,
- .name = "palmas-rtc",
+ .probe = palmas_rtc_probe,
+ .remove = palmas_rtc_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "palmas-rtc",
+ .pm = &palmas_rtc_pm_ops,
.of_match_table = of_palmas_match_tbl,
},
};
-static int __init palmas_rtc_init(void)
-{
- return platform_driver_register(&palmas_rtc_driver);
-}
-module_init(palmas_rtc_init);
-
-static void __exit palmas_rtc_exit(void)
-{
- platform_driver_unregister(&palmas_rtc_driver);
-}
-module_exit(palmas_rtc_exit);
+module_platform_driver(palmas_rtc_driver);
-MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
-MODULE_DESCRIPTION("Palmas RTC Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:palmas-rtc");
-MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
+MODULE_ALIAS("platform:palmas_rtc");
+MODULE_DESCRIPTION("TI PALMAS series RTC driver");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_LICENSE("GPL v2");
index c44d13f607bc586781221e144341c921aaf42010..56dcd7c8e09834f42263e74f01a3ffeb17a6fa5f 100644 (file)
add_memory_merged(0);
}
+#define MEM_SCT_SIZE (1UL << SECTION_SIZE_BITS)
+
static void __init insert_increment(u16 rn, int standby, int assigned)
{
struct memory_increment *incr, *new_incr;
new_incr->rn = rn;
new_incr->standby = standby;
if (!standby)
- new_incr->usecount = 1;
+ new_incr->usecount = rzm > MEM_SCT_SIZE ? rzm/MEM_SCT_SIZE : 1;
last_rn = 0;
prev = &sclp_mem_list;
list_for_each_entry(incr, &sclp_mem_list, list) {
index a43415a7fbedfa7dd537d2dc48581904adbb3db9..bc75528224d507c2fc3f3a279a221dd9c55a86c1 100644 (file)
return 0;
}
}
+
+void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
+{
+ u32 pmu_ctl = 0;
+
+ switch (cc->dev->bus->chip_id) {
+ case 0x4322:
+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
+ if (spuravoid == 1)
+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
+ else
+ ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
+ pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
+ break;
+ case 43222:
+ /* TODO: BCM43222 requires updating PLLs too */
+ return;
+ default:
+ ssb_printk(KERN_ERR PFX
+ "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
+ cc->dev->bus->chip_id);
+ return;
+ }
+
+ chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
+}
+EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
index 84eba0728844227bbb871fc7af850f649f89c357..79f217e9bd300de26bc2dc89707adf514a87e13c 100644 (file)
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
source "drivers/staging/net/Kconfig"
-source "drivers/staging/omapdrm/Kconfig"
-
source "drivers/staging/android/Kconfig"
source "drivers/staging/ozwpan/Kconfig"
index 5cce2cfe374c06fc6099cb0f7ba627d7a795f2d8..3081e1c0d62b0916c838472ccc14b3de0ddc987d 100644 (file)
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
obj-$(CONFIG_TOUCHSCREEN_CLEARPAD_TM1217) += cptm1217/
obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) += ste_rmi4/
obj-$(CONFIG_MFD_NVEC) += nvec/
-obj-$(CONFIG_DRM_OMAP) += omapdrm/
obj-$(CONFIG_ANDROID) += android/
obj-$(CONFIG_USB_WPAN_HCD) += ozwpan/
obj-$(CONFIG_USB_G_CCG) += ccg/
diff --git a/drivers/staging/omapdrm/TODO b/drivers/staging/omapdrm/TODO
+++ /dev/null
@@ -1,32 +0,0 @@
-TODO
-. add video decode/encode support (via syslink3 + codec-engine)
- . NOTE: with dmabuf this probably could be split into different driver
- so perhaps this TODO doesn't belong here
-. where should we do eviction (detatch_pages())? We aren't necessarily
- accessing the pages via a GART, so maybe we need some other threshold
- to put a cap on the # of pages that can be pin'd. (It is mostly only
- of interest in case you have a swap partition/file.. which a lot of
- these devices do not.. but it doesn't hurt for the driver to do the
- right thing anyways.)
- . Use mm_shrinker to trigger unpinning pages. Need to figure out how
- to handle next issue first (I think?)
- . Note TTM already has some mm_shrinker stuff.. maybe an argument to
- move to TTM? Or maybe something that could be factored out in common?
-. GEM/shmem backed pages can have existing mappings (kernel linear map,
- etc..), which isn't really ideal.
-. Revisit GEM sync object infrastructure.. TTM has some framework for this
- already. Possibly this could be refactored out and made more common?
- There should be some way to do this with less wheel-reinvention.
-. Solve PM sequencing on resume. DMM/TILER must be reloaded before any
- access is made from any component in the system. Which means on suspend
- CRTC's should be disabled, and on resume the LUT should be reprogrammed
- before CRTC's are re-enabled, to prevent DSS from trying to DMA from a
- buffer mapped in DMM/TILER before LUT is reloaded.
-
-Userspace:
-. git://github.com/robclark/xf86-video-omap.git
-
-Currently tested on
-. OMAP3530 beagleboard
-. OMAP4430 pandaboard
-. OMAP4460 pandaboard
index e81375fb21552413f3df4689e4c950aab820eb8e..bd4c7beba67915200d6e44c505a49f44a3442978 100644 (file)
This includes alert interrupts generation and also the TSHUT
support.
+
+config DRA752_THERMAL
+ bool "Texas Instruments DRA752 thermal support"
+ depends on TI_SOC_THERMAL
+ depends on SOC_DRA7XX
+ help
+ If you say yes here you get thermal support for the Texas Instruments
+ DRA752 SoC family. The current chip supported are:
+ - DRA752
+
+ This includes alert interrupts generation and also the TSHUT
+ support.
index 0ca034fb419de8dbfa05d5894195f9a4065d5f85..1226b2484e550cba08e6233c6fdb56f02a54fef0 100644 (file)
obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal.o
ti-soc-thermal-y := ti-bandgap.o
ti-soc-thermal-$(CONFIG_TI_THERMAL) += ti-thermal-common.o
+ti-soc-thermal-$(CONFIG_DRA752_THERMAL) += dra752-thermal-data.o
ti-soc-thermal-$(CONFIG_OMAP4_THERMAL) += omap4-thermal-data.o
ti-soc-thermal-$(CONFIG_OMAP5_THERMAL) += omap5-thermal-data.o
diff --git a/drivers/staging/ti-soc-thermal/dra752-bandgap.h b/drivers/staging/ti-soc-thermal/dra752-bandgap.h
--- /dev/null
@@ -0,0 +1,280 @@
+/*
+ * DRA752 bandgap registers, bitfields and temperature definitions
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact:
+ * Eduardo Valentin <eduardo.valentin@ti.com>
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This is an auto generated file.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+#ifndef __DRA752_BANDGAP_H
+#define __DRA752_BANDGAP_H
+
+/**
+ * *** DRA752 ***
+ *
+ * Below, in sequence, are the Register definitions,
+ * the bitfields and the temperature definitions for DRA752.
+ */
+
+/**
+ * DRA752 register definitions
+ *
+ * Registers are defined as offsets. The offsets are
+ * relative to FUSE_OPP_BGAP_GPU on DRA752.
+ * DRA752_BANDGAP_BASE 0x4a0021e0
+ *
+ * Register below are grouped by domain (not necessarily in offset order)
+ */
+
+
+/* DRA752.common register offsets */
+#define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0
+#define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8
+#define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c
+#define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8
+
+/* DRA752.core register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
+#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
+#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
+#define DRA752_BANDGAP_TSHUT_CORE_OFFSET 0x1b8
+#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4
+#define DRA752_DTEMP_CORE_0_OFFSET 0x208
+#define DRA752_DTEMP_CORE_1_OFFSET 0x20c
+#define DRA752_DTEMP_CORE_2_OFFSET 0x210
+#define DRA752_DTEMP_CORE_3_OFFSET 0x214
+#define DRA752_DTEMP_CORE_4_OFFSET 0x218
+
+/* DRA752.iva register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
+#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
+#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
+#define DRA752_BANDGAP_TSHUT_IVA_OFFSET 0x3ac
+#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4
+#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0
+#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
+#define DRA752_DTEMP_IVA_2_OFFSET 0x3d8
+#define DRA752_DTEMP_IVA_3_OFFSET 0x3dc
+#define DRA752_DTEMP_IVA_4_OFFSET 0x3e0
+
+/* DRA752.mpu register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
+#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
+#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
+#define DRA752_BANDGAP_TSHUT_MPU_OFFSET 0x1b0
+#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc
+#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0
+#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
+#define DRA752_DTEMP_MPU_2_OFFSET 0x1e8
+#define DRA752_DTEMP_MPU_3_OFFSET 0x1ec
+#define DRA752_DTEMP_MPU_4_OFFSET 0x1f0
+
+/* DRA752.dspeve register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
+#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
+#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
+#define DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET 0x3a8
+#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0
+#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc
+#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
+#define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4
+#define DRA752_DTEMP_DSPEVE_3_OFFSET 0x3c8
+#define DRA752_DTEMP_DSPEVE_4_OFFSET 0x3cc
+
+/* DRA752.gpu register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
+#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
+#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
+#define DRA752_BANDGAP_TSHUT_GPU_OFFSET 0x1b4
+#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0
+#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4
+#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
+#define DRA752_DTEMP_GPU_2_OFFSET 0x1fc
+#define DRA752_DTEMP_GPU_3_OFFSET 0x200
+#define DRA752_DTEMP_GPU_4_OFFSET 0x204
+
+/**
+ * Register bitfields for DRA752
+ *
+ * All the macros bellow define the required bits for
+ * controlling temperature on DRA752. Bit defines are
+ * grouped by register.
+ */
+
+/* DRA752.BANDGAP_STATUS_1 */
+#define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31)
+#define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
+#define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
+#define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
+#define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2)
+#define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1)
+#define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0)
+
+/* DRA752.BANDGAP_CTRL_2 */
+#define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
+#define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
+#define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19)
+#define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK BIT(18)
+#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK BIT(16)
+#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK BIT(15)
+#define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3)
+#define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2)
+#define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1)
+#define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0)
+
+/* DRA752.BANDGAP_STATUS_2 */
+#define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3)
+#define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2)
+#define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1)
+#define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0)
+
+/* DRA752.BANDGAP_CTRL_1 */
+#define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK (0x3 << 30)
+#define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27)
+#define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23)
+#define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22)
+#define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK BIT(20)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK BIT(19)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK BIT(18)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK BIT(17)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK BIT(16)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK BIT(15)
+#define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5)
+#define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4)
+#define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3)
+#define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2)
+#define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1)
+#define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0)
+
+/* DRA752.TEMP_SENSOR */
+#define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11)
+#define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10)
+#define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
+
+/* DRA752.BANDGAP_THRESHOLD */
+#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
+#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
+
+/* DRA752.TSHUT_THRESHOLD */
+#define DRA752_TSHUT_THRESHOLD_MUXCTRL_MASK BIT(31)
+#define DRA752_TSHUT_THRESHOLD_HOT_MASK (0x3ff << 16)
+#define DRA752_TSHUT_THRESHOLD_COLD_MASK (0x3ff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
+#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_IVA */
+#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK (0xffffffff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_MPU */
+#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */
+#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK (0xffffffff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_GPU */
+#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
+
+/**
+ * Temperature limits and thresholds for DRA752
+ *
+ * All the macros bellow are definitions for handling the
+ * ADC conversions and representation of temperature limits
+ * and thresholds for DRA752. Definitions are grouped
+ * by temperature domain.
+ */
+
+/* DRA752.common temperature definitions */
+/* ADC conversion table limits */
+#define DRA752_ADC_START_VALUE 540
+#define DRA752_ADC_END_VALUE 945
+
+/* DRA752.GPU temperature definitions */
+/* bandgap clock limits */
+#define DRA752_GPU_MAX_FREQ 1500000
+#define DRA752_GPU_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_GPU_MIN_TEMP -40000
+#define DRA752_GPU_MAX_TEMP 125000
+#define DRA752_GPU_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_GPU_TSHUT_HOT 915
+#define DRA752_GPU_TSHUT_COLD 900
+#define DRA752_GPU_T_HOT 800
+#define DRA752_GPU_T_COLD 795
+
+/* DRA752.MPU temperature definitions */
+/* bandgap clock limits */
+#define DRA752_MPU_MAX_FREQ 1500000
+#define DRA752_MPU_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_MPU_MIN_TEMP -40000
+#define DRA752_MPU_MAX_TEMP 125000
+#define DRA752_MPU_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_MPU_TSHUT_HOT 915
+#define DRA752_MPU_TSHUT_COLD 900
+#define DRA752_MPU_T_HOT 800
+#define DRA752_MPU_T_COLD 795
+
+/* DRA752.CORE temperature definitions */
+/* bandgap clock limits */
+#define DRA752_CORE_MAX_FREQ 1500000
+#define DRA752_CORE_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_CORE_MIN_TEMP -40000
+#define DRA752_CORE_MAX_TEMP 125000
+#define DRA752_CORE_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_CORE_TSHUT_HOT 915
+#define DRA752_CORE_TSHUT_COLD 900
+#define DRA752_CORE_T_HOT 800
+#define DRA752_CORE_T_COLD 795
+
+/* DRA752.DSPEVE temperature definitions */
+/* bandgap clock limits */
+#define DRA752_DSPEVE_MAX_FREQ 1500000
+#define DRA752_DSPEVE_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_DSPEVE_MIN_TEMP -40000
+#define DRA752_DSPEVE_MAX_TEMP 125000
+#define DRA752_DSPEVE_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_DSPEVE_TSHUT_HOT 915
+#define DRA752_DSPEVE_TSHUT_COLD 900
+#define DRA752_DSPEVE_T_HOT 800
+#define DRA752_DSPEVE_T_COLD 795
+
+/* DRA752.IVA temperature definitions */
+/* bandgap clock limits */
+#define DRA752_IVA_MAX_FREQ 1500000
+#define DRA752_IVA_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_IVA_MIN_TEMP -40000
+#define DRA752_IVA_MAX_TEMP 125000
+#define DRA752_IVA_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_IVA_TSHUT_HOT 915
+#define DRA752_IVA_TSHUT_COLD 900
+#define DRA752_IVA_T_HOT 800
+#define DRA752_IVA_T_COLD 795
+
+#endif /* __DRA752_BANDGAP_H */
diff --git a/drivers/staging/ti-soc-thermal/dra752-thermal-data.c b/drivers/staging/ti-soc-thermal/dra752-thermal-data.c
--- /dev/null
@@ -0,0 +1,476 @@
+/*
+ * DRA752 thermal data.
+ *
+ * Copyright (C) 2013 Texas Instruments Inc.
+ * Contact:
+ * Eduardo Valentin <eduardo.valentin@ti.com>
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This file is partially autogenerated.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "ti-thermal.h"
+#include "ti-bandgap.h"
+#include "dra752-bandgap.h"
+
+/*
+ * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
+ * IVA and DSPEVE need to describe the individual registers and
+ * bit fields.
+ */
+
+/*
+ * DRA752 CORE thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_core_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
+};
+
+/*
+ * DRA752 IVA thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_iva_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
+};
+
+/*
+ * DRA752 MPU thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_mpu_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
+};
+
+/*
+ * DRA752 DSPEVE thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_dspeve_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
+};
+
+/*
+ * DRA752 GPU thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_gpu_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_GPU_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
+};
+
+/* Thresholds and limits for DRA752 MPU temperature sensor */
+static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
+ .tshut_hot = DRA752_MPU_TSHUT_HOT,
+ .tshut_cold = DRA752_MPU_TSHUT_COLD,
+ .t_hot = DRA752_MPU_T_HOT,
+ .t_cold = DRA752_MPU_T_COLD,
+ .min_freq = DRA752_MPU_MIN_FREQ,
+ .max_freq = DRA752_MPU_MAX_FREQ,
+ .max_temp = DRA752_MPU_MAX_TEMP,
+ .min_temp = DRA752_MPU_MIN_TEMP,
+ .hyst_val = DRA752_MPU_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/* Thresholds and limits for DRA752 GPU temperature sensor */
+static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
+ .tshut_hot = DRA752_GPU_TSHUT_HOT,
+ .tshut_cold = DRA752_GPU_TSHUT_COLD,
+ .t_hot = DRA752_GPU_T_HOT,
+ .t_cold = DRA752_GPU_T_COLD,
+ .min_freq = DRA752_GPU_MIN_FREQ,
+ .max_freq = DRA752_GPU_MAX_FREQ,
+ .max_temp = DRA752_GPU_MAX_TEMP,
+ .min_temp = DRA752_GPU_MIN_TEMP,
+ .hyst_val = DRA752_GPU_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/* Thresholds and limits for DRA752 CORE temperature sensor */
+static struct temp_sensor_data dra752_core_temp_sensor_data = {
+ .tshut_hot = DRA752_CORE_TSHUT_HOT,
+ .tshut_cold = DRA752_CORE_TSHUT_COLD,
+ .t_hot = DRA752_CORE_T_HOT,
+ .t_cold = DRA752_CORE_T_COLD,
+ .min_freq = DRA752_CORE_MIN_FREQ,
+ .max_freq = DRA752_CORE_MAX_FREQ,
+ .max_temp = DRA752_CORE_MAX_TEMP,
+ .min_temp = DRA752_CORE_MIN_TEMP,
+ .hyst_val = DRA752_CORE_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/* Thresholds and limits for DRA752 DSPEVE temperature sensor */
+static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
+ .tshut_hot = DRA752_DSPEVE_TSHUT_HOT,
+ .tshut_cold = DRA752_DSPEVE_TSHUT_COLD,
+ .t_hot = DRA752_DSPEVE_T_HOT,
+ .t_cold = DRA752_DSPEVE_T_COLD,
+ .min_freq = DRA752_DSPEVE_MIN_FREQ,
+ .max_freq = DRA752_DSPEVE_MAX_FREQ,
+ .max_temp = DRA752_DSPEVE_MAX_TEMP,
+ .min_temp = DRA752_DSPEVE_MIN_TEMP,
+ .hyst_val = DRA752_DSPEVE_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/* Thresholds and limits for DRA752 IVA temperature sensor */
+static struct temp_sensor_data dra752_iva_temp_sensor_data = {
+ .tshut_hot = DRA752_IVA_TSHUT_HOT,
+ .tshut_cold = DRA752_IVA_TSHUT_COLD,
+ .t_hot = DRA752_IVA_T_HOT,
+ .t_cold = DRA752_IVA_T_COLD,
+ .min_freq = DRA752_IVA_MIN_FREQ,
+ .max_freq = DRA752_IVA_MAX_FREQ,
+ .max_temp = DRA752_IVA_MAX_TEMP,
+ .min_temp = DRA752_IVA_MIN_TEMP,
+ .hyst_val = DRA752_IVA_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/*
+ * DRA752 : Temperature values in milli degree celsius
+ * ADC code values from 540 to 945
+ */
+static
+int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = {
+ /* Index 540 - 549 */
+ -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
+ -37800,
+ /* Index 550 - 559 */
+ -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
+ -33400,
+ /* Index 560 - 569 */
+ -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
+ -29400,
+ /* Index 570 - 579 */
+ -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
+ -25000,
+ /* Index 580 - 589 */
+ -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400,
+ -21000,
+ /* Index 590 - 599 */
+ -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
+ -16600,
+ /* Index 600 - 609 */
+ -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
+ -12500,
+ /* Index 610 - 619 */
+ -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
+ -8200,
+ /* Index 620 - 629 */
+ -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500,
+ -3900,
+ /* Index 630 - 639 */
+ -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200,
+ 200,
+ /* Index 640 - 649 */
+ 600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900,
+ 4500,
+ /* Index 650 - 659 */
+ 5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200,
+ 8600,
+ /* Index 660 - 669 */
+ 9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200,
+ 12700,
+ /* Index 670 - 679 */
+ 13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600,
+ 17000,
+ /* Index 680 - 689 */
+ 17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600,
+ 21000,
+ /* Index 690 - 699 */
+ 21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000,
+ 25400,
+ /* Index 700 - 709 */
+ 25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000,
+ 29400,
+ /* Index 710 - 719 */
+ 29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400,
+ 33800,
+ /* Index 720 - 729 */
+ 34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400,
+ 37800,
+ /* Index 730 - 739 */
+ 38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400,
+ 41800,
+ /* Index 740 - 749 */
+ 42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800,
+ 46200,
+ /* Index 750 - 759 */
+ 46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800,
+ 50200,
+ /* Index 760 - 769 */
+ 50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800,
+ 54200,
+ /* Index 770 - 779 */
+ 54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200,
+ 58600,
+ /* Index 780 - 789 */
+ 59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200,
+ 62600,
+ /* Index 790 - 799 */
+ 63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
+ 66600,
+ /* Index 800 - 809 */
+ 67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200,
+ 70600,
+ /* Index 810 - 819 */
+ 71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600,
+ 75000,
+ /* Index 820 - 829 */
+ 75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600,
+ 79000,
+ /* Index 830 - 839 */
+ 79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600,
+ 83000,
+ /* Index 840 - 849 */
+ 83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600,
+ 87000,
+ /* Index 850 - 859 */
+ 87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600,
+ 91000,
+ /* Index 860 - 869 */
+ 91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600,
+ 95000,
+ /* Index 870 - 879 */
+ 95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000,
+ 99400,
+ /* Index 880 - 889 */
+ 99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
+ 103400,
+ /* Index 890 - 899 */
+ 103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
+ 107400,
+ /* Index 900 - 909 */
+ 107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
+ 111400,
+ /* Index 910 - 919 */
+ 111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
+ 115400,
+ /* Index 920 - 929 */
+ 115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
+ 119400,
+ /* Index 930 - 939 */
+ 119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000,
+ 123400,
+ /* Index 940 - 945 */
+ 123800, 124200, 124600, 124900, 125000, 125000,
+};
+
+/* DRA752 data */
+const struct ti_bandgap_data dra752_data = {
+ .features = TI_BANDGAP_FEATURE_TSHUT_CONFIG |
+ TI_BANDGAP_FEATURE_FREEZE_BIT |
+ TI_BANDGAP_FEATURE_TALERT |
+ TI_BANDGAP_FEATURE_COUNTER_DELAY |
+ TI_BANDGAP_FEATURE_HISTORY_BUFFER,
+ .fclock_name = "l3instr_ts_gclk_div",
+ .div_ck_name = "l3instr_ts_gclk_div",
+ .conv_table = dra752_adc_to_temp,
+ .adc_start_val = DRA752_ADC_START_VALUE,
+ .adc_end_val = DRA752_ADC_END_VALUE,
+ .expose_sensor = ti_thermal_expose_sensor,
+ .remove_sensor = ti_thermal_remove_sensor,
+ .sensors = {
+ {
+ .registers = &dra752_mpu_temp_sensor_registers,
+ .ts_data = &dra752_mpu_temp_sensor_data,
+ .domain = "cpu",
+ .register_cooling = ti_thermal_register_cpu_cooling,
+ .unregister_cooling = ti_thermal_unregister_cpu_cooling,
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ {
+ .registers = &dra752_gpu_temp_sensor_registers,
+ .ts_data = &dra752_gpu_temp_sensor_data,
+ .domain = "gpu",
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ {
+ .registers = &dra752_core_temp_sensor_registers,
+ .ts_data = &dra752_core_temp_sensor_data,
+ .domain = "core",
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ {
+ .registers = &dra752_dspeve_temp_sensor_registers,
+ .ts_data = &dra752_dspeve_temp_sensor_data,
+ .domain = "dspeve",
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ {
+ .registers = &dra752_iva_temp_sensor_registers,
+ .ts_data = &dra752_iva_temp_sensor_data,
+ .domain = "iva",
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ },
+ .sensor_count = 5,
+};
diff --git a/drivers/staging/ti-soc-thermal/ti-bandgap.c b/drivers/staging/ti-soc-thermal/ti-bandgap.c
index 4c25aea26f7d3356260abb20608900626e22622c..16dd07b6850a42ebf55ff51c565337a63114ca70 100644 (file)
.compatible = "ti,omap5430-bandgap",
.data = (void *)&omap5430_data,
},
+#endif
+#ifdef CONFIG_DRA752_THERMAL
+ {
+ .compatible = "ti,dra752-bandgap",
+ .data = (void *)&dra752_data,
+ },
#endif
/* Sentinel */
{ },
diff --git a/drivers/staging/ti-soc-thermal/ti-bandgap.h b/drivers/staging/ti-soc-thermal/ti-bandgap.h
index 5f4794abf58345d5b4b7bc09f8636e203c48c5fd..b3adf72f252d310779e5014b9ee272bf2a499946 100644 (file)
#define omap5430_data NULL
#endif
+#ifdef CONFIG_DRA752_THERMAL
+extern const struct ti_bandgap_data dra752_data;
+#else
+#define dra752_data NULL
+#endif
#endif
diff --git a/drivers/staging/ti-soc-thermal/ti-thermal-common.c b/drivers/staging/ti-soc-thermal/ti-thermal-common.c
index e3c5e677eaa5c7a13007354b9fa3d2f99bc4b125..8e67ebf98404bcc69dad79f146133ba17d52d17e 100644 (file)
/* common data structures */
struct ti_thermal_data {
struct thermal_zone_device *ti_thermal;
+ struct thermal_zone_device *pcb_tz;
struct thermal_cooling_device *cool_dev;
struct ti_bandgap *bgp;
enum thermal_device_mode mode;
static inline int ti_thermal_get_temp(struct thermal_zone_device *thermal,
unsigned long *temp)
{
+ struct thermal_zone_device *pcb_tz = NULL;
struct ti_thermal_data *data = thermal->devdata;
struct ti_bandgap *bgp;
const struct ti_temp_sensor *s;
- int ret, tmp, pcb_temp, slope, constant;
+ int ret, tmp, slope, constant;
+ unsigned long pcb_temp;
if (!data)
return 0;
if (ret)
return ret;
- pcb_temp = 0;
- /* TODO: Introduce pcb temperature lookup */
+ /* Default constants */
+ slope = s->slope;
+ constant = s->constant;
+
+ pcb_tz = data->pcb_tz;
/* In case pcb zone is available, use the extrapolation rule with it */
- if (pcb_temp) {
- tmp -= pcb_temp;
- slope = s->slope_pcb;
- constant = s->constant_pcb;
- } else {
- slope = s->slope;
- constant = s->constant;
+ if (!IS_ERR_OR_NULL(pcb_tz)) {
+ ret = thermal_zone_get_temp(pcb_tz, &pcb_temp);
+ if (!ret) {
+ tmp -= pcb_temp; /* got a valid PCB temp */
+ slope = s->slope_pcb;
+ constant = s->constant_pcb;
+ } else {
+ dev_err(bgp->dev,
+ "Failed to read PCB state. Using defaults\n");
+ }
}
*temp = ti_thermal_hotspot_temperature(tmp, slope, constant);
data->sensor_id = id;
data->bgp = bgp;
data->mode = THERMAL_DEVICE_ENABLED;
+ data->pcb_tz = thermal_zone_get_zone_by_name("pcb");
INIT_WORK(&data->thermal_wq, ti_thermal_work);
return data;
diff --git a/drivers/staging/ti-soc-thermal/ti-thermal.h b/drivers/staging/ti-soc-thermal/ti-thermal.h
index 8e9256d6c65cc65604f648c8ef55a875855c80c4..9e538035690269c1962688e4e7fa71ea114e1035 100644 (file)
#define OMAP_GRADIENT_SLOPE_5430_GPU 117
#define OMAP_GRADIENT_CONST_5430_GPU -2992
+#define DRA752_GRADIENT_SLOPE 0
+#define DRA752_GRADIENT_CONST 2000
+
/* PCB sensor calculation constants */
#define OMAP_GRADIENT_SLOPE_W_PCB_4430 0
#define OMAP_GRADIENT_CONST_W_PCB_4430 20000
#define OMAP_GRADIENT_SLOPE_W_PCB_5430_GPU 464
#define OMAP_GRADIENT_CONST_W_PCB_5430_GPU -5102
+#define DRA752_GRADIENT_SLOPE_W_PCB 0
+#define DRA752_GRADIENT_CONST_W_PCB 2000
+
/* trip points of interest in milicelsius (at hotspot level) */
#define OMAP_TRIP_COLD 100000
#define OMAP_TRIP_HOT 110000
diff --git a/drivers/staging/ti-soc-thermal/ti_soc_thermal.txt b/drivers/staging/ti-soc-thermal/ti_soc_thermal.txt
index a4a33d1a07464a75b0b00e31adcb1b5c159144ce..25697a53a98e19e55d48beb1fcf1b354da06e14f 100644 (file)
0x4a0023C0 0x3c>;
compatible = "ti,omap5430-bandgap";
};
+
+DRA752:
+bandgap {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50>;
+ compatible = "ti,dra752-bandgap";
+ interrupts = <0 126 4>; /* talert */
+};
index 908456565796770c44065eb432622071bf8cbcf2..7fab032298f33986cd55b518d3db60eebadb4d9b 100644 (file)
config ZSMALLOC
- tristate "Memory allocator for compressed pages"
+ bool "Memory allocator for compressed pages"
default n
help
zsmalloc is a slab-based memory allocator designed to store
index 223c7361cf9787bc52bdc42bf7689b5bdb391ca5..851a2fff3705c7f3079ff57e27ea50fb1f93b377 100644 (file)
struct page *pages[2], int off, int size)
{
unsigned long addr = (unsigned long)area->vm_addr;
- unsigned long end = addr + (PAGE_SIZE * 2);
- flush_cache_vunmap(addr, end);
- unmap_kernel_range_noflush(addr, PAGE_SIZE * 2);
- flush_tlb_kernel_range(addr, end);
+ unmap_kernel_range(addr, PAGE_SIZE * 2);
}
#else /* USE_PGTABLE_MAPPING */
index 1a19a2f4ba2744b7a7d06abe1f949224f83ad3c5..9edf0e321637daf3c532bb7f95e1553dde0a08cc 100644 (file)
{
enum thermal_trend trend;
- if (!tz->ops->get_trend || tz->ops->get_trend(tz, trip, &trend)) {
+ if (tz->emul_temperature || !tz->ops->get_trend ||
+ tz->ops->get_trend(tz, trip, &trend)) {
if (tz->temperature > tz->last_temperature)
trend = THERMAL_TREND_RAISING;
else if (tz->temperature < tz->last_temperature)
monitor_thermal_zone(tz);
}
-static int thermal_zone_get_temp(struct thermal_zone_device *tz,
- unsigned long *temp)
+/**
+ * thermal_zone_get_temp() - returns its the temperature of thermal zone
+ * @tz: a valid pointer to a struct thermal_zone_device
+ * @temp: a valid pointer to where to store the resulting temperature.
+ *
+ * When a valid thermal zone reference is passed, it will fetch its
+ * temperature and fill @temp.
+ *
+ * Return: On success returns 0, an error code otherwise
+ */
+int thermal_zone_get_temp(struct thermal_zone_device *tz, unsigned long *temp)
{
- int ret = 0;
+ int ret = -EINVAL;
#ifdef CONFIG_THERMAL_EMULATION
int count;
unsigned long crit_temp = -1UL;
enum thermal_trip_type type;
#endif
+ if (IS_ERR_OR_NULL(tz))
+ goto exit;
+
mutex_lock(&tz->lock);
ret = tz->ops->get_temp(tz, temp);
skip_emul:
#endif
mutex_unlock(&tz->lock);
+exit:
return ret;
}
+EXPORT_SYMBOL_GPL(thermal_zone_get_temp);
static void update_temperature(struct thermal_zone_device *tz)
{
}
EXPORT_SYMBOL(thermal_zone_device_unregister);
+/**
+ * thermal_zone_get_zone_by_name() - search for a zone and returns its ref
+ * @name: thermal zone name to fetch the temperature
+ *
+ * When only one zone is found with the passed name, returns a reference to it.
+ *
+ * Return: On success returns a reference to an unique thermal zone with
+ * matching name equals to @name, an ERR_PTR otherwise (-EINVAL for invalid
+ * paramenters, -ENODEV for not found and -EEXIST for multiple matches).
+ */
+struct thermal_zone_device *thermal_zone_get_zone_by_name(const char *name)
+{
+ struct thermal_zone_device *pos = NULL, *ref = ERR_PTR(-EINVAL);
+ unsigned int found = 0;
+
+ if (!name)
+ goto exit;
+
+ mutex_lock(&thermal_list_lock);
+ list_for_each_entry(pos, &thermal_tz_list, node)
+ if (!strnicmp(name, pos->type, THERMAL_NAME_LENGTH)) {
+ found++;
+ ref = pos;
+ }
+ mutex_unlock(&thermal_list_lock);
+
+ /* nothing has been found, thus an error code for it */
+ if (found == 0)
+ ref = ERR_PTR(-ENODEV);
+ else if (found > 1)
+ /* Success only when an unique zone is found */
+ ref = ERR_PTR(-EEXIST);
+
+exit:
+ return ref;
+}
+EXPORT_SYMBOL_GPL(thermal_zone_get_zone_by_name);
+
#ifdef CONFIG_NET
static struct genl_family thermal_event_genl_family = {
.id = GENL_ID_GENERATE,
diff --git a/drivers/tty/pty.c b/drivers/tty/pty.c
index ac35c901c8590a58a0ebc9d82310d163c8b081f8..c830b604c96f6e41a15e1ca919bf1ac0fc7be17b 100644 (file)
--- a/drivers/tty/pty.c
+++ b/drivers/tty/pty.c
nonseekable_open(inode, filp);
+ /* We refuse fsnotify events on ptmx, since it's a shared resource */
+ filp->f_mode |= FMODE_NONOTIFY;
+
retval = tty_alloc_file(filp);
if (retval)
return retval;
index 7c23c4f4c58d4ddceaadc0a768559692c2f4a185..4d791711396ce01aad59f30778b66b1903e7d794 100644 (file)
static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id);
static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port);
-
-/* Simple macro to test if a port is console or not. This one is taken
- * for serial_core.c and maybe should be moved to serial_core.h ? */
-#ifdef CONFIG_SERIAL_CORE_CONSOLE
-#define uart_console(port) \
- ((port)->cons && (port)->cons->index == (port)->line)
-#else
-#define uart_console(port) (0)
-#endif
-
/* ======================================================================== */
/* PSC fifo operations for isolating differences between 52xx and 512x */
/* ======================================================================== */
index 5722eaf302944e5b3e56f20b88703d1a71973242..352fcef5e8dda71fd7bc984302824f369f5dc370 100644 (file)
/* SCR register bitmasks */
#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
+#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
/* FCR register bitmasks */
u32 calc_latency;
struct work_struct qos_work;
struct pinctrl *pins;
+ bool is_suspending;
};
#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
pdata->enable_wakeup(up->dev, enable);
}
+/*
+ * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
+ * @port: uart port info
+ * @baud: baudrate for which mode needs to be determined
+ *
+ * Returns true if baud rate is MODE16X and false if MODE13X
+ * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
+ * and Error Rates" determines modes not for all common baud rates.
+ * E.g. for 1000000 baud rate mode must be 16x, but according to that
+ * table it's determined as 13x.
+ */
+static bool
+serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
+{
+ unsigned int n13 = port->uartclk / (13 * baud);
+ unsigned int n16 = port->uartclk / (16 * baud);
+ int baudAbsDiff13 = baud - (port->uartclk / (13 * n13));
+ int baudAbsDiff16 = baud - (port->uartclk / (16 * n16));
+ if(baudAbsDiff13 < 0)
+ baudAbsDiff13 = -baudAbsDiff13;
+ if(baudAbsDiff16 < 0)
+ baudAbsDiff16 = -baudAbsDiff16;
+
+ return (baudAbsDiff13 > baudAbsDiff16);
+}
+
/*
* serial_omap_get_divisor - calculate divisor value
* @port: uart port info
* @baud: baudrate for which divisor needs to be calculated.
- *
- * We have written our own function to get the divisor so as to support
- * 13x mode. 3Mbps Baudrate as an different divisor.
- * Reference OMAP TRM Chapter 17:
- * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
- * referring to oversampling - divisor value
- * baudrate 460,800 to 3,686,400 all have divisor 13
- * except 3,000,000 which has divisor value 16
*/
static unsigned int
serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
{
unsigned int divisor;
- if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
+ if (!serial_omap_baud_is_mode16(port, baud))
divisor = 13;
else
divisor = 16;
struct circ_buf *xmit = &up->port.state->xmit;
int count;
- if (!(lsr & UART_LSR_THRE))
- return;
-
if (up->port.x_char) {
serial_out(up, UART_TX, up->port.x_char);
up->port.icount.tx++;
cval |= UART_LCR_PARITY;
if (!(termios->c_cflag & PARODD))
cval |= UART_LCR_EPAR;
+ if (termios->c_cflag & CMSPAR)
+ cval |= UART_LCR_SPAR;
/*
* Ask the core to calculate the divisor for us.
serial_out(up, UART_IER, up->ier);
serial_out(up, UART_LCR, cval); /* reset DLAB */
up->lcr = cval;
- up->scr = OMAP_UART_SCR_TX_EMPTY;
+ up->scr = 0;
/* FIFOs and DMA Settings */
/* FIFO ENABLE, DMA MODE */
up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
+ /*
+ * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
+ * sets Enables the granularity of 1 for TRIGGER RX
+ * level. Along with setting RX FIFO trigger level
+ * to 1 (as noted below, 16 characters) and TLR[3:0]
+ * to zero this will result RX FIFO threshold level
+ * to 1 character, instead of 16 as noted in comment
+ * below.
+ */
/* Set receive FIFO threshold to 16 characters and
* transmit FIFO threshold to 16 spaces
serial_out(up, UART_EFR, up->efr);
serial_out(up, UART_LCR, cval);
- if (baud > 230400 && baud != 3000000)
+ if (!serial_omap_baud_is_mode16(port, baud))
up->mdr1 = UART_OMAP_MDR1_13X_MODE;
else
up->mdr1 = UART_OMAP_MDR1_16X_MODE;
};
#ifdef CONFIG_PM_SLEEP
+static int serial_omap_prepare(struct device *dev)
+{
+ struct uart_omap_port *up = dev_get_drvdata(dev);
+
+ up->is_suspending = true;
+
+ return 0;
+}
+
+static void serial_omap_complete(struct device *dev)
+{
+ struct uart_omap_port *up = dev_get_drvdata(dev);
+
+ up->is_suspending = false;
+}
+
static int serial_omap_suspend(struct device *dev)
{
struct uart_omap_port *up = dev_get_drvdata(dev);
return 0;
}
-#endif
+#else
+#define serial_omap_prepare NULL
+#define serial_omap_prepare NULL
+#endif /* CONFIG_PM_SLEEP */
static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
{
struct uart_omap_port *up = dev_get_drvdata(dev);
struct omap_uart_port_info *pdata = dev->platform_data;
+ /*
+ * When using 'no_console_suspend', the console UART must not be
+ * suspended. Since driver suspend is managed by runtime suspend,
+ * preventing runtime suspend (by returning error) will keep device
+ * active during suspend.
+ */
+ if (up->is_suspending && !console_suspend_enabled &&
+ uart_console(&up->port))
+ return -EBUSY;
+
if (!up)
return -EINVAL;
SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
serial_omap_runtime_resume, NULL)
+ .prepare = serial_omap_prepare,
+ .complete = serial_omap_complete,
};
#if defined(CONFIG_OF)
index aa2e85dc1e2251e29e32af6f06ca15bc55f7c902..cbbd11a0722f8b5793fc1dbefd6b54af9d178273 100644 (file)
#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
-#ifdef CONFIG_SERIAL_CORE_CONSOLE
-#define uart_console(port) ((port)->cons && (port)->cons->index == (port)->line)
-#else
-#define uart_console(port) (0)
-#endif
-
static void uart_change_speed(struct tty_struct *tty, struct uart_state *state,
struct ktermios *old_termios);
static void uart_wait_until_sent(struct tty_struct *tty, int timeout);
mutex_unlock(&port->mutex);
return 0;
}
+ put_device(tty_dev);
+
if (console_suspend_enabled || !uart_console(uport))
uport->suspended = 1;
disable_irq_wake(uport->irq);
uport->irq_wake = 0;
}
+ put_device(tty_dev);
mutex_unlock(&port->mutex);
return 0;
}
+ put_device(tty_dev);
uport->suspended = 0;
/*
diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c
index da9fde85075499404c3e77ffb9291ac58f5d7785..f34f98df509d03dfeb47174f2bc38a55d5880b5b 100644 (file)
--- a/drivers/tty/tty_io.c
+++ b/drivers/tty/tty_io.c
EXPORT_SYMBOL(start_tty);
+/* We limit tty time update visibility to every 8 seconds or so. */
+static void tty_update_time(struct timespec *time)
+{
+ unsigned long sec = get_seconds() & ~7;
+ if ((long)(sec - time->tv_sec) > 0)
+ time->tv_sec = sec;
+}
+
/**
* tty_read - read method for tty device files
* @file: pointer to tty file
else
i = -EIO;
tty_ldisc_deref(ld);
+
if (i > 0)
- inode->i_atime = current_fs_time(inode->i_sb);
+ tty_update_time(&inode->i_atime);
+
return i;
}
}
if (written) {
struct inode *inode = file->f_path.dentry->d_inode;
- inode->i_mtime = current_fs_time(inode->i_sb);
+ tty_update_time(&inode->i_mtime);
ret = written;
}
out:
index 2f45bba8561d10a5f8b52607344cfdeb957a540e..c0f40663bed7584bb3e9a2f487402a5a3d020b6b 100644 (file)
mReq->ptr->page[i] =
(mReq->req.dma + i * CI13XXX_PAGE_SIZE) & ~TD_RESERVED_MASK;
+ wmb();
+
if (!list_empty(&mEp->qh.queue)) {
struct ci13xxx_req *mReqPrev;
int n = hw_ep_bit(mEp->num, mEp->dir);
struct ci13xxx_req *mReq = \
list_entry(mEp->qh.queue.next,
struct ci13xxx_req, queue);
+
+ if (mReq->zptr) {
+ dma_pool_free(mEp->td_pool, mReq->zptr, mReq->zdma);
+ mReq->zptr = NULL;
+ }
+
list_del_init(&mReq->queue);
mReq->req.status = -ESHUTDOWN;
index 4ff2384d7ca8170ca0a57d1e04e8b5b6237643e0..d12e8b59b11028bf497e561eacaab2cd513a5076 100644 (file)
#define TD_CURR_OFFSET (0x0FFFUL << 0)
#define TD_FRAME_NUM (0x07FFUL << 0)
#define TD_RESERVED_MASK (0x0FFFUL << 0)
-} __attribute__ ((packed));
+} __attribute__ ((packed, aligned(4)));
/* DMA layout of queue heads */
struct ci13xxx_qh {
/* 9 */
u32 RESERVED;
struct usb_ctrlrequest setup;
-} __attribute__ ((packed));
+} __attribute__ ((packed, aligned(4)));
/**
* struct ci13xxx_req - usb request representation
index b78fbe222b72c2e3bc662973e9f9f08941ce2628..ea0a9a14014b14512f2d751c9139d4f68e1177ff 100644 (file)
--- a/drivers/usb/core/devio.c
+++ b/drivers/usb/core/devio.c
index &= 0xff;
switch (requesttype & USB_RECIP_MASK) {
case USB_RECIP_ENDPOINT:
+ if ((index & ~USB_DIR_IN) == 0)
+ return 0;
ret = findintfep(ps->dev, index);
if (ret >= 0)
ret = checkintf(ps, ret);
index 442b7915ab81c6ddd7ecb52f3f4eb089e1ec840d..e410e026bec99feb04c06c72c7500bba1654f017 100644 (file)
if (retval)
return retval;
- if (ehci_is_TDI(ehci))
- tdi_reset(ehci);
-
ehci_reset(ehci);
return 0;
index f2845f1da5ba7bf45041525dc6d931ed1395be00..2573cf4de9ea7fa6b4b528b5ea684562c32f4a21 100644 (file)
* TD list.
*/
if (list_empty(&ep_ring->td_list)) {
- xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
- "with no TDs queued?\n",
- TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
- ep_index);
- xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
- (le32_to_cpu(event->flags) &
- TRB_TYPE_BITMASK)>>10);
- xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
+ /*
+ * A stopped endpoint may generate an extra completion
+ * event if the device was suspended. Don't print
+ * warnings.
+ */
+ if (!(trb_comp_code == COMP_STOP ||
+ trb_comp_code == COMP_STOP_INVAL)) {
+ xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
+ TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
+ ep_index);
+ xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
+ (le32_to_cpu(event->flags) &
+ TRB_TYPE_BITMASK)>>10);
+ xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
+ }
if (ep->skip) {
ep->skip = false;
xhci_dbg(xhci, "td_list is empty while skip "
index 0fc6e5fc745fbf0de60d97e7059d93dc6ad82348..ba6a5d6e618e20092842c0974b3e5788461b651d 100644 (file)
{ APPLEDISPLAY_DEVICE(0x9219) },
{ APPLEDISPLAY_DEVICE(0x921c) },
{ APPLEDISPLAY_DEVICE(0x921d) },
+ { APPLEDISPLAY_DEVICE(0x9236) },
/* Terminating entry */
{ }
index 8e4f40ba66fda71815f42402d05fbbac027fb296..77f78adf73e5e82b901876777a14642dc7ac3023 100644 (file)
{ USB_DEVICE(FTDI_VID, FTDI_OPENDCC_THROTTLE_PID) },
{ USB_DEVICE(FTDI_VID, FTDI_OPENDCC_GATEWAY_PID) },
{ USB_DEVICE(FTDI_VID, FTDI_OPENDCC_GBM_PID) },
+ { USB_DEVICE(FTDI_VID, FTDI_OPENDCC_GBM_BOOST_PID) },
{ USB_DEVICE(NEWPORT_VID, NEWPORT_AGILIS_PID) },
{ USB_DEVICE(INTERBIOMETRICS_VID, INTERBIOMETRICS_IOBOARD_PID) },
{ USB_DEVICE(INTERBIOMETRICS_VID, INTERBIOMETRICS_MINI_IOBOARD_PID) },
{ USB_DEVICE(FTDI_VID, FTDI_DOTEC_PID) },
{ USB_DEVICE(QIHARDWARE_VID, MILKYMISTONE_JTAGSERIAL_PID),
.driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
- { USB_DEVICE(ST_VID, ST_STMCLT1030_PID),
+ { USB_DEVICE(ST_VID, ST_STMCLT_2232_PID),
+ .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk },
+ { USB_DEVICE(ST_VID, ST_STMCLT_4232_PID),
.driver_info = (kernel_ulong_t)&ftdi_stmclite_quirk },
{ USB_DEVICE(FTDI_VID, FTDI_RF_R106) },
{ USB_DEVICE(FTDI_VID, FTDI_DISTORTEC_JTAG_LOCK_PICK_PID),
}
/*
- * First and second port on STMCLiteadaptors is reserved for JTAG interface
- * and the forth port for pio
+ * First two ports on JTAG adaptors using an FT4232 such as STMicroelectronics's
+ * ST Micro Connect Lite are reserved for JTAG or other non-UART interfaces and
+ * can be accessed from userspace.
+ * The next two ports are enabled as UARTs by default, where port 2 is
+ * a conventional RS-232 UART.
*/
static int ftdi_stmclite_probe(struct usb_serial *serial)
{
struct usb_device *udev = serial->dev;
struct usb_interface *interface = serial->interface;
- if (interface == udev->actconfig->interface[2])
- return 0;
-
- dev_info(&udev->dev, "Ignoring serial port reserved for JTAG\n");
+ if (interface == udev->actconfig->interface[0] ||
+ interface == udev->actconfig->interface[1]) {
+ dev_info(&udev->dev, "Ignoring serial port reserved for JTAG\n");
+ return -ENODEV;
+ }
- return -ENODEV;
+ return 0;
}
/*
index e79861eeed4cca1471e4531ff727f0f8425e7892..98528270c43c21f5f8d66ccf594a269b32f0600f 100644 (file)
#define FTDI_OPENDCC_THROTTLE_PID 0xBFDA
#define FTDI_OPENDCC_GATEWAY_PID 0xBFDB
#define FTDI_OPENDCC_GBM_PID 0xBFDC
+#define FTDI_OPENDCC_GBM_BOOST_PID 0xBFDD
/* NZR SEM 16+ USB (http://www.nzr.de) */
#define FTDI_NZR_SEM_USB_PID 0xC1E0 /* NZR SEM-LOG16+ */
* STMicroelectonics
*/
#define ST_VID 0x0483
-#define ST_STMCLT1030_PID 0x3747 /* ST Micro Connect Lite STMCLT1030 */
+#define ST_STMCLT_2232_PID 0x3746
+#define ST_STMCLT_4232_PID 0x3747
/*
* Papouch products (http://www.papouch.com/)
index 558adfc05007dbdf46f2dc9a5280579b3cdbdab2..bff059a19e2fa9b07ad3636eeb2ec11b62b53f11 100644 (file)
/* Olivetti products */
#define OLIVETTI_VENDOR_ID 0x0b3c
#define OLIVETTI_PRODUCT_OLICARD100 0xc000
+#define OLIVETTI_PRODUCT_OLICARD145 0xc003
/* Celot products */
#define CELOT_VENDOR_ID 0x211f
{ USB_DEVICE(SIEMENS_VENDOR_ID, CINTERION_PRODUCT_HC28_MDMNET) },
{ USB_DEVICE(OLIVETTI_VENDOR_ID, OLIVETTI_PRODUCT_OLICARD100) },
+ { USB_DEVICE(OLIVETTI_VENDOR_ID, OLIVETTI_PRODUCT_OLICARD145) },
{ USB_DEVICE(CELOT_VENDOR_ID, CELOT_PRODUCT_CT680M) }, /* CT-650 CDMA 450 1xEVDO modem */
{ USB_DEVICE(ONDA_VENDOR_ID, ONDA_MT825UP) }, /* ONDA MT825UP modem */
{ USB_DEVICE_AND_INTERFACE_INFO(SAMSUNG_VENDOR_ID, SAMSUNG_PRODUCT_GT_B3730, USB_CLASS_CDC_DATA, 0x00, 0x00) }, /* Samsung GT-B3730 LTE USB modem.*/
{ USB_DEVICE(TPLINK_VENDOR_ID, TPLINK_PRODUCT_MA180),
.driver_info = (kernel_ulong_t)&net_intf4_blacklist },
{ USB_DEVICE(CHANGHONG_VENDOR_ID, CHANGHONG_PRODUCT_CH690) },
+ { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x7d01, 0xff, 0x02, 0x01) }, /* D-Link DWM-156 (variant) */
+ { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x7d01, 0xff, 0x00, 0x00) }, /* D-Link DWM-156 (variant) */
+ { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x7d02, 0xff, 0x02, 0x01) },
+ { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x7d02, 0xff, 0x00, 0x00) },
+ { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x7d03, 0xff, 0x02, 0x01) },
+ { USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x7d03, 0xff, 0x00, 0x00) },
{ } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, option_ids);
index 070b5c0ebbf98d0d822723c4fe04b9ee984c5bf5..d9440882cdc9c76e1435bf912b8cbad0f7ab8f43 100644 (file)
{
struct us_data *us;
int result;
+ struct usb_device *device;
result = usb_stor_probe1(&us, intf, id,
(id - cypress_usb_ids) + cypress_unusual_dev_list);
if (result)
return result;
- us->protocol_name = "Transparent SCSI with Cypress ATACB";
- us->proto_handler = cypress_atacb_passthrough;
+ /* Among CY7C68300 chips, the A revision does not support Cypress ATACB
+ * Filter out this revision from EEPROM default descriptor values
+ */
+ device = interface_to_usbdev(intf);
+ if (device->descriptor.iManufacturer != 0x38 ||
+ device->descriptor.iProduct != 0x4e ||
+ device->descriptor.iSerialNumber != 0x64) {
+ us->protocol_name = "Transparent SCSI with Cypress ATACB";
+ us->proto_handler = cypress_atacb_passthrough;
+ } else {
+ us->protocol_name = "Transparent SCSI";
+ us->proto_handler = usb_stor_transparent_scsi_command;
+ }
result = usb_stor_probe2(us);
return result;
index 501c599e75493b2424877617dc09a8c9fbaa7b12..6e696e662dba0a9e92062c020071499e048022a9 100644 (file)
finished:
fbcon_free_font(p, free_font);
+ if (free_font)
+ vc->vc_font.data = NULL;
if (!con_is_bound(&fb_con))
fbcon_exit();
diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c
index dc61c12ecf8ca516e7910fc5156e81e9701bb788..0a494561f6ebc6a8078b271aed00f6e4361cf470 100644 (file)
--- a/drivers/video/fbmem.c
+++ b/drivers/video/fbmem.c
{
struct fb_info *info = file_fb_info(file);
struct fb_ops *fb;
- unsigned long off;
+ unsigned long mmio_pgoff;
unsigned long start;
u32 len;
if (!info)
return -ENODEV;
- if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
- return -EINVAL;
- off = vma->vm_pgoff << PAGE_SHIFT;
fb = info->fbops;
if (!fb)
return -ENODEV;
return res;
}
- /* frame buffer memory */
+ /*
+ * Ugh. This can be either the frame buffer mapping, or
+ * if pgoff points past it, the mmio mapping.
+ */
start = info->fix.smem_start;
- len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.smem_len);
- if (off >= len) {
- /* memory mapped io */
- off -= len;
- if (info->var.accel_flags) {
- mutex_unlock(&info->mm_lock);
- return -EINVAL;
- }
+ len = info->fix.smem_len;
+ mmio_pgoff = PAGE_ALIGN((start & ~PAGE_MASK) + len) >> PAGE_SHIFT;
+ if (vma->vm_pgoff >= mmio_pgoff) {
+ vma->vm_pgoff -= mmio_pgoff;
start = info->fix.mmio_start;
- len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.mmio_len);
+ len = info->fix.mmio_len;
}
mutex_unlock(&info->mm_lock);
- start &= PAGE_MASK;
- if ((vma->vm_end - vma->vm_start + off) > len)
- return -EINVAL;
- off += start;
- vma->vm_pgoff = off >> PAGE_SHIFT;
- /* VM_IO | VM_DONTEXPAND | VM_DONTDUMP are set by io_remap_pfn_range()*/
+
vma->vm_page_prot = vm_get_page_prot(vma->vm_flags);
- fb_pgprotect(file, vma, off);
- if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
- vma->vm_end - vma->vm_start, vma->vm_page_prot))
- return -EAGAIN;
- return 0;
+ fb_pgprotect(file, vma, start);
+
+ return vm_iomap_memory(vma, start, len);
}
static int
index 2535345b7cd3a2835eff85ff5f76d1fd0f93bb5f..0f480fa17c6481ba6d2e7a6e0c7ac43960612c03 100644 (file)
A mini-projector used in TI's SDP4430 and EVM boards
For more info please visit http://www.dlp.com/projector/
+config PANEL_TFCS9700
+ tristate "Three Five DPI panel"
+ depends on OMAP2_DSS_DPI && I2C
+ help
+ A TFT LCD DPI panel used on the LCD daughter board of Vayu EVM
+
config PANEL_TAAL
tristate "Taal DSI Panel"
depends on OMAP2_DSS_DSI
index f866c6024c7a731f92bd05b4acdecd7918dd44c5..bb27e88844abe9b3cd59a1127eac02f6217c63c9 100644 (file)
obj-$(CONFIG_PANEL_NEC_NL8048HL11_01B) += panel-nec-nl8048hl11-01b.o
obj-$(CONFIG_PANEL_TAAL) += panel-taal.o
+obj-$(CONFIG_PANEL_TFCS9700) += panel-tfcs9700.o
+
obj-$(CONFIG_PANEL_LG4591) += panel-lg4591.o
obj-$(CONFIG_PANEL_PICODLP) += panel-picodlp.o
obj-$(CONFIG_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o
diff --git a/drivers/video/omap2/displays/panel-tfcs9700.c b/drivers/video/omap2/displays/panel-tfcs9700.c
--- /dev/null
@@ -0,0 +1,477 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Inc
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <linux/of_i2c.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+
+#include <video/omapdss.h>
+#include <video/omap-panel-tfcs9700.h>
+
+#define TLC_NAME "tlc59108"
+#define TLC_I2C_ADDR 0x40
+
+#define TLC59108_MODE1 0x00
+#define TLC59108_PWM2 0x04
+#define TLC59108_LEDOUT0 0x0c
+#define TLC59108_LEDOUT1 0x0d
+
+struct tlc_data {
+ struct device *dev;
+ struct regmap *regmap;
+ int p_gpio;
+};
+
+static const struct omap_video_timings tfc_s9700_default_timings = {
+ .x_res = 800,
+ .y_res = 480,
+
+ .pixel_clock = 29232,
+
+ .hfp = 41,
+ .hsw = 49,
+ .hbp = 41,
+
+ .vfp = 13,
+ .vsw = 4,
+ .vbp = 29,
+
+ .vsync_level = OMAPDSS_SIG_ACTIVE_LOW,
+ .hsync_level = OMAPDSS_SIG_ACTIVE_LOW,
+ .data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE,
+ .de_level = OMAPDSS_SIG_ACTIVE_HIGH,
+ .sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
+};
+
+struct panel_drv_data {
+ struct omap_dss_device *dssdev;
+
+ struct i2c_client *tlc_client;
+ struct mutex lock;
+
+ int dith;
+};
+
+static int tlc_init(struct i2c_client *client)
+{
+ struct tlc_data *data = dev_get_drvdata(&client->dev);
+ struct regmap *map = data->regmap;
+
+ /* init the TLC chip */
+ regmap_write(map, TLC59108_MODE1, 0x01);
+
+ /*
+ * set LED1(AVDD) to ON state(default), enable LED2 in PWM mode, enable
+ * LED0 to OFF state
+ */
+ regmap_write(map, TLC59108_LEDOUT0, 0x21);
+
+ /* set LED2 PWM to full freq */
+ regmap_write(map, TLC59108_PWM2, 0xff);
+
+ /* set LED4(UPDN) and LED6(MODE3) to OFF state */
+ regmap_write(map, TLC59108_LEDOUT1, 0x11);
+
+ return 0;
+}
+
+static int tlc_uninit(struct i2c_client *client)
+{
+ struct tlc_data *data = dev_get_drvdata(&client->dev);
+ struct regmap *map = data->regmap;
+
+ /* clear TLC chip regs */
+ regmap_write(map, TLC59108_PWM2, 0x0);
+ regmap_write(map, TLC59108_LEDOUT0, 0x0);
+ regmap_write(map, TLC59108_LEDOUT1, 0x0);
+
+ regmap_write(map, TLC59108_MODE1, 0x0);
+
+ return 0;
+}
+
+static int tfc_s9700_power_on(struct omap_dss_device *dssdev)
+{
+ struct panel_drv_data *ddata = dev_get_drvdata(&dssdev->dev);
+ int r;
+
+ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
+ return 0;
+
+ omapdss_dpi_set_timings(dssdev, &dssdev->panel.timings);
+ omapdss_dpi_set_data_lines(dssdev, dssdev->phy.dpi.data_lines);
+
+ r = omapdss_dpi_display_enable(dssdev);
+ if (r)
+ goto err0;
+
+ tlc_init(ddata->tlc_client);
+
+ return 0;
+err0:
+ return r;
+}
+
+static void tfc_s9700_power_off(struct omap_dss_device *dssdev)
+{
+ struct panel_drv_data *ddata = dev_get_drvdata(&dssdev->dev);
+
+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE)
+ return;
+
+ tlc_uninit(ddata->tlc_client);
+
+ omapdss_dpi_display_disable(dssdev);
+}
+
+static int tfc_s9700_probe_of(struct omap_dss_device *dssdev,
+ struct panel_drv_data *ddata)
+{
+ struct device_node *node = dssdev->dev.of_node;
+ struct device_node *tlc;
+ struct i2c_client *client;
+ int r, datalines;
+
+ r = of_property_read_u32(node, "data-lines", &datalines);
+ if (r) {
+ dev_err(&dssdev->dev, "failed to parse datalines");
+ return r;
+ }
+
+ tlc = of_parse_phandle(node, "tlc", 0);
+ if (!tlc) {
+ dev_err(&dssdev->dev, "could not find tlc device\n");
+ return -EINVAL;
+ }
+
+ client = of_find_i2c_device_by_node(tlc);
+ if (!client) {
+ dev_err(&dssdev->dev, "failed to find tlc i2c client device\n");
+ return -EINVAL;
+ }
+
+ ddata->tlc_client = client;
+
+ dssdev->phy.dpi.data_lines = datalines;
+
+ return 0;
+}
+
+static struct i2c_board_info tlc_i2c_board_info = {
+ I2C_BOARD_INFO(TLC_NAME, TLC_I2C_ADDR),
+};
+
+static int tfc_s9700_probe(struct omap_dss_device *dssdev)
+{
+ struct panel_drv_data *ddata;
+ struct device *i2c_dev;
+ int r;
+
+ ddata = devm_kzalloc(&dssdev->dev, sizeof(*ddata), GFP_KERNEL);
+ if (!ddata)
+ return -ENOMEM;
+
+ dssdev->panel.timings = tfc_s9700_default_timings;
+
+ ddata->dssdev = dssdev;
+ mutex_init(&ddata->lock);
+
+ if (dssdev->dev.of_node) {
+ r = tfc_s9700_probe_of(dssdev, ddata);
+ if (r)
+ return r;
+ } else if (dssdev->data) {
+ struct tfc_s9700_platform_data *pdata = dssdev->data;
+ struct i2c_client *client;
+ struct i2c_adapter *adapter;
+ int tlc_adapter_id;
+
+ dssdev->phy.dpi.data_lines = pdata->datalines;
+
+ tlc_adapter_id = pdata->tlc_adapter_id;
+
+ adapter = i2c_get_adapter(tlc_adapter_id);
+ if (!adapter) {
+ dev_err(&dssdev->dev, "can't get i2c adapter\n");
+ return -ENODEV;
+ }
+
+ client = i2c_new_device(adapter, &tlc_i2c_board_info);
+ if (!client) {
+ dev_err(&dssdev->dev, "can't add i2c device\n");
+ return -ENODEV;
+ }
+
+ ddata->tlc_client = client;
+ } else {
+ return -EINVAL;
+ }
+
+ i2c_dev = &ddata->tlc_client->dev;
+ if (!i2c_dev->driver) {
+ dev_err(&dssdev->dev, "tlc i2c client has no driver\n");
+ return -EINVAL;
+ }
+
+ if (dssdev->phy.dpi.data_lines == 24)
+ ddata->dith = 0;
+ else if (dssdev->phy.dpi.data_lines == 18)
+ ddata->dith = 1;
+ else
+ return -EINVAL;
+
+ dev_set_drvdata(&dssdev->dev, ddata);
+
+ return 0;
+}
+
+static void __exit tfc_s9700_remove(struct omap_dss_device *dssdev)
+{
+ struct panel_drv_data *ddata = dev_get_drvdata(&dssdev->dev);
+
+ mutex_lock(&ddata->lock);
+
+ dev_set_drvdata(&dssdev->dev, NULL);
+
+ mutex_unlock(&ddata->lock);
+}
+
+static int tfc_s9700_enable(struct omap_dss_device *dssdev)
+{
+ struct panel_drv_data *ddata = dev_get_drvdata(&dssdev->dev);
+ int r;
+
+ mutex_lock(&ddata->lock);
+
+ r = tfc_s9700_power_on(dssdev);
+ if (r == 0)
+ dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
+
+ mutex_unlock(&ddata->lock);
+
+ return r;
+}
+
+static void tfc_s9700_disable(struct omap_dss_device *dssdev)
+{
+ struct panel_drv_data *ddata = dev_get_drvdata(&dssdev->dev);
+
+ mutex_lock(&ddata->lock);
+
+ tfc_s9700_power_off(dssdev);
+
+ dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+
+ mutex_unlock(&ddata->lock);
+}
+
+static void tfc_s9700_set_timings(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings)
+{
+ struct panel_drv_data *ddata = dev_get_drvdata(&dssdev->dev);
+
+ mutex_lock(&ddata->lock);
+ omapdss_dpi_set_timings(dssdev, timings);
+ dssdev->panel.timings = *timings;
+ mutex_unlock(&ddata->lock);
+}
+
+static void tfc_s9700_get_timings(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings)
+{
+ struct panel_drv_data *ddata = dev_get_drvdata(&dssdev->dev);
+
+ mutex_lock(&ddata->lock);
+ *timings = dssdev->panel.timings;
+ mutex_unlock(&ddata->lock);
+}
+
+static int tfc_s9700_check_timings(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings)
+{
+ struct panel_drv_data *ddata = dev_get_drvdata(&dssdev->dev);
+ int r;
+
+ mutex_lock(&ddata->lock);
+ r = dpi_check_timings(dssdev, timings);
+ mutex_unlock(&ddata->lock);
+
+ return r;
+}
+
+#if defined(CONFIG_OF)
+static const struct of_device_id tfc_s9700_of_match[] = {
+ {
+ .compatible = "ti,tfc_s9700",
+ },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, tfc_s9700_of_match);
+#else
+#define dss_of_match NULL
+#endif
+
+static struct omap_dss_driver tfc_s9700_driver = {
+ .probe = tfc_s9700_probe,
+ .remove = __exit_p(tfc_s9700_remove),
+
+ .enable = tfc_s9700_enable,
+ .disable = tfc_s9700_disable,
+
+ .set_timings = tfc_s9700_set_timings,
+ .get_timings = tfc_s9700_get_timings,
+ .check_timings = tfc_s9700_check_timings,
+
+ .driver = {
+ .name = "tfc_s9700",
+ .owner = THIS_MODULE,
+ .of_match_table = tfc_s9700_of_match,
+ },
+};
+
+struct regmap_config tlc59108_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+};
+
+static int tlc59108_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int r;
+ struct regmap *regmap;
+ struct tlc_data *data;
+ struct device *dev = &client->dev;
+ struct device_node *node = dev->of_node;
+ unsigned int val;
+ int gpio;
+
+ regmap = devm_regmap_init_i2c(client, &tlc59108_regmap_config);
+ if (IS_ERR(regmap)) {
+ r = PTR_ERR(regmap);
+ dev_err(&client->dev, "Failed to init regmap: %d\n", r);
+ return r;
+ }
+
+ data = devm_kzalloc(dev, sizeof(struct tlc_data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ gpio = of_get_gpio(node, 0);
+
+ if (gpio_is_valid(gpio)) {
+ data->p_gpio = gpio;
+ } else if (gpio == -ENOENT) {
+ data->p_gpio = -1;
+ } else {
+ dev_err(dev, "failed to parse Power gpio\n");
+ return gpio;
+ }
+
+ if (gpio_is_valid(data->p_gpio)) {
+ r = devm_gpio_request_one(dev, data->p_gpio, GPIOF_OUT_INIT_LOW,
+ "tfc_s9700 p_gpio");
+ if (r) {
+ dev_err(dev, "Failed to request Power GPIO %d\n",
+ data->p_gpio);
+ return r;
+ }
+ }
+
+ dev_set_drvdata(dev, data);
+ data->dev = dev;
+ data->regmap = regmap;
+
+ msleep(10);
+
+ /* Try to read a TLC register to verify if i2c works */
+ r = regmap_read(data->regmap, TLC59108_MODE1, &val);
+ if (r < 0) {
+ dev_err(dev, "Failed to set MODE1: %d\n", r);
+ return r;
+ }
+
+ dev_info(dev, "Successfully initialized %s\n", TLC_NAME);
+
+ return 0;
+}
+
+static int tlc59108_i2c_remove(struct i2c_client *client)
+{
+ struct tlc_data *data = dev_get_drvdata(&client->dev);
+
+ if (gpio_is_valid(data->p_gpio))
+ gpio_set_value_cansleep(data->p_gpio, 1);
+
+ return 0;
+}
+
+static const struct i2c_device_id tlc59108_id[] = {
+ { TLC_NAME, 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, tlc59108_id);
+
+static const struct of_device_id tlc59108_of_match[] = {
+ { .compatible = "ti,tlc59108", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, tlc59108_of_match);
+
+static struct i2c_driver tlc59108_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = TLC_NAME,
+ .of_match_table = tlc59108_of_match,
+ },
+ .id_table = tlc59108_id,
+ .probe = tlc59108_i2c_probe,
+ .remove = tlc59108_i2c_remove,
+};
+
+static int __init tfc_s9700_init(void)
+{
+ int r;
+
+ r = i2c_add_driver(&tlc59108_i2c_driver);
+ if (r) {
+ printk(KERN_WARNING "tlc59108 driver" \
+ " registration failed\n");
+ return r;
+ }
+
+ r = omap_dss_register_driver(&tfc_s9700_driver);
+ if (r)
+ i2c_del_driver(&tlc59108_i2c_driver);
+
+ return r;
+}
+
+static void __exit tfc_s9700_exit(void)
+{
+ omap_dss_unregister_driver(&tfc_s9700_driver);
+}
+
+module_init(tfc_s9700_init);
+module_exit(tfc_s9700_exit);
+MODULE_LICENSE("GPL");
index 28159e2d96ef0f95427a9ebac39c85da25187a5e..ef906e8d8334ebf90e63cf9e47ea750c9098cb42 100644 (file)
help
DPI Interface. This is the Parallel Display Interface.
+config OMAP2_DSS_DRA7XX_DPI
+ bool "DRA75X DPI support"
+ default n
+ help
+ Vayu DPI Interface. This is the Parallel Display Interface.
+
config OMAP2_DSS_RFBI
bool "RFBI support"
default n
config OMAP4_DSS_HDMI
bool "OMAP4 HDMI support"
default y
+ select I2C_ALGOBIT
help
HDMI Interface. This adds the High Definition Multimedia Interface.
See http://www.hdmi.org/ for HDMI specification.
index 8abdc8165341a1b029f44da7e6e744517bf64b32..fdcbcda307b6abb1b77bba49cbe69262d4183b99 100644 (file)
obj-$(CONFIG_OMAP2_DSS) += omapdss.o
# Core DSS files
-omapdss-y := core.o dss.o dss_features.o dispc.o dispc_coefs.o display.o \
- output.o
+omapdss-y := core.o dss.o dss_dpll.o dss_features.o dispc.o dispc_coefs.o \
+ display.o output.o
# DSS compat layer files
omapdss-y += manager.o manager-sysfs.o overlay.o overlay-sysfs.o apply.o \
dispc-compat.o display-sysfs.o
-omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o
+omapdss-$(CONFIG_OMAP2_DSS_DPI) += dpi.o dpi_common.o
+omapdss-$(CONFIG_OMAP2_DSS_DRA7XX_DPI) += dra7xx_dpi.o dpi_common.o
omapdss-$(CONFIG_OMAP2_DSS_RFBI) += rfbi.o
omapdss-$(CONFIG_OMAP2_DSS_VENC) += venc.o venc_panel.o
omapdss-$(CONFIG_OMAP2_DSS_SDI) += sdi.o
index 0ddaae61a0e48d3cbe139e025e6f4426af063de7..f9c294b3babe7962407ca74a013fdce29e76bd88 100644 (file)
dsi_init_platform_driver,
#endif
#ifdef CONFIG_OMAP2_DSS_DPI
- dpi_init_platform_driver,
+ omap_dpi_init_platform_driver,
+#endif
+#ifdef CONFIG_OMAP2_DSS_DRA7XX_DPI
+ dra7xx_dpi_init_platform_driver,
#endif
#ifdef CONFIG_OMAP2_DSS_SDI
sdi_init_platform_driver,
dsi_uninit_platform_driver,
#endif
#ifdef CONFIG_OMAP2_DSS_DPI
- dpi_uninit_platform_driver,
+ omap_dpi_uninit_platform_driver,
+#endif
+#ifdef CONFIG_OMAP2_DSS_DRA7XX_DPI
+ dra7xx_dpi_uninit_platform_driver,
#endif
#ifdef CONFIG_OMAP2_DSS_SDI
sdi_uninit_platform_driver,
index 4e8b6c8c67b9815a0cff74ec97ea2b0378246206..1ca4a677384fd34ad9e15f8cde1f0d06b56954ab 100644 (file)
break;
case OMAPDSS_VER_OMAP5:
+ case OMAPDSS_VER_DRA7xx:
src = &omap54xx_dispc_feats;
break;
index d06b8c66ca83db952958a17c7fbce39fc653b918..5e63e210226fbbe6acdbb704d3899c2f4a4bcde3 100644 (file)
dss_mgr_set_lcd_config(mgr, &dpi.mgr_config);
}
-int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
+static int omap_dpi_display_enable(struct omap_dss_device *dssdev)
{
struct omap_dss_output *out = dssdev->output;
int r;
if (r)
goto err_get_dispc;
- r = dss_dpi_select_source(dssdev->channel);
+ r = dss_dpi_select_source(0, dssdev->channel);
if (r)
goto err_src_sel;
mutex_unlock(&dpi.lock);
return r;
}
-EXPORT_SYMBOL(omapdss_dpi_display_enable);
-void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
+static void omap_dpi_display_disable(struct omap_dss_device *dssdev)
{
struct omap_overlay_manager *mgr = dssdev->output->manager;
mutex_unlock(&dpi.lock);
}
-EXPORT_SYMBOL(omapdss_dpi_display_disable);
-void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
+static void omap_dpi_set_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
DSSDBG("dpi_set_timings\n");
mutex_unlock(&dpi.lock);
}
-EXPORT_SYMBOL(omapdss_dpi_set_timings);
-int dpi_check_timings(struct omap_dss_device *dssdev,
+static int omap_dpi_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
int r;
return 0;
}
-EXPORT_SYMBOL(dpi_check_timings);
-void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
+static void omap_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
{
mutex_lock(&dpi.lock);
mutex_unlock(&dpi.lock);
}
-EXPORT_SYMBOL(omapdss_dpi_set_data_lines);
static int __init dpi_verify_dsi_pll(struct platform_device *dsidev)
{
dss_unregister_output(out);
}
+static struct dpi_common_ops ops = {
+ .enable = omap_dpi_display_enable,
+ .disable = omap_dpi_display_disable,
+ .set_timings = omap_dpi_set_timings,
+ .check_timings = omap_dpi_check_timings,
+ .set_data_lines = omap_dpi_set_data_lines,
+};
+
static int __init omap_dpi_probe(struct platform_device *pdev)
{
mutex_init(&dpi.lock);
+ dpi_common_set_ops(&ops);
+
dpi_init_output(pdev);
if (pdev->dev.of_node)
},
};
-int __init dpi_init_platform_driver(void)
+int __init omap_dpi_init_platform_driver(void)
{
return platform_driver_probe(&omap_dpi_driver, omap_dpi_probe);
}
-void __exit dpi_uninit_platform_driver(void)
+void __exit omap_dpi_uninit_platform_driver(void)
{
platform_driver_unregister(&omap_dpi_driver);
}
diff --git a/drivers/video/omap2/dss/dpi_common.c b/drivers/video/omap2/dss/dpi_common.c
--- /dev/null
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Ltd.
+ *
+ * Some code and ideas taken from drivers/video/omap/ driver
+ * by Imre Deak.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/export.h>
+
+#include <video/omapdss.h>
+
+#include "dss.h"
+#include "dss_features.h"
+
+static struct dpi_common_ops dpi_ops;
+
+int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
+{
+ return dpi_ops.enable(dssdev);
+}
+EXPORT_SYMBOL(omapdss_dpi_display_enable);
+
+void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
+{
+ dpi_ops.disable(dssdev);
+}
+EXPORT_SYMBOL(omapdss_dpi_display_disable);
+
+void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings)
+{
+ dpi_ops.set_timings(dssdev, timings);
+}
+EXPORT_SYMBOL(omapdss_dpi_set_timings);
+
+int dpi_check_timings(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings)
+{
+ return dpi_ops.check_timings(dssdev, timings);
+}
+EXPORT_SYMBOL(dpi_check_timings);
+
+void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
+{
+ dpi_ops.set_data_lines(dssdev, data_lines);
+}
+EXPORT_SYMBOL(omapdss_dpi_set_data_lines);
+
+void dpi_common_set_ops(struct dpi_common_ops *ops)
+{
+ dpi_ops = *ops;
+}
+
diff --git a/drivers/video/omap2/dss/dra7xx_dpi.c b/drivers/video/omap2/dss/dra7xx_dpi.c
--- /dev/null
@@ -0,0 +1,564 @@
+/*
+ * Some code and ideas taken from drivers/video/omap/ driver
+ * by Imre Deak.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#define DSS_SUBSYS_NAME "DRA7XX_DPI"
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/export.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+
+#include <video/omapdss.h>
+
+#include "dss.h"
+#include "dss_features.h"
+
+struct dpi_data {
+ enum dss_dpll dpll;
+
+ struct mutex lock;
+
+ u32 module_id;
+
+ struct omap_video_timings timings;
+ struct dss_lcd_mgr_config mgr_config;
+ int data_lines;
+
+ struct omap_dss_output output;
+};
+
+/*
+ * On vayu, we will try to use the DPLL_VIDEOx PLLs, only if we can't get one,
+ * we will try to modify the DSS_FCLK to get the pixel clock. Leave HDMI PLL out
+ * for now
+ */
+
+enum dss_dpll dpi_get_dpll(struct platform_device *pdev)
+{
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+
+ switch (dpi->module_id) {
+ case 0:
+ if (dss_dpll_disabled(DSS_DPLL_VIDEO1))
+ return DSS_DPLL_VIDEO1;
+ else
+ return DSS_DPLL_NONE;
+ case 1:
+ case 2:
+ if (dss_dpll_disabled(DSS_DPLL_VIDEO1))
+ return DSS_DPLL_VIDEO1;
+ else if (dss_dpll_disabled(DSS_DPLL_VIDEO2))
+ return DSS_DPLL_VIDEO2;
+ else
+ return DSS_DPLL_NONE;
+ default:
+ return DSS_DPLL_NONE;
+ }
+
+ return DSS_DPLL_NONE;
+}
+
+static int dpi_set_dss_dpll_clk(struct dpi_data *dpi, enum dss_dpll dpll,
+ unsigned long pck_req, unsigned long *fck, u16 *lck_div,
+ u16 *pck_div)
+{
+ struct dss_dpll_cinfo dpll_cinfo;
+ struct dispc_clock_info dispc_cinfo;
+ int r;
+
+ r = dss_dpll_calc_clock_div_pck(dpll, pck_req, &dpll_cinfo, &dispc_cinfo);
+ if (r)
+ return r;
+
+ r = dss_dpll_set_clock_div(dpll, &dpll_cinfo);
+ if (r)
+ return r;
+
+ dpi->mgr_config.clock_info = dispc_cinfo;
+
+ *fck = dpll_cinfo.hsdiv_clk;
+ *lck_div = dispc_cinfo.lck_div;
+ *pck_div = dispc_cinfo.pck_div;
+
+ return 0;
+}
+
+static int dpi_set_dispc_clk(struct dpi_data *dpi, unsigned long pck_req,
+ unsigned long *fck, u16 *lck_div, u16 *pck_div)
+{
+ struct dss_clock_info dss_cinfo;
+ struct dispc_clock_info dispc_cinfo;
+ int r;
+
+ r = dss_calc_clock_div(pck_req, &dss_cinfo, &dispc_cinfo);
+ if (r)
+ return r;
+
+ r = dss_set_clock_div(&dss_cinfo);
+ if (r)
+ return r;
+
+ dpi->mgr_config.clock_info = dispc_cinfo;
+
+ *fck = dss_cinfo.fck;
+ *lck_div = dispc_cinfo.lck_div;
+ *pck_div = dispc_cinfo.pck_div;
+
+ return 0;
+}
+
+static int dpi_set_mode(struct platform_device *pdev, enum dss_dpll dpll)
+{
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+ struct omap_video_timings *t = &dpi->timings;
+ struct omap_dss_output *out = &dpi->output;
+ struct omap_overlay_manager *mgr = out->manager;
+ unsigned long fck = 0;
+ unsigned long pck;
+ u16 lcd, pcd;
+ int r = 0;
+
+ if (dpll != DSS_DPLL_NONE)
+ r = dpi_set_dss_dpll_clk(dpi, dpll, t->pixel_clock * 1000,
+ &fck, &lcd, &pcd);
+ else
+ r = dpi_set_dispc_clk(dpi, t->pixel_clock * 1000, &fck,
+ &lcd, &pcd);
+ if (r)
+ return r;
+
+ pck = fck / lcd / pcd / 1000;
+
+ if (pck != t->pixel_clock) {
+ DSSWARN("Could not find exact pixel clock. "
+ "Requested %d kHz, got %lu kHz\n",
+ t->pixel_clock, pck);
+
+ t->pixel_clock = pck;
+ }
+
+ dss_mgr_set_timings(mgr, t);
+
+ return 0;
+}
+
+static void dpi_config_lcd_manager(struct platform_device *pdev)
+{
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+ struct omap_dss_output *out = &dpi->output;
+
+ dpi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
+
+ dpi->mgr_config.stallmode = false;
+ dpi->mgr_config.fifohandcheck = false;
+
+ dpi->mgr_config.video_port_width = dpi->data_lines;
+
+ dpi->mgr_config.lcden_sig_polarity = 0;
+
+ dss_mgr_set_lcd_config(out->manager, &dpi->mgr_config);
+}
+
+static int dra7xx_dpi_display_enable(struct omap_dss_device *dssdev)
+{
+ struct omap_dss_output *out = dssdev->output;
+ struct platform_device *pdev = out->pdev;
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+ enum omap_channel channel = dssdev->channel;
+ int r;
+
+ mutex_lock(&dpi->lock);
+
+ if (out == NULL || out->manager == NULL) {
+ DSSERR("failed to enable display: no output/manager\n");
+ r = -ENODEV;
+ goto err_no_out_mgr;
+ }
+
+ r = omap_dss_start_device(dssdev);
+ if (r) {
+ DSSERR("failed to start device\n");
+ goto err_start_dev;
+ }
+
+ r = dispc_runtime_get();
+ if (r)
+ goto err_get_dispc;
+
+ r = dss_dpi_select_source(dpi->module_id, channel);
+ if (r)
+ goto err_src_sel;
+
+ /* try to get a free dpll, if not, try to change DSS_FCLK */
+ dpi->dpll = dpi_get_dpll(pdev);
+ if (dpi->dpll != DSS_DPLL_NONE) {
+ DSSDBG("using DPLL %d for DPI%d\n", dpi->dpll, dpi->module_id);
+
+ dss_dpll_activate(dpi->dpll);
+ dss_dpll_set_control_mux(channel, dpi->dpll);
+ }
+
+ r = dpi_set_mode(pdev, dpi->dpll);
+ if (r)
+ goto err_set_mode;
+
+ dss_use_dpll_lcd(channel, dpi->dpll != DSS_DPLL_NONE);
+
+ dpi_config_lcd_manager(pdev);
+
+ mdelay(2);
+
+ r = dss_mgr_enable(out->manager);
+ if (r)
+ goto err_mgr_enable;
+
+ mutex_unlock(&dpi->lock);
+
+ return 0;
+
+err_mgr_enable:
+err_set_mode:
+ if (dpi->dpll != DSS_DPLL_NONE)
+ dss_dpll_disable(dpi->dpll);
+err_src_sel:
+ dispc_runtime_put();
+err_get_dispc:
+err_start_dev:
+err_no_out_mgr:
+ mutex_unlock(&dpi->lock);
+ return r;
+}
+
+static void dra7xx_dpi_display_disable(struct omap_dss_device *dssdev)
+{
+ struct platform_device *pdev = dssdev->output->pdev;
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+ struct omap_overlay_manager *mgr = dssdev->output->manager;
+
+ mutex_lock(&dpi->lock);
+
+ dss_mgr_disable(mgr);
+
+ if (dpi->dpll != DSS_DPLL_NONE) {
+ dss_use_dpll_lcd(dssdev->channel, false);
+ dss_dpll_disable(dpi->dpll);
+ dpi->dpll = DSS_DPLL_NONE;
+ }
+
+ dispc_runtime_put();
+
+ omap_dss_stop_device(dssdev);
+
+ mutex_unlock(&dpi->lock);
+}
+
+static void dra7xx_dpi_set_timings(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings)
+{
+ struct platform_device *pdev = dssdev->output->pdev;
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+
+ DSSDBG("set_timings\n");
+
+ mutex_lock(&dpi->lock);
+
+ dpi->timings = *timings;
+
+ mutex_unlock(&dpi->lock);
+}
+
+static int dra7xx_dpi_check_timings(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings)
+{
+ DSSDBG("check_timings\n");
+
+ return 0;
+}
+
+static void dra7xx_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
+{
+ struct platform_device *pdev = dssdev->output->pdev;
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+
+ mutex_lock(&dpi->lock);
+
+ dpi->data_lines = data_lines;
+
+ mutex_unlock(&dpi->lock);
+}
+
+static int __init dpi_init_display(struct omap_dss_device *dssdev)
+{
+ DSSDBG("init_display\n");
+
+ return 0;
+}
+
+static struct omap_dss_device * __init dpi_find_dssdev(struct platform_device *pdev)
+{
+ struct omap_dss_board_info *pdata = pdev->dev.platform_data;
+ const char *def_disp_name = omapdss_get_default_display_name();
+ struct omap_dss_device *def_dssdev;
+ int i;
+
+ def_dssdev = NULL;
+
+ for (i = 0; i < pdata->num_devices; ++i) {
+ struct omap_dss_device *dssdev = pdata->devices[i];
+
+ if (dssdev->type != OMAP_DISPLAY_TYPE_DPI)
+ continue;
+
+ if (def_dssdev == NULL)
+ def_dssdev = dssdev;
+
+ if (def_disp_name != NULL &&
+ strcmp(dssdev->name, def_disp_name) == 0) {
+ def_dssdev = dssdev;
+ break;
+ }
+ }
+
+ return def_dssdev;
+}
+
+static void __init dra7xx_dpi_probe_pdata(struct platform_device *pdev)
+{
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+ struct omap_dss_device *plat_dssdev;
+ struct omap_dss_device *dssdev;
+ int r;
+
+ plat_dssdev = dpi_find_dssdev(pdev);
+
+ if (!plat_dssdev)
+ return;
+
+ dssdev = dss_alloc_and_init_device(&pdev->dev);
+ if (!dssdev)
+ return;
+
+ dss_copy_device_pdata(dssdev, plat_dssdev);
+
+ r = dpi_init_display(dssdev);
+ if (r) {
+ DSSERR("device %s init failed: %d\n", dssdev->name, r);
+ dss_put_device(dssdev);
+ return;
+ }
+
+ r = omapdss_output_set_device(&dpi->output, dssdev);
+ if (r) {
+ DSSERR("failed to connect output to new device: %s\n",
+ dssdev->name);
+ dss_put_device(dssdev);
+ return;
+ }
+
+ r = dss_add_device(dssdev);
+ if (r) {
+ DSSERR("device %s register failed: %d\n", dssdev->name, r);
+ omapdss_output_unset_device(&dpi->output);
+ dss_put_device(dssdev);
+ return;
+ }
+}
+
+static void __init dra7xx_dpi_probe_of(struct platform_device *pdev)
+{
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+ struct device_node *node = pdev->dev.of_node;
+ struct device_node *child;
+ struct omap_dss_device *dssdev;
+ enum omap_channel channel;
+ u32 v;
+ int r;
+
+ child = of_get_next_available_child(node, NULL);
+
+ if (!child)
+ return;
+
+ r = of_property_read_u32(node, "video-source", &v);
+ if (r) {
+ DSSERR("parsing channel failed\n");
+ return;
+ }
+
+ channel = v;
+
+ dssdev = dss_alloc_and_init_device(&pdev->dev);
+ if (!dssdev)
+ return;
+
+ dssdev->dev.of_node = child;
+ dssdev->type = OMAP_DISPLAY_TYPE_DPI;
+ dssdev->name = child->name;
+ dssdev->channel = channel;
+
+ r = dpi_init_display(dssdev);
+ if (r) {
+ DSSERR("device %s init failed: %d\n", dssdev->name, r);
+ dss_put_device(dssdev);
+ return;
+ }
+
+ r = omapdss_output_set_device(&dpi->output, dssdev);
+ if (r) {
+ DSSERR("failed to connect output to new device: %s\n",
+ dssdev->name);
+ dss_put_device(dssdev);
+ return;
+ }
+
+ r = dss_add_device(dssdev);
+ if (r) {
+ DSSERR("dss_add_device failed %d\n", r);
+ dss_put_device(dssdev);
+ return;
+ }
+}
+
+static void __init dra7xx_dpi_init_output(struct platform_device *pdev)
+{
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+ struct omap_dss_output *out = &dpi->output;
+
+ out->pdev = pdev;
+
+ switch (dpi->module_id) {
+ case 0:
+ out->id = OMAP_DSS_OUTPUT_DPI;
+ break;
+ case 1:
+ out->id = OMAP_DSS_OUTPUT_DPI1;
+ break;
+ case 2:
+ out->id = OMAP_DSS_OUTPUT_DPI2;
+ break;
+ };
+
+ out->type = OMAP_DISPLAY_TYPE_DPI;
+
+ dss_register_output(out);
+}
+
+static void __exit dra7xx_dpi_uninit_output(struct platform_device *pdev)
+{
+ struct dpi_data *dpi = dev_get_drvdata(&pdev->dev);
+ struct omap_dss_output *out = &dpi->output;
+
+ dss_unregister_output(out);
+}
+
+static struct dpi_common_ops ops = {
+ .enable = dra7xx_dpi_display_enable,
+ .disable = dra7xx_dpi_display_disable,
+ .set_timings = dra7xx_dpi_set_timings,
+ .check_timings = dra7xx_dpi_check_timings,
+ .set_data_lines = dra7xx_dpi_set_data_lines,
+};
+
+static int __init dra7xx_dpi_probe(struct platform_device *pdev)
+{
+ int r;
+ struct dpi_data *dpi;
+
+ dpi = devm_kzalloc(&pdev->dev, sizeof(*dpi), GFP_KERNEL);
+ if (!dpi)
+ return -ENOMEM;
+
+ dpi_common_set_ops(&ops);
+
+ dev_set_drvdata(&pdev->dev, dpi);
+
+ mutex_init(&dpi->lock);
+
+ if (pdev->dev.of_node) {
+ u32 id;
+ r = of_property_read_u32(pdev->dev.of_node, "reg", &id);
+ if (r) {
+ DSSERR("failed to read DPI module ID\n");
+ return r;
+ }
+
+ dpi->module_id = id;
+ } else {
+ dpi->module_id = pdev->id;
+ }
+
+ dra7xx_dpi_init_output(pdev);
+
+ if (pdev->dev.of_node)
+ dra7xx_dpi_probe_of(pdev);
+ else if (pdev->dev.platform_data)
+ dra7xx_dpi_probe_pdata(pdev);
+
+ r = dispc_runtime_get();
+ if (r)
+ DSSERR("DPI error runtime_get\n");
+
+ dispc_runtime_put();
+
+ return 0;
+}
+
+static int __exit dra7xx_dpi_remove(struct platform_device *pdev)
+{
+ dss_unregister_child_devices(&pdev->dev);
+
+ dra7xx_dpi_uninit_output(pdev);
+
+ return 0;
+}
+
+#if defined(CONFIG_OF)
+static const struct of_device_id dpi_of_match[] = {
+ {
+ .compatible = "ti,dra7xx-dpi",
+ },
+ {},
+};
+#else
+#define dpi_of_match NULL
+#endif
+
+static struct platform_driver dra7xx_dpi_driver = {
+ .remove = __exit_p(dra7xx_dpi_remove),
+ .driver = {
+ .name = "omapdss_dra7xx_dpi",
+ .owner = THIS_MODULE,
+ .of_match_table = dpi_of_match,
+ },
+};
+
+int __init dra7xx_dpi_init_platform_driver(void)
+{
+ return platform_driver_probe(&dra7xx_dpi_driver, dra7xx_dpi_probe);
+}
+
+void __exit dra7xx_dpi_uninit_platform_driver(void)
+{
+ platform_driver_unregister(&dra7xx_dpi_driver);
+}
index 3cafa87e6cb814698466e89fbffa6ec92d4a5ccd..f4e6f437e520b8aebe8fa52b1b9fb9156a2b065f 100644 (file)
u8 fck_div_max;
u8 dss_fck_multiplier;
const char *clk_name;
- int (*dpi_select_source)(enum omap_channel channel);
+ int (*dpi_select_source)(int module_id, enum omap_channel channel);
+ bool dpll_clks;
};
static struct {
dss.lcd_clk_source[ix] = clk_src;
}
+void dss_use_dpll_lcd(enum omap_channel channel, bool use_dpll)
+{
+ u8 bit;
+
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ bit = 0;
+ break;
+ case OMAP_DSS_CHANNEL_LCD2:
+ bit = 12;
+ break;
+ case OMAP_DSS_CHANNEL_LCD3:
+ bit = 19;
+ break;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ default:
+ return;
+ }
+
+ REG_FLD_MOD(DSS_CONTROL, use_dpll, bit, bit);
+}
+
enum omap_dss_clk_source dss_get_dispc_clk_source(void)
{
return dss.dispc_clk_source;
return REG_GET(DSS_CONTROL, 15, 15);
}
-static int dss_dpi_select_source_omap2_omap3(enum omap_channel channel)
+static int dss_dpi_select_source_omap2_omap3(int module_id,
+ enum omap_channel channel)
{
if (channel != OMAP_DSS_CHANNEL_LCD)
return -EINVAL;
return 0;
}
-static int dss_dpi_select_source_omap4(enum omap_channel channel)
+static int dss_dpi_select_source_omap4(int module_id, enum omap_channel channel)
{
int val;
return 0;
}
-static int dss_dpi_select_source_omap5(enum omap_channel channel)
+static int dss_dpi_select_source_omap5(int module_id, enum omap_channel channel)
{
int val;
return 0;
}
-int dss_dpi_select_source(enum omap_channel channel)
+static int dss_dpi_select_source_dra7xx(int module_id, enum omap_channel channel)
+{
+ if (module_id != 0)
+ return 0;
+
+ return dss_dpi_select_source_omap5(module_id, channel);
+}
+
+int dss_dpi_select_source(int module_id, enum omap_channel channel)
{
- return dss.feat->dpi_select_source(channel);
+ return dss.feat->dpi_select_source(module_id, channel);
}
static int dss_get_clocks(void)
dss.dpll4_m4_ck = clk;
+
return 0;
err:
.dpi_select_source = &dss_dpi_select_source_omap5,
};
+static const struct dss_features dra7xx_dss_feats __initconst = {
+ .fck_div_max = 64,
+ .dss_fck_multiplier = 1,
+ .clk_name = "dpll_per_h12x2_ck",
+ .dpi_select_source = &dss_dpi_select_source_dra7xx,
+ .dpll_clks = true,
+};
+
static int __init dss_init_features(struct platform_device *pdev)
{
const struct dss_features *src;
src = &omap54xx_dss_feats;
break;
+ case OMAPDSS_VER_DRA7xx:
+ src = &dra7xx_dss_feats;
+ break;
+
default:
return -ENODEV;
}
dss_debugfs_create_file("dss", dss_dump_regs);
+ if (dss.feat->dpll_clks) {
+ r = dss_dpll_configure(pdev);
+ if (r)
+ goto err_runtime_get;
+ r = dss_dpll_configure_ctrl();
+ if (r)
+ goto err_runtime_get;
+ }
+
return 0;
err_runtime_get:
{
pm_runtime_disable(&pdev->dev);
+ if (dss.feat->dpll_clks)
+ dss_dpll_unconfigure_ctrl();
+
dss_put_clocks();
return 0;
index 2d4c1fde79e6f0f2c4ae4b83420d992a46511970..6212bd6877b36055dbaa796b7985a31b3e59588d 100644 (file)
#define __OMAP2_DSS_H
#include <linux/interrupt.h>
+#include <linux/i2c.h>
#ifdef pr_fmt
#undef pr_fmt
DSS_WB_LCD3_MGR = 7,
};
+enum dss_dpll {
+ DSS_DPLL_VIDEO1 = 0,
+ DSS_DPLL_VIDEO2,
+ DSS_DPLL_HDMI,
+ DSS_DPLL_NONE,
+};
+
struct dss_clock_info {
/* rates that we get with dividers below */
unsigned long fck;
u16 lp_clk_div;
};
+struct dss_dpll_cinfo {
+ unsigned long fint, clkin, clkout, hsdiv_clk;
+
+ u16 regm, regn, regm_hsdiv;
+};
+
struct reg_field {
u16 reg;
u8 high;
int lcden_sig_polarity;
};
+struct dpi_common_ops {
+ int (*enable) (struct omap_dss_device *dssdev);
+ void (*disable) (struct omap_dss_device *dssdev);
+ void (*set_timings) (struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ int (*check_timings) (struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*set_data_lines) (struct omap_dss_device *dssdev,
+ int data_lines);
+};
+
struct seq_file;
struct platform_device;
void dss_uninit_platform_driver(void);
unsigned long dss_get_dispc_clk_rate(void);
-int dss_dpi_select_source(enum omap_channel channel);
+int dss_dpi_select_source(int module_id, enum omap_channel channel);
void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
+void dss_use_dpll_lcd(enum omap_channel channel, bool use_dpll);
const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
void dss_dump_clocks(struct seq_file *s);
#endif
/* DPI */
-int dpi_init_platform_driver(void) __init;
-void dpi_uninit_platform_driver(void) __exit;
+void dpi_common_set_ops(struct dpi_common_ops *ops);
+int omap_dpi_init_platform_driver(void) __init;
+void omap_dpi_uninit_platform_driver(void) __exit;
+
+int dra7xx_dpi_init_platform_driver(void) __init;
+void dra7xx_dpi_uninit_platform_driver(void) __exit;
/* DISPC */
int dispc_init_platform_driver(void) __init;
return 0;
}
#endif
+struct i2c_adapter *omapdss_hdmi_adapter(void);
int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev);
void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev);
int omapdss_hdmi_core_enable(struct omap_dss_device *dssdev);
bool hdmi_restart);
int omapdss_hdmi_display_3d_enable(struct omap_dss_device *dssdev,
struct s3d_disp_info *info, int code);
+void sel_i2c(void);
+void sel_hdmi(void);
int hdmi_panel_init(void);
void hdmi_panel_exit(void);
#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
}
#endif
+bool dss_dpll_disabled(enum dss_dpll dpll);
+int dss_dpll_calc_clock_div_pck(enum dss_dpll dpll, unsigned long pck_req,
+ struct dss_dpll_cinfo *dpll_cinfo,
+ struct dispc_clock_info *dispc_cinfo);
+int dss_dpll_set_clock_div(enum dss_dpll dpll, struct dss_dpll_cinfo *cinfo);
+void dss_dpll_enable_ctrl(enum dss_dpll dpll, bool enable);
+int dss_dpll_activate(enum dss_dpll dpll);
+void dss_dpll_set_control_mux(enum omap_channel channel, enum dss_dpll dpll);
+void dss_dpll_disable(enum dss_dpll dpll);
+int dss_dpll_configure(struct platform_device *pdev);
+int dss_dpll_configure_ctrl(void);
+void dss_dpll_unconfigure_ctrl(void);
+
#endif
diff --git a/drivers/video/omap2/dss/dss_dpll.c b/drivers/video/omap2/dss/dss_dpll.c
--- /dev/null
@@ -0,0 +1,574 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Ltd
+ *
+ * Copy of the DSI PLL code
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+
+#include <video/omapdss.h>
+
+#include "dss.h"
+#include "dss_features.h"
+
+#define CLK_CTRL 0x054
+#define PLL_CONTROL 0x300
+#define PLL_STATUS 0x304
+#define PLL_GO 0x308
+#define PLL_CONFIGURATION1 0x30C
+#define PLL_CONFIGURATION2 0x310
+#define PLL_CONFIGURATION3 0x314
+#define PLL_SSC_CONFIGURATION1 0x318
+#define PLL_SSC_CONFIGURATION2 0x31C
+
+#define CTRL_BASE 0x4a002500
+#define DSS_PLL_CONTROL 0x38
+
+#define REG_GET(dpll, idx, start, end) \
+ FLD_GET(dpll_read_reg(dpll, idx), start, end)
+
+#define REG_FLD_MOD(dpll, idx, val, start, end) \
+ dpll_write_reg(dpll, idx, FLD_MOD(dpll_read_reg(dpll, idx), val, start, end))
+
+static struct {
+ struct platform_device *pdev;
+ struct regulator *vdda_video_reg;
+
+ void __iomem *base[2], *control_base;
+ unsigned scp_refcount[2];
+ struct clk *sys_clk[2];
+} dss_dpll;
+
+static inline u32 dpll_read_reg(enum dss_dpll dpll, u16 offset)
+{
+ return __raw_readl(dss_dpll.base[dpll] + offset);
+}
+
+static inline void dpll_write_reg(enum dss_dpll dpll, u16 offset, u32 val)
+{
+ __raw_writel(val, dss_dpll.base[dpll] + offset);
+}
+
+#define CTRL_REG_GET(start, end) \
+ FLD_GET(ctrl_read_reg(), start, end)
+
+#define CTRL_REG_FLD_MOD(val, start, end) \
+ ctrl_write_reg(FLD_MOD(ctrl_read_reg(), val, start, end))
+
+static inline u32 ctrl_read_reg(void)
+{
+ return __raw_readl(dss_dpll.control_base + DSS_PLL_CONTROL);
+}
+
+static inline void ctrl_write_reg(u32 val)
+{
+ __raw_writel(val, dss_dpll.control_base + DSS_PLL_CONTROL);
+}
+
+static inline int wait_for_bit_change(enum dss_dpll dpll,
+ const u16 offset, int bitnum, int value)
+{
+ unsigned long timeout;
+ ktime_t wait;
+ int t;
+
+ /* first busyloop to see if the bit changes right away */
+ t = 100;
+ while (t-- > 0) {
+ if (REG_GET(dpll, offset, bitnum, bitnum) == value)
+ return value;
+ }
+
+ /* then loop for 500ms, sleeping for 1ms in between */
+ timeout = jiffies + msecs_to_jiffies(500);
+ while (time_before(jiffies, timeout)) {
+ if (REG_GET(dpll, offset, bitnum, bitnum) == value)
+ return value;
+
+ wait = ns_to_ktime(1000 * 1000);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
+ }
+
+ return !value;
+}
+
+bool dss_dpll_disabled(enum dss_dpll dpll)
+{
+ if (dpll == DSS_DPLL_VIDEO1)
+ return CTRL_REG_GET(0, 0);
+ else if (dpll == DSS_DPLL_VIDEO2)
+ return CTRL_REG_GET(1, 1);
+ else /* DSS_DPLL_HDMI */
+ return CTRL_REG_GET(2, 2);
+}
+
+int dss_dpll_calc_clock_div_pck(enum dss_dpll dpll, unsigned long req_pck,
+ struct dss_dpll_cinfo *dpll_cinfo, struct dispc_clock_info *dispc_cinfo)
+{
+ struct dss_dpll_cinfo cur, best;
+ struct dispc_clock_info best_dispc;
+ int min_fck_per_pck;
+ int match = 0;
+ unsigned long dss_sys_clk, max_dss_fck;
+ unsigned long fint_min, fint_max, regn_max, regm_max, regm_hsdiv_max;
+
+ dss_sys_clk = clk_get_rate(dss_dpll.sys_clk[dpll]);
+
+ fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
+ fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
+ regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
+ regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
+ regm_hsdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
+
+ max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
+
+ min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
+
+ if (min_fck_per_pck &&
+ req_pck * min_fck_per_pck > max_dss_fck) {
+ DSSERR("Requested pixel clock not possible with the current "
+ "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
+ "the constraint off.\n");
+ min_fck_per_pck = 0;
+ }
+
+ DSSDBG("dss_dpll_calc\n");
+
+retry:
+ memset(&best, 0, sizeof(best));
+ memset(&best_dispc, 0, sizeof(best_dispc));
+
+ memset(&cur, 0, sizeof(cur));
+ cur.clkin = dss_sys_clk;
+
+ for (cur.regn = 1; cur.regn < regn_max; ++cur.regn) {
+ cur.fint = cur.clkin / cur.regn;
+
+ if (cur.fint > fint_max || cur.fint < fint_min)
+ continue;
+
+ for (cur.regm = 1; cur.regm < regm_max; ++cur.regm) {
+ unsigned long a, b;
+ a = 2 * cur.regm * (cur.clkin / 1000);
+ b = cur.regn;
+ cur.clkout = a / b * 1000;
+
+ if (cur.clkout > 1800 * 1000 * 1000)
+ break;
+
+ for (cur.regm_hsdiv = 1;
+ cur.regm_hsdiv < regm_hsdiv_max;
+ ++cur.regm_hsdiv) {
+ struct dispc_clock_info cur_dispc;
+ cur.hsdiv_clk = cur.clkout / cur.regm_hsdiv;
+
+ if (cur.regm_hsdiv > 1 &&
+ cur.regm_hsdiv % 2 != 0 &&
+ req_pck >= 1000000)
+ continue;
+
+ /* this will narrow down the search a bit,
+ * but still give pixclocks below what was
+ * requested */
+ if (cur.hsdiv_clk < req_pck)
+ break;
+
+ if (cur.hsdiv_clk > max_dss_fck)
+ continue;
+
+ if (min_fck_per_pck && cur.hsdiv_clk <
+ req_pck * min_fck_per_pck)
+ continue;
+
+ match = 1;
+
+ dispc_find_clk_divs(req_pck, cur.hsdiv_clk, &cur_dispc);
+
+ if (abs(cur_dispc.pck - req_pck) <
+ abs(best_dispc.pck - req_pck)) {
+ best = cur;
+ best_dispc = cur_dispc;
+
+ if (cur_dispc.pck == req_pck)
+ goto found;
+ }
+ }
+ }
+ }
+
+found:
+ if (!match) {
+ if (min_fck_per_pck) {
+ DSSERR("Could not find suitable clock settings.\n"
+ "Turning FCK/PCK constraint off and"
+ "trying again.\n");
+ min_fck_per_pck = 0;
+ goto retry;
+ }
+
+ DSSERR("Could not find suitable clock settings.\n");
+
+ return -EINVAL;
+ }
+
+ if (dpll_cinfo)
+ *dpll_cinfo = best;
+ if (dispc_cinfo)
+ *dispc_cinfo = best_dispc;
+
+ return 0;
+}
+
+int dss_dpll_set_clock_div(enum dss_dpll dpll, struct dss_dpll_cinfo *cinfo)
+{
+ int r = 0;
+ u32 l;
+ u8 regn_start, regn_end, regm_start, regm_end;
+ u8 regm_hsdiv_start, regm_hsdiv_end;
+
+ DSSDBG("DPLL_VIDEO%d clock config starts\n", dpll + 1);
+
+ DSSDBG("DPLL Fint %ld\n", cinfo->fint);
+
+ DSSDBG("clkin rate %ld\n", cinfo->clkin);
+
+ DSSDBG("CLKOUT = 2 * %d / %d * %lu = %lu\n",
+ cinfo->regm,
+ cinfo->regn,
+ cinfo->clkin,
+ cinfo->clkout);
+
+ DSSDBG("regm_hsdiv = %d\n", cinfo->regm_hsdiv);
+
+ dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
+ dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
+ dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_hsdiv_start,
+ ®m_hsdiv_end);
+
+ /* PLL_AUTOMODE = manual */
+ REG_FLD_MOD(dpll, PLL_CONTROL, 0, 0, 0);
+
+ /* CONFIGURATION1 */
+ l = dpll_read_reg(dpll, PLL_CONFIGURATION1);
+ /* PLL_REGN */
+ l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
+ /* PLL_REGM */
+ l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
+ /* M4_CLOCK_DIV */
+ l = FLD_MOD(l, cinfo->regm_hsdiv > 0 ? cinfo->regm_hsdiv - 1 : 0,
+ regm_hsdiv_start, regm_hsdiv_end);
+ dpll_write_reg(dpll, PLL_CONFIGURATION1, l);
+
+ /* CONFIGURATION2 */
+ l = dpll_read_reg(dpll, PLL_CONFIGURATION2);
+ l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */
+ l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
+ l = FLD_MOD(l, 1, 20, 20); /* HSDIVBYPASS */
+ l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
+ dpll_write_reg(dpll, PLL_CONFIGURATION2, l);
+
+ REG_FLD_MOD(dpll, PLL_GO, 1, 0, 0); /* PLL_GO */
+
+ if (wait_for_bit_change(dpll, PLL_GO, 0, 0) != 0) {
+ DSSERR("dsi pll go bit not going down.\n");
+ r = -EIO;
+ goto err;
+ }
+
+ if (wait_for_bit_change(dpll, PLL_STATUS, 1, 1) != 1) {
+ DSSERR("cannot lock PLL\n");
+ r = -EIO;
+ goto err;
+ }
+
+ l = dpll_read_reg(dpll, PLL_CONFIGURATION2);
+ l = FLD_MOD(l, 0, 0, 0); /* PLL_IDLE */
+ l = FLD_MOD(l, 0, 5, 5); /* PLL_PLLLPMODE */
+ l = FLD_MOD(l, 0, 6, 6); /* PLL_LOWCURRSTBY */
+ l = FLD_MOD(l, 0, 7, 7); /* PLL_TIGHTPHASELOCK */
+ l = FLD_MOD(l, 0, 8, 8); /* PLL_DRIFTGUARDEN */
+ l = FLD_MOD(l, 0, 10, 9); /* PLL_LOCKSEL */
+ l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */
+ l = FLD_MOD(l, 1, 14, 14); /* PHY_CLKINEN */
+ l = FLD_MOD(l, 0, 15, 15); /* BYPASSEN */
+ l = FLD_MOD(l, 1, 16, 16); /* CLOCK_EN */
+ l = FLD_MOD(l, 0, 17, 17); /* CLOCK_PWDN */
+ l = FLD_MOD(l, 1, 18, 18); /* PROTO_CLOCK_EN */
+ l = FLD_MOD(l, 0, 19, 19); /* PROTO_CLOCK_PWDN */
+ l = FLD_MOD(l, 0, 20, 20); /* HSDIVBYPASS */
+ dpll_write_reg(dpll, PLL_CONFIGURATION2, l);
+
+ DSSDBG("PLL config done\n");
+
+err:
+ return r;
+}
+
+static void dss_dpll_disable_scp_clk(enum dss_dpll dpll)
+{
+ unsigned *refcount;
+
+ refcount = &dss_dpll.scp_refcount[dpll];
+
+ WARN_ON(*refcount == 0);
+ if (--(*refcount) == 0)
+ REG_FLD_MOD(dpll, CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
+}
+
+static void dss_dpll_enable_scp_clk(enum dss_dpll dpll)
+{
+ unsigned *refcount;
+
+ refcount = &dss_dpll.scp_refcount[dpll];
+
+ if ((*refcount)++ == 0)
+ REG_FLD_MOD(dpll, CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
+}
+
+static int dpll_power(enum dss_dpll dpll, int state)
+{
+ int t = 0;
+ /* PLL_PWR_CMD = enable both hsdiv and clkout*/
+ REG_FLD_MOD(dpll, CLK_CTRL, state, 31, 30);
+
+ /*
+ * PLL_PWR_STATUS doesn't correctly reflect the power state set on
+ * DRA7xx. Ignore the reg field and add a small delay for the power
+ * state to change.
+ */
+ if (omapdss_get_version() == OMAPDSS_VER_DRA7xx) {
+ msleep(1);
+ return 0;
+ }
+
+ /* PLL_PWR_STATUS */
+ while (FLD_GET(dpll_read_reg(dpll, CLK_CTRL), 29, 28) != state) {
+ if (++t > 1000) {
+ DSSERR("Failed to set DPLL power mode to %d\n", state);
+ return -ENODEV;
+ return 0;
+ }
+ udelay(1);
+ }
+
+ return 0;
+}
+
+void dss_dpll_enable_ctrl(enum dss_dpll dpll, bool enable)
+{
+ u8 bit;
+
+ switch (dpll) {
+ case DSS_DPLL_VIDEO1:
+ bit = 0;
+ break;
+ case DSS_DPLL_VIDEO2:
+ bit = 1;
+ break;
+ case DSS_DPLL_HDMI:
+ bit = 2;
+ break;
+ default:
+ DSSERR("invalid dpll\n");
+ return;
+ }
+
+ CTRL_REG_FLD_MOD(!enable, bit, bit);
+}
+
+static int dpll_init(enum dss_dpll dpll)
+{
+ int r;
+
+ clk_prepare_enable(dss_dpll.sys_clk[dpll]);
+ dss_dpll_enable_scp_clk(dpll);
+
+ r = regulator_enable(dss_dpll.vdda_video_reg);
+ if (r)
+ goto err_reg;
+
+ if (wait_for_bit_change(dpll, PLL_STATUS, 0, 1) != 1) {
+ DSSERR("PLL not coming out of reset.\n");
+ r = -ENODEV;
+ goto err_reset;
+ }
+
+ r = dpll_power(dpll, 0x2);
+ if (r)
+ goto err_reset;
+
+ return 0;
+
+err_reset:
+ regulator_disable(dss_dpll.vdda_video_reg);
+err_reg:
+ dss_dpll_disable_scp_clk(dpll);
+ clk_disable_unprepare(dss_dpll.sys_clk[dpll]);
+
+ return r;
+}
+
+int dss_dpll_activate(enum dss_dpll dpll)
+{
+ int r;
+
+ /* enable from control module */
+ dss_dpll_enable_ctrl(dpll, true);
+
+ r = dpll_init(dpll);
+
+ return r;
+}
+
+void dss_dpll_set_control_mux(enum omap_channel channel, enum dss_dpll dpll)
+{
+ u8 start, end;
+ u8 val;
+
+ if (channel == OMAP_DSS_CHANNEL_LCD) {
+ start = 4;
+ end = 3;
+
+ switch (dpll) {
+ case DSS_DPLL_VIDEO1:
+ val = 0;
+ break;
+ default:
+ printk("error in mux config\n");
+ return;
+ }
+ } else if (channel == OMAP_DSS_CHANNEL_LCD2) {
+ start = 6;
+ end = 5;
+
+ switch (dpll) {
+ case DSS_DPLL_VIDEO1:
+ val = 1;
+ break;
+ case DSS_DPLL_VIDEO2:
+ val = 0;
+ break;
+ default:
+ printk("error in mux config\n");
+ return;
+ }
+ } else {
+ start = 7;
+ end = 8;
+
+ switch (dpll) {
+ case DSS_DPLL_VIDEO1:
+ val = 0;
+ break;
+ case DSS_DPLL_VIDEO2:
+ val = 1;
+ break;
+ default:
+ printk("error in mux config\n");
+ return;
+ }
+ }
+
+ CTRL_REG_FLD_MOD(val, start, end);
+}
+
+void dss_dpll_disable(enum dss_dpll dpll)
+{
+ dpll_power(dpll, 0);
+
+ regulator_disable(dss_dpll.vdda_video_reg);
+
+ dss_dpll_disable_scp_clk(dpll);
+ clk_disable_unprepare(dss_dpll.sys_clk[dpll]);
+
+ dss_dpll_enable_ctrl(dpll, false);
+}
+
+static int dss_dpll_configure_one(struct platform_device *pdev,
+ enum dss_dpll dpll)
+{
+ struct resource *dpll_mem;
+
+ dpll_mem = platform_get_resource(pdev, IORESOURCE_MEM, dpll + 1);
+ if (!dpll_mem) {
+ DSSERR("can't get IORESOURCE_MEM for DPLL %d\n", dpll);
+ return -EINVAL;
+ }
+
+ dss_dpll.base[dpll] = devm_ioremap(&pdev->dev, dpll_mem->start,
+ resource_size(dpll_mem));
+ if (!dss_dpll.base[dpll]) {
+ DSSERR("can't ioremap DPLL %d\n", dpll);
+ return -ENOMEM;
+ }
+
+ dss_dpll.sys_clk[dpll] = devm_clk_get(&pdev->dev,
+ dpll == DSS_DPLL_VIDEO1 ? "video1_clk" : "video2_clk");
+ if (IS_ERR(dss_dpll.sys_clk[dpll])) {
+ DSSERR("can't get sys clock for DPLL_VIDEO%d\n", dpll + 1);
+ return PTR_ERR(dss_dpll.sys_clk[dpll]);
+ }
+
+ return 0;
+}
+
+int dss_dpll_configure(struct platform_device *pdev)
+{
+ int r;
+
+ r = dss_dpll_configure_one(pdev, DSS_DPLL_VIDEO1);
+ if (r)
+ return r;
+
+ r = dss_dpll_configure_one(pdev, DSS_DPLL_VIDEO2);
+ if (r)
+ return r;
+
+ dss_dpll.vdda_video_reg = devm_regulator_get(&pdev->dev, "vdda_video");
+ if (IS_ERR(dss_dpll.vdda_video_reg)) {
+ DSSERR("can't get vdda_video regulator\n");
+ return PTR_ERR(dss_dpll.vdda_video_reg);
+ }
+
+ dss_dpll.pdev = pdev;
+
+ return 0;
+}
+
+int dss_dpll_configure_ctrl(void)
+{
+ dss_dpll.control_base = ioremap(CTRL_BASE, SZ_1K);
+
+ if (!dss_dpll.control_base) {
+ DSSERR("can't ioremap control base\n");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+void dss_dpll_unconfigure_ctrl(void) {
+ if (dss_dpll.control_base)
+ iounmap(dss_dpll.control_base);
+}
index a29f40168852c6ddf2110587802eb77d546d15d6..8ae30bd19cb9e1be3cabd81d1fbb003668a7d219 100644 (file)
};
struct dss_param_range {
- int min, max;
+ unsigned long min, max;
};
struct omap_dss_features {
OMAP_DISPLAY_TYPE_DSI,
};
+static const enum omap_display_type dra7xx_dss_supported_displays[] = {
+ /* OMAP_DSS_CHANNEL_LCD */
+ OMAP_DISPLAY_TYPE_DPI,
+
+ /* OMAP_DSS_CHANNEL_DIGIT */
+ OMAP_DISPLAY_TYPE_HDMI | OMAP_DISPLAY_TYPE_DPI,
+
+ /* OMAP_DSS_CHANNEL_LCD2 */
+ OMAP_DISPLAY_TYPE_DPI,
+
+ /* OMAP_DSS_CHANNEL_LCD3 */
+ OMAP_DISPLAY_TYPE_DPI,
+};
+
static const enum omap_dss_output_id omap2_dss_supported_outputs[] = {
/* OMAP_DSS_CHANNEL_LCD */
OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI,
OMAP_DSS_OUTPUT_DSI2,
};
+static const enum omap_dss_output_id dra7xx_dss_supported_outputs[] = {
+ /* OMAP_DSS_CHANNEL_LCD */
+ OMAP_DSS_OUTPUT_DPI,
+
+ /* OMAP_DSS_CHANNEL_DIGIT */
+ OMAP_DSS_OUTPUT_HDMI | OMAP_DSS_OUTPUT_DPI,
+
+ /* OMAP_DSS_CHANNEL_LCD2 */
+ OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DPI1,
+
+ /* OMAP_DSS_CHANNEL_LCD3 */
+ OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DPI2,
+};
+
static const enum omap_color_mode omap2_dss_supported_color_modes[] = {
/* OMAP_DSS_GFX */
OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
* scaler cannot scale a image with width more than 768.
*/
[FEAT_PARAM_LINEWIDTH] = { 1, 768 },
+ [FEAT_PARAM_HDMI_PCLK] = { 0, 0 },
+ [FEAT_PARAM_HDMIPLL_FINT] = { 0, 0 },
+ [FEAT_PARAM_HDMIPLL_REGM] = { 0, 0 },
+ [FEAT_PARAM_DCOFREQ_LOW] = { 0, 0 },
+ [FEAT_PARAM_DCOFREQ_HIGH] = { 0, 0 },
};
static const struct dss_param_range omap3_dss_param_range[] = {
[FEAT_PARAM_DSI_FCK] = { 0, 173000000 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 1024 },
+ [FEAT_PARAM_HDMI_PCLK] = { 0, 0 },
+ [FEAT_PARAM_HDMIPLL_FINT] = { 0, 0 },
+ [FEAT_PARAM_HDMIPLL_REGM] = { 0, 0 },
+ [FEAT_PARAM_DCOFREQ_LOW] = { 0, 0 },
+ [FEAT_PARAM_DCOFREQ_HIGH] = { 0, 0 },
};
static const struct dss_param_range omap4_dss_param_range[] = {
[FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
+ [FEAT_PARAM_HDMI_PCLK] = { 1, 185675000 },
+ [FEAT_PARAM_HDMIPLL_FINT] = { 500000, 2500000 },
+ [FEAT_PARAM_HDMIPLL_REGM] = { 0, (1 << 12) - 1 },
+ [FEAT_PARAM_DCOFREQ_LOW] = { 500000000, 1000000000 },
+ [FEAT_PARAM_DCOFREQ_HIGH] = { 1000000000, 2000000000 },
};
static const struct dss_param_range omap5_dss_param_range[] = {
[FEAT_PARAM_DSI_FCK] = { 0, 170000000 },
[FEAT_PARAM_DOWNSCALE] = { 1, 4 },
[FEAT_PARAM_LINEWIDTH] = { 1, 2048 },
+ [FEAT_PARAM_HDMI_PCLK] = { 1, 186000000 },
+ [FEAT_PARAM_HDMIPLL_FINT] = { 500000, 2500000 },
+ [FEAT_PARAM_HDMIPLL_REGM] = { 20, 2046 },
+ [FEAT_PARAM_DCOFREQ_LOW] = { 750000000, 1500000000 },
+ [FEAT_PARAM_DCOFREQ_HIGH] = { 1250000000, 2500000000UL },
};
static const enum dss_feat_id omap2_dss_feat_list[] = {
.burst_size_unit = 16,
};
+/* DRA DSS Features */
+static const struct omap_dss_features dra7xx_dss_features = {
+ .reg_fields = omap5_dss_reg_fields,
+ .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields),
+
+ .features = omap5_dss_feat_list,
+ .num_features = ARRAY_SIZE(omap5_dss_feat_list),
+
+ .num_mgrs = 4,
+ .num_ovls = 4,
+ .supported_displays = dra7xx_dss_supported_displays,
+ .supported_outputs = dra7xx_dss_supported_outputs,
+ .supported_color_modes = omap4_dss_supported_color_modes,
+ .overlay_caps = omap4_dss_overlay_caps,
+ .clksrc_names = omap5_dss_clk_source_names,
+ .dss_params = omap5_dss_param_range,
+ .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER,
+ .buffer_size_unit = 16,
+ .burst_size_unit = 16,
+};
+
#if defined(CONFIG_OMAP4_DSS_HDMI) || defined(CONFIG_OMAP5_DSS_HDMI)
/* HDMI OMAP4 Functions*/
static const struct ti_hdmi_ip_ops omap4_hdmi_functions = {
ip_data->ops = &omap4_hdmi_functions;
break;
case OMAPDSS_VER_OMAP5:
+ case OMAPDSS_VER_DRA7xx:
ip_data->ops = &omap5_hdmi_functions;
break;
default:
omap_current_dss_features = &omap5_dss_features;
break;
+ case OMAPDSS_VER_DRA7xx:
+ omap_current_dss_features = &dra7xx_dss_features;
+ break;
+
case OMAPDSS_VER_AM35xx:
omap_current_dss_features = &am35xx_dss_features;
break;
index 188ceececf5082a21e261f533948367c14d5542c..2dc25fb89d4ea28f19a1774e1d12a19a60f48e02 100644 (file)
FEAT_PARAM_DSI_FCK,
FEAT_PARAM_DOWNSCALE,
FEAT_PARAM_LINEWIDTH,
+ FEAT_PARAM_HDMI_PCLK,
+ FEAT_PARAM_HDMIPLL_FINT,
+ FEAT_PARAM_HDMIPLL_REGM,
+ FEAT_PARAM_DCOFREQ_LOW,
+ FEAT_PARAM_DCOFREQ_HIGH,
};
/* DSS Feature Functions */
index 1ad294ad52f493e8072c1902378d404c6a76f0bf..133da16ef8633f9af75d99606adfefd3a822208d 100644 (file)
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/of_gpio.h>
+#include <linux/of_i2c.h>
#include <video/omapdss.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
#include "ti_hdmi.h"
#include "dss.h"
#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4
#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4
-#define HDMI_DEFAULT_REGN 16
-#define HDMI_DEFAULT_REGM2 1
-
static struct {
struct mutex lock;
struct platform_device *pdev;
struct clk *sys_clk;
struct regulator *vdda_hdmi_dac_reg;
+ /* GPIO pins */
int ct_cp_hpd_gpio;
int ls_oe_gpio;
int hpd_gpio;
+ /* level shifter state */
+ enum level_shifter_state ls_state;
+
+ /*
+ * i2c adapter info(this could be either a bitbanged adapter, or a
+ * 'real' i2c adapter
+ */
+ struct i2c_adapter *adap;
+
+ /* these are needed in case it's a bitbanged adapter */
+ struct i2c_algo_bit_data bit_data;
+ int scl_pin;
+ int sda_pin;
+
struct omap_dss_output output;
} hdmi;
},
};
+static void hdmi_set_ls_state(enum level_shifter_state state)
+{
+ bool hpd_enable = false;
+ bool ls_enable = false;
+
+ /* return early if we have nothing to do */
+ if (state == hdmi.ls_state)
+ return;
+
+ sel_i2c();
+
+ switch (state) {
+ case LS_HPD_ON:
+ hpd_enable = true;
+ break;
+
+ case LS_ENABLED:
+ hpd_enable = true;
+ ls_enable = true;
+ break;
+
+ case LS_DISABLED:
+ default:
+ break;
+ }
+
+ gpio_set_value_cansleep(hdmi.ct_cp_hpd_gpio, hpd_enable);
+
+ gpio_set_value_cansleep(hdmi.ls_oe_gpio, ls_enable);
+
+ /* wait 300us after asserting CT_CP_HPD for the 5V rail to reach 90% */
+ if (hdmi.ls_state == LS_DISABLED)
+ udelay(300);
+
+ hdmi.ls_state = state;
+
+ sel_hdmi();
+}
+
static int hdmi_runtime_get(void)
{
int r;
return hdmi.ip_data.cfg.timings.pixel_clock * 1000;
}
-static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
+static int hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
struct hdmi_pll_info *pi)
{
unsigned long clkin, refclk;
- enum omapdss_version version = omapdss_get_version();
+ int phy_calc;
+ unsigned long regn_max, regn_min, regm_min, regm_max;
+ unsigned long fint_min, fint_max;
+ unsigned long dco_low_min, dco_high_min;
+ bool found = false;
u32 mf;
clkin = clk_get_rate(hdmi.sys_clk) / 10000;
- /*
- * Input clock is predivided by N + 1
- * out put of which is reference clk
- */
- if (dssdev->clocks.hdmi.regn == 0)
- pi->regn = HDMI_DEFAULT_REGN;
- else
- pi->regn = dssdev->clocks.hdmi.regn;
- refclk = clkin / pi->regn;
+ fint_min = dss_feat_get_param_min(FEAT_PARAM_HDMIPLL_FINT) / 10000;
+ fint_max = dss_feat_get_param_max(FEAT_PARAM_HDMIPLL_FINT) / 10000;
- if (dssdev->clocks.hdmi.regm2 == 0) {
- switch (version)
- {
- case OMAPDSS_VER_OMAP4430_ES1:
- case OMAPDSS_VER_OMAP4430_ES2:
- case OMAPDSS_VER_OMAP4:
- pi->regm2 = HDMI_DEFAULT_REGM2;
- break;
- case OMAPDSS_VER_OMAP5:
- if (phy <= 50000)
- pi->regm2 = 5;
- else
- pi->regm2 = 1;
- break;
- default:
- DSSWARN("invalid omapdss version");
- break;
+ /* clkin limits */
+ /* .62 MHz < CLKIN/REGN < 2.5MHz */
+ regn_min = clkin / fint_max + 1;
+ regn_max = clkin / fint_min;
+
+ /* Fractional limits on REGM */
+ regm_min = dss_feat_get_param_min(FEAT_PARAM_HDMIPLL_REGM);
+ regm_max = dss_feat_get_param_max(FEAT_PARAM_HDMIPLL_REGM);
+
+ /* DCO frequency ranges */
+
+ /* DCO lowest frequency supported */
+ dco_low_min = dss_feat_get_param_min(FEAT_PARAM_DCOFREQ_LOW) / 10000;
+
+ /* Starting frequency of high frequency range(in Mhz) */
+ dco_high_min = dss_feat_get_param_min(FEAT_PARAM_DCOFREQ_HIGH);
+
+ /* set dcofreq to 1 if required clock is > 1.25GHz */
+ pi->dcofreq = phy > (dco_high_min / 10000);
+
+ if (phy < dco_low_min) {
+ /* Calculate CLKOUTLDO - low frequency */
+ for (pi->regn = regn_min; pi->regn < regn_max; pi->regn++) {
+ refclk = clkin / pi->regn;
+ regm_min = ((dco_low_min / refclk) < regm_min) ?
+ regm_min : (dco_low_min / refclk);
+
+ for (pi->regm2 = 3; pi->regm2 <= 127; pi->regm2++) {
+ pi->regm = phy * pi->regm2 / refclk;
+ if (pi->regm < regm_min || pi->regm > regm_max)
+ continue;
+
+ pi->regsd = DIV_ROUND_UP((pi->regm * clkin / 100),
+ pi->regn * 250);
+ phy_calc = clkin * pi->regm / pi->regn /
+ pi->regm2;
+
+ if (pi->regsd && pi->regsd < 255 &&
+ phy_calc <= phy) {
+ found = true;
+ break;
+ }
+ }
+
+ if (found)
+ break;
}
} else {
- pi->regm2 = dssdev->clocks.hdmi.regm2;
+ pi->regm2 = 1;
+
+ /* CLKDCOLDO - high frequency */
+ for (pi->regn = regn_min; pi->regn < regn_max; pi->regn++) {
+ refclk = clkin / pi->regn;
+ pi->regm = phy / refclk;
+
+ if (pi->regm < regm_min || pi->regm > regm_max)
+ continue;
+
+ pi->regsd = DIV_ROUND_UP((pi->regm * clkin / 100),
+ pi->regn * 250);
+
+ phy_calc = clkin * pi->regm / pi->regn;
+
+ if (pi->regsd < 255 && phy_calc <= phy) {
+ found = true;
+ break;
+ }
+ }
}
- /*
- * multiplier is pixel_clk/ref_clk
- * Multiplying by 100 to avoid fractional part removal
- */
- pi->regm = phy * pi->regm2 / refclk;
+ if (!found) {
+ DSSERR("Failed to find pll settings\n");
+ return 1;
+ }
/*
* fractional multiplier is remainder of the difference between
* multiplier and actual phy(required pixel clock thus should be
* multiplied by 2^18(262144) divided by the reference clock
*/
- mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
+ mf = (phy - refclk * pi->regm / pi->regm2) * 262144;
pi->regmf = pi->regm2 * mf / refclk;
- /*
- * Dcofreq should be set to 1 if required pixel clock
- * is greater than 1000MHz
- */
- pi->dcofreq = phy > 1000 * 100;
- pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
+ if (pi->regmf > 262144)
+ pi->regmf = 0;
/* Set the reference clock to sysclk reference */
pi->refsel = HDMI_REFSEL_SYSCLK;
- DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
- DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
+ DSSERR("M = %d Mf = %d\n", pi->regm, pi->regmf);
+ DSSERR("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
+
+ return 0;
}
static int hdmi_power_on_core(struct omap_dss_device *dssdev)
{
int r;
- if (gpio_cansleep(hdmi.ct_cp_hpd_gpio))
- gpio_set_value_cansleep(hdmi.ct_cp_hpd_gpio, 1);
- else
- gpio_set_value(hdmi.ct_cp_hpd_gpio, 1);
-
- if (gpio_cansleep(hdmi.ls_oe_gpio))
- gpio_set_value_cansleep(hdmi.ls_oe_gpio, 1);
- else
- gpio_set_value(hdmi.ls_oe_gpio, 1);
-
- /* wait 300us after CT_CP_HPD for the 5V power output to reach 90% */
- udelay(300);
+ hdmi_set_ls_state(LS_ENABLED);
r = regulator_enable(hdmi.vdda_hdmi_dac_reg);
if (r)
err_runtime_get:
regulator_disable(hdmi.vdda_hdmi_dac_reg);
err_vdac_enable:
- if (gpio_cansleep(hdmi.ct_cp_hpd_gpio))
- gpio_set_value_cansleep(hdmi.ct_cp_hpd_gpio, 0);
- else
- gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
-
- if (gpio_cansleep(hdmi.ls_oe_gpio))
- gpio_set_value_cansleep(hdmi.ls_oe_gpio, 0);
- else
- gpio_set_value(hdmi.ls_oe_gpio, 0);
+ hdmi_set_ls_state(LS_HPD_ON);
return r;
}
{
hdmi_runtime_put();
regulator_disable(hdmi.vdda_hdmi_dac_reg);
- if (gpio_cansleep(hdmi.ct_cp_hpd_gpio))
- gpio_set_value_cansleep(hdmi.ct_cp_hpd_gpio, 0);
- else
- gpio_set_value(hdmi.ct_cp_hpd_gpio, 0);
- if (gpio_cansleep(hdmi.ls_oe_gpio))
- gpio_set_value_cansleep(hdmi.ls_oe_gpio, 0);
- else
- gpio_set_value(hdmi.ls_oe_gpio, 0);
+ hdmi_set_ls_state(LS_HPD_ON);
}
static int hdmi_power_on_full(struct omap_dss_device *dssdev)
phy = (p->pixel_clock * 125) / 100 ;
break;
case HDMI_DEEP_COLOR_36BIT:
- if (p->pixel_clock >= 148500) {
+ phy = (p->pixel_clock * 150) / 100;
+
+ if (phy >= dss_feat_get_param_max(FEAT_PARAM_HDMI_PCLK)) {
DSSERR("36 bit deep color not supported for the pixel clock %d\n",
p->pixel_clock);
goto err_deep_color;
}
- phy = (p->pixel_clock * 150) / 100;
break;
case HDMI_DEEP_COLOR_24BIT:
default:
break;
}
- hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data);
+ if (hdmi_compute_pll(dssdev, phy, &hdmi.ip_data.pll_data))
+ goto err_pll_compute;
hdmi.ip_data.ops->video_disable(&hdmi.ip_data);
}
r = hdmi.ip_data.ops->phy_enable(&hdmi.ip_data);
+ /*
+ * DRA7xx doesn't show the correct PHY transition changes in the
+ * WP_PWR_CTRL register, need to investigate
+ */
+ if (omapdss_get_version() == OMAPDSS_VER_DRA7xx)
+ r = 0;
+
if (r) {
DSSDBG("Failed to start PHY\n");
goto err_phy_enable;
err_phy_enable:
hdmi.ip_data.ops->pll_disable(&hdmi.ip_data);
err_pll_enable:
+err_pll_compute:
err_deep_color:
hdmi_power_off_core(dssdev);
return -EIO;
int omapdss_hdmi_read_edid(u8 *buf, int len)
{
int r;
+ enum level_shifter_state restore_state = hdmi.ls_state;
+
+ /* skip if no monitor attached */
+ if (!gpio_get_value(hdmi.hpd_gpio))
+ return -ENODEV;
mutex_lock(&hdmi.lock);
r = hdmi_runtime_get();
BUG_ON(r);
+
+ hdmi_set_ls_state(LS_ENABLED);
+
r = hdmi.ip_data.ops->read_edid(&hdmi.ip_data, buf, len);
+ /* restore level shifter state */
+ hdmi_set_ls_state(restore_state);
+
hdmi_runtime_put();
mutex_unlock(&hdmi.lock);
}
}
+struct i2c_adapter *omapdss_hdmi_adapter(void)
+{
+ return hdmi.adap;
+}
+
+static void ddc_set_sda(void *data, int state)
+{
+ if (state)
+ gpio_direction_input(hdmi.sda_pin);
+ else
+ gpio_direction_output(hdmi.sda_pin, 0);
+}
+
+static void ddc_set_scl(void *data, int state)
+{
+ if (state)
+ gpio_direction_input(hdmi.scl_pin);
+ else
+ gpio_direction_output(hdmi.scl_pin, 0);
+}
+
+static int ddc_get_sda(void *data)
+{
+ return gpio_get_value(hdmi.sda_pin);
+}
+
+static int ddc_get_scl(void *data)
+{
+ return gpio_get_value(hdmi.scl_pin);
+}
+
+static int ddc_pre_xfer(struct i2c_adapter *adap)
+{
+ /* don't read if no hdmi connected */
+ if (!gpio_get_value(hdmi.hpd_gpio))
+ return -ENODEV;
+
+ gpio_set_value_cansleep(hdmi.ls_oe_gpio, 1);
+
+ return 0;
+}
+static void ddc_post_xfer(struct i2c_adapter *adap)
+{
+ hdmi_set_ls_state(hdmi.ls_state);
+}
+
+static void ddc_i2c_init(struct platform_device *pdev)
+{
+
+ hdmi.adap = kzalloc(sizeof(*hdmi.adap), GFP_KERNEL);
+
+ if (!hdmi.adap) {
+ pr_err("Failed to allocate i2c adapter\n");
+ return;
+ }
+
+ hdmi.adap->owner = THIS_MODULE;
+ hdmi.adap->class = I2C_CLASS_DDC;
+ hdmi.adap->dev.parent = &pdev->dev;
+ hdmi.adap->algo_data = &hdmi.bit_data;
+ hdmi.adap->algo = &i2c_bit_algo;
+ hdmi.bit_data.udelay = 2;
+ hdmi.bit_data.timeout = HZ/10;
+ hdmi.bit_data.setsda = ddc_set_sda;
+ hdmi.bit_data.setscl = ddc_set_scl;
+ hdmi.bit_data.getsda = ddc_get_sda;
+ hdmi.bit_data.getscl = ddc_get_scl;
+ hdmi.bit_data.pre_xfer = ddc_pre_xfer;
+ hdmi.bit_data.post_xfer = ddc_post_xfer;
+
+ gpio_request(hdmi.sda_pin, "DDC SDA");
+ gpio_request(hdmi.scl_pin, "DDC SCL");
+ snprintf(hdmi.adap->name, sizeof(hdmi.adap->name),
+ "DSS DDC-EDID adapter");
+ if (i2c_add_adapter(hdmi.adap)) {
+ DSSERR("Cannot initialize DDC I2c\n");
+ kfree(hdmi.adap);
+ hdmi.adap = NULL;
+ }
+}
+
+static void init_sel_i2c_hdmi(void)
+{
+ void __iomem *clk_base = ioremap(0x4A009000, SZ_4K);
+ void __iomem *mcasp2_base = ioremap(0x48464000, SZ_1K);
+ void __iomem *pinmux = ioremap(0x4a003600, SZ_1K);
+ u32 val;
+
+ if (omapdss_get_version() != OMAPDSS_VER_DRA7xx)
+ goto err;
+
+ if (!clk_base || !mcasp2_base || !pinmux)
+ DSSERR("couldn't ioremap for clk or mcasp2\n");
+
+ __raw_writel(0x40000, pinmux + 0xfc);
+ /* sw supervised wkup */
+ __raw_writel(0x2, clk_base + 0x8fc);
+
+ /* enable clock domain */
+ __raw_writel(0x2, clk_base + 0x860);
+
+ /* see what status looks like */
+ val = __raw_readl(clk_base + 0x8fc);
+ printk("CM_L4PER2_CLKSTCTRL %x\n", val);
+
+ /*
+ * mcasp2 regs should be hopefully accessible, make mcasp2_aclkr
+ * a gpio, write necessary stuff to MCASP_PFUNC and PDIR
+ */
+ __raw_writel(0x1 << 29, mcasp2_base + 0x10);
+ __raw_writel(0x1 << 29, mcasp2_base + 0x14);
+
+err:
+ iounmap(clk_base);
+ iounmap(mcasp2_base);
+ iounmap(pinmux);
+}
+
+/* use this to configure the pcf8575@22 to set LS_OE and CT_HPD */
+void sel_i2c(void)
+{
+ void __iomem *base = ioremap(0x48464000, SZ_1K);
+
+ if (omapdss_get_version() != OMAPDSS_VER_DRA7xx)
+ goto err;
+
+ /* PDOUT */
+ __raw_writel(0x0, base + 0x18);
+
+ DSSDBG("PDOUT sel_i2c %x\n", __raw_readl(base + 0x18));
+
+err:
+ iounmap(base);
+}
+
+/* use this to read edid and detect hpd ? */
+void sel_hdmi(void)
+{
+ void __iomem *base = ioremap(0x48464000, SZ_1K);
+
+ if (omapdss_get_version() != OMAPDSS_VER_DRA7xx)
+ goto err;
+
+ /* PDOUT */
+ __raw_writel(0x20000000, base + 0x18);
+
+ DSSDBG("PDOUT sel_hdmi %x\n", __raw_readl(base + 0x18));
+
+err:
+ iounmap(base);
+}
+
static void __init hdmi_probe_of(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
struct device_node *child;
struct omap_dss_device *dssdev;
+ struct device_node *adapter_node;
+ struct i2c_adapter *adapter = NULL;
int r, gpio;
enum omap_channel channel;
u32 v;
+ int gpio_count;
r = of_property_read_u32(node, "video-source", &v);
if (r) {
if (!child)
return;
- if (of_gpio_count(node) != 3) {
+ gpio_count = of_gpio_count(node);
+
+ /* OMAP4 derivatives have 3 pins defined, OMAP5 derivatives have 5 */
+ if (gpio_count != 5 && gpio_count != 3) {
DSSERR("wrong number of GPIOs\n");
return;
}
return;
}
+ adapter_node = of_parse_phandle(node, "hdmi_ddc", 0);
+ if (adapter_node)
+ adapter = of_find_i2c_adapter_by_node(adapter_node);
+
+ /*
+ * if I2C SCL and SDA pins are defined, parse them, if an adapter is
+ * present, use the i2c adapter rather than bitbanging i2c. If there
+ * isn't an adapter either, assume that we are using the hdmi core IP's
+ * ddc.
+ */
+ if (gpio_count == 5) {
+ gpio = of_get_gpio(node, 3);
+ if (gpio_is_valid(gpio)) {
+ hdmi.scl_pin = gpio;
+ } else {
+ DSSERR("failed to parse SCL gpio\n");
+ return;
+ }
+
+ gpio = of_get_gpio(node, 4);
+ if (gpio_is_valid(gpio)) {
+ hdmi.sda_pin = gpio;
+ } else {
+ DSSERR("failed to parse SDA gpio\n");
+ return;
+ }
+ } else if (adapter != NULL) {
+ hdmi.adap = adapter;
+
+ /*
+ * we have SEL_I2C_HDMI pin which acts as a control line to
+ * a demux which choses the i2c lines to go either to hdmi
+ * or to the other i2c2 slaves. This line is used as a mcasp2
+ * gpio. Init the gpio pin so that it can be used to control
+ * the demux.
+ */
+ init_sel_i2c_hdmi();
+ sel_i2c();
+ }
+
dssdev = dss_alloc_and_init_device(&pdev->dev);
if (!dssdev)
return;
else if (pdev->dev.platform_data)
hdmi_probe_pdata(pdev);
+ /* if i2c pins defined, setup I2C adapter */
+ if (hdmi.scl_pin && hdmi.sda_pin)
+ ddc_i2c_init(pdev);
+
#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO) || \
defined(CONFIG_OMAP5_DSS_HDMI_AUDIO)
r = hdmi_probe_audio(pdev);
platform_device_unregister(hdmi.audio_pdev);
#endif
+ kfree(hdmi.adap);
+
device_for_each_child(&pdev->dev, NULL, hdmi_remove_child);
dss_unregister_child_devices(&pdev->dev);
index 9574f4dbddc9661ef7bd3b4b37c8adf90aa7cbf6..95090f27daaf6c26d363f153900536d5f48021f2 100644 (file)
omapdss_hdmi_display_set_timing(dssdev, &dssdev->panel.timings);
+ hdmi.dssdev = dssdev;
+
return 0;
}
index 02eae1508d0f7216917622a75eb551d590e63826..2966a3af5884053afe3a31e603c5c2b1cfddb038 100644 (file)
struct hdmi_audio_dma;
#endif
+enum level_shifter_state {
+ LS_DISABLED = 0, /* HPD off, LS off */
+ LS_HPD_ON, /* HPD on, LS off */
+ LS_ENABLED, /* HPD on, LS on */
+};
+
enum hdmi_pll_pwr {
HDMI_PLLPWRCMD_ALLOFF = 0,
HDMI_PLLPWRCMD_PLLONLY = 1,
u16 regsd;
u16 dcofreq;
enum hdmi_clk_refsel refsel;
+
+ /* pll constraints */
+ u32 dco_limit;
+ u32 refclk_min;
+ u32 refclk_max;
};
struct hdmi_irq_vector {
index 947ec62aec58270ab9c366f0e892e21e5bb8bec9..2b79e861a837a6ff027248b76cc342765fbb9de8 100644 (file)
val = 0;
break;
case OMAPDSS_VER_OMAP5:
+ case OMAPDSS_VER_DRA7xx:
val = 1;
break;
default:
{
u16 r = 0;
+ if (omapdss_get_version() == OMAPDSS_VER_DRA7xx)
+ dss_dpll_enable_ctrl(DSS_DPLL_HDMI, true);
+
r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
if (r)
return r;
void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
{
hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
+
+ if (omapdss_get_version() == OMAPDSS_VER_DRA7xx)
+ dss_dpll_enable_ctrl(DSS_DPLL_HDMI, false);
}
static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data)
r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
else
r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
+
/*
- * HDMI_WP_PWR_CTRL doesn't seem to reflect the change in power
- * states, ignore the error for now
+ * DRA7xx doesn't show the correct PHY transition changes in the
+ * WP_PWR_CTRL register, need to investigate
*/
-#if 0
+ if (omapdss_get_version() == OMAPDSS_VER_DRA7xx)
+ r = 0;
+
if (r) {
DSSERR("Failed to %s PHY TX power\n",
hpd ? "enable" : "disable");
goto err;
}
-#endif
-
-#if 0
err:
-#endif
mutex_unlock(&ip_data->lock);
return r;
}
void __iomem *phy_base = hdmi_phy_base(ip_data);
enum omapdss_version version = omapdss_get_version();
unsigned long pclk = ip_data->cfg.timings.pixel_clock;
+ unsigned long dcofreq_min = dss_feat_get_param_max(FEAT_PARAM_DCOFREQ_LOW) / 1000;
u16 freqout = 1;
/*
* In OMAP5, the HFBITCLK must be divided by 2 before issuing the
* HDMI_PHYPWRCMD_LDOON command.
*/
- if (version == OMAPDSS_VER_OMAP5)
+ if (version == OMAPDSS_VER_OMAP5 || version == OMAPDSS_VER_DRA7xx)
REG_FLD_MOD(phy_base, HDMI_TXPHY_BIST_CONTROL, 1, 11, 11);
r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
-
- /*
- * HDMI_WP_PWR_CTRL doesn't seem to reflect the change in power
- * states, ignore the error for now
- */
-#if 0
if (r)
return r;
-#endif
/*
* Read address 0 in order to get the SCP reset done completed
freqout = 1;
break;
case OMAPDSS_VER_OMAP5:
- if (pclk < 62500) {
+ case OMAPDSS_VER_DRA7xx:
+ if (pclk < dcofreq_min) {
freqout = 0;
- } else if ((pclk >= 62500) && (pclk < 185000)) {
+ } else if ((pclk >= dcofreq_min) && (pclk < 185000)) {
freqout = 1;
} else {
/* clock frequency > 185MHz */
/* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
- /* Setup max LDO voltage */
- REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
+ /* OMAP5 HDMI PHY has these bits reserved */
+ if (version != OMAPDSS_VER_OMAP5 && version != OMAPDSS_VER_DRA7xx)
+ /* Setup max LDO voltage */
+ REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
/* Write to phy address 3 to change the polarity control */
REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
{
+ enum omapdss_version ver = omapdss_get_version();
+
#define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
hdmi_read_reg(hdmi_phy_base(ip_data), r))
DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
DUMPPHY(HDMI_TXPHY_POWER_CTRL);
DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
- if (omapdss_get_version() == OMAPDSS_VER_OMAP5)
+ if (ver == OMAPDSS_VER_OMAP5 || ver == OMAPDSS_VER_DRA7xx)
DUMPPHY(HDMI_TXPHY_BIST_CONTROL);
}
index 69570cbd5d74065ff8ea7116ad54b82ccf543b37..232d708df0e2e50e4dd092160b1a30a6032d54ec 100644 (file)
REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_OPERATION, 1, 0, 0);
}
-static void hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
-{
- void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
-
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_SDA_HOLD_ADDR, 0x19, 7, 0);
-
- /*Mask the interrupts*/
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_CTLINT, 0x0, 2, 2);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_CTLINT, 0x0, 6, 6);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_INT, 0x0, 2, 2);
-
- /* Master clock division */
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_DIV, 0x5, 3, 0);
-
- /* Standard speed counter */
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, 0x0,
- 7, 0);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, 0x79,
- 7, 0);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, 0x0,
- 7, 0);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, 0x91,
- 7, 0);
-
- /* Fast speed counter*/
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, 0x0,
- 7, 0);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, 0x0F,
- 7, 0);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR, 0x0,
- 7, 0);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR, 0x21,
- 7, 0);
-
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_SLAVE, 0x50, 6, 0);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_SEGADDR, 0x30, 6, 0);
-}
+#define EDID_LENGTH 128
-static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
- u8 *pedid, int ext)
+static int read_one_block(u8 *edid, unsigned int block)
{
- u8 cur_addr = 0;
- char checksum = 0;
- void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
+ struct i2c_adapter *adapter = omapdss_hdmi_adapter();
+ unsigned char start = block * EDID_LENGTH;
+ unsigned char segment = block >> 1;
+ unsigned char xfers = segment ? 3 : 2;
+
+ struct i2c_msg msgs[] = {
+ {
+ .addr = 0x30,
+ .flags = 0,
+ .len = 1,
+ .buf = &segment,
+ },
+ {
+ .addr = 0x50,
+ .flags = 0,
+ .len = 1,
+ .buf = &start,
+ },
+ {
+ .addr = 0x50,
+ .flags = I2C_M_RD,
+ .len = EDID_LENGTH,
+ .buf = edid,
+ }
+ };
- hdmi_core_ddc_req_addr(ip_data, cur_addr, ext);
+ int r, retries = 5;
- /* Unmask the interrupts*/
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_CTLINT, 0x1, 2, 2);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_CTLINT, 0x1, 6, 6);
- REG_FLD_MOD(core_sys_base, HDMI_CORE_I2CM_INT, 0x1, 2, 2);
+ if (!adapter)
+ return -ENODEV;
- /* FIXME:This is a hack to read only 128 bytes data with a mdelay
- * Ideally the read has to be based on the done interrupt and
- * status which is not received thus it is ignored for now
- */
- while (cur_addr < 128) {
- #if 0
- if (hdmi_wait_for_bit_change(HDMI_CORE_I2CM_INT,
- 0, 0, 1) != 1) {
- DSSERR("Failed to recieve done interrupt\n");
- return -ETIMEDOUT;
- }
- #endif
- mdelay(1);
- pedid[cur_addr] = REG_GET(core_sys_base,
- HDMI_CORE_I2CM_DATAI, 7, 0);
- DSSDBG("pedid[%d] = %d", cur_addr, pedid[cur_addr]);
- checksum += pedid[cur_addr++];
- hdmi_core_ddc_req_addr(ip_data, cur_addr, ext);
- }
+ do {
+ r = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
- return 0;
+ } while (r != xfers && --retries);
+ return r == xfers ? 0 : -1;
}
int ti_hdmi_5xxx_read_edid(struct hdmi_ip_data *ip_data,
u8 *edid, int len)
{
- int r, l;
+ int num_extensions, bytes_read = 0, i;
- if (len < 128)
- return -EINVAL;
+ /* get base block */
+ if (read_one_block(edid, 0))
+ goto bad;
- hdmi_core_ddc_init(ip_data);
+ num_extensions = edid[0x7e];
+ bytes_read += EDID_LENGTH;
- r = hdmi_core_ddc_edid(ip_data, edid, 0);
- if (r)
- return r;
+ for (i = 1; i <= num_extensions; i++) {
+ if (bytes_read >= len)
+ break;
- l = 128;
+ if (read_one_block(edid + EDID_LENGTH * i, i))
+ break;
+
+ bytes_read += EDID_LENGTH;
- if (len >= 128 * 2 && edid[0x7e] > 0) {
- r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
- if (r)
- return r;
- l += 128;
}
- return l;
+ return bytes_read;
+bad:
+ return 0;
}
+
void ti_hdmi_5xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
{
diff --git a/fs/aio.c b/fs/aio.c
index 71f613cf4a85a36e08044840f65b36b0c9fc4579..ed762aebb4ab47ba6a7f5a93451eaf8504d9d406 100644 (file)
--- a/fs/aio.c
+++ b/fs/aio.c
spin_unlock(&info->ring_lock);
out:
- kunmap_atomic(ring);
dprintk("leaving aio_read_evt: %d h%lu t%lu\n", ret,
(unsigned long)ring->head, (unsigned long)ring->tail);
+ kunmap_atomic(ring);
return ret;
}
diff --git a/fs/autofs4/expire.c b/fs/autofs4/expire.c
index 01443ce43ee75f072158afbc313a6e206bb2f10d..13ddec92341cdaaa63cf811ee1037a2038994191 100644 (file)
--- a/fs/autofs4/expire.c
+++ b/fs/autofs4/expire.c
/* This is an autofs submount, we can't expire it */
if (autofs_type_indirect(sbi->type))
goto done;
-
- /*
- * Otherwise it's an offset mount and we need to check
- * if we can umount its mount, if there is one.
- */
- if (!d_mountpoint(path.dentry)) {
- status = 0;
- goto done;
- }
}
/* Update the expiry counter if fs is busy */
diff --git a/fs/binfmt_elf.c b/fs/binfmt_elf.c
index 0c42cdbabecff0c4c8d9d0e597273ff4fce79507..5843a4740f6414dc43e9550135c21a18b4ce8774 100644 (file)
--- a/fs/binfmt_elf.c
+++ b/fs/binfmt_elf.c
goto whole;
if (!(vma->vm_flags & VM_SHARED) && FILTER(HUGETLB_PRIVATE))
goto whole;
+ return 0;
}
/* Do not dump I/O mapped devices or special mappings */
diff --git a/fs/btrfs/delayed-ref.c b/fs/btrfs/delayed-ref.c
index ae94117733973e2d7aa8ea590c171fcf2e6bd26a..105b265470dde40bd61ea175b8849d608a5138c2 100644 (file)
--- a/fs/btrfs/delayed-ref.c
+++ b/fs/btrfs/delayed-ref.c
* compare two delayed tree backrefs with same bytenr and type
*/
static int comp_tree_refs(struct btrfs_delayed_tree_ref *ref2,
- struct btrfs_delayed_tree_ref *ref1)
+ struct btrfs_delayed_tree_ref *ref1, int type)
{
- if (ref1->root < ref2->root)
- return -1;
- if (ref1->root > ref2->root)
- return 1;
- if (ref1->parent < ref2->parent)
- return -1;
- if (ref1->parent > ref2->parent)
- return 1;
+ if (type == BTRFS_TREE_BLOCK_REF_KEY) {
+ if (ref1->root < ref2->root)
+ return -1;
+ if (ref1->root > ref2->root)
+ return 1;
+ } else {
+ if (ref1->parent < ref2->parent)
+ return -1;
+ if (ref1->parent > ref2->parent)
+ return 1;
+ }
return 0;
}
if (ref1->type == BTRFS_TREE_BLOCK_REF_KEY ||
ref1->type == BTRFS_SHARED_BLOCK_REF_KEY) {
return comp_tree_refs(btrfs_delayed_node_to_tree_ref(ref2),
- btrfs_delayed_node_to_tree_ref(ref1));
+ btrfs_delayed_node_to_tree_ref(ref1),
+ ref1->type);
} else if (ref1->type == BTRFS_EXTENT_DATA_REF_KEY ||
ref1->type == BTRFS_SHARED_DATA_REF_KEY) {
return comp_data_refs(btrfs_delayed_node_to_data_ref(ref2),
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 7c4e6ccdba3f7d5a254ec17bcd8e524cba77c36b..4b5398c9f62bd6d3b05a1843bc030e7248472736 100644 (file)
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
* block must be cow'd
*/
static noinline int can_nocow_odirect(struct btrfs_trans_handle *trans,
- struct inode *inode, u64 offset, u64 len)
+ struct inode *inode, u64 offset, u64 *len,
+ u64 *orig_start, u64 *orig_block_len,
+ u64 *ram_bytes)
{
struct btrfs_path *path;
int ret;
disk_bytenr = btrfs_file_extent_disk_bytenr(leaf, fi);
backref_offset = btrfs_file_extent_offset(leaf, fi);
+ *orig_start = key.offset - backref_offset;
+ *orig_block_len = btrfs_file_extent_disk_num_bytes(leaf, fi);
+ *ram_bytes = btrfs_file_extent_ram_bytes(leaf, fi);
+
extent_end = key.offset + btrfs_file_extent_num_bytes(leaf, fi);
- if (extent_end < offset + len) {
+ if (extent_end < offset + *len) {
/* extent doesn't include our full range, must cow */
goto out;
}
*/
disk_bytenr += backref_offset;
disk_bytenr += offset - key.offset;
- num_bytes = min(offset + len, extent_end) - offset;
+ num_bytes = min(offset + *len, extent_end) - offset;
if (csum_exist_in_range(root, disk_bytenr, num_bytes))
goto out;
/*
* all of the above have passed, it is safe to overwrite this extent
* without cow
*/
+ *len = num_bytes;
ret = 1;
out:
btrfs_free_path(path);
em->block_start != EXTENT_MAP_HOLE)) {
int type;
int ret;
- u64 block_start;
+ u64 block_start, orig_start, orig_block_len, ram_bytes;
if (test_bit(EXTENT_FLAG_PREALLOC, &em->flags))
type = BTRFS_ORDERED_PREALLOC;
if (IS_ERR(trans))
goto must_cow;
- if (can_nocow_odirect(trans, inode, start, len) == 1) {
- u64 orig_start = em->orig_start;
- u64 orig_block_len = em->orig_block_len;
-
+ if (can_nocow_odirect(trans, inode, start, &len, &orig_start,
+ &orig_block_len, &ram_bytes) == 1) {
if (type == BTRFS_ORDERED_PREALLOC) {
free_extent_map(em);
em = create_pinned_em(inode, start, len,
diff --git a/fs/btrfs/tree-log.c b/fs/btrfs/tree-log.c
index 744a69b2eb0f45d9b79bb1126ee60a240782479d..8a00e2f00dc6f826e593c387b5ad1184dd748aab 100644 (file)
--- a/fs/btrfs/tree-log.c
+++ b/fs/btrfs/tree-log.c
unsigned long src_ptr;
unsigned long dst_ptr;
int overwrite_root = 0;
+ bool inode_item = key->type == BTRFS_INODE_ITEM_KEY;
if (root->root_key.objectid != BTRFS_TREE_LOG_OBJECTID)
overwrite_root = 1;
/* look for the key in the destination tree */
ret = btrfs_search_slot(NULL, root, key, path, 0, 0);
+ if (ret < 0)
+ return ret;
+
if (ret == 0) {
char *src_copy;
char *dst_copy;
return 0;
}
+ /*
+ * We need to load the old nbytes into the inode so when we
+ * replay the extents we've logged we get the right nbytes.
+ */
+ if (inode_item) {
+ struct btrfs_inode_item *item;
+ u64 nbytes;
+
+ item = btrfs_item_ptr(path->nodes[0], path->slots[0],
+ struct btrfs_inode_item);
+ nbytes = btrfs_inode_nbytes(path->nodes[0], item);
+ item = btrfs_item_ptr(eb, slot,
+ struct btrfs_inode_item);
+ btrfs_set_inode_nbytes(eb, item, nbytes);
+ }
+ } else if (inode_item) {
+ struct btrfs_inode_item *item;
+
+ /*
+ * New inode, set nbytes to 0 so that the nbytes comes out
+ * properly when we replay the extents.
+ */
+ item = btrfs_item_ptr(eb, slot, struct btrfs_inode_item);
+ btrfs_set_inode_nbytes(eb, item, 0);
}
insert:
btrfs_release_path(path);
u64 mask = root->sectorsize - 1;
u64 extent_end;
u64 start = key->offset;
- u64 saved_nbytes;
+ u64 nbytes = 0;
struct btrfs_file_extent_item *item;
struct inode *inode = NULL;
unsigned long size;
found_type = btrfs_file_extent_type(eb, item);
if (found_type == BTRFS_FILE_EXTENT_REG ||
- found_type == BTRFS_FILE_EXTENT_PREALLOC)
- extent_end = start + btrfs_file_extent_num_bytes(eb, item);
- else if (found_type == BTRFS_FILE_EXTENT_INLINE) {
+ found_type == BTRFS_FILE_EXTENT_PREALLOC) {
+ nbytes = btrfs_file_extent_num_bytes(eb, item);
+ extent_end = start + nbytes;
+
+ /*
+ * We don't add to the inodes nbytes if we are prealloc or a
+ * hole.
+ */
+ if (btrfs_file_extent_disk_bytenr(eb, item) == 0)
+ nbytes = 0;
+ } else if (found_type == BTRFS_FILE_EXTENT_INLINE) {
size = btrfs_file_extent_inline_len(eb, item);
+ nbytes = btrfs_file_extent_ram_bytes(eb, item);
extent_end = (start + size + mask) & ~mask;
} else {
ret = 0;
}
btrfs_release_path(path);
- saved_nbytes = inode_get_bytes(inode);
/* drop any overlapping extents */
ret = btrfs_drop_extents(trans, root, inode, start, extent_end, 1);
BUG_ON(ret);
BUG_ON(ret);
}
- inode_set_bytes(inode, saved_nbytes);
+ inode_add_bytes(inode, nbytes);
ret = btrfs_update_inode(trans, root, inode);
out:
if (inode)
diff --git a/fs/dcache.c b/fs/dcache.c
index c3bbf85475372ec5ea69f51e1852074751c7c162..de73da20f335b979af48a7fda232643a111f4f6b 100644 (file)
--- a/fs/dcache.c
+++ b/fs/dcache.c
LIST_HEAD(dispose);
int found;
- while ((found = select_parent(parent, &dispose)) != 0)
+ while ((found = select_parent(parent, &dispose)) != 0) {
shrink_dentry_list(&dispose);
+ cond_resched();
+ }
}
EXPORT_SYMBOL(shrink_dcache_parent);
diff --git a/fs/exec.c b/fs/exec.c
index 547eaaaeb89c58456303ee11a1eb8c25cb52dcb6..ac014f1009aaf90475f4deaa116aa46073db61b3 100644 (file)
--- a/fs/exec.c
+++ b/fs/exec.c
sig->notify_count = -1; /* for exit_notify() */
for (;;) {
+ threadgroup_change_begin(tsk);
write_lock_irq(&tasklist_lock);
if (likely(leader->exit_state))
break;
__set_current_state(TASK_KILLABLE);
write_unlock_irq(&tasklist_lock);
+ threadgroup_change_end(tsk);
schedule();
if (unlikely(__fatal_signal_pending(tsk)))
goto killed;
if (unlikely(leader->ptrace))
__wake_up_parent(leader, leader->parent);
write_unlock_irq(&tasklist_lock);
+ threadgroup_change_end(tsk);
release_task(leader);
}
diff --git a/fs/ext4/Kconfig b/fs/ext4/Kconfig
index 987358740cb970dab82917f952f8cc8bfae4361c..efea5d5c44ce4e0cf0910db50020dca4008779c0 100644 (file)
--- a/fs/ext4/Kconfig
+++ b/fs/ext4/Kconfig
Enables run-time debugging support for the ext4 filesystem.
If you select Y here, then you will be able to turn on debugging
- with a command such as "echo 1 > /sys/kernel/debug/ext4/mballoc-debug"
+ with a command such as:
+ echo 1 > /sys/module/ext4/parameters/mballoc_debug
diff --git a/fs/ext4/ext4_jbd2.h b/fs/ext4/ext4_jbd2.h
index 7177f9b21cb2b58cbfece8c8b636281dc5acff6d..dbd9ae199e189182c2f0540c226a35c097534329 100644 (file)
--- a/fs/ext4/ext4_jbd2.h
+++ b/fs/ext4/ext4_jbd2.h
* ext4_journal_callback_del: delete a registered callback
* @handle: active journal transaction handle on which callback was registered
* @jce: registered journal callback entry to unregister
+ * Return true if object was sucessfully removed
*/
-static inline void ext4_journal_callback_del(handle_t *handle,
+static inline bool ext4_journal_callback_try_del(handle_t *handle,
struct ext4_journal_cb_entry *jce)
{
+ bool deleted;
struct ext4_sb_info *sbi =
EXT4_SB(handle->h_transaction->t_journal->j_private);
spin_lock(&sbi->s_md_lock);
+ deleted = !list_empty(&jce->jce_list);
list_del_init(&jce->jce_list);
spin_unlock(&sbi->s_md_lock);
+ return deleted;
}
int
diff --git a/fs/ext4/fsync.c b/fs/ext4/fsync.c
index 3278e64e57b61ac51a41db3ceebeecd21003985a..e0ba8a408def07583b9cd04a57259e3c56183057 100644 (file)
--- a/fs/ext4/fsync.c
+++ b/fs/ext4/fsync.c
if (journal->j_flags & JBD2_BARRIER &&
!jbd2_trans_will_send_data_barrier(journal, commit_tid))
needs_barrier = true;
- jbd2_log_start_commit(journal, commit_tid);
- ret = jbd2_log_wait_commit(journal, commit_tid);
+ ret = jbd2_complete_transaction(journal, commit_tid);
if (needs_barrier) {
err = blkdev_issue_flush(inode->i_sb->s_bdev, GFP_KERNEL, NULL);
if (!ret)
diff --git a/fs/ext4/inode.c b/fs/ext4/inode.c
index 22c5c67ab4d1d49422eda0351038128c65568500..c0fbd963ca4c21cbdc887e9232f1766f2341d141 100644 (file)
--- a/fs/ext4/inode.c
+++ b/fs/ext4/inode.c
__u16 csum_hi = 0;
__u32 csum;
- csum_lo = raw->i_checksum_lo;
+ csum_lo = le16_to_cpu(raw->i_checksum_lo);
raw->i_checksum_lo = 0;
if (EXT4_INODE_SIZE(inode->i_sb) > EXT4_GOOD_OLD_INODE_SIZE &&
EXT4_FITS_IN_INODE(raw, ei, i_checksum_hi)) {
- csum_hi = raw->i_checksum_hi;
+ csum_hi = le16_to_cpu(raw->i_checksum_hi);
raw->i_checksum_hi = 0;
}
csum = ext4_chksum(sbi, ei->i_csum_seed, (__u8 *)raw,
EXT4_INODE_SIZE(inode->i_sb));
- raw->i_checksum_lo = csum_lo;
+ raw->i_checksum_lo = cpu_to_le16(csum_lo);
if (EXT4_INODE_SIZE(inode->i_sb) > EXT4_GOOD_OLD_INODE_SIZE &&
EXT4_FITS_IN_INODE(raw, ei, i_checksum_hi))
- raw->i_checksum_hi = csum_hi;
+ raw->i_checksum_hi = cpu_to_le16(csum_hi);
return csum;
}
journal_t *journal = EXT4_SB(inode->i_sb)->s_journal;
tid_t commit_tid = EXT4_I(inode)->i_datasync_tid;
- jbd2_log_start_commit(journal, commit_tid);
- jbd2_log_wait_commit(journal, commit_tid);
+ jbd2_complete_transaction(journal, commit_tid);
filemap_write_and_wait(&inode->i_data);
}
truncate_inode_pages(&inode->i_data, 0);
diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c
index 82f8c2d92e1748cc5951bdc4f8bf3e5880cfe00c..b443e62b65c244cba8e06436164841d0e8e527ae 100644 (file)
--- a/fs/ext4/mballoc.c
+++ b/fs/ext4/mballoc.c
node = rb_prev(new_node);
if (node) {
entry = rb_entry(node, struct ext4_free_data, efd_node);
- if (can_merge(entry, new_entry)) {
+ if (can_merge(entry, new_entry) &&
+ ext4_journal_callback_try_del(handle, &entry->efd_jce)) {
new_entry->efd_start_cluster = entry->efd_start_cluster;
new_entry->efd_count += entry->efd_count;
rb_erase(node, &(db->bb_free_root));
- ext4_journal_callback_del(handle, &entry->efd_jce);
kmem_cache_free(ext4_free_data_cachep, entry);
}
}
node = rb_next(new_node);
if (node) {
entry = rb_entry(node, struct ext4_free_data, efd_node);
- if (can_merge(new_entry, entry)) {
+ if (can_merge(new_entry, entry) &&
+ ext4_journal_callback_try_del(handle, &entry->efd_jce)) {
new_entry->efd_count += entry->efd_count;
rb_erase(node, &(db->bb_free_root));
- ext4_journal_callback_del(handle, &entry->efd_jce);
kmem_cache_free(ext4_free_data_cachep, entry);
}
}
diff --git a/fs/ext4/mmp.c b/fs/ext4/mmp.c
index 44734f1ca55466e28d1d4129cb094b17dae55897..fe201c608a75ad6b721ce828978f0e6ecbc8e744 100644 (file)
--- a/fs/ext4/mmp.c
+++ b/fs/ext4/mmp.c
#include "ext4.h"
/* Checksumming functions */
-static __u32 ext4_mmp_csum(struct super_block *sb, struct mmp_struct *mmp)
+static __le32 ext4_mmp_csum(struct super_block *sb, struct mmp_struct *mmp)
{
struct ext4_sb_info *sbi = EXT4_SB(sb);
int offset = offsetof(struct mmp_struct, mmp_checksum);
diff --git a/fs/ext4/resize.c b/fs/ext4/resize.c
index 9eace360466dcba11a341d2f8d448ba16c7dc979..0cfa2f45abc151afdfc55300d2685cd11341bf20 100644 (file)
--- a/fs/ext4/resize.c
+++ b/fs/ext4/resize.c
/* Update the global fs size fields */
sbi->s_groups_count += flex_gd->count;
+ sbi->s_blockfile_groups = min_t(ext4_group_t, sbi->s_groups_count,
+ (EXT4_MAX_BLOCK_FILE_PHYS / EXT4_BLOCKS_PER_GROUP(sb)));
/* Update the reserved block counts only once the new group is
* active. */
return 0;
ext4_get_group_no_and_offset(sb, n_blocks_count - 1, &n_group, &offset);
+ if (n_group > (0xFFFFFFFFUL / EXT4_INODES_PER_GROUP(sb))) {
+ ext4_warning(sb, "resize would cause inodes_count overflow");
+ return -EINVAL;
+ }
ext4_get_group_no_and_offset(sb, o_blocks_count - 1, &o_group, &offset);
n_desc_blocks = num_desc_blocks(sb, n_group + 1);
diff --git a/fs/ext4/super.c b/fs/ext4/super.c
index 24c767d0b0f402a9e6698ff001defacf1d2acfca..5575a451508ce620f92f4f7f1b2b49fb51a1bf41 100644 (file)
--- a/fs/ext4/super.c
+++ b/fs/ext4/super.c
@@ -452,10 +452,13 @@ static void ext4_journal_commit_callback(journal_t *journal, transaction_t *txn)
struct super_block *sb = journal->j_private;
struct ext4_sb_info *sbi = EXT4_SB(sb);
int error = is_journal_aborted(journal);
- struct ext4_journal_cb_entry *jce, *tmp;
+ struct ext4_journal_cb_entry *jce;
+ BUG_ON(txn->t_state == T_FINISHED);
spin_lock(&sbi->s_md_lock);
- list_for_each_entry_safe(jce, tmp, &txn->t_private_list, jce_list) {
+ while (!list_empty(&txn->t_private_list)) {
+ jce = list_entry(txn->t_private_list.next,
+ struct ext4_journal_cb_entry, jce_list);
list_del_init(&jce->jce_list);
spin_unlock(&sbi->s_md_lock);
jce->jce_func(sb, jce, error);
diff --git a/fs/fscache/stats.c b/fs/fscache/stats.c
index 8179e8bc4a3d668bc48c2625bde6a0448e54fc2e..40d13c70ef518e492565ae59a86ee758244cdd65 100644 (file)
--- a/fs/fscache/stats.c
+++ b/fs/fscache/stats.c
.open = fscache_stats_open,
.read = seq_read,
.llseek = seq_lseek,
- .release = seq_release,
+ .release = single_release,
};
diff --git a/fs/hfsplus/extents.c b/fs/hfsplus/extents.c
index eba76eab6d625f68aadcba26f04c001040b244c2..fc8ddc1ecd555b4b0721f98bf7cde06a95b339c4 100644 (file)
--- a/fs/hfsplus/extents.c
+++ b/fs/hfsplus/extents.c
struct address_space *mapping = inode->i_mapping;
struct page *page;
void *fsdata;
- u32 size = inode->i_size;
+ loff_t size = inode->i_size;
res = pagecache_write_begin(NULL, mapping, size, 0,
AOP_FLAG_UNINTERRUPTIBLE,
diff --git a/fs/hugetlbfs/inode.c b/fs/hugetlbfs/inode.c
index 78bde32ea9518d3fffe72d24864b6959bb369781..d0de769bcf20fd44e191c757d5989b47e3d231f5 100644 (file)
--- a/fs/hugetlbfs/inode.c
+++ b/fs/hugetlbfs/inode.c
* way when do_mmap_pgoff unwinds (may be important on powerpc
* and ia64).
*/
- vma->vm_flags |= VM_HUGETLB | VM_DONTEXPAND | VM_DONTDUMP;
+ vma->vm_flags |= VM_HUGETLB | VM_DONTEXPAND;
vma->vm_ops = &hugetlb_vm_ops;
if (vma->vm_pgoff & (~huge_page_mask(h) >> PAGE_SHIFT))
static int get_hstate_idx(int page_size_log)
{
- struct hstate *h;
+ struct hstate *h = hstate_sizelog(page_size_log);
- if (!page_size_log)
- return default_hstate_idx;
- h = size_to_hstate(1 << page_size_log);
if (!h)
return -1;
return h - hstates;
}
-struct file *hugetlb_file_setup(const char *name, unsigned long addr,
- size_t size, vm_flags_t acctflag,
- struct user_struct **user,
+/*
+ * Note that size should be aligned to proper hugepage size in caller side,
+ * otherwise hugetlb_reserve_pages reserves one less hugepages than intended.
+ */
+struct file *hugetlb_file_setup(const char *name, size_t size,
+ vm_flags_t acctflag, struct user_struct **user,
int creat_flags, int page_size_log)
{
int error = -ENOMEM;
struct path path;
struct dentry *root;
struct qstr quick_string;
- struct hstate *hstate;
- unsigned long num_pages;
int hstate_idx;
hstate_idx = get_hstate_idx(page_size_log);
if (!inode)
goto out_dentry;
- hstate = hstate_inode(inode);
- size += addr & ~huge_page_mask(hstate);
- num_pages = ALIGN(size, huge_page_size(hstate)) >>
- huge_page_shift(hstate);
error = -ENOMEM;
- if (hugetlb_reserve_pages(inode, 0, num_pages, NULL, acctflag))
+ if (hugetlb_reserve_pages(inode, 0,
+ size >> huge_page_shift(hstate_inode(inode)), NULL,
+ acctflag))
goto out_inode;
d_instantiate(path.dentry, inode);
diff --git a/fs/jbd2/commit.c b/fs/jbd2/commit.c
index 3091d42992f0d934eb4355022efaa5c83ad1be0d..069bf58428c08dadb3c610c6001e6504d7deb31b 100644 (file)
--- a/fs/jbd2/commit.c
+++ b/fs/jbd2/commit.c
int space_left = 0;
int first_tag = 0;
int tag_flag;
- int i, to_free = 0;
+ int i;
int tag_bytes = journal_tag_bytes(journal);
struct buffer_head *cbh = NULL; /* For transactional checksums */
__u32 crc32_sum = ~0;
journal->j_stats.run.rs_blocks_logged += stats.run.rs_blocks_logged;
spin_unlock(&journal->j_history_lock);
- commit_transaction->t_state = T_FINISHED;
+ commit_transaction->t_state = T_COMMIT_CALLBACK;
J_ASSERT(commit_transaction == journal->j_committing_transaction);
journal->j_commit_sequence = commit_transaction->t_tid;
journal->j_committing_transaction = NULL;
journal->j_average_commit_time*3) / 4;
else
journal->j_average_commit_time = commit_time;
+
write_unlock(&journal->j_state_lock);
- if (commit_transaction->t_checkpoint_list == NULL &&
- commit_transaction->t_checkpoint_io_list == NULL) {
- __jbd2_journal_drop_transaction(journal, commit_transaction);
- to_free = 1;
+ if (journal->j_checkpoint_transactions == NULL) {
+ journal->j_checkpoint_transactions = commit_transaction;
+ commit_transaction->t_cpnext = commit_transaction;
+ commit_transaction->t_cpprev = commit_transaction;
} else {
- if (journal->j_checkpoint_transactions == NULL) {
- journal->j_checkpoint_transactions = commit_transaction;
- commit_transaction->t_cpnext = commit_transaction;
- commit_transaction->t_cpprev = commit_transaction;
- } else {
- commit_transaction->t_cpnext =
- journal->j_checkpoint_transactions;
- commit_transaction->t_cpprev =
- commit_transaction->t_cpnext->t_cpprev;
- commit_transaction->t_cpnext->t_cpprev =
- commit_transaction;
- commit_transaction->t_cpprev->t_cpnext =
+ commit_transaction->t_cpnext =
+ journal->j_checkpoint_transactions;
+ commit_transaction->t_cpprev =
+ commit_transaction->t_cpnext->t_cpprev;
+ commit_transaction->t_cpnext->t_cpprev =
+ commit_transaction;
+ commit_transaction->t_cpprev->t_cpnext =
commit_transaction;
- }
}
spin_unlock(&journal->j_list_lock);
-
+ /* Drop all spin_locks because commit_callback may be block.
+ * __journal_remove_checkpoint() can not destroy transaction
+ * under us because it is not marked as T_FINISHED yet */
if (journal->j_commit_callback)
journal->j_commit_callback(journal, commit_transaction);
trace_jbd2_end_commit(journal, commit_transaction);
jbd_debug(1, "JBD2: commit %d complete, head %d\n",
journal->j_commit_sequence, journal->j_tail_sequence);
- if (to_free)
- jbd2_journal_free_transaction(commit_transaction);
+ write_lock(&journal->j_state_lock);
+ spin_lock(&journal->j_list_lock);
+ commit_transaction->t_state = T_FINISHED;
+ /* Recheck checkpoint lists after j_list_lock was dropped */
+ if (commit_transaction->t_checkpoint_list == NULL &&
+ commit_transaction->t_checkpoint_io_list == NULL) {
+ __jbd2_journal_drop_transaction(journal, commit_transaction);
+ jbd2_journal_free_transaction(commit_transaction);
+ }
+ spin_unlock(&journal->j_list_lock);
+ write_unlock(&journal->j_state_lock);
wake_up(&journal->j_wait_done_commit);
}
diff --git a/fs/jbd2/journal.c b/fs/jbd2/journal.c
index dbf41f9452db602efdebb778f86cf544b28d0399..42f8cf6cd5da8ebc216ff8636d3ee389a0a94db0 100644 (file)
--- a/fs/jbd2/journal.c
+++ b/fs/jbd2/journal.c
return err;
}
+/*
+ * When this function returns the transaction corresponding to tid
+ * will be completed. If the transaction has currently running, start
+ * committing that transaction before waiting for it to complete. If
+ * the transaction id is stale, it is by definition already completed,
+ * so just return SUCCESS.
+ */
+int jbd2_complete_transaction(journal_t *journal, tid_t tid)
+{
+ int need_to_wait = 1;
+
+ read_lock(&journal->j_state_lock);
+ if (journal->j_running_transaction &&
+ journal->j_running_transaction->t_tid == tid) {
+ if (journal->j_commit_request != tid) {
+ /* transaction not yet started, so request it */
+ read_unlock(&journal->j_state_lock);
+ jbd2_log_start_commit(journal, tid);
+ goto wait_commit;
+ }
+ } else if (!(journal->j_committing_transaction &&
+ journal->j_committing_transaction->t_tid == tid))
+ need_to_wait = 0;
+ read_unlock(&journal->j_state_lock);
+ if (!need_to_wait)
+ return 0;
+wait_commit:
+ return jbd2_log_wait_commit(journal, tid);
+}
+EXPORT_SYMBOL(jbd2_complete_transaction);
+
/*
* Log buffer allocation routines:
*/
diff --git a/fs/lockd/clntlock.c b/fs/lockd/clntlock.c
index ca0a08001449a999e7070253ba51f7607291285e..193f04cc97ba9c8374fcca8fb6adcd4fb12fa3c0 100644 (file)
--- a/fs/lockd/clntlock.c
+++ b/fs/lockd/clntlock.c
timeout);
if (ret < 0)
return -ERESTARTSYS;
+ /* Reset the lock status after a server reboot so we resend */
+ if (block->b_status == nlm_lck_denied_grace_period)
+ block->b_status = nlm_lck_blocked;
req->a_res.status = block->b_status;
return 0;
}
diff --git a/fs/lockd/clntproc.c b/fs/lockd/clntproc.c
index 52e5120bb159f14cd286f91ed2f72848f8aeb5d9..54f9e6ce0430ae88d742709bc47499c0d1b71731 100644 (file)
--- a/fs/lockd/clntproc.c
+++ b/fs/lockd/clntproc.c
status = nlmclnt_block(block, req, NLMCLNT_POLL_TIMEOUT);
if (status < 0)
break;
- /* Resend the blocking lock request after a server reboot */
- if (resp->status == nlm_lck_denied_grace_period)
- continue;
if (resp->status != nlm_lck_blocked)
break;
}
diff --git a/fs/nfs/nfs4proc.c b/fs/nfs/nfs4proc.c
index 3d905e3ca4919d5a0b101228ed78c9bd9e25c19d..e3c6121bdf023f439068e021a8c6446e1801619e 100644 (file)
--- a/fs/nfs/nfs4proc.c
+++ b/fs/nfs/nfs4proc.c
@@ -1374,6 +1374,12 @@ int nfs4_open_delegation_recall(struct nfs_open_context *ctx, struct nfs4_state
case -ENOMEM:
err = 0;
goto out;
+ case -NFS4ERR_DELAY:
+ case -NFS4ERR_GRACE:
+ set_bit(NFS_DELEGATED_STATE, &state->flags);
+ ssleep(1);
+ err = -EAGAIN;
+ goto out;
}
err = nfs4_handle_exception(server, err, &exception);
} while (exception.retry);
@@ -4507,9 +4513,9 @@ static int nfs4_proc_unlck(struct nfs4_state *state, int cmd, struct file_lock *
if (status != 0)
goto out;
/* Is this a delegated lock? */
- if (test_bit(NFS_DELEGATED_STATE, &state->flags))
- goto out;
lsp = request->fl_u.nfs4_fl.owner;
+ if (test_bit(NFS_LOCK_INITIALIZED, &lsp->ls_flags) == 0)
+ goto out;
seqid = nfs_alloc_seqid(&lsp->ls_seqid, GFP_KERNEL);
status = -ENOMEM;
if (seqid == NULL)
diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c
index 9d1c5dba2bbb6625df90cebca48a364a29b9fe97..ec668e1283c7df2fc2ac10539494a43356faf579 100644 (file)
--- a/fs/nfsd/nfs4proc.c
+++ b/fs/nfsd/nfs4proc.c
nfs4_lock_state();
status = nfs4_preprocess_stateid_op(SVC_NET(rqstp),
cstate, stateid, WR_STATE, &filp);
- if (filp)
- get_file(filp);
- nfs4_unlock_state();
-
if (status) {
+ nfs4_unlock_state();
dprintk("NFSD: nfsd4_write: couldn't process stateid!\n");
return status;
}
+ if (filp)
+ get_file(filp);
+ nfs4_unlock_state();
cnt = write->wr_buflen;
write->wr_how_written = write->wr_stable_how;
diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c
index a8309c688f0764b51e73eae7c729eec1f0714a3f..53a7c643f2271f7dab9be9a54aedc0e1a27b951f 100644 (file)
--- a/fs/nfsd/nfs4state.c
+++ b/fs/nfsd/nfs4state.c
{
if (atomic_dec_and_test(&fp->fi_access[oflag])) {
nfs4_file_put_fd(fp, oflag);
- /*
- * It's also safe to get rid of the RDWR open *if*
- * we no longer have need of the other kind of access
- * or if we already have the other kind of open:
- */
- if (fp->fi_fds[1-oflag]
- || atomic_read(&fp->fi_access[1 - oflag]) == 0)
+ if (atomic_read(&fp->fi_access[1 - oflag]) == 0)
nfs4_file_put_fd(fp, O_RDWR);
}
}
diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c
index d1dd7100a556173743a423038c532dffa7811bb3..cd5e6c155bcf8dce55914268d3a11eb77d203161 100644 (file)
--- a/fs/nfsd/nfs4xdr.c
+++ b/fs/nfsd/nfs4xdr.c
all 32 bits of 'nseconds'. */
READ_BUF(12);
len += 12;
- READ32(dummy32);
- if (dummy32)
- return nfserr_inval;
- READ32(iattr->ia_atime.tv_sec);
+ READ64(iattr->ia_atime.tv_sec);
READ32(iattr->ia_atime.tv_nsec);
if (iattr->ia_atime.tv_nsec >= (u32)1000000000)
return nfserr_inval;
all 32 bits of 'nseconds'. */
READ_BUF(12);
len += 12;
- READ32(dummy32);
- if (dummy32)
- return nfserr_inval;
- READ32(iattr->ia_mtime.tv_sec);
+ READ64(iattr->ia_mtime.tv_sec);
READ32(iattr->ia_mtime.tv_nsec);
if (iattr->ia_mtime.tv_nsec >= (u32)1000000000)
return nfserr_inval;
if (bmval1 & FATTR4_WORD1_TIME_ACCESS) {
if ((buflen -= 12) < 0)
goto out_resource;
- WRITE32(0);
- WRITE32(stat.atime.tv_sec);
+ WRITE64((s64)stat.atime.tv_sec);
WRITE32(stat.atime.tv_nsec);
}
if (bmval1 & FATTR4_WORD1_TIME_DELTA) {
if (bmval1 & FATTR4_WORD1_TIME_METADATA) {
if ((buflen -= 12) < 0)
goto out_resource;
- WRITE32(0);
- WRITE32(stat.ctime.tv_sec);
+ WRITE64((s64)stat.ctime.tv_sec);
WRITE32(stat.ctime.tv_nsec);
}
if (bmval1 & FATTR4_WORD1_TIME_MODIFY) {
if ((buflen -= 12) < 0)
goto out_resource;
- WRITE32(0);
- WRITE32(stat.mtime.tv_sec);
+ WRITE64((s64)stat.mtime.tv_sec);
WRITE32(stat.mtime.tv_nsec);
}
if (bmval1 & FATTR4_WORD1_MOUNTED_ON_FILEID) {
index 07f7a92fe88e5cc69be0d8db0ce498a2d81aaf31..595343ee24c647fd23ec8afc7241f4361d6b9f5e 100644 (file)
int add = (arg & IN_MASK_ADD);
int ret;
- /* don't allow invalid bits: we don't want flags set */
mask = inotify_arg_to_mask(arg);
fsn_mark = fsnotify_find_inode_mark(group, inode);
struct idr *idr = &group->inotify_data.idr;
spinlock_t *idr_lock = &group->inotify_data.idr_lock;
- /* don't allow invalid bits: we don't want flags set */
mask = inotify_arg_to_mask(arg);
tmp_i_mark = kmem_cache_alloc(inotify_inode_mark_cachep, GFP_KERNEL);
int ret;
unsigned flags = 0;
+ /* don't allow invalid bits: we don't want flags set */
+ if (unlikely(!(mask & ALL_INOTIFY_BITS)))
+ return -EINVAL;
+
f = fdget(fd);
if (unlikely(!f.file))
return -EBADF;
diff --git a/fs/proc/array.c b/fs/proc/array.c
index 6a91e6ffbcbded857c4513cee0182ec61f899b74..be3c22f5729a8385938965cee9aa317840a90030 100644 (file)
--- a/fs/proc/array.c
+++ b/fs/proc/array.c
"x (dead)", /* 64 */
"K (wakekill)", /* 128 */
"W (waking)", /* 256 */
+ "P (parked)", /* 512 */
};
static inline const char *get_task_state(struct task_struct *tsk)
diff --git a/fs/sysfs/dir.c b/fs/sysfs/dir.c
index 1f8c823f7d8b48d8cf3ee150f8e870af864ac205..d924812dd16c948020725d6b62981643a54303f7 100644 (file)
--- a/fs/sysfs/dir.c
+++ b/fs/sysfs/dir.c
@@ -1012,6 +1012,7 @@ static int sysfs_readdir(struct file * filp, void * dirent, filldir_t filldir)
enum kobj_ns_type type;
const void *ns;
ino_t ino;
+ loff_t off;
type = sysfs_ns_type(parent_sd);
ns = sysfs_info(dentry->d_sb)->ns[type];
@@ -1034,6 +1035,7 @@ static int sysfs_readdir(struct file * filp, void * dirent, filldir_t filldir)
return 0;
}
mutex_lock(&sysfs_mutex);
+ off = filp->f_pos;
for (pos = sysfs_dir_pos(ns, parent_sd, filp->f_pos, pos);
pos;
pos = sysfs_dir_next_pos(ns, parent_sd, filp->f_pos, pos)) {
@@ -1045,19 +1047,24 @@ static int sysfs_readdir(struct file * filp, void * dirent, filldir_t filldir)
len = strlen(name);
ino = pos->s_ino;
type = dt_type(pos);
- filp->f_pos = pos->s_hash;
+ off = filp->f_pos = pos->s_hash;
filp->private_data = sysfs_get(pos);
mutex_unlock(&sysfs_mutex);
- ret = filldir(dirent, name, len, filp->f_pos, ino, type);
+ ret = filldir(dirent, name, len, off, ino, type);
mutex_lock(&sysfs_mutex);
if (ret < 0)
break;
}
mutex_unlock(&sysfs_mutex);
- if ((filp->f_pos > 1) && !pos) { /* EOF */
- filp->f_pos = INT_MAX;
+
+ /* don't reference last entry if its refcount is dropped */
+ if (!pos) {
filp->private_data = NULL;
+
+ /* EOF and not changed as 0 or 1 in read/write path */
+ if (off == filp->f_pos && off > 1)
+ filp->f_pos = INT_MAX;
}
return 0;
}
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index fad21c927a3884e7b7c230f8cea24263f2ed73a9..881fb15d00c1263692b51d6b25bbba014346a0a7 100644 (file)
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -1559,9 +1559,8 @@ extern void drm_prime_gem_destroy(struct drm_gem_object *obj, struct sg_table *s
void drm_prime_init_file_private(struct drm_prime_file_private *prime_fpriv);
void drm_prime_destroy_file_private(struct drm_prime_file_private *prime_fpriv);
-int drm_prime_add_imported_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf, uint32_t handle);
-int drm_prime_lookup_imported_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf, uint32_t *handle);
-void drm_prime_remove_imported_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf);
+int drm_prime_lookup_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf, uint32_t *handle);
+void drm_prime_remove_buf_handle(struct drm_prime_file_private *prime_fpriv, struct dma_buf *dma_buf);
int drm_prime_add_dma_buf(struct drm_device *dev, struct drm_gem_object *obj);
int drm_prime_lookup_obj(struct drm_device *dev, struct dma_buf *buf,
index 1cdbfe9b462559d5c703b912b907b97dbfada566..d7da55c10195d1eee9d99447a9c05d109b387f6d 100644 (file)
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
{0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|RADEON_NEW_MEMMAP}, \
{0x1002, 0x9999, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x999A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x999B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x999C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ {0x1002, 0x999D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x99A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x99A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
{0x1002, 0x99A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARUBA|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 96c4d118062f5128dfbb2dfb4c30277faac400b0..bf39ae25fa5001f267fab114be663fefa47350af 100644 (file)
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
unsigned int cmd_flags)
{
if (unlikely(cmd_flags & REQ_DISCARD))
- return q->limits.max_discard_sectors;
+ return min(q->limits.max_discard_sectors, UINT_MAX >> 9);
if (unlikely(cmd_flags & REQ_WRITE_SAME))
return q->limits.max_write_same_sectors;
index 98503b7923698e3b527dc278aa32d5db1da1dfe1..d9a4f7f40f329b22c81f86e31c72b259d4acb4bf 100644 (file)
#define _KERNEL_CAP_T_SIZE (sizeof(kernel_cap_t))
+struct file;
struct inode;
struct dentry;
struct user_namespace;
extern bool ns_capable(struct user_namespace *ns, int cap);
extern bool nsown_capable(int cap);
extern bool inode_capable(const struct inode *inode, int cap);
+extern bool file_ns_capable(const struct file *file, struct user_namespace *ns, int cap);
/* audit system wants to get cap info from files as well */
extern int get_vfs_caps_from_disk(const struct dentry *dentry, struct cpu_vfs_cap_data *cpu_caps);
diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h
index a96c512803f7e6ea83f3d88d5565f6a4ef6f1732..40ca0101bdccd52b7a0087450b68593cfa6a477a 100644 (file)
--- a/include/linux/cgroup.h
+++ b/include/linux/cgroup.h
/* CFTYPE_* flags */
unsigned int flags;
- /* file xattrs */
- struct simple_xattrs xattrs;
-
int (*open)(struct inode *inode, struct file *file);
ssize_t (*read)(struct cgroup *cgrp, struct cftype *cft,
struct file *file,
index 0c80d3f57a5b7e3e2275f3754bbc91d026e6713a..db695d5035a33d6c57f0b8b9c0b7020541d6a2db 100644 (file)
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
extern const struct file_operations hugetlbfs_file_operations;
extern const struct vm_operations_struct hugetlb_vm_ops;
-struct file *hugetlb_file_setup(const char *name, unsigned long addr,
- size_t size, vm_flags_t acct,
+struct file *hugetlb_file_setup(const char *name, size_t size, vm_flags_t acct,
struct user_struct **user, int creat_flags,
int page_size_log);
#define is_file_hugepages(file) 0
static inline struct file *
-hugetlb_file_setup(const char *name, unsigned long addr, size_t size,
- vm_flags_t acctflag, struct user_struct **user, int creat_flags,
+hugetlb_file_setup(const char *name, size_t size, vm_flags_t acctflag,
+ struct user_struct **user, int creat_flags,
int page_size_log)
{
return ERR_PTR(-ENOSYS);
return hstate_inode(f->f_dentry->d_inode);
}
+static inline struct hstate *hstate_sizelog(int page_size_log)
+{
+ if (!page_size_log)
+ return &default_hstate;
+ return size_to_hstate(1 << page_size_log);
+}
+
static inline struct hstate *hstate_vma(struct vm_area_struct *vma)
{
return hstate_file(vma->vm_file);
return h - hstates;
}
-#else
+#else /* CONFIG_HUGETLB_PAGE */
struct hstate {};
#define alloc_huge_page_node(h, nid) NULL
#define alloc_bootmem_huge_page(h) NULL
#define hstate_file(f) NULL
+#define hstate_sizelog(s) NULL
#define hstate_vma(v) NULL
#define hstate_inode(i) NULL
#define huge_page_size(h) PAGE_SIZE
}
#define hstate_index_to_shift(index) 0
#define hstate_index(h) 0
-#endif
+#endif /* CONFIG_HUGETLB_PAGE */
#endif /* _LINUX_HUGETLB_H */
index 49269a2aa329ee84f99e3807cc0b782a53c9f85f..6a66b4d1ac2c34cfaeaea4d0b53f1275f7651b39 100644 (file)
* A step configured to read a single
* co-ordinate value, can be applied
* more number of times for better results.
+ * @wire_config: Different EVM's could have a different order
+ * for connecting wires on touchscreen.
+ * We need to provide an 8 bit number where in
+ * the 1st four bits represent the analog lines
+ * and the next 4 bits represent positive/
+ * negative terminal on that input line.
+ * Notations to represent the input lines and
+ * terminals resoectively is as follows:
+ * AIN0 = 0, AIN1 = 1 and so on till AIN7 = 7.
+ * XP = 0, XN = 1, YP = 2, YN = 3.
+ *
*/
struct tsc_data {
int wires;
int x_plate_resistance;
int steps_to_configure;
+ int wire_config[10];
};
#endif
index ae221a7b509237a649e8ccfed988265e22f07fa5..c4d870b0d5e6e26580bfd717d64489fce8d59aa6 100644 (file)
size_t shm_ctlmax;
size_t shm_ctlall;
+ unsigned long shm_tot;
int shm_ctlmni;
- int shm_tot;
/*
* Defines whether IPC_RMID is forced for _all_ shm segments regardless
* of shmctl()
diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h
index e30b66346942a90a4c79cdc5a0362b3899db0521..383bef083281d4793a337bd50994d9c1bd114c2d 100644 (file)
--- a/include/linux/jbd2.h
+++ b/include/linux/jbd2.h
T_COMMIT,
T_COMMIT_DFLUSH,
T_COMMIT_JFLUSH,
+ T_COMMIT_CALLBACK,
T_FINISHED
} t_state;
int jbd2_journal_start_commit(journal_t *journal, tid_t *tid);
int jbd2_journal_force_commit_nested(journal_t *journal);
int jbd2_log_wait_commit(journal_t *journal, tid_t tid);
+int jbd2_complete_transaction(journal_t *journal, tid_t tid);
int jbd2_log_do_checkpoint(journal_t *journal);
int jbd2_trans_will_send_data_barrier(journal_t *journal, tid_t tid);
index 2c497ab0d03d41f7c8e85531a46776cba47f8d14..ffdf8b731e8c00a1369b3bb8aa26230a70a36604 100644 (file)
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
int kvm_write_guest_cached(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
void *data, unsigned long len);
int kvm_gfn_to_hva_cache_init(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
- gpa_t gpa);
+ gpa_t gpa, unsigned long len);
int kvm_clear_guest_page(struct kvm *kvm, gfn_t gfn, int offset, int len);
int kvm_clear_guest(struct kvm *kvm, gpa_t gpa, unsigned long len);
struct kvm_memory_slot *gfn_to_memslot(struct kvm *kvm, gfn_t gfn);
index fa7cc7244cbdbf019591f644e42622145c8dd28b..b0bcce0ddc95a531dd30c30e91a89c92e961b8d4 100644 (file)
u64 generation;
gpa_t gpa;
unsigned long hva;
+ unsigned long len;
struct kvm_memory_slot *memslot;
};
index 46dbfb7f87852e2f8ab6b3de606a6837c20a6f84..bbe280e1343bf9396127bde0933063082bab299e 100644 (file)
int designrev;
int sw_revision;
+ int palmas_id;
/* IRQ Data */
int irq;
u32 irq_mask;
};
+enum pmic_ids {
+ TWL6035,
+ TWL6037,
+ TPS65913,
+ TPS659038,
+};
+
enum palmas_regulators {
/* SMPS regulators */
PALMAS_REG_SMPS12,
enum omap_dwc3_vbus_id_status linkstat;
};
+/**
+ * struct palmas_pmic_data - Maintains the specific data for PMICs of PALMAS
+ * family
+ * @irq_chip: regmap_irq_chip specific to individual members
+ * of PALMAS family.
+ * @regmap_config: regmap_config specific to the individual members
+ * of PALMAS family.
+ * @mfd_cell: mfd cell specific to the individual members of
+ * PALMAS family.
+ * @id: Id of the member of the PALMAS family.
+ * @has_usb: Flag indicating whether PMIC supports USB
+ */
+struct palmas_pmic_data {
+ struct regmap_irq_chip *irq_chip;
+ const struct regmap_config *regmap_config;
+ const struct mfd_cell *mfd_cell;
+ int id;
+ int has_usb;
+};
+
#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
enum usb_irq_events {
#define PALMAS_GPADC_TRIM15 0xE
#define PALMAS_GPADC_TRIM16 0xF
+static inline int palmas_read(struct palmas *palmas, unsigned int base,
+ unsigned int reg, unsigned int *val)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_read(palmas->regmap[slave_id], addr, val);
+}
+
+static inline int palmas_write(struct palmas *palmas, unsigned int base,
+ unsigned int reg, unsigned int value)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_write(palmas->regmap[slave_id], addr, value);
+}
+
+static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
+ unsigned int reg, const void *val, size_t val_count)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_bulk_write(palmas->regmap[slave_id], addr,
+ val, val_count);
+}
+
+static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
+ unsigned int reg, void *val, size_t val_count)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_bulk_read(palmas->regmap[slave_id], addr,
+ val, val_count);
+}
+
+static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
+ unsigned int reg, unsigned int mask, unsigned int val)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
+}
+
+static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
+{
+ return regmap_irq_get_virq(palmas->irq_data, irq);
+}
+
#endif /* __LINUX_MFD_PALMAS_H */
index c79ad5d2f2716d38aaee8054b74af1c41734761d..50a245f7fca550f0f63e665498180ab780abcea1 100644 (file)
#define STEPENB_MASK (0x1FFFF << 0)
#define STEPENB(val) ((val) << 0)
#define STPENB_STEPENB STEPENB(0x1FFFF)
-#define STPENB_STEPENB_TC STEPENB(0x1FFF)
/* IRQ enable */
#define IRQENB_HW_PEN BIT(0)
#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
#define STEPCONFIG_INP_MASK (0xF << 19)
#define STEPCONFIG_INP(val) ((val) << 19)
-#define STEPCONFIG_INP_AN2 STEPCONFIG_INP(2)
-#define STEPCONFIG_INP_AN3 STEPCONFIG_INP(3)
#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
#define STEPCONFIG_FIFO1 BIT(26)
#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
#define STEPCHARGE_INP_MASK (0xF << 19)
#define STEPCHARGE_INP(val) ((val) << 19)
-#define STEPCHARGE_INP_AN1 STEPCHARGE_INP(1)
#define STEPCHARGE_RFM_MASK (3 << 23)
#define STEPCHARGE_RFM(val) ((val) << 23)
#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
#define CNTRLREG_TSCENB BIT(7)
+#define XPP STEPCONFIG_XPP
+#define XNP STEPCONFIG_XNP
+#define XNN STEPCONFIG_XNN
+#define YPP STEPCONFIG_YPP
+#define YPN STEPCONFIG_YPN
+#define YNN STEPCONFIG_YNN
+
#define ADC_CLK 3000000
#define MAX_CLK_DIV 7
#define TOTAL_STEPS 16
#define TSCADC_CELLS 2
-enum tscadc_cells {
- TSC_CELL,
- ADC_CELL,
-};
-
struct mfd_tscadc_board {
struct tsc_data *tsc_init;
struct adc_data *adc_init;
struct regmap *regmap_tscadc;
void __iomem *tscadc_base;
int irq;
+ int used_cells; /* 0-2 */
+ int tsc_cell; /* -1 if not used */
+ int adc_cell; /* -1 if not used */
struct mfd_cell cells[TSCADC_CELLS];
/* tsc device */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 85fb463571275e80fff5f9d131ae5ea11209293f..b2b1b1cfc436fddfbe44791207633f5e1f41e6e8 100644 (file)
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
unsigned long pfn);
int vm_insert_mixed(struct vm_area_struct *vma, unsigned long addr,
unsigned long pfn);
+int vm_iomap_memory(struct vm_area_struct *vma, phys_addr_t start, unsigned long len);
+
struct page *follow_page(struct vm_area_struct *, unsigned long address,
unsigned int foll_flags);
index 9ef07d0868b6012da1d1089daa2c9b0d7d304389..0e182f9f7d40d0da57fbb0072651b4a2c552e8f9 100644 (file)
#define NETDEV_HW_ADDR_T_SLAVE 3
#define NETDEV_HW_ADDR_T_UNICAST 4
#define NETDEV_HW_ADDR_T_MULTICAST 5
- bool synced;
bool global_use;
int refcount;
+ int synced;
struct rcu_head rcu_head;
};
index d10bb0f39c5e72fd6bb7747e47761d062f75c981..eea5af05a948b0c2cafa8bc89a0f2c180ad9d4a8 100644 (file)
struct blocking_notifier_head notifier;
struct mutex mutex; /* consumer lock */
+ struct task_struct *lock_owner;
+ int lock_count;
struct module *owner;
struct device dev;
struct regulation_constraints *constraints;
diff --git a/include/linux/sched.h b/include/linux/sched.h
index a4d9b893144fac75b54882f79e416c1afff0e782..ed1650699563747ea9d48ff28b7192db9bb41c66 100644 (file)
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
#define TASK_DEAD 64
#define TASK_WAKEKILL 128
#define TASK_WAKING 256
-#define TASK_STATE_MAX 512
+#define TASK_PARKED 512
+#define TASK_STATE_MAX 1024
-#define TASK_STATE_TO_CHAR_STR "RSDTtZXxKW"
+#define TASK_STATE_TO_CHAR_STR "RSDTtZXxKWP"
extern char ___assert_task_state[1 - 2*!!(
sizeof(TASK_STATE_TO_CHAR_STR)-1 != ilog2(TASK_STATE_MAX)+1)];
*
* Lock the threadgroup @tsk belongs to. No new task is allowed to enter
* and member tasks aren't allowed to exit (as indicated by PF_EXITING) or
- * perform exec. This is useful for cases where the threadgroup needs to
- * stay stable across blockable operations.
+ * change ->group_leader/pid. This is useful for cases where the threadgroup
+ * needs to stay stable across blockable operations.
*
* fork and exit paths explicitly call threadgroup_change_{begin|end}() for
* synchronization. While held, no new task will be added to threadgroup
* and no existing live task will have its PF_EXITING set.
*
- * During exec, a task goes and puts its thread group through unusual
- * changes. After de-threading, exclusive access is assumed to resources
- * which are usually shared by tasks in the same group - e.g. sighand may
- * be replaced with a new one. Also, the exec'ing task takes over group
- * leader role including its pid. Exclude these changes while locked by
- * grabbing cred_guard_mutex which is used to synchronize exec path.
+ * de_thread() does threadgroup_change_{begin|end}() when a non-leader
+ * sub-thread becomes a new leader.
*/
static inline void threadgroup_lock(struct task_struct *tsk)
{
- /*
- * exec uses exit for de-threading nesting group_rwsem inside
- * cred_guard_mutex. Grab cred_guard_mutex first.
- */
- mutex_lock(&tsk->signal->cred_guard_mutex);
down_write(&tsk->signal->group_rwsem);
}
static inline void threadgroup_unlock(struct task_struct *tsk)
{
up_write(&tsk->signal->group_rwsem);
- mutex_unlock(&tsk->signal->cred_guard_mutex);
}
#else
static inline void threadgroup_change_begin(struct task_struct *tsk) {}
index 6cf2d59dbcbe5b81f8a942897a84e17e0d0d8cae..c52e642fac08fee0c08a027895e716efb16af075 100644 (file)
#include <linux/pps_kernel.h>
#include <uapi/linux/serial_core.h>
+#ifdef CONFIG_SERIAL_CORE_CONSOLE
+#define uart_console(port) \
+ ((port)->cons && (port)->cons->index == (port)->line)
+#else
+#define uart_console(port) (0)
+#endif
+
struct uart_port;
struct serial_struct;
struct device;
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 98399e262e3a8d4ad8677a2ec3e15a7741a337b7..9fe54b674e13a99d36ef6aeb2f68f4a3b7223a13 100644 (file)
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
#endif
}
+static inline void nf_reset_trace(struct sk_buff *skb)
+{
+#if IS_ENABLED(CONFIG_NETFILTER_XT_TARGET_TRACE)
+ skb->nf_trace = 0;
+#endif
+}
+
/* Note: This doesn't put any conntrack and bridge info in dst. */
static inline void __nf_copy(struct sk_buff *dst, const struct sk_buff *src)
{
index 9e492be5244b40d8ead3340aa7ac475cb51e56ff..6fcfe99bd999d295e0eb8efb967d0b2892335afc 100644 (file)
#define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
#define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
+#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
#define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
#define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
#define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
enum ssb_pmu_ldo_volt_id id, u32 voltage);
void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
+void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
#endif /* LINUX_SSB_CHIPCO_H_ */
index e3c0ae9bb1faf876afca191701e481ecc30a4f1b..6400245bf3f64b0687cca473cbf37a42240b27cf 100644 (file)
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
struct thermal_cooling_device *thermal_cooling_device_register(char *, void *,
const struct thermal_cooling_device_ops *);
void thermal_cooling_device_unregister(struct thermal_cooling_device *);
+struct thermal_zone_device *thermal_zone_get_zone_by_name(const char *name);
+int thermal_zone_get_temp(struct thermal_zone_device *tz, unsigned long *temp);
int get_tz_trend(struct thermal_zone_device *, int);
struct thermal_instance *get_thermal_instance(struct thermal_zone_device *,
diff --git a/include/net/scm.h b/include/net/scm.h
index 975cca01048bee3b7da9017725654053921250ae..b11708105681e04f5c24f7ed206f732e2c37dc02 100644 (file)
--- a/include/net/scm.h
+++ b/include/net/scm.h
scm->pid = get_pid(pid);
scm->cred = cred ? get_cred(cred) : NULL;
scm->creds.pid = pid_vnr(pid);
- scm->creds.uid = cred ? cred->euid : INVALID_UID;
- scm->creds.gid = cred ? cred->egid : INVALID_GID;
+ scm->creds.uid = cred ? cred->uid : INVALID_UID;
+ scm->creds.gid = cred ? cred->gid : INVALID_GID;
}
static __inline__ void scm_destroy_cred(struct scm_cookie *scm)
index f841ba4bacb81985f1a52257c8230a22de0333e2..dfb42ca6d0436539ada89bcd063c26e5c4e85d86 100644 (file)
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
unsigned int next_free_voice;
const struct firmware *firmware;
+ const struct firmware *dock_fw;
#ifdef CONFIG_PM_SLEEP
unsigned int *saved_ptr;
index 5a8671e8a67ff8fa8f715311300901181555d78e..e5586caff67a973c962a3ed6bf43d4cc01664083 100644 (file)
__print_flags(__entry->prev_state & (TASK_STATE_MAX-1), "|",
{ 1, "S"} , { 2, "D" }, { 4, "T" }, { 8, "t" },
{ 16, "Z" }, { 32, "X" }, { 64, "x" },
- { 128, "W" }) : "R",
+ { 128, "K" }, { 256, "W" }, { 512, "P" }) : "R",
__entry->prev_state & TASK_STATE_MAX ? "+" : "",
__entry->next_comm, __entry->next_pid, __entry->next_prio)
);
similarity index 99%
rename from drivers/staging/omapdrm/omap_drm.h
rename to include/uapi/drm/omap_drm.h
index f0ac34a8973e06f0f1f0286ffb5ae500e3acf2e9..1d0b1172664e8d8666dc49ae9f1690bf6e9feb70 100644 (file)
rename from drivers/staging/omapdrm/omap_drm.h
rename to include/uapi/drm/omap_drm.h
index f0ac34a8973e06f0f1f0286ffb5ae500e3acf2e9..1d0b1172664e8d8666dc49ae9f1690bf6e9feb70 100644 (file)
/*
- * include/drm/omap_drm.h
+ * include/uapi/drm/omap_drm.h
*
* Copyright (C) 2011 Texas Instruments
* Author: Rob Clark <rob@ti.com>
diff --git a/include/video/omap-panel-tfcs9700.h b/include/video/omap-panel-tfcs9700.h
--- /dev/null
@@ -0,0 +1,11 @@
+#ifndef __PANEL_TFCS9700_H
+#define __PANEL_TFCS9700_H
+/**
+ * struct : tfc s9700 panel data
+ */
+struct tfc_s9700_platform_data {
+ int p_gpio;
+ int datalines;
+ int tlc_adapter_id;
+};
+#endif /* __PANEL_PICODLP_H */
index 7fd3d65065622a8bc0cb4f41645de417a32e3df6..7ca219a63c62ac2436cbc28c2cccd4bcb331b046 100644 (file)
--- a/include/video/omapdss.h
+++ b/include/video/omapdss.h
OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
OMAP_DSS_OUTPUT_VENC = 1 << 5,
OMAP_DSS_OUTPUT_HDMI = 1 << 6,
+ OMAP_DSS_OUTPUT_DPI1 = 1 << 7,
+ OMAP_DSS_OUTPUT_DPI2 = 1 << 8,
};
/* Stereoscopic Panel types
OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
OMAPDSS_VER_OMAP4, /* All other OMAP4s */
OMAPDSS_VER_OMAP5,
+ OMAPDSS_VER_DRA7xx,
};
/* Board specific data */
diff --git a/ipc/shm.c b/ipc/shm.c
index 4fa6d8fee730c05e3fe4e4fbb93fa40690ede3bc..9ec2316143034e13fa805f988ce9342808cdeba6 100644 (file)
--- a/ipc/shm.c
+++ b/ipc/shm.c
size_t size = params->u.size;
int error;
struct shmid_kernel *shp;
- int numpages = (size + PAGE_SIZE -1) >> PAGE_SHIFT;
+ size_t numpages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
struct file * file;
char name[13];
int id;
sprintf (name, "SYSV%08x", key);
if (shmflg & SHM_HUGETLB) {
+ struct hstate *hs = hstate_sizelog((shmflg >> SHM_HUGE_SHIFT)
+ & SHM_HUGE_MASK);
+ size_t hugesize = ALIGN(size, huge_page_size(hs));
+
/* hugetlb_file_setup applies strict accounting */
if (shmflg & SHM_NORESERVE)
acctflag = VM_NORESERVE;
- file = hugetlb_file_setup(name, 0, size, acctflag,
+ file = hugetlb_file_setup(name, hugesize, acctflag,
&shp->mlock_user, HUGETLB_SHMFS_INODE,
(shmflg >> SHM_HUGE_SHIFT) & SHM_HUGE_MASK);
} else {
diff --git a/kernel/audit_tree.c b/kernel/audit_tree.c
index 642a89c4f3d60c23cabf89b86d387f2a29b2bea9..a291aa23fb3fa770756b05f7453be4c92531004c 100644 (file)
--- a/kernel/audit_tree.c
+++ b/kernel/audit_tree.c
}
spin_unlock(&hash_lock);
trim_marked(tree);
- put_tree(tree);
drop_collected_mounts(root_mnt);
skip_it:
+ put_tree(tree);
mutex_lock(&audit_filter_mutex);
}
list_del(&cursor);
diff --git a/kernel/capability.c b/kernel/capability.c
index 493d97259484cfef006c59b934be4fcf9663d1ac..f6c2ce5701e1c3c723d03e3d917c62f584c3a074 100644 (file)
--- a/kernel/capability.c
+++ b/kernel/capability.c
}
EXPORT_SYMBOL(ns_capable);
+/**
+ * file_ns_capable - Determine if the file's opener had a capability in effect
+ * @file: The file we want to check
+ * @ns: The usernamespace we want the capability in
+ * @cap: The capability to be tested for
+ *
+ * Return true if task that opened the file had a capability in effect
+ * when the file was opened.
+ *
+ * This does not set PF_SUPERPRIV because the caller may not
+ * actually be privileged.
+ */
+bool file_ns_capable(const struct file *file, struct user_namespace *ns, int cap)
+{
+ if (WARN_ON_ONCE(!cap_valid(cap)))
+ return false;
+
+ if (security_capable(file->f_cred, ns, cap) == 0)
+ return true;
+
+ return false;
+}
+EXPORT_SYMBOL(file_ns_capable);
+
/**
* capable - Determine if the current task has a superior capability in effect
* @cap: The capability to be tested for
diff --git a/kernel/cgroup.c b/kernel/cgroup.c
index 21762fc354fbcd14c3fba6abbfa0dc51f649de25..f28c151d30cabe4d32855d1393cafc9f52c12f3c 100644 (file)
--- a/kernel/cgroup.c
+++ b/kernel/cgroup.c
struct list_head node;
struct dentry *dentry;
struct cftype *type;
+
+ /* file xattrs */
+ struct simple_xattrs xattrs;
};
/*
} else {
struct cfent *cfe = __d_cfe(dentry);
struct cgroup *cgrp = dentry->d_parent->d_fsdata;
- struct cftype *cft = cfe->type;
WARN_ONCE(!list_empty(&cfe->node) &&
cgrp != &cgrp->root->top_cgroup,
"cfe still linked for %s\n", cfe->type->name);
+ simple_xattrs_free(&cfe->xattrs);
kfree(cfe);
- simple_xattrs_free(&cft->xattrs);
}
iput(inode);
}
@@ -2066,7 +2068,7 @@ static int cgroup_attach_proc(struct cgroup *cgrp, struct task_struct *leader)
if (!group)
return -ENOMEM;
/* pre-allocate to guarantee space while iterating in rcu read-side. */
- retval = flex_array_prealloc(group, 0, group_size - 1, GFP_KERNEL);
+ retval = flex_array_prealloc(group, 0, group_size, GFP_KERNEL);
if (retval)
goto out_free_group_list;
if (S_ISDIR(dentry->d_inode->i_mode))
return &__d_cgrp(dentry)->xattrs;
else
- return &__d_cft(dentry)->xattrs;
+ return &__d_cfe(dentry)->xattrs;
}
static inline int xattr_enabled(struct dentry *dentry)
umode_t mode;
char name[MAX_CGROUP_TYPE_NAMELEN + MAX_CFTYPE_NAME + 2] = { 0 };
- simple_xattrs_init(&cft->xattrs);
-
if (subsys && !test_bit(ROOT_NOPREFIX, &cgrp->root->flags)) {
strcpy(name, subsys->name);
strcat(name, ".");
cfe->type = (void *)cft;
cfe->dentry = dentry;
dentry->d_fsdata = cfe;
+ simple_xattrs_init(&cfe->xattrs);
list_add_tail(&cfe->node, &parent->files);
cfe = NULL;
}
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 7b6646a8c067b4ec9143585746fd2b2bccb73f0c..0600d3bf1cddac7f3767126ab2b2e3b5321aacd9 100644 (file)
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
static int perf_swevent_init(struct perf_event *event)
{
- int event_id = event->attr.config;
+ u64 event_id = event->attr.config;
if (event->attr.type != PERF_TYPE_SOFTWARE)
return -ENOENT;
diff --git a/kernel/hrtimer.c b/kernel/hrtimer.c
index cdd5607c0cebab46fc829d9a586a80cdeb716b66..60f7e326b6c8affc04d6e18c398db9a3abfdb26f 100644 (file)
--- a/kernel/hrtimer.c
+++ b/kernel/hrtimer.c
DEFINE_PER_CPU(struct hrtimer_cpu_base, hrtimer_bases) =
{
+ .lock = __RAW_SPIN_LOCK_UNLOCKED(hrtimer_bases.lock),
.clock_base =
{
{
} else {
unsigned long rem = do_div(nsec, NSEC_PER_SEC);
+ /* Make sure nsec fits into long */
+ if (unlikely(nsec > KTIME_SEC_MAX))
+ return (ktime_t){ .tv64 = KTIME_MAX };
+
tmp = ktime_set((long)nsec, rem);
}
expires = ktime_sub(hrtimer_get_expires(timer),
base->offset);
+ if (expires.tv64 < 0)
+ expires.tv64 = KTIME_MAX;
if (expires.tv64 < expires_next.tv64)
expires_next = expires;
break;
struct hrtimer_cpu_base *cpu_base = &per_cpu(hrtimer_bases, cpu);
int i;
- raw_spin_lock_init(&cpu_base->lock);
-
for (i = 0; i < HRTIMER_MAX_CLOCK_BASES; i++) {
cpu_base->clock_base[i].cpu_base = cpu_base;
timerqueue_init_head(&cpu_base->clock_base[i].active);
diff --git a/kernel/kthread.c b/kernel/kthread.c
index 691dc2ef9baf241c121144799360a7e1237afcb5..9eb7fed0bbaa9895973a14e551c76de31fffe533 100644 (file)
--- a/kernel/kthread.c
+++ b/kernel/kthread.c
static void __kthread_parkme(struct kthread *self)
{
- __set_current_state(TASK_INTERRUPTIBLE);
+ __set_current_state(TASK_PARKED);
while (test_bit(KTHREAD_SHOULD_PARK, &self->flags)) {
if (!test_and_set_bit(KTHREAD_IS_PARKED, &self->flags))
complete(&self->parked);
schedule();
- __set_current_state(TASK_INTERRUPTIBLE);
+ __set_current_state(TASK_PARKED);
}
clear_bit(KTHREAD_IS_PARKED, &self->flags);
__set_current_state(TASK_RUNNING);
}
EXPORT_SYMBOL(kthread_create_on_node);
-static void __kthread_bind(struct task_struct *p, unsigned int cpu)
+static void __kthread_bind(struct task_struct *p, unsigned int cpu, long state)
{
+ /* Must have done schedule() in kthread() before we set_task_cpu */
+ if (!wait_task_inactive(p, state)) {
+ WARN_ON(1);
+ return;
+ }
/* It's safe because the task is inactive. */
do_set_cpus_allowed(p, cpumask_of(cpu));
p->flags |= PF_THREAD_BOUND;
*/
void kthread_bind(struct task_struct *p, unsigned int cpu)
{
- /* Must have done schedule() in kthread() before we set_task_cpu */
- if (!wait_task_inactive(p, TASK_UNINTERRUPTIBLE)) {
- WARN_ON(1);
- return;
- }
- __kthread_bind(p, cpu);
+ __kthread_bind(p, cpu, TASK_UNINTERRUPTIBLE);
}
EXPORT_SYMBOL(kthread_bind);
return NULL;
}
+static void __kthread_unpark(struct task_struct *k, struct kthread *kthread)
+{
+ clear_bit(KTHREAD_SHOULD_PARK, &kthread->flags);
+ /*
+ * We clear the IS_PARKED bit here as we don't wait
+ * until the task has left the park code. So if we'd
+ * park before that happens we'd see the IS_PARKED bit
+ * which might be about to be cleared.
+ */
+ if (test_and_clear_bit(KTHREAD_IS_PARKED, &kthread->flags)) {
+ if (test_bit(KTHREAD_IS_PER_CPU, &kthread->flags))
+ __kthread_bind(k, kthread->cpu, TASK_PARKED);
+ wake_up_state(k, TASK_PARKED);
+ }
+}
+
/**
* kthread_unpark - unpark a thread created by kthread_create().
* @k: thread created by kthread_create().
{
struct kthread *kthread = task_get_live_kthread(k);
- if (kthread) {
- clear_bit(KTHREAD_SHOULD_PARK, &kthread->flags);
- /*
- * We clear the IS_PARKED bit here as we don't wait
- * until the task has left the park code. So if we'd
- * park before that happens we'd see the IS_PARKED bit
- * which might be about to be cleared.
- */
- if (test_and_clear_bit(KTHREAD_IS_PARKED, &kthread->flags)) {
- if (test_bit(KTHREAD_IS_PER_CPU, &kthread->flags))
- __kthread_bind(k, kthread->cpu);
- wake_up_process(k);
- }
- }
+ if (kthread)
+ __kthread_unpark(k, kthread);
put_task_struct(k);
}
trace_sched_kthread_stop(k);
if (kthread) {
set_bit(KTHREAD_SHOULD_STOP, &kthread->flags);
- clear_bit(KTHREAD_SHOULD_PARK, &kthread->flags);
+ __kthread_unpark(k, kthread);
wake_up_process(k);
wait_for_completion(&kthread->exited);
}
diff --git a/kernel/rcutree_trace.c b/kernel/rcutree_trace.c
index 0d095dcaa6708b8517153bf604cf70762ea28323..93f8e8fbfbc6c896feb56382dcfb1870a605dd30 100644 (file)
--- a/kernel/rcutree_trace.c
+++ b/kernel/rcutree_trace.c
.open = rcubarrier_open,
.read = seq_read,
.llseek = no_llseek,
- .release = seq_release,
+ .release = single_release,
};
#ifdef CONFIG_RCU_BOOST
.open = rcuexp_open,
.read = seq_read,
.llseek = no_llseek,
- .release = seq_release,
+ .release = single_release,
};
#ifdef CONFIG_RCU_BOOST
.open = rcuhier_open,
.read = seq_read,
.llseek = no_llseek,
- .release = seq_release,
+ .release = single_release,
};
static void show_one_rcugp(struct seq_file *m, struct rcu_state *rsp)
.open = rcugp_open,
.read = seq_read,
.llseek = no_llseek,
- .release = seq_release,
+ .release = single_release,
};
static void print_one_rcu_pending(struct seq_file *m, struct rcu_data *rdp)
diff --git a/kernel/sched/core.c b/kernel/sched/core.c
index a1173717253edd90f91355031ca7491da20065ee..0f8f7714f33e80c5f131825ab9275cc0b35bca6f 100644 (file)
--- a/kernel/sched/core.c
+++ b/kernel/sched/core.c
{
struct rq *rq = task_rq(p);
- BUG_ON(rq != this_rq());
- BUG_ON(p == current);
+ if (WARN_ON_ONCE(rq != this_rq()) ||
+ WARN_ON_ONCE(p == current))
+ return;
+
lockdep_assert_held(&rq->lock);
if (!raw_spin_trylock(&p->pi_lock)) {
}
static int min_load_idx = 0;
-static int max_load_idx = CPU_LOAD_IDX_MAX;
+static int max_load_idx = CPU_LOAD_IDX_MAX-1;
static void
set_table_entry(struct ctl_table *entry,
diff --git a/kernel/signal.c b/kernel/signal.c
index dec9c305aec440622418abc4bc638c5f8d2eab0c..50e425cbc8874a01621d2f8fef3c5b4e252885e6 100644 (file)
--- a/kernel/signal.c
+++ b/kernel/signal.c
static int do_tkill(pid_t tgid, pid_t pid, int sig)
{
- struct siginfo info;
+ struct siginfo info = {};
info.si_signo = sig;
info.si_errno = 0;
index a13987af44fdad01a8f66c82fafc16c720269435..239a323b3e525c0e5475d91701f564e8fcf67453 100644 (file)
*/
int tick_check_broadcast_device(struct clock_event_device *dev)
{
+ struct clock_event_device *cur = tick_broadcast_device.evtdev;
+
if ((dev->features & CLOCK_EVT_FEAT_DUMMY) ||
(tick_broadcast_device.evtdev &&
tick_broadcast_device.evtdev->rating >= dev->rating) ||
return 0;
clockevents_exchange_device(tick_broadcast_device.evtdev, dev);
+ if (cur)
+ cur->event_handler = clockevents_handle_noop;
tick_broadcast_device.evtdev = dev;
if (!cpumask_empty(tick_get_broadcast_mask()))
tick_broadcast_start_periodic(dev);
index b1600a6973f4492d18df06483e2245443fc91201..7076b3f53e8f9534b3d8a3d99c0ce36d04be0665 100644 (file)
*/
dev->mode = CLOCK_EVT_MODE_UNUSED;
clockevents_exchange_device(dev, NULL);
+ dev->event_handler = clockevents_handle_noop;
td->evtdev = NULL;
}
raw_spin_unlock_irqrestore(&tick_device_lock, flags);
diff --git a/kernel/trace/ftrace.c b/kernel/trace/ftrace.c
index 35cc3a8909d6d3f0b19e80bd60c0aa640ff844b9..03dbc77b4bdfea0e31173eff12eb8bb5943ef9d4 100644 (file)
--- a/kernel/trace/ftrace.c
+++ b/kernel/trace/ftrace.c
pages = DIV_ROUND_UP(functions, PROFILES_PER_PAGE);
- for (i = 0; i < pages; i++) {
+ for (i = 1; i < pages; i++) {
pg->next = (void *)get_zeroed_page(GFP_KERNEL);
if (!pg->next)
goto out_free;
if (fail)
return -EINVAL;
- ftrace_graph_filter_enabled = 1;
+ ftrace_graph_filter_enabled = !!(*idx);
+
return 0;
}
diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index fe1d581a150afffafe2cd6d0c5e0d8fb58108451..55a9d0501ee71ae5b2505d932f524b3f5b1c1a6c 100644 (file)
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
trace_access_lock_init();
d_tracer = tracing_init_dentry();
+ if (!d_tracer)
+ return 0;
trace_create_file("trace_options", 0644, d_tracer,
NULL, &tracing_iter_fops);
iter->cpu_file = TRACE_PIPE_ALL_CPU;
}
-static void
-__ftrace_dump(bool disable_tracing, enum ftrace_dump_mode oops_dump_mode)
+void ftrace_dump(enum ftrace_dump_mode oops_dump_mode)
{
- static arch_spinlock_t ftrace_dump_lock =
- (arch_spinlock_t)__ARCH_SPIN_LOCK_UNLOCKED;
/* use static because iter can be a bit big for the stack */
static struct trace_iterator iter;
+ static atomic_t dump_running;
unsigned int old_userobj;
- static int dump_ran;
unsigned long flags;
int cnt = 0, cpu;
- /* only one dump */
- local_irq_save(flags);
- arch_spin_lock(&ftrace_dump_lock);
- if (dump_ran)
- goto out;
-
- dump_ran = 1;
+ /* Only allow one dump user at a time. */
+ if (atomic_inc_return(&dump_running) != 1) {
+ atomic_dec(&dump_running);
+ return;
+ }
+ /*
+ * Always turn off tracing when we dump.
+ * We don't need to show trace output of what happens
+ * between multiple crashes.
+ *
+ * If the user does a sysrq-z, then they can re-enable
+ * tracing with echo 1 > tracing_on.
+ */
tracing_off();
- /* Did function tracer already get disabled? */
- if (ftrace_is_dead()) {
- printk("# WARNING: FUNCTION TRACING IS CORRUPTED\n");
- printk("# MAY BE MISSING FUNCTION EVENTS\n");
- }
-
- if (disable_tracing)
- ftrace_kill();
+ local_irq_save(flags);
trace_init_global_iter(&iter);
printk(KERN_TRACE "Dumping ftrace buffer:\n");
+ /* Did function tracer already get disabled? */
+ if (ftrace_is_dead()) {
+ printk("# WARNING: FUNCTION TRACING IS CORRUPTED\n");
+ printk("# MAY BE MISSING FUNCTION EVENTS\n");
+ }
+
/*
* We need to stop all tracing on all CPUS to read the
* the next buffer. This is a bit expensive, but is
printk(KERN_TRACE "---------------------------------\n");
out_enable:
- /* Re-enable tracing if requested */
- if (!disable_tracing) {
- trace_flags |= old_userobj;
+ trace_flags |= old_userobj;
- for_each_tracing_cpu(cpu) {
- atomic_dec(&iter.tr->data[cpu]->disabled);
- }
- tracing_on();
+ for_each_tracing_cpu(cpu) {
+ atomic_dec(&iter.tr->data[cpu]->disabled);
}
-
- out:
- arch_spin_unlock(&ftrace_dump_lock);
+ atomic_dec(&dump_running);
local_irq_restore(flags);
}
-
-/* By default: disable tracing after the dump */
-void ftrace_dump(enum ftrace_dump_mode oops_dump_mode)
-{
- __ftrace_dump(true, oops_dump_mode);
-}
EXPORT_SYMBOL_GPL(ftrace_dump);
__init static int tracer_alloc_buffers(void)
index 47623169a815def678e012083aa70a21fd7c8ec9..81f6275fc5499cd47ca97059f3b2466a70c2c474 100644 (file)
char *func_name;
int len;
int ret;
- int cnt;
/* The previous test PASSED */
pr_cont("PASSED\n");
unregister_ftrace_function(&test_recsafe_probe);
- /*
- * If arch supports all ftrace features, and no other task
- * was on the list, we should be fine.
- */
- if (!ftrace_nr_registered_ops() && !FTRACE_FORCE_LIST_FUNC)
- cnt = 2; /* Should have recursed */
- else
- cnt = 1;
-
ret = -1;
- if (trace_selftest_recursion_cnt != cnt) {
- pr_cont("*callback not called expected %d times (%d)* ",
- cnt, trace_selftest_recursion_cnt);
+ if (trace_selftest_recursion_cnt != 2) {
+ pr_cont("*callback not called expected 2 times (%d)* ",
+ trace_selftest_recursion_cnt);
goto out;
}
/* Maximum number of functions to trace before diagnosing a hang */
#define GRAPH_MAX_FUNC_TEST 100000000
-static void
-__ftrace_dump(bool disable_tracing, enum ftrace_dump_mode oops_dump_mode);
static unsigned int graph_hang_thresh;
/* Wrap the real function entry probe to avoid possible hanging */
if (unlikely(++graph_hang_thresh > GRAPH_MAX_FUNC_TEST)) {
ftrace_graph_stop();
printk(KERN_WARNING "BUG: Function graph tracer hang!\n");
- if (ftrace_dump_on_oops)
- __ftrace_dump(false, DUMP_ALL);
+ if (ftrace_dump_on_oops) {
+ ftrace_dump(DUMP_ALL);
+ /* ftrace_dump() disables tracing */
+ tracing_on();
+ }
return 0;
}
index 83a8b5b7bd35fa01a5e0302d83bf3d33d81f9557..b20428c5efe26ba54ef2a6e83bb9ad711a9f85b5 100644 (file)
#define STACK_TRACE_ENTRIES 500
+#ifdef CC_USING_FENTRY
+# define fentry 1
+#else
+# define fentry 0
+#endif
+
static unsigned long stack_dump_trace[STACK_TRACE_ENTRIES+1] =
{ [0 ... (STACK_TRACE_ENTRIES)] = ULONG_MAX };
static unsigned stack_dump_index[STACK_TRACE_ENTRIES];
+/*
+ * Reserve one entry for the passed in ip. This will allow
+ * us to remove most or all of the stack size overhead
+ * added by the stack tracer itself.
+ */
static struct stack_trace max_stack_trace = {
- .max_entries = STACK_TRACE_ENTRIES,
- .entries = stack_dump_trace,
+ .max_entries = STACK_TRACE_ENTRIES - 1,
+ .entries = &stack_dump_trace[1],
};
static unsigned long max_stack_size;
int stack_tracer_enabled;
static int last_stack_tracer_enabled;
-static inline void check_stack(void)
+static inline void
+check_stack(unsigned long ip, unsigned long *stack)
{
unsigned long this_size, flags;
unsigned long *p, *top, *start;
+ static int tracer_frame;
+ int frame_size = ACCESS_ONCE(tracer_frame);
int i;
- this_size = ((unsigned long)&this_size) & (THREAD_SIZE-1);
+ this_size = ((unsigned long)stack) & (THREAD_SIZE-1);
this_size = THREAD_SIZE - this_size;
+ /* Remove the frame of the tracer */
+ this_size -= frame_size;
if (this_size <= max_stack_size)
return;
/* we do not handle interrupt stacks yet */
- if (!object_is_on_stack(&this_size))
+ if (!object_is_on_stack(stack))
return;
local_irq_save(flags);
arch_spin_lock(&max_stack_lock);
+ /* In case another CPU set the tracer_frame on us */
+ if (unlikely(!frame_size))
+ this_size -= tracer_frame;
+
/* a race could have already updated it */
if (this_size <= max_stack_size)
goto out;
save_stack_trace(&max_stack_trace);
+ /*
+ * Add the passed in ip from the function tracer.
+ * Searching for this on the stack will skip over
+ * most of the overhead from the stack tracer itself.
+ */
+ stack_dump_trace[0] = ip;
+ max_stack_trace.nr_entries++;
+
/*
* Now find where in the stack these are.
*/
i = 0;
- start = &this_size;
+ start = stack;
top = (unsigned long *)
(((unsigned long)start & ~(THREAD_SIZE-1)) + THREAD_SIZE);
found = 1;
/* Start the search from here */
start = p + 1;
+ /*
+ * We do not want to show the overhead
+ * of the stack tracer stack in the
+ * max stack. If we haven't figured
+ * out what that is, then figure it out
+ * now.
+ */
+ if (unlikely(!tracer_frame) && i == 1) {
+ tracer_frame = (p - stack) *
+ sizeof(unsigned long);
+ max_stack_size -= tracer_frame;
+ }
}
}
stack_trace_call(unsigned long ip, unsigned long parent_ip,
struct ftrace_ops *op, struct pt_regs *pt_regs)
{
+ unsigned long stack;
int cpu;
preempt_disable_notrace();
if (per_cpu(trace_active, cpu)++ != 0)
goto out;
- check_stack();
+ /*
+ * When fentry is used, the traced function does not get
+ * its stack frame set up, and we lose the parent.
+ * The ip is pretty useless because the function tracer
+ * was called before that function set up its stack frame.
+ * In this case, we use the parent ip.
+ *
+ * By adding the return address of either the parent ip
+ * or the current ip we can disregard most of the stack usage
+ * caused by the stack tracer itself.
+ *
+ * The function tracer always reports the address of where the
+ * mcount call was, but the stack will hold the return address.
+ */
+ if (fentry)
+ ip = parent_ip;
+ else
+ ip += MCOUNT_INSN_SIZE;
+
+ check_stack(ip, &stack);
out:
per_cpu(trace_active, cpu)--;
struct dentry *d_tracer;
d_tracer = tracing_init_dentry();
+ if (!d_tracer)
+ return 0;
trace_create_file("stack_max_size", 0644, d_tracer,
&max_stack_size, &stack_max_size_fops);
index 96cffb269e7360e131e445c8c0013c90419f0921..847f88a6194b4e4183e0ed08dd03828f6e5ff1bd 100644 (file)
struct dentry *d_tracing;
d_tracing = tracing_init_dentry();
+ if (!d_tracing)
+ return 0;
stat_dir = debugfs_create_dir("trace_stat", d_tracing);
if (!stat_dir)
index f45e12899c18f58447aabc0234cc150daab2336c..f359dc7fb8c589642ac60ffa2b7c2b583ed7ae9c 100644 (file)
--- a/kernel/user_namespace.c
+++ b/kernel/user_namespace.c
static struct kmem_cache *user_ns_cachep __read_mostly;
-static bool new_idmap_permitted(struct user_namespace *ns, int cap_setid,
+static bool new_idmap_permitted(const struct file *file,
+ struct user_namespace *ns, int cap_setid,
struct uid_gid_map *map);
static void set_cred_user_ns(struct cred *cred, struct user_namespace *user_ns)
if (map->nr_extents != 0)
goto out;
- /* Require the appropriate privilege CAP_SETUID or CAP_SETGID
- * over the user namespace in order to set the id mapping.
+ /*
+ * Adjusting namespace settings requires capabilities on the target.
*/
- if (cap_valid(cap_setid) && !ns_capable(ns, cap_setid))
+ if (cap_valid(cap_setid) && !file_ns_capable(file, ns, CAP_SYS_ADMIN))
goto out;
/* Get a buffer */
ret = -EPERM;
/* Validate the user is allowed to use user id's mapped to. */
- if (!new_idmap_permitted(ns, cap_setid, &new_map))
+ if (!new_idmap_permitted(file, ns, cap_setid, &new_map))
goto out;
/* Map the lower ids from the parent user namespace to the
&ns->projid_map, &ns->parent->projid_map);
}
-static bool new_idmap_permitted(struct user_namespace *ns, int cap_setid,
+static bool new_idmap_permitted(const struct file *file,
+ struct user_namespace *ns, int cap_setid,
struct uid_gid_map *new_map)
{
/* Allow mapping to your own filesystem ids */
u32 id = new_map->extent[0].lower_first;
if (cap_setid == CAP_SETUID) {
kuid_t uid = make_kuid(ns->parent, id);
- if (uid_eq(uid, current_fsuid()))
+ if (uid_eq(uid, file->f_cred->fsuid))
return true;
}
else if (cap_setid == CAP_SETGID) {
kgid_t gid = make_kgid(ns->parent, id);
- if (gid_eq(gid, current_fsgid()))
+ if (gid_eq(gid, file->f_cred->fsgid))
return true;
}
}
/* Allow the specified ids if we have the appropriate capability
* (CAP_SETUID or CAP_SETGID) over the parent user namespace.
+ * And the opener of the id file also had the approprpiate capability.
*/
- if (ns_capable(ns->parent, cap_setid))
+ if (ns_capable(ns->parent, cap_setid) &&
+ file_ns_capable(file, ns->parent, cap_setid))
return true;
return false;
diff --git a/lib/oid_registry.c b/lib/oid_registry.c
index d8de11f45908a88c8856a8adc8a2fb0f26f31671..318f382a010d62f0f6b0c536ee038f41100e57cf 100644 (file)
--- a/lib/oid_registry.c
+++ b/lib/oid_registry.c
* 2 of the Licence, or (at your option) any later version.
*/
+#include <linux/module.h>
#include <linux/export.h>
#include <linux/oid_registry.h>
#include <linux/kernel.h>
#include <linux/bug.h>
#include "oid_registry_data.c"
+MODULE_DESCRIPTION("OID Registry");
+MODULE_AUTHOR("Red Hat, Inc.");
+MODULE_LICENSE("GPL");
+
/**
* look_up_OID - Find an OID registration for the specified data
* @data: Binary representation of the OID
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index d7cec923b3f3b6508eaad49cabf80e4c4937c082..88eb939a9a22a91ce1bf338de84b527bbb610287 100644 (file)
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
break;
}
- if (absent ||
+ /*
+ * We need call hugetlb_fault for both hugepages under migration
+ * (in which case hugetlb_fault waits for the migration,) and
+ * hwpoisoned hugepages (in which case we need to prevent the
+ * caller from accessing to them.) In order to do this, we use
+ * here is_swap_pte instead of is_hugetlb_entry_migration and
+ * is_hugetlb_entry_hwpoisoned. This is because it simply covers
+ * both cases, and because we can't follow correct pages
+ * directly from any kind of swap entries.
+ */
+ if (absent || is_swap_pte(huge_ptep_get(pte)) ||
((flags & FOLL_WRITE) && !pte_write(huge_ptep_get(pte)))) {
int ret;
diff --git a/mm/memory.c b/mm/memory.c
index f8b734a701635c524cab15db13003fea0091bc94..32a495a60cf4f4c2fccb4fdc42b1b0d8deb77d60 100644 (file)
--- a/mm/memory.c
+++ b/mm/memory.c
}
EXPORT_SYMBOL(remap_pfn_range);
+/**
+ * vm_iomap_memory - remap memory to userspace
+ * @vma: user vma to map to
+ * @start: start of area
+ * @len: size of area
+ *
+ * This is a simplified io_remap_pfn_range() for common driver use. The
+ * driver just needs to give us the physical memory range to be mapped,
+ * we'll figure out the rest from the vma information.
+ *
+ * NOTE! Some drivers might want to tweak vma->vm_page_prot first to get
+ * whatever write-combining details or similar.
+ */
+int vm_iomap_memory(struct vm_area_struct *vma, phys_addr_t start, unsigned long len)
+{
+ unsigned long vm_len, pfn, pages;
+
+ /* Check that the physical memory area passed in looks valid */
+ if (start + len < start)
+ return -EINVAL;
+ /*
+ * You *really* shouldn't map things that aren't page-aligned,
+ * but we've historically allowed it because IO memory might
+ * just have smaller alignment.
+ */
+ len += start & ~PAGE_MASK;
+ pfn = start >> PAGE_SHIFT;
+ pages = (len + ~PAGE_MASK) >> PAGE_SHIFT;
+ if (pfn + pages < pfn)
+ return -EINVAL;
+
+ /* We start the mapping 'vm_pgoff' pages into the area */
+ if (vma->vm_pgoff > pages)
+ return -EINVAL;
+ pfn += vma->vm_pgoff;
+ pages -= vma->vm_pgoff;
+
+ /* Can we fit all of the mapping? */
+ vm_len = vma->vm_end - vma->vm_start;
+ if (vm_len >> PAGE_SHIFT > pages)
+ return -EINVAL;
+
+ /* Ok, let it rip */
+ return io_remap_pfn_range(vma, vma->vm_start, pfn, vm_len, vma->vm_page_prot);
+}
+EXPORT_SYMBOL(vm_iomap_memory);
+
static int apply_to_pte_range(struct mm_struct *mm, pmd_t *pmd,
unsigned long addr, unsigned long end,
pte_fn_t fn, void *data)
diff --git a/mm/mmap.c b/mm/mmap.c
index 32f337296e002ec1d3cd5da46710788f1627adeb..e6beac4805a410fe041b5d26513ee12b6c476aa5 100644 (file)
--- a/mm/mmap.c
+++ b/mm/mmap.c
file = fget(fd);
if (!file)
goto out;
+ if (is_file_hugepages(file))
+ len = ALIGN(len, huge_page_size(hstate_file(file)));
} else if (flags & MAP_HUGETLB) {
struct user_struct *user = NULL;
+
+ len = ALIGN(len, huge_page_size(hstate_sizelog(
+ (flags >> MAP_HUGE_SHIFT) & MAP_HUGE_MASK)));
/*
* VM_NORESERVE is used because the reservations will be
* taken when vm_ops->mmap() is called
* A dummy user value is used because we are not locking
* memory so no accounting is necessary
*/
- file = hugetlb_file_setup(HUGETLB_ANON_FILE, addr, len,
+ file = hugetlb_file_setup(HUGETLB_ANON_FILE, len,
VM_NORESERVE,
&user, HUGETLB_ANONHUGE_INODE,
(flags >> MAP_HUGE_SHIFT) & MAP_HUGE_MASK);
diff --git a/mm/page_io.c b/mm/page_io.c
index 78eee32ee4860b17155413bb37c211bbd8b9b60a..61828703c4a2c412d10d36a84a7581ccb4aa45c8 100644 (file)
--- a/mm/page_io.c
+++ b/mm/page_io.c
kiocb.ki_left = PAGE_SIZE;
kiocb.ki_nbytes = PAGE_SIZE;
+ set_page_writeback(page);
unlock_page(page);
ret = mapping->a_ops->direct_IO(KERNEL_WRITE,
&kiocb, &iov,
if (ret == PAGE_SIZE) {
count_vm_event(PSWPOUT);
ret = 0;
+ } else {
+ /*
+ * In the case of swap-over-nfs, this can be a
+ * temporary failure if the system has limited
+ * memory for allocating transmit buffers.
+ * Mark the page dirty and avoid
+ * rotate_reclaimable_page but rate-limit the
+ * messages but do not flag PageError like
+ * the normal direct-to-bio case as it could
+ * be temporary.
+ */
+ set_page_dirty(page);
+ ClearPageReclaim(page);
+ pr_err_ratelimited("Write error on dio swapfile (%Lu)\n",
+ page_file_offset(page));
}
+ end_page_writeback(page);
return ret;
}
diff --git a/net/atm/common.c b/net/atm/common.c
index 806fc0a400514b677ca1d74abf1c55a055097822..cf4b7e667a6e497a0d5d748eed8c8ccabc9bd667 100644 (file)
--- a/net/atm/common.c
+++ b/net/atm/common.c
struct sk_buff *skb;
int copied, error = -EINVAL;
+ msg->msg_namelen = 0;
+
if (sock->state != SS_CONNECTED)
return -ENOTCONN;
diff --git a/net/ax25/af_ax25.c b/net/ax25/af_ax25.c
index 779095ded689918de025f48c47db880aa9b5d724..d53a123e36a04e13d7560941c8a6016637de60d6 100644 (file)
--- a/net/ax25/af_ax25.c
+++ b/net/ax25/af_ax25.c
ax25_address src;
const unsigned char *mac = skb_mac_header(skb);
+ memset(sax, 0, sizeof(struct full_sockaddr_ax25));
ax25_addr_parse(mac + 1, skb->data - mac - 1, &src, NULL,
&digi, NULL, NULL);
sax->sax25_family = AF_AX25;
index 49a708557276ce3dbebe86b32f64e9f7898dfa44..342efaef95de8f5ae37ff17a22dacd92eb411dac 100644 (file)
if (flags & (MSG_OOB))
return -EOPNOTSUPP;
+ msg->msg_namelen = 0;
+
skb = skb_recv_datagram(sk, flags, noblock, &err);
if (!skb) {
if (sk->sk_shutdown & RCV_SHUTDOWN)
return err;
}
- msg->msg_namelen = 0;
-
copied = skb->len;
if (len < copied) {
msg->msg_flags |= MSG_TRUNC;
index ce3f6658f4b284f627325021d59920262f8a7afc..970fc13d8e399e271a0228dec0be9c457a6d6336 100644 (file)
if (test_and_clear_bit(RFCOMM_DEFER_SETUP, &d->flags)) {
rfcomm_dlc_accept(d);
+ msg->msg_namelen = 0;
return 0;
}
diff --git a/net/bluetooth/sco.c b/net/bluetooth/sco.c
index f54d743581977dd0006d218057b1a15993257a63..2ea5b06cb794abba9410123eaccd82178a5be094 100644 (file)
--- a/net/bluetooth/sco.c
+++ b/net/bluetooth/sco.c
test_bit(BT_SK_DEFER_SETUP, &bt_sk(sk)->flags)) {
hci_conn_accept(pi->conn->hcon, 0);
sk->sk_state = BT_CONFIG;
+ msg->msg_namelen = 0;
release_sock(sk);
return 0;
diff --git a/net/caif/caif_socket.c b/net/caif/caif_socket.c
index 095259f839023a99a2127d1d4173bb29737471df..ff2ff3ce6965a73dcf74918cd5c5bcc1b4a7d51b 100644 (file)
--- a/net/caif/caif_socket.c
+++ b/net/caif/caif_socket.c
if (m->msg_flags&MSG_OOB)
goto read_error;
+ m->msg_namelen = 0;
+
skb = skb_recv_datagram(sk, flags, 0 , &ret);
if (!skb)
goto read_error;
diff --git a/net/core/dev.c b/net/core/dev.c
index 5d9c43dca7308b3907ce60cc1bfcd1faba0a2220..d592214b1393bec9031c572cb29cb7c17bc86ca4 100644 (file)
--- a/net/core/dev.c
+++ b/net/core/dev.c
skb->mark = 0;
secpath_reset(skb);
nf_reset(skb);
+ nf_reset_trace(skb);
return netif_rx(skb);
}
EXPORT_SYMBOL_GPL(dev_forward_skb);
struct net_device *dev = skb->dev;
const char *driver = "";
+ if (!net_ratelimit())
+ return;
+
if (dev && dev->dev.parent)
driver = dev_driver_string(dev->dev.parent);
index b079c7bbc157a3c047db12e7a39595da380071e8..7841d87b86f8f9e668125405dc049b5fa663a897 100644 (file)
ha->type = addr_type;
ha->refcount = 1;
ha->global_use = global;
- ha->synced = false;
+ ha->synced = 0;
list_add_tail_rcu(&ha->list, &list->list);
list->count++;
addr_len, ha->type);
if (err)
break;
- ha->synced = true;
+ ha->synced++;
ha->refcount++;
} else if (ha->refcount == 1) {
__hw_addr_del(to_list, ha->addr, addr_len, ha->type);
if (ha->synced) {
__hw_addr_del(to_list, ha->addr,
addr_len, ha->type);
- ha->synced = false;
+ ha->synced--;
__hw_addr_del(from_list, ha->addr,
addr_len, ha->type);
}
diff --git a/net/core/rtnetlink.c b/net/core/rtnetlink.c
index 6212ec9c2df74d902d011a56c603a0d4f9bd3c26..055fb130de1de6a1a7bef39e398b4792e5674869 100644 (file)
--- a/net/core/rtnetlink.c
+++ b/net/core/rtnetlink.c
rcu_read_lock();
cb->seq = net->dev_base_seq;
- if (nlmsg_parse(cb->nlh, sizeof(struct rtgenmsg), tb, IFLA_MAX,
+ if (nlmsg_parse(cb->nlh, sizeof(struct ifinfomsg), tb, IFLA_MAX,
ifla_policy) >= 0) {
if (tb[IFLA_EXT_MASK])
u32 ext_filter_mask = 0;
u16 min_ifinfo_dump_size = 0;
- if (nlmsg_parse(nlh, sizeof(struct rtgenmsg), tb, IFLA_MAX,
+ if (nlmsg_parse(nlh, sizeof(struct ifinfomsg), tb, IFLA_MAX,
ifla_policy) >= 0) {
if (tb[IFLA_EXT_MASK])
ext_filter_mask = nla_get_u32(tb[IFLA_EXT_MASK]);
diff --git a/net/ipv4/esp4.c b/net/ipv4/esp4.c
index 3b4f0cd2e63edbd136683577873b288712a4b92a..4cfe34d4cc967a94ed15f2deef3d249d2429e846 100644 (file)
--- a/net/ipv4/esp4.c
+++ b/net/ipv4/esp4.c
/* skb is pure payload to encrypt */
- err = -ENOMEM;
-
esp = x->data;
aead = esp->aead;
alen = crypto_aead_authsize(aead);
}
tmp = esp_alloc_tmp(aead, nfrags + sglists, seqhilen);
- if (!tmp)
+ if (!tmp) {
+ err = -ENOMEM;
goto error;
+ }
seqhi = esp_tmp_seqhi(tmp);
iv = esp_tmp_iv(aead, tmp, seqhilen);
diff --git a/net/ipv4/ip_fragment.c b/net/ipv4/ip_fragment.c
index a8fc332d07f7e33255728ef7d112d1b3610d164c..0fcfee37227edac26a8a18132bbf3132c07bb685 100644 (file)
--- a/net/ipv4/ip_fragment.c
+++ b/net/ipv4/ip_fragment.c
if (!head->dev)
goto out_rcu_unlock;
- /* skb dst is stale, drop it, and perform route lookup again */
- skb_dst_drop(head);
+ /* skb has no dst, perform route lookup again */
iph = ip_hdr(head);
err = ip_route_input_noref(head, iph->daddr, iph->saddr,
iph->tos, head->dev);
qp->q.max_size = skb->len + ihl;
if (qp->q.last_in == (INET_FRAG_FIRST_IN | INET_FRAG_LAST_IN) &&
- qp->q.meat == qp->q.len)
- return ip_frag_reasm(qp, prev, dev);
+ qp->q.meat == qp->q.len) {
+ unsigned long orefdst = skb->_skb_refdst;
+
+ skb->_skb_refdst = 0UL;
+ err = ip_frag_reasm(qp, prev, dev);
+ skb->_skb_refdst = orefdst;
+ return err;
+ }
+
+ skb_dst_drop(skb);
write_lock(&ip4_frags.lock);
list_move_tail(&qp->q.lru_list, &qp->q.net->lru_list);
index c30130062cd6515f31d7497eaa6a403d2b1d629d..c49dcd0284a06c6bb4b4e6787af5888289ba50f3 100644 (file)
return dev_match;
}
+static bool rpfilter_is_local(const struct sk_buff *skb)
+{
+ const struct rtable *rt = skb_rtable(skb);
+ return rt && (rt->rt_flags & RTCF_LOCAL);
+}
+
static bool rpfilter_mt(const struct sk_buff *skb, struct xt_action_param *par)
{
const struct xt_rpfilter_info *info;
info = par->matchinfo;
invert = info->flags & XT_RPFILTER_INVERT;
- if (par->in->flags & IFF_LOOPBACK)
+ if (rpfilter_is_local(skb))
return true ^ invert;
iph = ip_hdr(skb);
diff --git a/net/ipv4/syncookies.c b/net/ipv4/syncookies.c
index b236ef04914f99585455269fe2c9a18241088461..f962f19dabe22e2cdac27bd255eaaa7e5956d7f3 100644 (file)
--- a/net/ipv4/syncookies.c
+++ b/net/ipv4/syncookies.c
* hasn't changed since we received the original syn, but I see
* no easy way to do this.
*/
- flowi4_init_output(&fl4, 0, sk->sk_mark, RT_CONN_FLAGS(sk),
- RT_SCOPE_UNIVERSE, IPPROTO_TCP,
+ flowi4_init_output(&fl4, sk->sk_bound_dev_if, sk->sk_mark,
+ RT_CONN_FLAGS(sk), RT_SCOPE_UNIVERSE, IPPROTO_TCP,
inet_sk_flowi_flags(sk),
(opt && opt->srr) ? opt->faddr : ireq->rmt_addr,
ireq->loc_addr, th->source, th->dest);
diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c
index 9841a716370ad03abf3c91452ab09a4b3529f871..b4e8b797a09b4c13cfa2f9a0af88dbdb549707af 100644 (file)
--- a/net/ipv4/tcp_input.c
+++ b/net/ipv4/tcp_input.c
#define FLAG_DSACKING_ACK 0x800 /* SACK blocks contained D-SACK info */
#define FLAG_NONHEAD_RETRANS_ACKED 0x1000 /* Non-head rexmitted data was ACKed */
#define FLAG_SACK_RENEGING 0x2000 /* snd_una advanced to a sacked seq */
+#define FLAG_UPDATE_TS_RECENT 0x4000 /* tcp_replace_ts_recent() */
#define FLAG_ACKED (FLAG_DATA_ACKED|FLAG_SYN_ACKED)
#define FLAG_NOT_DUP (FLAG_DATA|FLAG_WIN_UPDATE|FLAG_ACKED)
}
}
+static void tcp_store_ts_recent(struct tcp_sock *tp)
+{
+ tp->rx_opt.ts_recent = tp->rx_opt.rcv_tsval;
+ tp->rx_opt.ts_recent_stamp = get_seconds();
+}
+
+static void tcp_replace_ts_recent(struct tcp_sock *tp, u32 seq)
+{
+ if (tp->rx_opt.saw_tstamp && !after(seq, tp->rcv_wup)) {
+ /* PAWS bug workaround wrt. ACK frames, the PAWS discard
+ * extra check below makes sure this can only happen
+ * for pure ACK frames. -DaveM
+ *
+ * Not only, also it occurs for expired timestamps.
+ */
+
+ if (tcp_paws_check(&tp->rx_opt, 0))
+ tcp_store_ts_recent(tp);
+ }
+}
+
/* This routine deals with incoming acks, but not outgoing ones. */
static int tcp_ack(struct sock *sk, const struct sk_buff *skb, int flag)
{
prior_fackets = tp->fackets_out;
prior_in_flight = tcp_packets_in_flight(tp);
+ /* ts_recent update must be made after we are sure that the packet
+ * is in window.
+ */
+ if (flag & FLAG_UPDATE_TS_RECENT)
+ tcp_replace_ts_recent(tp, TCP_SKB_CB(skb)->seq);
+
if (!(flag & FLAG_SLOWPATH) && after(ack, prior_snd_una)) {
/* Window is constant, pure forward advance.
* No more checks are required.
EXPORT_SYMBOL(tcp_parse_md5sig_option);
#endif
-static inline void tcp_store_ts_recent(struct tcp_sock *tp)
-{
- tp->rx_opt.ts_recent = tp->rx_opt.rcv_tsval;
- tp->rx_opt.ts_recent_stamp = get_seconds();
-}
-
-static inline void tcp_replace_ts_recent(struct tcp_sock *tp, u32 seq)
-{
- if (tp->rx_opt.saw_tstamp && !after(seq, tp->rcv_wup)) {
- /* PAWS bug workaround wrt. ACK frames, the PAWS discard
- * extra check below makes sure this can only happen
- * for pure ACK frames. -DaveM
- *
- * Not only, also it occurs for expired timestamps.
- */
-
- if (tcp_paws_check(&tp->rx_opt, 0))
- tcp_store_ts_recent(tp);
- }
-}
-
/* Sorry, PAWS as specified is broken wrt. pure-ACKs -DaveM
*
* It is not fatal. If this ACK does _not_ change critical state (seqs, window)
return 0;
step5:
- if (tcp_ack(sk, skb, FLAG_SLOWPATH) < 0)
+ if (tcp_ack(sk, skb, FLAG_SLOWPATH | FLAG_UPDATE_TS_RECENT) < 0)
goto discard;
- /* ts_recent update must be made after we are sure that the packet
- * is in window.
- */
- tcp_replace_ts_recent(tp, TCP_SKB_CB(skb)->seq);
-
tcp_rcv_rtt_measure_ts(sk, skb);
/* Process urgent data. */
/* step 5: check the ACK field */
if (true) {
- int acceptable = tcp_ack(sk, skb, FLAG_SLOWPATH) > 0;
+ int acceptable = tcp_ack(sk, skb, FLAG_SLOWPATH |
+ FLAG_UPDATE_TS_RECENT) > 0;
switch (sk->sk_state) {
case TCP_SYN_RECV:
}
}
- /* ts_recent update must be made after we are sure that the packet
- * is in window.
- */
- tcp_replace_ts_recent(tp, TCP_SKB_CB(skb)->seq);
-
/* step 6: check the URG bit */
tcp_urg(sk, skb, th);
diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
index 17d659e6fb692c8048933665fceb078490416064..a9f50ee49e52e9ad4e78663933aefaecaefe2162 100644 (file)
--- a/net/ipv4/tcp_output.c
+++ b/net/ipv4/tcp_output.c
*/
TCP_SKB_CB(skb)->when = tcp_time_stamp;
- /* make sure skb->data is aligned on arches that require it */
- if (unlikely(NET_IP_ALIGN && ((unsigned long)skb->data & 3))) {
+ /* make sure skb->data is aligned on arches that require it
+ * and check if ack-trimming & collapsing extended the headroom
+ * beyond what csum_start can cover.
+ */
+ if (unlikely((NET_IP_ALIGN && ((unsigned long)skb->data & 3)) ||
+ skb_headroom(skb) >= 0xFFFF)) {
struct sk_buff *nskb = __pskb_copy(skb, MAX_TCP_HEADER,
GFP_ATOMIC);
return nskb ? tcp_transmit_skb(sk, nskb, 0, GFP_ATOMIC) :
diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
index a36d17e4008022b5eb6eca9b7c158dd4392e101d..e8676c21a9b61a47efe8c26e89c41a5a2fd39dd5 100644 (file)
--- a/net/ipv6/addrconf.c
+++ b/net/ipv6/addrconf.c
static void init_loopback(struct net_device *dev)
{
struct inet6_dev *idev;
+ struct net_device *sp_dev;
+ struct inet6_ifaddr *sp_ifa;
+ struct rt6_info *sp_rt;
/* ::1 */
}
add_addr(idev, &in6addr_loopback, 128, IFA_HOST);
+
+ /* Add routes to other interface's IPv6 addresses */
+ for_each_netdev(dev_net(dev), sp_dev) {
+ if (!strcmp(sp_dev->name, dev->name))
+ continue;
+
+ idev = __in6_dev_get(sp_dev);
+ if (!idev)
+ continue;
+
+ read_lock_bh(&idev->lock);
+ list_for_each_entry(sp_ifa, &idev->addr_list, if_list) {
+
+ if (sp_ifa->flags & (IFA_F_DADFAILED | IFA_F_TENTATIVE))
+ continue;
+
+ sp_rt = addrconf_dst_alloc(idev, &sp_ifa->addr, 0);
+
+ /* Failure cases are ignored */
+ if (!IS_ERR(sp_rt))
+ ip6_ins_rt(sp_rt);
+ }
+ read_unlock_bh(&idev->lock);
+ }
}
static void addrconf_add_linklocal(struct inet6_dev *idev, const struct in6_addr *addr)
index 83acc1405a18dcef218625e8517431978393ac12..0ea43c7024d5cf9beac5e44b90c06c3fe82b197d 100644 (file)
if (pfx_len - i >= 32)
mask = 0;
else
- mask = htonl(~((1 << (pfx_len - i)) - 1));
+ mask = htonl((1 << (i - pfx_len + 32)) - 1);
idx = i / 32;
addr->s6_addr32[idx] &= mask;
index 5060d54199abbc180d7dc87ba072bace2bc167f7..e0983f3648a628410c6f6bfd9549ec339a325353 100644 (file)
return ret;
}
+static bool rpfilter_is_local(const struct sk_buff *skb)
+{
+ const struct rt6_info *rt = (const void *) skb_dst(skb);
+ return rt && (rt->rt6i_flags & RTF_LOCAL);
+}
+
static bool rpfilter_mt(const struct sk_buff *skb, struct xt_action_param *par)
{
const struct xt_rpfilter_info *info = par->matchinfo;
struct ipv6hdr *iph;
bool invert = info->flags & XT_RPFILTER_INVERT;
- if (par->in->flags & IFF_LOOPBACK)
+ if (rpfilter_is_local(skb))
return true ^ invert;
iph = ipv6_hdr(skb);
diff --git a/net/ipv6/reassembly.c b/net/ipv6/reassembly.c
index d9ba8a27fde329a4dc6176ae8b6536a598c12e43..7a610a673638e62b813f344a81c9bf86563b5387 100644 (file)
--- a/net/ipv6/reassembly.c
+++ b/net/ipv6/reassembly.c
}
if (fq->q.last_in == (INET_FRAG_FIRST_IN | INET_FRAG_LAST_IN) &&
- fq->q.meat == fq->q.len)
- return ip6_frag_reasm(fq, prev, dev);
+ fq->q.meat == fq->q.len) {
+ int res;
+ unsigned long orefdst = skb->_skb_refdst;
+
+ skb->_skb_refdst = 0UL;
+ res = ip6_frag_reasm(fq, prev, dev);
+ skb->_skb_refdst = orefdst;
+ return res;
+ }
+
+ skb_dst_drop(skb);
write_lock(&ip6_frags.lock);
list_move_tail(&fq->q.lru_list, &fq->q.net->lru_list);
diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c
index 8d19346b7a31e66b70e12c98db406c23573d6e8b..89dfeddb026922d02ae1c382d4e9b3413d2ce5dc 100644 (file)
--- a/net/ipv6/tcp_ipv6.c
+++ b/net/ipv6/tcp_ipv6.c
if (dst)
dst->ops->redirect(dst, sk, skb);
+ goto out;
}
if (type == ICMPV6_PKT_TOOBIG) {
diff --git a/net/irda/af_irda.c b/net/irda/af_irda.c
index 4d04105a3f06b8ac65e55e4e9a44b39026736619..3c9bd5949d7afbdc0238e2d49d0c696655d126a6 100644 (file)
--- a/net/irda/af_irda.c
+++ b/net/irda/af_irda.c
IRDA_DEBUG(4, "%s()\n", __func__);
+ msg->msg_namelen = 0;
+
skb = skb_recv_datagram(sk, flags & ~MSG_DONTWAIT,
flags & MSG_DONTWAIT, &err);
if (!skb)
diff --git a/net/iucv/af_iucv.c b/net/iucv/af_iucv.c
index cd6f7a991d8035bdfc6d883a8bcf21a433405030..625bc50391ccf7aa75fb4f424ec18cf800b7dd93 100644 (file)
--- a/net/iucv/af_iucv.c
+++ b/net/iucv/af_iucv.c
struct sk_buff *skb, *rskb, *cskb;
int err = 0;
+ msg->msg_namelen = 0;
+
if ((sk->sk_state == IUCV_DISCONN) &&
skb_queue_empty(&iucv->backlog_skb_q) &&
skb_queue_empty(&sk->sk_receive_queue) &&
diff --git a/net/l2tp/l2tp_ip6.c b/net/l2tp/l2tp_ip6.c
index 8ee4a86ae996ca624e06a1422e4e07a2e957c584..9e1822e811367700d950f991ead479c841897b08 100644 (file)
--- a/net/l2tp/l2tp_ip6.c
+++ b/net/l2tp/l2tp_ip6.c
lsa->l2tp_addr = ipv6_hdr(skb)->saddr;
lsa->l2tp_flowinfo = 0;
lsa->l2tp_scope_id = 0;
+ lsa->l2tp_conn_id = 0;
if (ipv6_addr_type(&lsa->l2tp_addr) & IPV6_ADDR_LINKLOCAL)
lsa->l2tp_scope_id = IP6CB(skb)->iif;
}
diff --git a/net/llc/af_llc.c b/net/llc/af_llc.c
index 88709882c4641f7d147fbeaa9f48323cfc8637eb..48aaa89253e037c9b7f2e07f3bc1d03d837266fd 100644 (file)
--- a/net/llc/af_llc.c
+++ b/net/llc/af_llc.c
int target; /* Read at least this many bytes */
long timeo;
+ msg->msg_namelen = 0;
+
lock_sock(sk);
copied = -ENOTCONN;
if (unlikely(sk->sk_type == SOCK_STREAM && sk->sk_state == TCP_LISTEN))
diff --git a/net/mac80211/mlme.c b/net/mac80211/mlme.c
index 2c6e4788dde3a7b6892b957219edaa3d1445b836..cbce371c23d8a4a995481b6eca518933ea55f1d8 100644 (file)
--- a/net/mac80211/mlme.c
+++ b/net/mac80211/mlme.c
/* prep auth_data so we don't go into idle on disassoc */
ifmgd->auth_data = auth_data;
- if (ifmgd->associated)
- ieee80211_set_disassoc(sdata, 0, 0, false, NULL);
+ if (ifmgd->associated) {
+ u8 frame_buf[IEEE80211_DEAUTH_FRAME_LEN];
+
+ ieee80211_set_disassoc(sdata, IEEE80211_STYPE_DEAUTH,
+ WLAN_REASON_UNSPECIFIED,
+ false, frame_buf);
+
+ __cfg80211_send_deauth(sdata->dev, frame_buf,
+ sizeof(frame_buf));
+ }
sdata_info(sdata, "authenticate with %pM\n", req->bss->bssid);
mutex_lock(&ifmgd->mtx);
- if (ifmgd->associated)
- ieee80211_set_disassoc(sdata, 0, 0, false, NULL);
+ if (ifmgd->associated) {
+ u8 frame_buf[IEEE80211_DEAUTH_FRAME_LEN];
+
+ ieee80211_set_disassoc(sdata, IEEE80211_STYPE_DEAUTH,
+ WLAN_REASON_UNSPECIFIED,
+ false, frame_buf);
+
+ __cfg80211_send_deauth(sdata->dev, frame_buf,
+ sizeof(frame_buf));
+ }
if (ifmgd->auth_data && !ifmgd->auth_data->done) {
err = -EBUSY;
diff --git a/net/mac80211/pm.c b/net/mac80211/pm.c
index e45b83610e850fdf8df47f9f2774686665a13f8d..a179bf8d1ea698074fef91a0cff76683bd3747bc 100644 (file)
--- a/net/mac80211/pm.c
+++ b/net/mac80211/pm.c
ieee80211_stop_queues_by_reason(hw,
IEEE80211_QUEUE_STOP_REASON_SUSPEND);
- /* flush out all packets */
- synchronize_net();
+ /* flush out all packets and station cleanup call_rcu()s */
+ rcu_barrier();
drv_flush(local, false);
index 6d6d8f2b033e0505f88648b9646d3963d3aa10e0..38ca630eeeb8afa7c45e7d78d743ffbe16e8ce85 100644 (file)
if (ret == -EAGAIN)
ret = 1;
- return ret < 0 ? ret : ret > 0 ? 0 : -IPSET_ERR_EXIST;
+ return (ret < 0 && ret != -ENOTEMPTY) ? ret :
+ ret > 0 ? 0 : -IPSET_ERR_EXIST;
}
/* Get headed data of a set */
index 8371c2bac2e4240eb5c4b3f6abd0faa48f6212ce..09c744aa89829cb7f99878974ef2471364135f27 100644 (file)
{
const struct set_elem *e = list_set_elem(map, i);
- if (i == map->size - 1 && e->id != IPSET_INVALID_ID)
- /* Last element replaced: e.g. add new,before,last */
- ip_set_put_byindex(e->id);
+ if (e->id != IPSET_INVALID_ID) {
+ const struct set_elem *x = list_set_elem(map, map->size - 1);
+
+ /* Last element replaced or pushed off */
+ if (x->id != IPSET_INVALID_ID)
+ ip_set_put_byindex(x->id);
+ }
if (with_timeout(map->timeout))
list_elem_tadd(map, i, id, ip_set_timeout_set(timeout));
else
index 12475ef88dafe571bbc2e031af50890c08d91a54..e5920fb7ad01ac0d0927f6d7e1daffe85e597856 100644 (file)
if (ret > 0)
break;
if (!ret)
- return 0;
+ return -EINVAL;
dataoff += *matchoff;
}
- /* Empty callid is useless */
- if (!*matchlen)
- return -EINVAL;
-
/* Too large is useless */
if (*matchlen > IP_VS_PEDATA_MAXLEN)
return -EINVAL;
index 884f2b39319a258ffbaa4360736fd7f83b867195..91527d5ba018c568318b008380e81f18f6fd978e 100644 (file)
/* We only allow helper re-assignment of the same sort since
* we cannot reallocate the helper extension area.
*/
- if (help->helper != helper) {
+ struct nf_conntrack_helper *tmp = rcu_dereference(help->helper);
+
+ if (tmp && tmp->help != helper->help) {
RCU_INIT_POINTER(help->helper, NULL);
goto out;
}
index 627b0e50b2389120e86ed107a3af01d690e07a29..a081915e0531879fe013176b26c4bfa096115143 100644 (file)
if (nlh->nlmsg_flags & NLM_F_CREATE) {
enum ip_conntrack_events events;
+ if (!cda[CTA_TUPLE_ORIG] || !cda[CTA_TUPLE_REPLY])
+ return -EINVAL;
+
ct = ctnetlink_create_conntrack(net, zone, cda, &otuple,
&rtuple, u3);
if (IS_ERR(ct))
index df8f4f284481042800b3da96ab41bf3589ef512e..b4e0d1c23cd3231aa024655ea4c3e0367dc7436a 100644 (file)
msglen = origlen = end - dptr;
if (msglen > datalen)
- return NF_DROP;
+ return NF_ACCEPT;
ret = process_sip_msg(skb, ct, protoff, dataoff,
&dptr, &msglen);
index 5f2f9109f4615e3dc1fa510c5136d10bfa20fba8..4bc2aafcd4175bc131f4e2eb3c6ad5c97801dd35 100644 (file)
struct nf_nat_proto_clean {
u8 l3proto;
u8 l4proto;
- bool hash;
};
-/* Clear NAT section of all conntracks, in case we're loaded again. */
-static int nf_nat_proto_clean(struct nf_conn *i, void *data)
+/* kill conntracks with affected NAT section */
+static int nf_nat_proto_remove(struct nf_conn *i, void *data)
{
const struct nf_nat_proto_clean *clean = data;
struct nf_conn_nat *nat = nfct_nat(i);
if (!nat)
return 0;
- if (!(i->status & IPS_SRC_NAT_DONE))
- return 0;
+
if ((clean->l3proto && nf_ct_l3num(i) != clean->l3proto) ||
(clean->l4proto && nf_ct_protonum(i) != clean->l4proto))
return 0;
- if (clean->hash) {
- spin_lock_bh(&nf_nat_lock);
- hlist_del_rcu(&nat->bysource);
- spin_unlock_bh(&nf_nat_lock);
- } else {
- memset(nat, 0, sizeof(*nat));
- i->status &= ~(IPS_NAT_MASK | IPS_NAT_DONE_MASK |
- IPS_SEQ_ADJUST);
- }
- return 0;
+ return i->status & IPS_NAT_MASK ? 1 : 0;
}
static void nf_nat_l4proto_clean(u8 l3proto, u8 l4proto)
struct net *net;
rtnl_lock();
- /* Step 1 - remove from bysource hash */
- clean.hash = true;
for_each_net(net)
- nf_ct_iterate_cleanup(net, nf_nat_proto_clean, &clean);
- synchronize_rcu();
-
- /* Step 2 - clean NAT section */
- clean.hash = false;
- for_each_net(net)
- nf_ct_iterate_cleanup(net, nf_nat_proto_clean, &clean);
+ nf_ct_iterate_cleanup(net, nf_nat_proto_remove, &clean);
rtnl_unlock();
}
struct net *net;
rtnl_lock();
- /* Step 1 - remove from bysource hash */
- clean.hash = true;
- for_each_net(net)
- nf_ct_iterate_cleanup(net, nf_nat_proto_clean, &clean);
- synchronize_rcu();
- /* Step 2 - clean NAT section */
- clean.hash = false;
for_each_net(net)
- nf_ct_iterate_cleanup(net, nf_nat_proto_clean, &clean);
+ nf_ct_iterate_cleanup(net, nf_nat_proto_remove, &clean);
rtnl_unlock();
}
{
struct nf_nat_proto_clean clean = {};
- nf_ct_iterate_cleanup(net, &nf_nat_proto_clean, &clean);
+ nf_ct_iterate_cleanup(net, &nf_nat_proto_remove, &clean);
synchronize_rcu();
nf_ct_free_hashtable(net->ct.nat_bysource, net->ct.nat_htable_size);
}
diff --git a/net/netrom/af_netrom.c b/net/netrom/af_netrom.c
index 7261eb81974ff9f3761976372c9272db04a62abd..14c106b49e990e89d81083177a72cdc2029dd06a 100644 (file)
--- a/net/netrom/af_netrom.c
+++ b/net/netrom/af_netrom.c
}
if (sax != NULL) {
+ memset(sax, 0, sizeof(sax));
sax->sax25_family = AF_NETROM;
skb_copy_from_linear_data_offset(skb, 7, sax->sax25_call.ax25_call,
AX25_ADDR_LEN);
diff --git a/net/nfc/llcp/sock.c b/net/nfc/llcp/sock.c
index 5332751943a9ec564befadda63a5a3749d7434c1..411c25bda0b4c40b708588c139efdb2a81517825 100644 (file)
--- a/net/nfc/llcp/sock.c
+++ b/net/nfc/llcp/sock.c
pr_debug("%p %zu\n", sk, len);
+ msg->msg_namelen = 0;
+
lock_sock(sk);
if (sk->sk_state == LLCP_CLOSED &&
diff --git a/net/rose/af_rose.c b/net/rose/af_rose.c
index c4719ce604c28040b1cfdc9bff0f3a9ee4d2200d..7f645d115795e87dfd493527ee4814e23250d5d0 100644 (file)
--- a/net/rose/af_rose.c
+++ b/net/rose/af_rose.c
skb_copy_datagram_iovec(skb, 0, msg->msg_iov, copied);
if (srose != NULL) {
+ memset(srose, 0, msg->msg_namelen);
srose->srose_family = AF_ROSE;
srose->srose_addr = rose->dest_addr;
srose->srose_call = rose->dest_call;
diff --git a/net/sched/sch_cbq.c b/net/sched/sch_cbq.c
index 0e19948470b88ce8dff6c3e1cded52a6121fe7ea..ced81a1583e29b651eee841543b9b5d1ed7d7ad6 100644 (file)
--- a/net/sched/sch_cbq.c
+++ b/net/sched/sch_cbq.c
cbq_update(q);
if ((incr -= incr2) < 0)
incr = 0;
+ q->now += incr;
+ } else {
+ if (now > q->now)
+ q->now = now;
}
- q->now += incr;
q->now_rt = now;
for (;;) {
diff --git a/net/tipc/socket.c b/net/tipc/socket.c
index 9b4e4833a484f959a891d5022ff468c671f38239..fc906d9391b7b06949a5a7f624236a80fd27cf99 100644 (file)
--- a/net/tipc/socket.c
+++ b/net/tipc/socket.c
if (addr) {
addr->family = AF_TIPC;
addr->addrtype = TIPC_ADDR_ID;
+ memset(&addr->addr, 0, sizeof(addr->addr));
addr->addr.id.ref = msg_origport(msg);
addr->addr.id.node = msg_orignode(msg);
addr->addr.name.domain = 0; /* could leave uninitialized */
goto exit;
}
+ /* will be updated in set_orig_addr() if needed */
+ m->msg_namelen = 0;
+
timeout = sock_rcvtimeo(sk, flags & MSG_DONTWAIT);
restart:
goto exit;
}
+ /* will be updated in set_orig_addr() if needed */
+ m->msg_namelen = 0;
+
target = sock_rcvlowat(sk, flags & MSG_WAITALL, buf_len);
timeout = sock_rcvtimeo(sk, flags & MSG_DONTWAIT);
diff --git a/net/unix/af_unix.c b/net/unix/af_unix.c
index b45eb6553ee73fab140c34e0772368171e9915f1..f347754e46250c46d514d4081e0d41adff75b4d3 100644 (file)
--- a/net/unix/af_unix.c
+++ b/net/unix/af_unix.c
if ((UNIXCB(skb).pid != siocb->scm->pid) ||
(UNIXCB(skb).cred != siocb->scm->cred))
break;
- } else {
+ } else if (test_bit(SOCK_PASSCRED, &sock->flags)) {
/* Copy credentials */
scm_set_cred(siocb->scm, UNIXCB(skb).pid, UNIXCB(skb).cred);
check_creds = 1;
diff --git a/net/wireless/reg.c b/net/wireless/reg.c
index de02d633c212eb6ea516a7d87e05978a2a1b3ba9..ecf566389961066f621effc71e3f96d5a3030404 100644 (file)
--- a/net/wireless/reg.c
+++ b/net/wireless/reg.c
return;
REG_DBG_PRINT("Disabling freq %d MHz\n", chan->center_freq);
- chan->flags = IEEE80211_CHAN_DISABLED;
+ chan->flags |= IEEE80211_CHAN_DISABLED;
return;
}
index 33689396953a7e46d5152df204ddb802ec4b2a39..68b85e1fe8f78d6da4513134e0250511ad7b0db8 100644 (file)
my $state = "NONE";
my $config;
- my @kconfigs;
my $cont = 0;
my $line;
# collect any Kconfig sources
if (/^source\s*"(.*)"/) {
- $kconfigs[$#kconfigs+1] = $1;
+ my $kconfig = $1;
+ # prevent reading twice.
+ if (!defined($read_kconfigs{$kconfig})) {
+ $read_kconfigs{$kconfig} = 1;
+ read_kconfig($kconfig);
+ }
+ next;
}
# configs found
}
}
close($kinfile);
-
- # read in any configs that were found.
- foreach my $kconfig (@kconfigs) {
- if (!defined($read_kconfigs{$kconfig})) {
- $read_kconfigs{$kconfig} = 1;
- read_kconfig($kconfig);
- }
- }
}
if ($kconfig) {
index 0a305e41ad203a6aee672cb42133b575d8c979e0..3c3c1c41c52623a5015fadb70153021ef3c98466 100644 (file)
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
int snd_pcm_lib_mmap_iomem(struct snd_pcm_substream *substream,
struct vm_area_struct *area)
{
- long size;
- unsigned long offset;
+ struct snd_pcm_runtime *runtime = substream->runtime;;
area->vm_page_prot = pgprot_noncached(area->vm_page_prot);
- area->vm_flags |= VM_IO;
- size = area->vm_end - area->vm_start;
- offset = area->vm_pgoff << PAGE_SHIFT;
- if (io_remap_pfn_range(area, area->vm_start,
- (substream->runtime->dma_addr + offset) >> PAGE_SHIFT,
- size, area->vm_page_prot))
- return -EAGAIN;
- return 0;
+ return vm_iomap_memory(area, runtime->dma_addr, runtime->dma_bytes);
}
EXPORT_SYMBOL(snd_pcm_lib_mmap_iomem);
index e6b016693240617451f6720c6f8f4643e8160c67..bdd888ec9a8422838144fd93e8c8b8cff92ee4fe 100644 (file)
return 0;
}
-static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu)
+static int snd_emu1010_load_firmware(struct snd_emu10k1 *emu,
+ const struct firmware *fw_entry)
{
int n, i;
int reg;
int value;
unsigned int write_post;
unsigned long flags;
- const struct firmware *fw_entry = emu->firmware;
if (!fw_entry)
return -EIO;
/* Return to Audio Dock programming mode */
snd_printk(KERN_INFO "emu1010: Loading Audio Dock Firmware\n");
snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, EMU_HANA_FPGA_CONFIG_AUDIODOCK);
- err = snd_emu1010_load_firmware(emu);
- if (err != 0)
- continue;
+
+ if (!emu->dock_fw) {
+ const char *filename = NULL;
+ switch (emu->card_capabilities->emu_model) {
+ case EMU_MODEL_EMU1010:
+ filename = DOCK_FILENAME;
+ break;
+ case EMU_MODEL_EMU1010B:
+ filename = MICRO_DOCK_FILENAME;
+ break;
+ case EMU_MODEL_EMU1616:
+ filename = MICRO_DOCK_FILENAME;
+ break;
+ }
+ if (filename) {
+ err = request_firmware(&emu->dock_fw,
+ filename,
+ &emu->pci->dev);
+ if (err)
+ continue;
+ }
+ }
+
+ if (emu->dock_fw) {
+ err = snd_emu1010_load_firmware(emu, emu->dock_fw);
+ if (err)
+ continue;
+ }
snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0);
snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, ®);
filename, emu->firmware->size);
}
- err = snd_emu1010_load_firmware(emu);
+ err = snd_emu1010_load_firmware(emu, emu->firmware);
if (err != 0) {
snd_printk(KERN_INFO "emu1010: Loading Firmware failed\n");
return err;
kthread_stop(emu->emu1010.firmware_thread);
if (emu->firmware)
release_firmware(emu->firmware);
+ if (emu->dock_fw)
+ release_firmware(emu->dock_fw);
if (emu->irq >= 0)
free_irq(emu->irq, emu);
/* remove reserved page */
index ee975a25a874af1713026f22d9e1a6ec3e9fed54..7f45d485f7ff3e800ed4370801d1304b00bee0a5 100644 (file)
ALC269_TYPE_ALC280,
ALC269_TYPE_ALC282,
ALC269_TYPE_ALC284,
+ ALC269_TYPE_ALC286,
};
/*
case ALC269_TYPE_ALC269VB:
case ALC269_TYPE_ALC269VD:
case ALC269_TYPE_ALC282:
+ case ALC269_TYPE_ALC286:
ssids = alc269_ssids;
break;
default:
case 0x10ec0292:
spec->codec_variant = ALC269_TYPE_ALC284;
break;
+ case 0x10ec0286:
+ spec->codec_variant = ALC269_TYPE_ALC286;
+ break;
}
/* automatic parse from the BIOS config */
{ .id = 0x10ec0282, .name = "ALC282", .patch = patch_alc269 },
{ .id = 0x10ec0283, .name = "ALC283", .patch = patch_alc269 },
{ .id = 0x10ec0284, .name = "ALC284", .patch = patch_alc269 },
+ { .id = 0x10ec0286, .name = "ALC286", .patch = patch_alc269 },
{ .id = 0x10ec0290, .name = "ALC290", .patch = patch_alc269 },
{ .id = 0x10ec0292, .name = "ALC292", .patch = patch_alc269 },
{ .id = 0x10ec0861, .rev = 0x100340, .name = "ALC660",
index a4c16fd70f77546450851951245f803ec4bf004c..5d3631921eda65e81090ba67b7be605997e68f6a 100644 (file)
ret);
goto err_access;
}
- dev_info(codec->dev, "revision %c\n", ret + 'A');
+ dev_info(codec->dev, "revision %c\n", ret - 0x40 + 'A');
snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV);
diff --git a/sound/soc/omap/Kconfig b/sound/soc/omap/Kconfig
index 3c9887f4597d9689da6e7eadbeb321729d518f58..9afb392e87e825cb9ac7958ac056c7aeec647517 100644 (file)
--- a/sound/soc/omap/Kconfig
+++ b/sound/soc/omap/Kconfig
config SND_OMAP_SOC_OMAP_ABE_TWL6040
tristate "SoC Audio support for OMAP boards using ABE and twl6040 codec"
- depends on TWL6040_CORE && SND_OMAP_SOC && ARCH_OMAP4
+ depends on TWL6040_CORE && SND_OMAP_SOC && (ARCH_OMAP4 || SOC_OMAP5)
select SND_OMAP_SOC_DMIC
select SND_OMAP_SOC_MCPDM
select SND_SOC_TWL6040
- SDP4430/Blaze boards
- PandaBoard (4430)
- PandaBoardES (4460)
+ - PandaBoard 5 (5432)
config SND_OMAP_SOC_OMAP_HDMI
tristate "SoC Audio support for Texas Instruments OMAP HDMI"
index cb0b4e8c09769fdb58936c407152c81349b4aa99..3963a24349c5dfdf0b06ca875b0125245166307c 100644 (file)
abe_ini.o \
abe_gain.o \
abe_port.o \
- abe_seq.o \
port_mgr.o \
obj-$(CONFIG_SND_OMAP_SOC_ABE) += snd-soc-abe-hal.o
index 0a25f6c9415be18c206e623a7d3d12de09c65db5..058401814775a199c08f44204fe513d40c0545c4 100644 (file)
*
* GPL LICENSE SUMMARY
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
#include <linux/slab.h>
#include <linux/io.h>
-#include "abe_def.h"
-#include "abe_typ.h"
-#include "abe_ext.h"
+#include "aess-fw.h"
#include <linux/debugfs.h>
#define OMAP_ABE_MAX_PORT_ID OMAP_ABE_FE_PORT_MM_DL_LP
-/* ABE copy function IDs */
-#define OMAP_AESS_COPY_FCT_NULL_ID 0
-#define OMAP_AESS_COPY_FCT_S2D_STEREO_16_16_ID 1
-#define OMAP_AESS_COPY_FCT_S2D_MONO_MSB_ID 2
-#define OMAP_AESS_COPY_FCT_S2D_STEREO_MSB_ID 3
-#define OMAP_AESS_COPY_FCT_S2D_STEREO_RSHIFTED_16_ID 4
-#define OMAP_AESS_COPY_FCT_S2D_MONO_RSHIFTED_16_ID 5
-#define OMAP_AESS_COPY_FCT_D2S_STEREO_16_16_ID 6
-#define OMAP_AESS_COPY_FCT_D2S_MONO_MSB_ID 7
-#define OMAP_AESS_COPY_FCT_D2S_MONO_RSHIFTED_16_ID 8
-#define OMAP_AESS_COPY_FCT_D2S_STEREO_RSHIFTED_16_ID 9
-#define OMAP_AESS_COPY_FCT_D2S_STEREO_MSB_ID 10
-#define OMAP_AESS_COPY_FCT_DMIC_ID 11
-#define OMAP_AESS_COPY_FCT_MCPDM_DL_ID 12
-#define OMAP_AESS_COPY_FCT_MM_UL_ID 13
-#define OMAP_AESS_COPY_FCT_SPLIT_SMEM_ID 14
-#define OMAP_AESS_COPY_FCT_MERGE_SMEM_ID 15
-#define OMAP_AESS_COPY_FCT_SPLIT_TDM_ID 16
-#define OMAP_AESS_COPY_FCT_MERGE_TDM_ID 17
-#define OMAP_AESS_COPY_FCT_ROUTE_MM_UL_ID 18
-#define OMAP_AESS_COPY_FCT_IO_IP_ID 19
-#define OMAP_AESS_COPY_FCT_COPY_UNDERFLOW_ID 20
-#define OMAP_AESS_COPY_FCT_COPY_MCPDM_DL_HF_PDL1_ID 21
-#define OMAP_AESS_COPY_FCT_COPY_MCPDM_DL_HF_PDL2_ID 22
-#define OMAP_AESS_COPY_FCT_S2D_MONO_16_16_ID 23
-#define OMAP_AESS_COPY_FCT_D2S_MONO_16_16_ID 24
-#define OMAP_AESS_COPY_FCT_DMIC_NO_PRESCALE_ID 25
-
-/* ABE buffer IDs */
-#define OMAP_AESS_BUFFER_ZERO_ID 0
-#define OMAP_AESS_BUFFER_DMIC1_L_ID 1
-#define OMAP_AESS_BUFFER_DMIC1_R_ID 2
-#define OMAP_AESS_BUFFER_DMIC2_L_ID 3
-#define OMAP_AESS_BUFFER_DMIC2_R_ID 4
-#define OMAP_AESS_BUFFER_DMIC3_L_ID 5
-#define OMAP_AESS_BUFFER_DMIC3_R_ID 6
-#define OMAP_AESS_BUFFER_BT_UL_L_ID 7
-#define OMAP_AESS_BUFFER_BT_UL_R_ID 8
-#define OMAP_AESS_BUFFER_MM_EXT_IN_L_ID 9
-#define OMAP_AESS_BUFFER_MM_EXT_IN_R_ID 10
-#define OMAP_AESS_BUFFER_AMIC_L_ID 11
-#define OMAP_AESS_BUFFER_AMIC_R_ID 12
-#define OMAP_AESS_BUFFER_VX_REC_L_ID 13
-#define OMAP_AESS_BUFFER_VX_REC_R_ID 14
-#define OMAP_AESS_BUFFER_MCU_IRQ_FIFO_PTR_ID 15
-#define OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID 16
-#define OMAP_AESS_BUFFER_MM_EXT_IN_ID 17
-
#define OMAP_ABE_D_MCUIRQFIFO_SIZE 0x40
struct omap_aess_addr *map;
int *fct_id;
int *label_id;
- struct omap_aess_init_task *init_table;
+ int nb_init_task;
+ struct omap_aess_task *init_table;
struct omap_aess_port *port;
struct omap_aess_port *ping_pong;
struct omap_aess_task *dl1_mono_mixer;
struct list_head list;
struct omap_aess *abe;
+ struct snd_pcm_substream *substream;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_lstate;
#endif
};
-struct omap_abe_port *omap_abe_port_open(struct omap_aess *abe, int logical_id);
-void omap_abe_port_close(struct omap_aess *abe, struct omap_abe_port *port);
-int omap_abe_port_enable(struct omap_aess *abe, struct omap_abe_port *port);
-int omap_abe_port_disable(struct omap_aess *abe, struct omap_abe_port *port);
-int omap_abe_port_is_enabled(struct omap_aess *abe, struct omap_abe_port *port);
+struct omap_abe_port *omap_abe_port_open(struct omap_aess *aess, int logical_id);
+void omap_abe_port_close(struct omap_aess *aess, struct omap_abe_port *port);
+int omap_abe_port_enable(struct omap_aess *aess, struct omap_abe_port *port);
+int omap_abe_port_disable(struct omap_aess *aess, struct omap_abe_port *port);
+int omap_abe_port_is_enabled(struct omap_aess *aess, struct omap_abe_port *port);
struct omap_aess *omap_abe_port_mgr_get(void);
-void omap_abe_port_mgr_put(struct omap_aess *abe);
-
-struct omap_aess_seq {
- u32 write_pointer;
- u32 irq_pingpong_player_id;
-};
+void omap_abe_port_mgr_put(struct omap_aess *aess);
/* main ABE structure */
struct omap_aess {
void __iomem *io_base[5];
u32 firmware_version_number;
u16 MultiFrame[25][8];
- u32 compensated_mixer_gain;
u8 muted_gains_indicator[MAX_NBGAIN_CMEM];
u32 desired_gains_decibel[MAX_NBGAIN_CMEM];
u32 muted_gains_decibel[MAX_NBGAIN_CMEM];
u32 size_pingpong;
/* number of ping/pong buffer being used */
u32 nb_pingpong;
- struct snd_pcm_substream *substream_pp;
u32 irq_dbg_read_ptr;
- struct omap_aess_seq seq;
struct omap_aess_mapping *fw_info;
/* List of open ABE logical ports */
#endif
};
-#include "abe_gain.h"
-
struct omap_aess_equ {
/* type of filter */
u32 equ_type;
struct omap_aess_dma {
- /* OCP L3 pointer to the first address of the */
void *data;
- /* destination buffer (either DMA or Ping-Pong read/write pointers). */
- /* address L3 when addressing the DMEM buffer instead of CBPr */
- void *l3_dmem;
- /* address L3 translated to L4 the ARM memory space */
- void *l4_dmem;
- /* number of iterations for the DMA data moves. */
u32 iter;
};
-int omap_aess_set_opp_processing(struct omap_aess *abe, u32 opp);
-int omap_aess_connect_debug_trace(struct omap_aess *abe,
+int omap_aess_set_opp_processing(struct omap_aess *aess, u32 opp);
+int omap_aess_connect_debug_trace(struct omap_aess *aess,
struct omap_aess_dma *dma2);
/* gain */
-int omap_aess_use_compensated_gain(struct omap_aess *abe, int on_off);
-int omap_aess_write_equalizer(struct omap_aess *abe, u32 id,
+int omap_aess_use_compensated_gain(struct omap_aess *aess, int on_off);
+int omap_aess_write_equalizer(struct omap_aess *aess, u32 id,
struct omap_aess_equ *param);
-int omap_aess_disable_gain(struct omap_aess *abe, u32 id);
-int omap_aess_enable_gain(struct omap_aess *abe, u32 id);
-int omap_aess_mute_gain(struct omap_aess *abe, u32 id);
-int omap_aess_unmute_gain(struct omap_aess *abe, u32 id);
-
-int omap_aess_write_gain(struct omap_aess *abe, u32 id, s32 f_g);
-int omap_aess_write_mixer(struct omap_aess *abe, u32 id, s32 f_g);
-int omap_aess_read_gain(struct omap_aess *abe, u32 id, u32 *f_g);
-int omap_aess_read_mixer(struct omap_aess *abe, u32 id, u32 *f_g);
-
-int omap_aess_init_mem(struct omap_aess *abe, struct device *dev,
- void __iomem **_io_base, u32 *fw_header);
-int omap_aess_reset_hal(struct omap_aess *abe);
-int omap_aess_load_fw(struct omap_aess *abe, u32 *firmware);
-int omap_aess_reload_fw(struct omap_aess *abe, u32 *firmware);
+int omap_aess_disable_gain(struct omap_aess *aess, u32 id);
+int omap_aess_enable_gain(struct omap_aess *aess, u32 id);
+int omap_aess_mute_gain(struct omap_aess *aess, u32 id);
+int omap_aess_unmute_gain(struct omap_aess *aess, u32 id);
+
+int omap_aess_write_gain(struct omap_aess *aess, u32 id, s32 f_g);
+int omap_aess_write_mixer(struct omap_aess *aess, u32 id, s32 f_g);
+int omap_aess_read_gain(struct omap_aess *aess, u32 id, u32 *f_g);
+int omap_aess_read_mixer(struct omap_aess *aess, u32 id, u32 *f_g);
+
+int omap_aess_init_mem(struct omap_aess *aess, struct device *dev,
+ void __iomem **_io_base, const void *fw_config);
+int omap_aess_reset_hal(struct omap_aess *aess);
+int omap_aess_load_fw(struct omap_aess *aess, const void *firmware);
+int omap_aess_reload_fw(struct omap_aess *aess, const void *firmware);
u32 omap_abe_get_supported_fw_version(void);
/* port */
-int omap_aess_mono_mixer(struct omap_aess *abe, u32 id, u32 on_off);
-int omap_aess_connect_serial_port(struct omap_aess *abe, u32 id,
+int omap_aess_mono_mixer(struct omap_aess *aess, u32 id, u32 on_off);
+void omap_aess_connect_serial_port(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *f,
- u32 mcbsp_id);
-int omap_aess_connect_cbpr_dmareq_port(struct omap_aess *abe, u32 id,
+ u32 mcbsp_id, struct omap_aess_dma *aess_dma);
+void omap_aess_connect_cbpr_dmareq_port(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *f, u32 d,
- struct omap_aess_dma *returned_dma_t);
-int omap_aess_read_port_address(struct omap_aess *abe,
- u32 port, struct omap_aess_dma *dma2);
-int omap_aess_connect_irq_ping_pong_port(struct omap_aess *abe, u32 id,
+ struct omap_aess_dma *aess_dma);
+int omap_aess_connect_irq_ping_pong_port(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *f,
u32 subroutine_id, u32 size,
u32 *sink, u32 dsp_mcu_flag);
-void omap_aess_write_pdmdl_offset(struct omap_aess *abe, u32 path,
+void omap_aess_write_pdmdl_offset(struct omap_aess *aess, u32 path,
u32 offset_left, u32 offset_right);
-int omap_aess_enable_data_transfer(struct omap_aess *abe, u32 id);
-int omap_aess_disable_data_transfer(struct omap_aess *abe, u32 id);
+int omap_aess_enable_data_transfer(struct omap_aess *aess, u32 id);
+int omap_aess_disable_data_transfer(struct omap_aess *aess, u32 id);
/* core */
-int omap_aess_check_activity(struct omap_aess *abe);
-int omap_aess_wakeup(struct omap_aess *abe);
-int omap_aess_set_router_configuration(struct omap_aess *abe, u32 *param);
-int omap_abe_read_next_ping_pong_buffer(struct omap_aess *abe,
+int omap_aess_check_activity(struct omap_aess *aess);
+int omap_aess_wakeup(struct omap_aess *aess);
+int omap_aess_set_router_configuration(struct omap_aess *aess, u32 *param);
+int omap_abe_read_next_ping_pong_buffer(struct omap_aess *aess,
u32 port, u32 *p, u32 *n);
-int omap_aess_read_next_ping_pong_buffer(struct omap_aess *abe,
+int omap_aess_read_next_ping_pong_buffer(struct omap_aess *aess,
u32 port, u32 *p, u32 *n);
-int omap_aess_irq_processing(struct omap_aess *abe);
-int omap_aess_set_ping_pong_buffer(struct omap_aess *abe,
+int omap_aess_irq_processing(struct omap_aess *aess);
+int omap_aess_set_ping_pong_buffer(struct omap_aess *aess,
u32 port, u32 n_bytes);
-int omap_aess_read_offset_from_ping_buffer(struct omap_aess *abe,
+int omap_aess_read_offset_from_ping_buffer(struct omap_aess *aess,
u32 id, u32 *n);
-/* seq */
-int omap_aess_plug_subroutine(struct omap_aess *abe, u32 *id,
- abe_subroutine2 f, u32 n, u32 *params);
-
#endif /* _ABE_H_ */
index 22f5a669a85620df67fe0afdba4d2696587186c0..bac94a6a329883cc0d84425d91f9d915813101d3 100644 (file)
#include "abe_mem.h"
#include "abe_aess.h"
+#define EVENT_GENERATOR_ON 1
+#define EVENT_GENERATOR_OFF 0
+
+#define EVENT_SOURCE_DMA 0
+#define EVENT_SOURCE_COUNTER 1
+
/**
* omap_aess_hw_configuration
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* Initialize the AESS HW registers for MPU and DMA
* request visibility.
*/
-void omap_aess_hw_configuration(struct omap_aess *abe)
+void omap_aess_hw_configuration(struct omap_aess *aess)
{
/* enable AESS auto gating (required to release all AESS clocks) */
- omap_aess_reg_writel(abe, AESS_AUTO_GATING_ENABLE, 1);
+ omap_aess_reg_writel(aess, OMAP_AESS_AUTO_GATING_ENABLE, 1);
/* enables the DMAreq from AESS AESS_DMAENABLE_SET = 255 */
- omap_aess_reg_writel(abe, AESS_DMAENABLE_SET, DMA_ENABLE_ALL);
+ omap_aess_reg_writel(aess, OMAP_AESS_DMAENABLE_SET, DMA_ENABLE_ALL);
/* enables the MCU IRQ from AESS to Cortex A9 */
- omap_aess_reg_writel(abe, AESS_MCU_IRQENABLE_SET, INT_SET);
+ omap_aess_reg_writel(aess, OMAP_AESS_MCU_IRQENABLE_SET, INT_SET);
}
/**
* omap_aess_clear_irq - clear ABE interrupt
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* This subroutine is called to clear MCU Irq
*/
-int omap_aess_clear_irq(struct omap_aess *abe)
+int omap_aess_clear_irq(struct omap_aess *aess)
{
- omap_aess_reg_writel(abe, ABE_MCU_IRQSTATUS, INT_CLR);
+ omap_aess_reg_writel(aess, OMAP_AESS_MCU_IRQSTATUS, INT_CLR);
return 0;
}
EXPORT_SYMBOL(omap_aess_clear_irq);
/**
* abe_write_event_generator - Selects event generator source
- * @abe: Pointer on abe handle
+ * @aess: Pointer on abe handle
* @e: Event Generation Counter, McPDM, DMIC or default.
*
* Loads the AESS event generator hardware source.
* (1<<1) in order to have the same speed at 50% and 100% OPP
* (only 15 MSB bits are used at OPP50%)
*/
-int omap_aess_write_event_generator(struct omap_aess *abe, u32 e)
+int omap_aess_write_event_generator(struct omap_aess *aess, u32 e)
{
u32 event, selection;
u32 counter = EVENT_GENERATOR_COUNTER_DEFAULT;
aess_err("Bad event generator selection");
return -AESS_EINVAL;
}
- omap_aess_reg_writel(abe, EVENT_GENERATOR_COUNTER, counter);
- omap_aess_reg_writel(abe, EVENT_SOURCE_SELECTION, selection);
- omap_aess_reg_writel(abe, EVENT_GENERATOR_START, EVENT_GENERATOR_ON);
- omap_aess_reg_writel(abe, AUDIO_ENGINE_SCHEDULER, event);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_GENERATOR_COUNTER, counter);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_SOURCE_SELECTION, selection);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_GENERATOR_START, EVENT_GENERATOR_ON);
+ omap_aess_reg_writel(aess, OMAP_AESS_AUDIO_ENGINE_SCHEDULER, event);
return 0;
}
EXPORT_SYMBOL(omap_aess_write_event_generator);
/**
* omap_aess_start_event_generator - Starts event generator source
- * @abe: Pointer on abe handle
+ * @aess: Pointer on abe handle
*
* Start the event genrator of AESS. No more event will be send to AESS engine.
* Upper layer must wait 1/96kHz to be sure that engine reaches
* the IDLE instruction.
*/
-int omap_aess_start_event_generator(struct omap_aess *abe)
+int omap_aess_start_event_generator(struct omap_aess *aess)
{
/* Start the event Generator */
- omap_aess_reg_writel(abe, EVENT_GENERATOR_START, 1);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_GENERATOR_START, 1);
return 0;
}
EXPORT_SYMBOL(omap_aess_start_event_generator);
/**
* omap_aess_stop_event_generator - Stops event generator source
- * @abe: Pointer on abe handle
+ * @aess: Pointer on abe handle
*
* Stop the event genrator of AESS. No more event will be send to AESS engine.
* Upper layer must wait 1/96kHz to be sure that engine reaches
* the IDLE instruction.
*/
-int omap_aess_stop_event_generator(struct omap_aess *abe)
+int omap_aess_stop_event_generator(struct omap_aess *aess)
{
/* Stop the event Generator */
- omap_aess_reg_writel(abe, EVENT_GENERATOR_START, 0);
+ omap_aess_reg_writel(aess, OMAP_AESS_EVENT_GENERATOR_START, 0);
return 0;
}
EXPORT_SYMBOL(omap_aess_stop_event_generator);
/**
* omap_aess_disable_irq - disable MCU/DSP ABE interrupt
- * @abe: Pointer on abe handle
+ * @aess: Pointer on abe handle
*
* This subroutine is disabling ABE MCU/DSP Irq
*/
-int omap_aess_disable_irq(struct omap_aess *abe)
+int omap_aess_disable_irq(struct omap_aess *aess)
{
/* disables the DMAreq from AESS AESS_DMAENABLE_CLR = 127
* DMA_Req7 will still be enabled as it is used for ABE trace */
- omap_aess_reg_writel(abe, AESS_DMAENABLE_CLR, 0x7F);
+ omap_aess_reg_writel(aess, OMAP_AESS_DMAENABLE_CLR, 0x7F);
/* disables the MCU IRQ from AESS to Cortex A9 */
- omap_aess_reg_writel(abe, AESS_MCU_IRQENABLE_CLR, 0x01);
+ omap_aess_reg_writel(aess, OMAP_AESS_MCU_IRQENABLE_CLR, 0x01);
return 0;
}
EXPORT_SYMBOL(omap_aess_disable_irq);
index c109eb7f6097d140e742798fbd361e691dbbf9df..b12f28051310caa5eef3b87a7e6db0a4cca92c3c 100644 (file)
#ifndef _ABE_AESS_H_
#define _ABE_AESS_H_
-#define AESS_REVISION 0x00
-#define AESS_MCU_IRQSTATUS 0x28
-#define AESS_MCU_IRQENABLE_SET 0x3C
-#define AESS_MCU_IRQENABLE_CLR 0x40
-#define AESS_DMAENABLE_SET 0x60
-#define AESS_DMAENABLE_CLR 0x64
-#define EVENT_GENERATOR_COUNTER 0x68
-#define EVENT_GENERATOR_START 0x6C
-#define EVENT_SOURCE_SELECTION 0x70
-#define AUDIO_ENGINE_SCHEDULER 0x74
-#define AESS_AUTO_GATING_ENABLE 0x7C
+#define OMAP_AESS_REVISION 0x00
+#define OMAP_AESS_MCU_IRQSTATUS_RAW 0x24
+#define OMAP_AESS_MCU_IRQSTATUS 0x28
+#define OMAP_AESS_MCU_IRQENABLE_SET 0x3C
+#define OMAP_AESS_MCU_IRQENABLE_CLR 0x40
+#define OMAP_AESS_DSP_IRQSTATUS_RAW 0x4C
+#define OMAP_AESS_DMAENABLE_SET 0x60
+#define OMAP_AESS_DMAENABLE_CLR 0x64
+#define OMAP_AESS_EVENT_GENERATOR_COUNTER 0x68
+#define OMAP_AESS_EVENT_GENERATOR_START 0x6C
+#define OMAP_AESS_EVENT_SOURCE_SELECTION 0x70
+#define OMAP_AESS_AUDIO_ENGINE_SCHEDULER 0x74
+#define OMAP_AESS_AUTO_GATING_ENABLE 0x7C
+#define OMAP_AESS_DMASTATUS_RAW 0x84
/*
* AESS_MCU_IRQSTATUS bit field
#define EVENT_GENERATOR_COUNTER_44100 (2228-1)
-int omap_aess_start_event_generator(struct omap_aess *abe);
-int omap_aess_stop_event_generator(struct omap_aess *abe);
-int omap_aess_write_event_generator(struct omap_aess *abe, u32 e);
+int omap_aess_start_event_generator(struct omap_aess *aess);
+int omap_aess_stop_event_generator(struct omap_aess *aess);
+int omap_aess_write_event_generator(struct omap_aess *aess, u32 e);
-int omap_aess_disable_irq(struct omap_aess *abe);
-int omap_aess_clear_irq(struct omap_aess *abe);
+int omap_aess_disable_irq(struct omap_aess *aess);
+int omap_aess_clear_irq(struct omap_aess *aess);
-void omap_aess_hw_configuration(struct omap_aess *abe);
+void omap_aess_hw_configuration(struct omap_aess *aess);
#endif /* _ABE_AESS_H_ */
index 69fbd3e4eed342f008606af9492b4c8b8d7f581c..c8db67b97d4cd1c74008e54bb3e0e8bf0a86bbb3 100644 (file)
*
* BSD LICENSE
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include "abe_port.h"
#include "abe_mem.h"
#include "abe_dbg.h"
-#include "abe_seq.h"
-
-#define IRQtag_COUNT 0x000c
-#define IRQtag_PP 0x000d
-#define OMAP_ABE_IRQ_FIFO_MASK ((OMAP_ABE_D_MCUIRQFIFO_SIZE >> 2) - 1)
/**
- * abe_omap_aess_reset_hal - reset the ABE/HAL
- * @abe: Pointer on aess handle
+ * omap_aess_reset_hal - reset the ABE/HAL
+ * @aess: Pointer on aess handle
*
* Operations : reset the ABE by reloading the static variables and
* default AESS registers.
* Called after a PRCM cold-start reset of ABE
*/
-int omap_aess_reset_hal(struct omap_aess *abe)
+int omap_aess_reset_hal(struct omap_aess *aess)
{
u32 i;
/* IRQ & DBG circular read pointer in DMEM */
- abe->irq_dbg_read_ptr = 0;
-
- /* default = disable the mixer's adaptive gain control */
- omap_aess_use_compensated_gain(abe, 0);
+ aess->irq_dbg_read_ptr = 0;
/* reset the default gain values */
for (i = 0; i < MAX_NBGAIN_CMEM; i++) {
- abe->muted_gains_indicator[i] = 0;
- abe->desired_gains_decibel[i] = (u32) GAIN_MUTE;
- abe->desired_gains_linear[i] = 0;
- abe->desired_ramp_delay_ms[i] = 0;
- abe->muted_gains_decibel[i] = (u32) GAIN_TOOLOW;
+ aess->muted_gains_indicator[i] = 0;
+ aess->desired_gains_decibel[i] = (u32) GAIN_MUTE;
+ aess->desired_gains_linear[i] = 0;
+ aess->desired_ramp_delay_ms[i] = 0;
+ aess->muted_gains_decibel[i] = (u32) GAIN_TOOLOW;
}
- omap_aess_hw_configuration(abe);
+ omap_aess_hw_configuration(aess);
return 0;
}
EXPORT_SYMBOL(omap_aess_reset_hal);
/**
* omap_aess_wakeup - Wakeup ABE
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* Wakeup ABE in case of retention
*/
-int omap_aess_wakeup(struct omap_aess *abe)
+int omap_aess_wakeup(struct omap_aess *aess)
{
/* Restart event generator */
- omap_aess_write_event_generator(abe, EVENT_TIMER);
+ omap_aess_write_event_generator(aess, EVENT_TIMER);
/* reconfigure DMA Req and MCU Irq visibility */
- omap_aess_hw_configuration(abe);
+ omap_aess_hw_configuration(aess);
return 0;
}
EXPORT_SYMBOL(omap_aess_wakeup);
-/**
- * omap_aess_monitoring
- * @abe: Pointer on aess handle
- *
- * checks the internal status of ABE and HAL
- */
-static void omap_aess_monitoring(struct omap_aess *abe)
-{
-
-}
-
-/**
- * omap_aess_irq_processing - Process ABE interrupt
- * @abe: Pointer on aess handle
- *
- * This subroutine is call upon reception of "MA_IRQ_99 ABE_MPU_IRQ" Audio
- * back-end interrupt. This subroutine will check the ATC Hrdware, the
- * IRQ_FIFO from the AE and act accordingly. Some IRQ source are originated
- * for the delivery of "end of time sequenced tasks" notifications, some are
- * originated from the Ping-Pong protocols, some are generated from
- * the embedded debugger when the firmware stops on programmable break-points,
- * etc ...
- */
-int omap_aess_irq_processing(struct omap_aess *abe)
-{
- u32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm;
- struct omap_aess_irq_data IRQ_data;
- struct omap_aess_addr addr;
-
- /* extract the write pointer index from CMEM memory (INITPTR format) */
- /* CMEM address of the write pointer in bytes */
- cmem_src = abe->fw_info->label_id[OMAP_AESS_BUFFER_MCU_IRQ_FIFO_PTR_ID] << 2;
- omap_abe_mem_read(abe, OMAP_ABE_CMEM, cmem_src,
- &sm_cm, sizeof(abe_irq_dbg_write_ptr));
- /* AESS left-pointer index located on MSBs */
- abe_irq_dbg_write_ptr = sm_cm >> 16;
- abe_irq_dbg_write_ptr &= 0xFF;
- /* loop on the IRQ FIFO content */
- for (i = 0; i < OMAP_ABE_D_MCUIRQFIFO_SIZE; i++) {
- /* stop when the FIFO is empty */
- if (abe_irq_dbg_write_ptr == abe->irq_dbg_read_ptr)
- break;
- /* read the IRQ/DBG FIFO */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_MCUIRQFIFO_ID],
- sizeof(struct omap_aess_addr));
- addr.offset += (abe->irq_dbg_read_ptr << 2);
- addr.bytes = sizeof(IRQ_data);
- omap_aess_mem_read(abe, addr, (u32 *)&IRQ_data);
- abe->irq_dbg_read_ptr = (abe->irq_dbg_read_ptr + 1) & OMAP_ABE_IRQ_FIFO_MASK;
- /* select the source of the interrupt */
- switch (IRQ_data.tag) {
- case IRQtag_PP:
- omap_aess_irq_ping_pong(abe);
- break;
- case IRQtag_COUNT:
- /*abe_irq_check_for_sequences(IRQ_data.data);*/
- omap_aess_monitoring(abe);
- break;
- default:
- break;
- }
- }
- return 0;
-}
-EXPORT_SYMBOL(omap_aess_irq_processing);
-
/**
* abe_set_router_configuration
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @param: list of output index of the route
*
* The uplink router takes its input from DMIC (6 samples), AMIC (2 samples)
* indexes 14 .. 15 = RESERVED (NULL)
* ZERO_labelID, ZERO_labelID,
*/
-int omap_aess_set_router_configuration(struct omap_aess *abe, u32 *param)
+int omap_aess_set_router_configuration(struct omap_aess *aess, u32 *param)
{
- omap_aess_mem_write(abe,
- abe->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID],
+ omap_aess_mem_write(aess,
+ aess->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID],
param);
return 0;
}
/**
* abe_set_opp_processing - Set OPP mode for ABE Firmware
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @opp: OOPP mode
*
* New processing network and OPP:
* this switch.
*
*/
-int omap_aess_set_opp_processing(struct omap_aess *abe, u32 opp)
+int omap_aess_set_opp_processing(struct omap_aess *aess, u32 opp)
{
u32 dOppMode32;
break;
}
/* Write Multiframe inside DMEM */
- omap_aess_mem_write(abe,
- abe->fw_info->map[OMAP_AESS_DMEM_MAXTASKBYTESINSLOT_ID],
+ omap_aess_mem_write(aess,
+ aess->fw_info->map[OMAP_AESS_DMEM_MAXTASKBYTESINSLOT_ID],
&dOppMode32);
return 0;
diff --git a/sound/soc/omap/aess/abe_def.h b/sound/soc/omap/aess/abe_def.h
+++ /dev/null
@@ -1,298 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef _ABE_DEF_H_
-#define _ABE_DEF_H_
-/*
- * HARDWARE AND PERIPHERAL DEFINITIONS
- */
-/* MM_DL */
-#define ABE_CBPR0_IDX 0
-/* VX_DL */
-#define ABE_CBPR1_IDX 1
-/* VX_UL */
-#define ABE_CBPR2_IDX 2
-/* MM_UL */
-#define ABE_CBPR3_IDX 3
-/* MM_UL2 */
-#define ABE_CBPR4_IDX 4
-/* TONES */
-#define ABE_CBPR5_IDX 5
-/* TDB */
-#define ABE_CBPR6_IDX 6
-/* DEBUG/CTL */
-#define ABE_CBPR7_IDX 7
-#define CIRCULAR_BUFFER_PERIPHERAL_R__0 (0x100 + ABE_CBPR0_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__1 (0x100 + ABE_CBPR1_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__2 (0x100 + ABE_CBPR2_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__3 (0x100 + ABE_CBPR3_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__4 (0x100 + ABE_CBPR4_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__5 (0x100 + ABE_CBPR5_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__6 (0x100 + ABE_CBPR6_IDX*4)
-#define CIRCULAR_BUFFER_PERIPHERAL_R__7 (0x100 + ABE_CBPR7_IDX*4)
-#define PING_PONG_WITH_MCU_IRQ 1
-#define PING_PONG_WITH_DSP_IRQ 2
-/* ID used for LIB memory copy subroutines */
-#define COPY_FROM_ABE_TO_HOST 1
-#define COPY_FROM_HOST_TO_ABE 2
-/*
- * INTERNAL DEFINITIONS
- */
-#define ABE_FIRMWARE_MAX_SIZE 26629
-/* 24 Q6.26 coefficients */
-#define NBEQ1 25
-/* 2x12 Q6.26 coefficients */
-#define NBEQ2 13
-/* TBD APS first set of parameters */
-#define NBAPS1 10
-/* TBD APS second set of parameters */
-#define NBAPS2 10
-/* Mixer used for sending tones to the uplink voice path */
-#define NBMIX_AUDIO_UL 2
-/* Main downlink mixer */
-#define NBMIX_DL1 4
-/* Handsfree downlink mixer */
-#define NBMIX_DL2 4
-/* Side-tone mixer */
-#define NBMIX_SDT 2
-/* Echo reference mixer */
-#define NBMIX_ECHO 2
-/* Voice record mixer */
-#define NBMIX_VXREC 4
-/* unsigned version of (-1) */
-#define CC_M1 0xFF
-#define CS_M1 0xFFFF
-#define CL_M1 0xFFFFFFFFL
-/*
- Mixer ID Input port ID Comments
- DL1_MIXER 0 MMDL path
- 1 MMUL2 path
- 2 VXDL path
- 3 TONES path
- SDT_MIXER 0 Uplink path
- 1 Downlink path
- ECHO_MIXER 0 DL1_MIXER path
- 1 DL2_MIXER path
- AUDUL_MIXER 0 TONES_DL path
- 1 Uplink path
- 2 MM_DL path
- VXREC_MIXER 0 TONES_DL path
- 1 VX_DL path
- 2 MM_DL path
- 3 VX_UL path
-*/
-#define MIX_VXUL_INPUT_MM_DL 0
-#define MIX_VXUL_INPUT_TONES 1
-#define MIX_VXUL_INPUT_VX_UL 2
-#define MIX_VXUL_INPUT_VX_DL 3
-#define MIX_DL1_INPUT_MM_DL 0
-#define MIX_DL1_INPUT_MM_UL2 1
-#define MIX_DL1_INPUT_VX_DL 2
-#define MIX_DL1_INPUT_TONES 3
-#define MIX_DL2_INPUT_MM_DL 0
-#define MIX_DL2_INPUT_MM_UL2 1
-#define MIX_DL2_INPUT_VX_DL 2
-#define MIX_DL2_INPUT_TONES 3
-#define MIX_SDT_INPUT_UP_MIXER 0
-#define MIX_SDT_INPUT_DL1_MIXER 1
-#define MIX_AUDUL_INPUT_MM_DL 0
-#define MIX_AUDUL_INPUT_TONES 1
-#define MIX_AUDUL_INPUT_UPLINK 2
-#define MIX_AUDUL_INPUT_VX_DL 3
-#define MIX_VXREC_INPUT_MM_DL 0
-#define MIX_VXREC_INPUT_TONES 1
-#define MIX_VXREC_INPUT_VX_UL 2
-#define MIX_VXREC_INPUT_VX_DL 3
-#define MIX_ECHO_DL1 0
-#define MIX_ECHO_DL2 1
-/* nb of samples to route */
-#define NBROUTE_UL 16
-/* 10 routing tables max */
-#define NBROUTE_CONFIG_MAX 10
-/* 5 pre-computed routing tables */
-#define NBROUTE_CONFIG 6
-/* AMIC on VX_UL */
-#define UPROUTE_CONFIG_AMIC 0
-/* DMIC first pair on VX_UL */
-#define UPROUTE_CONFIG_DMIC1 1
-/* DMIC second pair on VX_UL */
-#define UPROUTE_CONFIG_DMIC2 2
-/* DMIC last pair on VX_UL */
-#define UPROUTE_CONFIG_DMIC3 3
-/* BT_UL on VX_UL */
-#define UPROUTE_CONFIG_BT 4
-/* ECHO_REF on MM_UL2 */
-#define UPROUTE_ECHO_MMUL2 5
-/* max number of feature associated to a port */
-#define MAXFEATUREPORT 12
-#define SUB_0_PARAM 0
-/* number of parameters per sequence calls */
-#define SUB_1_PARAM 1
-#define SUB_2_PARAM 2
-#define SUB_3_PARAM 3
-#define SUB_4_PARAM 4
-/* active sequence mask = 0 means the line is free */
-#define FREE_LINE 0
-/* no ask for collision protection */
-#define NOMASK (1 << 0)
-/* do not allow a PDM OFF during the execution of this sequence */
-#define MASK_PDM_OFF (1 << 1)
-/* do not allow a PDM ON during the execution of this sequence */
-#define MASK_PDM_ON (1 << 2)
-/* explicit name of the feature */
-#define NBCHARFEATURENAME 16
-/* explicit name of the port */
-#define NBCHARPORTNAME 16
-/* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */
-#define SNK_P ABE_ATC_DIRECTION_IN
-/* source / ouptut port */
-#define SRC_P ABE_ATC_DIRECTION_OUT
-/* no ASRC applied */
-#define NODRIFT 0
-/* for abe_set_asrc_drift_control */
-#define FORCED_DRIFT_CONTROL 1
-/* for abe_set_asrc_drift_control */
-#define ADPATIVE_DRIFT_CONTROL 2
-/* number of task/slot depending on the OPP value */
-#define DOPPMODE32_OPP100 (0x00000010)
-#define DOPPMODE32_OPP50 (0x0000000C)
-#define DOPPMODE32_OPP25 (0x0000004)
-/*
- * ABE CONST AREA FOR PARAMETERS TRANSLATION
- */
-#define GAIN_MAXIMUM 3000L
-#define GAIN_24dB 2400L
-#define GAIN_18dB 1800L
-#define GAIN_12dB 1200L
-#define GAIN_6dB 600L
-/* default gain = 1 */
-#define GAIN_0dB 0L
-#define GAIN_M6dB -600L
-#define GAIN_M7dB -700L
-#define GAIN_M12dB -1200L
-#define GAIN_M18dB -1800L
-#define GAIN_M24dB -2400L
-#define GAIN_M30dB -3000L
-#define GAIN_M40dB -4000L
-#define GAIN_M50dB -5000L
-/* muted gain = -120 decibels */
-#define MUTE_GAIN -12000L
-#define GAIN_TOOLOW -13000L
-#define GAIN_MUTE MUTE_GAIN
-#define RAMP_MINLENGTH 0L
-/* ramp_t is in milli- seconds */
-#define RAMP_0MS 0L
-#define RAMP_1MS 1L
-#define RAMP_2MS 2L
-#define RAMP_5MS 5L
-#define RAMP_10MS 10L
-#define RAMP_20MS 20L
-#define RAMP_50MS 50L
-#define RAMP_100MS 100L
-#define RAMP_200MS 200L
-#define RAMP_500MS 500L
-#define RAMP_1000MS 1000L
-#define RAMP_MAXLENGTH 10000L
-/* for abe_translate_gain_format */
-#define LINABE_TO_DECIBELS 1
-#define DECIBELS_TO_LINABE 2
-/* for abe_translate_ramp_format */
-#define IIRABE_TO_MICROS 1
-#define MICROS_TO_IIABE 2
-/*
- * ABE CONST AREA FOR PERIPHERAL TUNING
- */
-/* port idled IDLE_P */
-#define OMAP_ABE_PORT_ACTIVITY_IDLE 1
-/* port initialized, ready to be activated */
-#define OMAP_ABE_PORT_INITIALIZED 3
-/* port activated RUN_P */
-#define OMAP_ABE_PORT_ACTIVITY_RUNNING 2
-#define NOCALLBACK 0
-#define NOPARAMETER 0
-/* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */
-#define MCPDM_UL_ITER 4
-/* All the McPDM FIFOs are enabled simultaneously */
-#define MCPDM_DL_ITER 24
-/* All the DMIC FIFOs are enabled simultaneously */
-#define DMIC_ITER 12
-/* TBD later if needed */
-#define MAX_PINGPONG_BUFFERS 2
-/*
- * Indexes to the subroutines
- */
-#define SUB_WRITE_MIXER 1
-#define SUB_WRITE_PORT_GAIN 2
-/* OLD WAY */
-#define c_feat_init_eq 1
-#define c_feat_read_eq1 2
-#define c_write_eq1 3
-#define c_feat_read_eq2 4
-#define c_write_eq2 5
-#define c_feat_read_eq3 6
-#define c_write_eq3 7
-/* max number of gain to be controlled by HAL */
-#define MAX_NBGAIN_CMEM 36
-/*
- * MACROS
- */
-#define maximum(a, b) (((a) < (b)) ? (b) : (a))
-#define minimum(a, b) (((a) > (b)) ? (b) : (a))
-#define absolute(a) (((a) > 0) ? (a) : ((-1)*(a)))
-#define HAL_VERSIONS 9
-#endif/* _ABE_DEF_H_ */
diff --git a/sound/soc/omap/aess/abe_ext.h b/sound/soc/omap/aess/abe_ext.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef _ABE_EXT_H_
-#define _ABE_EXT_H_
-
-/*
- * HARDWARE AND PERIPHERAL DEFINITIONS
- */
-/* PMEM SIZE in bytes (1024 words of 64 bits: : #32bits words x 4)*/
-#define ABE_PMEM_SIZE 8192
-/* CMEM SIZE in bytes (2048 coeff : #32bits words x 4)*/
-#define ABE_CMEM_SIZE 8192
-/* SMEM SIZE in bytes (3072 stereo samples : #32bits words x 4)*/
-#define ABE_SMEM_SIZE 24576
-/* DMEM SIZE in bytes */
-#define ABE_DMEM_SIZE 65536L
-/* ATC REGISTERS SIZE in bytes */
-#define ABE_ATC_DESC_SIZE 512
-/* holds the MCU Irq signal */
-#define ABE_MCU_IRQSTATUS_RAW 0x24
-/* status : clear the IRQ */
-#define ABE_MCU_IRQSTATUS 0x28
-/* holds the DSP Irq signal */
-#define ABE_DSP_IRQSTATUS_RAW 0x4C
-/* holds the DMA req lines to the sDMA */
-#define ABE_DMASTATUS_RAW 0x84
-#define EVENT_GENERATOR_COUNTER 0x68
-/* PLL output/desired sampling rate = (32768 * 6000)/96000 */
-#define EVENT_GENERATOR_COUNTER_DEFAULT (2048-1)
-/* PLL output/desired sampling rate = (32768 * 6000)/88200 */
-#define EVENT_GENERATOR_COUNTER_44100 (2228-1)
-/* start / stop the EVENT generator */
-#define EVENT_GENERATOR_START 0x6C
-#define EVENT_GENERATOR_ON 1
-#define EVENT_GENERATOR_OFF 0
-/* selection of the EVENT generator source */
-#define EVENT_SOURCE_SELECTION 0x70
-#define EVENT_SOURCE_DMA 0
-#define EVENT_SOURCE_COUNTER 1
-/* selection of the ABE DMA req line from ATC */
-#define AUDIO_ENGINE_SCHEDULER 0x74
-#define ABE_ATC_DMIC_DMA_REQ 1
-#define ABE_ATC_MCPDMDL_DMA_REQ 2
-#define ABE_ATC_MCPDMUL_DMA_REQ 3
-/* Direction=0 means input from ABE point of view */
-#define ABE_ATC_DIRECTION_IN 0
-/* Direction=1 means output from ABE point of view */
-#define ABE_ATC_DIRECTION_OUT 1
-/*
- * DMA requests
- */
-/*Internal connection doesn't connect at ABE boundary */
-#define External_DMA_0 0
-/*Transmit request digital microphone */
-#define DMIC_DMA_REQ 1
-/*Multichannel PDM downlink */
-#define McPDM_DMA_DL 2
-/*Multichannel PDM uplink */
-#define McPDM_DMA_UP 3
-/*MCBSP module 1 - transmit request */
-#define MCBSP1_DMA_TX 4
-/*MCBSP module 1 - receive request */
-#define MCBSP1_DMA_RX 5
-/*MCBSP module 2 - transmit request */
-#define MCBSP2_DMA_TX 6
-/*MCBSP module 2 - receive request */
-#define MCBSP2_DMA_RX 7
-/*MCBSP module 3 - transmit request */
-#define MCBSP3_DMA_TX 8
-/*MCBSP module 3 - receive request */
-#define MCBSP3_DMA_RX 9
-/*SLIMBUS module 1 - transmit request channel 0 */
-#define SLIMBUS1_DMA_TX0 10
-/*SLIMBUS module 1 - transmit request channel 1 */
-#define SLIMBUS1_DMA_TX1 11
-/*SLIMBUS module 1 - transmit request channel 2 */
-#define SLIMBUS1_DMA_TX2 12
-/*SLIMBUS module 1 - transmit request channel 3 */
-#define SLIMBUS1_DMA_TX3 13
-/*SLIMBUS module 1 - transmit request channel 4 */
-#define SLIMBUS1_DMA_TX4 14
-/*SLIMBUS module 1 - transmit request channel 5 */
-#define SLIMBUS1_DMA_TX5 15
-/*SLIMBUS module 1 - transmit request channel 6 */
-#define SLIMBUS1_DMA_TX6 16
-/*SLIMBUS module 1 - transmit request channel 7 */
-#define SLIMBUS1_DMA_TX7 17
-/*SLIMBUS module 1 - receive request channel 0 */
-#define SLIMBUS1_DMA_RX0 18
-/*SLIMBUS module 1 - receive request channel 1 */
-#define SLIMBUS1_DMA_RX1 19
-/*SLIMBUS module 1 - receive request channel 2 */
-#define SLIMBUS1_DMA_RX2 20
-/*SLIMBUS module 1 - receive request channel 3 */
-#define SLIMBUS1_DMA_RX3 21
-/*SLIMBUS module 1 - receive request channel 4 */
-#define SLIMBUS1_DMA_RX4 22
-/*SLIMBUS module 1 - receive request channel 5 */
-#define SLIMBUS1_DMA_RX5 23
-/*SLIMBUS module 1 - receive request channel 6 */
-#define SLIMBUS1_DMA_RX6 24
-/*SLIMBUS module 1 - receive request channel 7 */
-#define SLIMBUS1_DMA_RX7 25
-/*McASP - Data transmit DMA request line */
-#define McASP1_AXEVT 26
-/*McASP - Data receive DMA request line */
-#define McASP1_AREVT 29
-/*DUMMY FIFO @@@ */
-#define _DUMMY_FIFO_ 30
-/*DMA of the Circular buffer peripheral 0 */
-#define CBPr_DMA_RTX0 32
-/*DMA of the Circular buffer peripheral 1 */
-#define CBPr_DMA_RTX1 33
-/*DMA of the Circular buffer peripheral 2 */
-#define CBPr_DMA_RTX2 34
-/*DMA of the Circular buffer peripheral 3 */
-#define CBPr_DMA_RTX3 35
-/*DMA of the Circular buffer peripheral 4 */
-#define CBPr_DMA_RTX4 36
-/*DMA of the Circular buffer peripheral 5 */
-#define CBPr_DMA_RTX5 37
-/*DMA of the Circular buffer peripheral 6 */
-#define CBPr_DMA_RTX6 38
-/*DMA of the Circular buffer peripheral 7 */
-#define CBPr_DMA_RTX7 39
-/*
- * ATC DESCRIPTORS - DESTINATIONS
- */
-#define DEST_DMEM_access 0x00
-#define DEST_MCBSP1_TX 0x01
-#define DEST_MCBSP2_TX 0x02
-#define DEST_MCBSP3_TX 0x03
-#define DEST_SLIMBUS1_TX0 0x04
-#define DEST_SLIMBUS1_TX1 0x05
-#define DEST_SLIMBUS1_TX2 0x06
-#define DEST_SLIMBUS1_TX3 0x07
-#define DEST_SLIMBUS1_TX4 0x08
-#define DEST_SLIMBUS1_TX5 0x09
-#define DEST_SLIMBUS1_TX6 0x0A
-#define DEST_SLIMBUS1_TX7 0x0B
-#define DEST_MCPDM_DL 0x0C
-#define DEST_MCASP_TX0 0x0D
-#define DEST_MCASP_TX1 0x0E
-#define DEST_MCASP_TX2 0x0F
-#define DEST_MCASP_TX3 0x10
-#define DEST_EXTPORT0 0x11
-#define DEST_EXTPORT1 0x12
-#define DEST_EXTPORT2 0x13
-#define DEST_EXTPORT3 0x14
-#define DEST_MCPDM_ON 0x15
-#define DEST_CBP_CBPr 0x3F
-/*
- * ATC DESCRIPTORS - SOURCES
- */
-#define SRC_DMEM_access 0x0
-#define SRC_MCBSP1_RX 0x01
-#define SRC_MCBSP2_RX 0x02
-#define SRC_MCBSP3_RX 0x03
-#define SRC_SLIMBUS1_RX0 0x04
-#define SRC_SLIMBUS1_RX1 0x05
-#define SRC_SLIMBUS1_RX2 0x06
-#define SRC_SLIMBUS1_RX3 0x07
-#define SRC_SLIMBUS1_RX4 0x08
-#define SRC_SLIMBUS1_RX5 0x09
-#define SRC_SLIMBUS1_RX6 0x0A
-#define SRC_SLIMBUS1_RX7 0x0B
-#define SRC_DMIC_UP 0x0C
-#define SRC_MCPDM_UP 0x0D
-#define SRC_MCASP_RX0 0x0E
-#define SRC_MCASP_RX1 0x0F
-#define SRC_MCASP_RX2 0x10
-#define SRC_MCASP_RX3 0x11
-#define SRC_CBP_CBPr 0x3F
-#endif/* _ABE_EXT_H_ */
index c462786b5e8a1ca3ba0088a234f2ca0ddbe58f9b..f016cbe6a9853bdaf5088197b7ccaa0462358d4a 100644 (file)
*
* GPL LICENSE SUMMARY
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
/*
* ABE CONST AREA FOR PARAMETERS TRANSLATION
*/
-#define min_mdb (-12000)
-#define max_mdb (3000)
-#define sizeof_db2lin_table (1 + ((max_mdb - min_mdb)/100))
+#define OMAP_AESS_GAIN_MUTED (0x0001<<0)
+#define OMAP_AESS_GAIN_DISABLED (0x0001<<1)
+
+#define OMAP_AESS_GAIN_MIN_MDB (-12000)
+#define OMAP_AESS_GAIN_MAX_MDB (3000)
+#define OMAP_AESS_GAIN_DB2LIN_SIZE (1 + ((OMAP_AESS_GAIN_MAX_MDB - OMAP_AESS_GAIN_MIN_MDB)/100))
-static const u32 abe_db2lin_table[sizeof_db2lin_table] = {
+static const u32 abe_db2lin_table[OMAP_AESS_GAIN_DB2LIN_SIZE] = {
0x00000000, /* SMEM coding of -120 dB */
0x00000000, /* SMEM coding of -119 dB */
0x00000000, /* SMEM coding of -118 dB */
};
/**
- * abe_use_compensated_gain
- * @abe: Pointer on aess handle
- * @on_off: Enable dynamic gain compensation.
- *
- * Selects the automatic Mixer's gain management
- * on_off = 1 allows the "abe_write_gain" to adjust the overall
- * gains of the mixer to be tuned not to create saturation
- *
- */
-int omap_aess_use_compensated_gain(struct omap_aess *abe, int on_off)
-{
- abe->compensated_mixer_gain = on_off;
- return 0;
-}
-EXPORT_SYMBOL(omap_aess_use_compensated_gain);
-
-/**
- * oamp_abe_write_equalizer
- * @abe: Pointer on aess handle
+ * omap_aess_write_equalizer
+ * @aess: Pointer on aess handle
* @id: name of the equalizer
* @param: equalizer coefficients
*
* Load the coefficients in CMEM.
*/
-int omap_aess_write_equalizer(struct omap_aess *abe,
+int omap_aess_write_equalizer(struct omap_aess *aess,
u32 id, struct omap_aess_equ *param)
{
struct omap_aess_addr equ_addr;
switch (id) {
case OMAP_AESS_CMEM_DL1_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_DL2_L_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_DL2_R_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_SDT_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_SDT_F_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_SDT_F_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_96_48_AMIC_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_AMIC_96_48_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_AMIC_96_48_DATA_ID],
sizeof(struct omap_aess_addr));
break;
case OMAP_AESS_CMEM_96_48_DMIC_COEFS_ID:
memcpy(&equ_addr,
- &abe->fw_info->map[OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID],
+ &aess->fw_info->map[OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID],
sizeof(struct omap_aess_addr));
/* three DMIC are clear at the same time DMIC0 DMIC1 DMIC2 */
equ_addr.bytes *= 3;
}
/* reset SMEM buffers before the coefficients are loaded */
- omap_aess_reset_mem(abe, equ_addr);
+ omap_aess_reset_mem(aess, equ_addr);
length = param->equ_length;
src = (u32 *)((param->coef).type1);
- omap_aess_mem_write(abe, abe->fw_info->map[id], src);
+ omap_aess_mem_write(aess, aess->fw_info->map[id], src);
/* reset SMEM buffers after the coefficients are loaded */
- omap_aess_reset_mem(abe, equ_addr);
+ omap_aess_reset_mem(aess, equ_addr);
return 0;
}
EXPORT_SYMBOL(omap_aess_write_equalizer);
/**
* omap_aess_disable_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the gain
*
* Set gain to silence if not already mute or disable.
*/
-int omap_aess_disable_gain(struct omap_aess *abe, u32 id)
+int omap_aess_disable_gain(struct omap_aess *aess, u32 id)
{
u32 f_g;
f_g = GAIN_MUTE;
- if (!(abe->muted_gains_indicator[id] & OMAP_ABE_GAIN_DISABLED)) {
+ if (!(aess->muted_gains_indicator[id] & OMAP_AESS_GAIN_DISABLED)) {
/* Check if we are in mute */
- if (!(abe->muted_gains_indicator[id] &
- OMAP_ABE_GAIN_MUTED)) {
- abe->muted_gains_decibel[id] =
- abe->desired_gains_decibel[id];
+ if (!(aess->muted_gains_indicator[id] &
+ OMAP_AESS_GAIN_MUTED)) {
+ aess->muted_gains_decibel[id] =
+ aess->desired_gains_decibel[id];
/* mute the gain */
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
}
- abe->muted_gains_indicator[id] |= OMAP_ABE_GAIN_DISABLED;
+ aess->muted_gains_indicator[id] |= OMAP_AESS_GAIN_DISABLED;
}
return 0;
}
/**
* omap_aess_enable_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the gain
*
* Restore gain if we are in disable mode.
*/
-int omap_aess_enable_gain(struct omap_aess *abe, u32 id)
+int omap_aess_enable_gain(struct omap_aess *aess, u32 id)
{
u32 f_g;
- if ((abe->muted_gains_indicator[id] & OMAP_ABE_GAIN_DISABLED)) {
+ if ((aess->muted_gains_indicator[id] & OMAP_AESS_GAIN_DISABLED)) {
/* restore the input parameters for mute/unmute */
- f_g = abe->muted_gains_decibel[id];
- abe->muted_gains_indicator[id] &=
- ~OMAP_ABE_GAIN_DISABLED;
+ f_g = aess->muted_gains_decibel[id];
+ aess->muted_gains_indicator[id] &=
+ ~OMAP_AESS_GAIN_DISABLED;
/* unmute the gain */
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
}
return 0;
}
/**
* omap_aess_mute_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the gain
*
* Set gain to silence if not already mute.
*/
-int omap_aess_mute_gain(struct omap_aess *abe, u32 id)
+int omap_aess_mute_gain(struct omap_aess *aess, u32 id)
{
u32 f_g;
f_g = GAIN_MUTE;
- if (!abe->muted_gains_indicator[id]) {
- abe->muted_gains_decibel[id] =
- abe->desired_gains_decibel[id];
+ if (!aess->muted_gains_indicator[id]) {
+ aess->muted_gains_decibel[id] =
+ aess->desired_gains_decibel[id];
/* mute the gain */
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
}
- abe->muted_gains_indicator[id] |= OMAP_ABE_GAIN_MUTED;
+ aess->muted_gains_indicator[id] |= OMAP_AESS_GAIN_MUTED;
return 0;
}
EXPORT_SYMBOL(omap_aess_mute_gain);
/**
* omap_aess_unmute_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the gain
*
* Restore gain after mute.
*/
-int omap_aess_unmute_gain(struct omap_aess *abe, u32 id)
+int omap_aess_unmute_gain(struct omap_aess *aess, u32 id)
{
u32 f_g;
- if ((abe->muted_gains_indicator[id] & OMAP_ABE_GAIN_MUTED)) {
+ if ((aess->muted_gains_indicator[id] & OMAP_AESS_GAIN_MUTED)) {
/* restore the input parameters for mute/unmute */
- f_g = abe->muted_gains_decibel[id];
- abe->muted_gains_indicator[id] &=
- ~OMAP_ABE_GAIN_MUTED;
+ f_g = aess->muted_gains_decibel[id];
+ aess->muted_gains_indicator[id] &=
+ ~OMAP_AESS_GAIN_MUTED;
/* unmute the gain */
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
}
return 0;
}
/**
* omap_aess_write_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: gain name or mixer name
* @f_g: input gain for the mixer
*
* in mute state". A mixer is disabled with a network reconfiguration
* corresponding to an OPP value.
*/
-int omap_aess_write_gain(struct omap_aess *abe,
+int omap_aess_write_gain(struct omap_aess *aess,
u32 id, s32 f_g)
{
u32 lin_g, mixer_target;
s32 gain_index;
- gain_index = ((f_g - min_mdb) / 100);
- gain_index = maximum(gain_index, 0);
- gain_index = minimum(gain_index, sizeof_db2lin_table);
+ gain_index = ((f_g - OMAP_AESS_GAIN_MIN_MDB) / 100);
+ gain_index = max(gain_index, 0);
+ gain_index = min(gain_index, OMAP_AESS_GAIN_DB2LIN_SIZE);
lin_g = abe_db2lin_table[gain_index];
/* save the input parameters for mute/unmute */
- abe->desired_gains_linear[id] = lin_g;
- abe->desired_gains_decibel[id] = f_g;
+ aess->desired_gains_linear[id] = lin_g;
+ aess->desired_gains_decibel[id] = f_g;
/* SMEM address in bytes */
- mixer_target = abe->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
mixer_target += (id<<2);
- if (!abe->compensated_mixer_gain) {
- if (!abe->muted_gains_indicator[id])
- /* load the S_G_Target SMEM table */
- omap_abe_mem_write(abe, OMAP_ABE_SMEM,
- mixer_target, (u32 *)&lin_g,
- sizeof(lin_g));
- else
- /* update muted gain with new value */
- abe->muted_gains_decibel[id] = f_g;
- }
+ if (!aess->muted_gains_indicator[id])
+ /* load the S_G_Target SMEM table */
+ omap_abe_mem_write(aess, OMAP_ABE_SMEM,
+ mixer_target, (u32 *)&lin_g,
+ sizeof(lin_g));
+ else
+ /* update muted gain with new value */
+ aess->muted_gains_decibel[id] = f_g;
+
return 0;
}
EXPORT_SYMBOL(omap_aess_write_gain);
/**
* omap_aess_write_gain_ramp
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: gain name or mixer name
* @ramp: Gaim ramp time
*
* Loads the gain ramp for the associated gain.
*/
-int omap_aess_write_gain_ramp(struct omap_aess *abe, u32 id, u32 ramp)
+int omap_aess_write_gain_ramp(struct omap_aess *aess, u32 id, u32 ramp)
{
u32 mixer_target;
u32 alpha, beta;
u32 ramp_index;
- abe->desired_ramp_delay_ms[id] = ramp;
+ aess->desired_ramp_delay_ms[id] = ramp;
/* SMEM address in bytes */
- mixer_target = abe->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
mixer_target += (id<<2);
- ramp = maximum(minimum(RAMP_MAXLENGTH, ramp), RAMP_MINLENGTH);
+ ramp = max(min(RAMP_MAXLENGTH, ramp), RAMP_MINLENGTH);
/* ramp data should be interpolated in the table instead */
ramp_index = 3;
if ((RAMP_2MS <= ramp) && (ramp < RAMP_5MS))
beta = abe_alpha_iir[ramp_index];
alpha = abe_1_alpha_iir[ramp_index];
/* CMEM bytes address */
- mixer_target = abe->fw_info->map[OMAP_AESS_CMEM_1_ALPHA_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_CMEM_1_ALPHA_ID].offset;
/* a pair of gains is updated once in the firmware */
mixer_target += ((id) >> 1) << 2;
/* load the ramp delay data */
- omap_abe_mem_write(abe, OMAP_ABE_CMEM, mixer_target,
+ omap_abe_mem_write(aess, OMAP_ABE_CMEM, mixer_target,
(u32 *)&alpha, sizeof(alpha));
/* CMEM bytes address */
- mixer_target = abe->fw_info->map[OMAP_AESS_CMEM_ALPHA_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_CMEM_ALPHA_ID].offset;
/* a pair of gains is updated once in the firmware */
mixer_target += ((id) >> 1) << 2;
- omap_abe_mem_write(abe, OMAP_ABE_CMEM, mixer_target,
+ omap_abe_mem_write(aess, OMAP_ABE_CMEM, mixer_target,
(u32 *)&beta, sizeof(beta));
return 0;
}
/**
* omap_aess_write_mixer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the mixer
* @f_g: input gain for the mixer
*
* gain in mute state". A mixer is disabled with a network reconfiguration
* corresponding to an OPP value.
*/
-int omap_aess_write_mixer(struct omap_aess *abe, u32 id, s32 f_g)
+int omap_aess_write_mixer(struct omap_aess *aess, u32 id, s32 f_g)
{
- omap_aess_write_gain(abe, id, f_g);
+ omap_aess_write_gain(aess, id, f_g);
return 0;
}
EXPORT_SYMBOL(omap_aess_write_mixer);
/**
* omap_aess_read_gain
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the mixer
* @f_g: pointer on the gain for the mixer
*
* gain in mute state". A mixer is disabled with a network reconfiguration
* corresponding to an OPP value.
*/
-int omap_aess_read_gain(struct omap_aess *abe, u32 id, u32 *f_g)
+int omap_aess_read_gain(struct omap_aess *aess, u32 id, u32 *f_g)
{
u32 mixer_target, i;
/* SMEM bytes address */
- mixer_target = abe->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_SMEM_GTARGET1_ID].offset;
mixer_target += (id<<2);
- if (!abe->muted_gains_indicator[id]) {
+ if (!aess->muted_gains_indicator[id]) {
/* load the S_G_Target SMEM table */
- omap_abe_mem_read(abe, OMAP_ABE_SMEM, mixer_target,
+ omap_abe_mem_read(aess, OMAP_ABE_SMEM, mixer_target,
(u32 *)f_g, sizeof(*f_g));
- for (i = 0; i < sizeof_db2lin_table; i++) {
+ for (i = 0; i < OMAP_AESS_GAIN_DB2LIN_SIZE; i++) {
if (abe_db2lin_table[i] == *f_g)
goto found;
}
*f_g = 0;
return -1;
found:
- *f_g = (i * 100) + min_mdb;
+ *f_g = (i * 100) + OMAP_AESS_GAIN_MIN_MDB;
} else {
/* update muted gain with new value */
- *f_g = abe->muted_gains_decibel[id];
+ *f_g = aess->muted_gains_decibel[id];
}
return 0;
}
EXPORT_SYMBOL(omap_aess_read_gain);
/**
- * abe_read_mixer
- * @abe: Pointer on aess handle
+ * omap_aess_read_mixer
+ * @aess: Pointer on aess handle
* @id: name of the mixer
* @f_g: pointer on the gain for the mixer
*
* gain in mute state". A mixer is disabled with a network reconfiguration
* corresponding to an OPP value.
*/
-int omap_aess_read_mixer(struct omap_aess *abe, u32 id, u32 *f_g)
+int omap_aess_read_mixer(struct omap_aess *aess, u32 id, u32 *f_g)
{
- omap_aess_read_gain(abe, id, f_g);
+ omap_aess_read_gain(aess, id, f_g);
return 0;
}
EXPORT_SYMBOL(omap_aess_read_mixer);
/**
- * abe_reset_gain_mixer
- * @abe: Pointer on aess handle
+ * omap_aess_reset_gain_mixer
+ * @aess: Pointer on aess handle
* @id: name of the mixer
*
* restart the working gain value of the mixers when a port is enabled
*/
-void omap_aess_reset_gain_mixer(struct omap_aess *abe, u32 id)
+void omap_aess_reset_gain_mixer(struct omap_aess *aess, u32 id)
{
u32 lin_g, mixer_target;
/* SMEM bytes address for the CURRENT gain values */
- mixer_target = abe->fw_info->map[OMAP_AESS_SMEM_GCURRENT_ID].offset;
+ mixer_target = aess->fw_info->map[OMAP_AESS_SMEM_GCURRENT_ID].offset;
mixer_target += (id<<2);
lin_g = 0;
/* load the S_G_Target SMEM table */
- omap_abe_mem_write(abe, OMAP_ABE_SMEM, mixer_target,
+ omap_abe_mem_write(aess, OMAP_ABE_SMEM, mixer_target,
(u32 *)&lin_g, sizeof(lin_g));
}
index aedef8c5b2da4cbf0f4a23ab8ec89321fdf07b6f..eabf2472208089b4381bebaec1d39587a3776c1d 100644 (file)
*
* BSD LICENSE
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#ifndef _ABE_GAIN_H_
#define _ABE_GAIN_H_
-#include "abe_typ.h"
-
-#define OMAP_ABE_GAIN_MUTED (0x0001<<0)
-#define OMAP_ABE_GAIN_DISABLED (0x0001<<1)
+#include "aess-fw.h"
-#define OMAP_AESS_GAIN_DMIC1_LEFT 0
-#define OMAP_AESS_GAIN_DMIC1_RIGHT 1
-#define OMAP_AESS_GAIN_DMIC2_LEFT 2
-#define OMAP_AESS_GAIN_DMIC2_RIGHT 3
-#define OMAP_AESS_GAIN_DMIC3_LEFT 4
-#define OMAP_AESS_GAIN_DMIC3_RIGHT 5
-#define OMAP_AESS_GAIN_AMIC_LEFT 6
-#define OMAP_AESS_GAIN_AMIC_RIGHT 7
-#define OMAP_AESS_GAIN_DL1_LEFT 8
-#define OMAP_AESS_GAIN_DL1_RIGHT 9
-#define OMAP_AESS_GAIN_DL2_LEFT 10
-#define OMAP_AESS_GAIN_DL2_RIGHT 11
-#define OMAP_AESS_GAIN_SPLIT_LEFT 12
-#define OMAP_AESS_GAIN_SPLIT_RIGHT 13
-#define OMAP_AESS_MIXDL1_MM_DL 14
-#define OMAP_AESS_MIXDL1_MM_UL2 15
-#define OMAP_AESS_MIXDL1_VX_DL 16
-#define OMAP_AESS_MIXDL1_TONES 17
-#define OMAP_AESS_MIXDL2_MM_DL 18
-#define OMAP_AESS_MIXDL2_MM_UL2 19
-#define OMAP_AESS_MIXDL2_VX_DL 20
-#define OMAP_AESS_MIXDL2_TONES 21
-#define OMAP_AESS_MIXECHO_DL1 22
-#define OMAP_AESS_MIXECHO_DL2 23
-#define OMAP_AESS_MIXSDT_UL 24
-#define OMAP_AESS_MIXSDT_DL 25
-#define OMAP_AESS_MIXVXREC_MM_DL 26
-#define OMAP_AESS_MIXVXREC_TONES 27
-#define OMAP_AESS_MIXVXREC_VX_UL 28
-#define OMAP_AESS_MIXVXREC_VX_DL 29
-#define OMAP_AESS_MIXAUDUL_MM_DL 30
-#define OMAP_AESS_MIXAUDUL_TONES 31
-#define OMAP_AESS_MIXAUDUL_UPLINK 32
-#define OMAP_AESS_MIXAUDUL_VX_DL 33
-#define OMAP_AESS_GAIN_BTUL_LEFT 34
-#define OMAP_AESS_GAIN_BTUL_RIGHT 35
+#define GAIN_MAXIMUM 3000L
+#define GAIN_24dB 2400L
+#define GAIN_18dB 1800L
+#define GAIN_12dB 1200L
+#define GAIN_6dB 600L
+/* default gain = 1 */
+#define GAIN_0dB 0L
+#define GAIN_M6dB -600L
+#define GAIN_M7dB -700L
+#define GAIN_M12dB -1200L
+#define GAIN_M18dB -1800L
+#define GAIN_M24dB -2400L
+#define GAIN_M30dB -3000L
+#define GAIN_M40dB -4000L
+#define GAIN_M50dB -5000L
+/* muted gain = -120 decibels */
+#define MUTE_GAIN -12000L
+#define GAIN_TOOLOW -13000L
+#define GAIN_MUTE MUTE_GAIN
+#define RAMP_MINLENGTH 0L
+/* ramp_t is in milli- seconds */
+#define RAMP_0MS 0L
+#define RAMP_1MS 1L
+#define RAMP_2MS 2L
+#define RAMP_5MS 5L
+#define RAMP_10MS 10L
+#define RAMP_20MS 20L
+#define RAMP_50MS 50L
+#define RAMP_100MS 100L
+#define RAMP_200MS 200L
+#define RAMP_500MS 500L
+#define RAMP_1000MS 1000L
+#define RAMP_MAXLENGTH 10000L
-void omap_aess_reset_gain_mixer(struct omap_aess *abe, u32 id);
-int omap_aess_write_gain_ramp(struct omap_aess *abe, u32 id, u32 ramp);
+void omap_aess_reset_gain_mixer(struct omap_aess *aess, u32 id);
+int omap_aess_write_gain_ramp(struct omap_aess *aess, u32 id, u32 ramp);
#endif /* _ABE_GAIN_H_ */
index edcf86178ebfd9f82623328fc6d408057ff82a00..c15e6597f296067f0b24c3404869758e428ceea2 100644 (file)
#include "abe_gain.h"
#include "abe_mem.h"
#include "abe_port.h"
-#include "abe_seq.h"
/* FW version that this HAL supports.
* We cheat and since we include the FW in the driver atm we can get the
* Memory map of ABE memory space for PMEM/DMEM/SMEM/DMEM
*/
int omap_aess_init_mem(struct omap_aess *abe, struct device *dev,
- void __iomem **_io_base, u32 *fw_header)
+ void __iomem **_io_base, const void *fw_config)
{
+ u32 *fw_header = (u32*) fw_config;
int i, offset = 0;
u32 count;
if (abe->fw_info == NULL)
return -ENOMEM;
- abe->fw_info->init_table = kzalloc(sizeof(struct omap_aess_init_task), GFP_KERNEL);
- if (abe->fw_info->init_table == NULL) {
- kfree(abe->fw_info);
- return -ENOMEM;
- }
-
/* get mapping */
count = fw_header[offset];
dev_dbg(abe->dev, "Map %d items of size 0x%x at offset 0x%x\n", count,
count = fw_header[offset];
dev_dbg(abe->dev, "Tasks %d of size 0x%x at offset 0x%x\n", count,
sizeof(struct omap_aess_task), offset << 2);
- abe->fw_info->init_table->nb_task = count;
- abe->fw_info->init_table->task = (struct omap_aess_task *)&fw_header[++offset];
+ abe->fw_info->nb_init_task = count;
+ abe->fw_info->init_table = (struct omap_aess_task *)&fw_header[++offset];
offset += (sizeof(struct omap_aess_task) * count) / 4;
/* get ports */
*
* Load the different AESS memories PMEM/DMEM/SMEM/DMEM
*/
-static int omap_aess_load_fw_param(struct omap_aess *abe, u32 *data)
+static int omap_aess_load_fw_param(struct omap_aess *abe, const void *data)
{
u32 pmem_size, dmem_size, smem_size, cmem_size;
- u32 *pmem_ptr, *dmem_ptr, *smem_ptr, *cmem_ptr, *fw_ptr;
+ u32 *pmem_ptr, *dmem_ptr, *smem_ptr, *cmem_ptr;
+ u32 *fw_ptr = (u32*) data;
/* Analyze FW memories banks sizes */
- fw_ptr = data;
abe->firmware_version_number = *fw_ptr++;
pmem_size = *fw_ptr++;
cmem_size = *fw_ptr++;
return 0;
}
-EXPORT_SYMBOL(omap_aess_load_fw_param);
/**
* omap_aess_load_fw - Load ABE Firmware and initialize memories
* @firmware: Pointer on the ABE firmware (after the header)
*
*/
-int omap_aess_load_fw(struct omap_aess *abe, u32 *firmware)
+int omap_aess_load_fw(struct omap_aess *abe, const void *firmware)
{
omap_aess_load_fw_param(abe, firmware);
omap_aess_reset_all_ports(abe);
omap_aess_init_gain_ramp(abe);
omap_aess_build_scheduler_table(abe);
- omap_aess_reset_all_sequence(abe);
omap_aess_select_main_port(abe, OMAP_ABE_PDM_DL_PORT);
return 0;
}
* @abe: Pointer on aess handle
* @firmware: Pointer on the ABE firmware (after the header)
*/
-int omap_aess_reload_fw(struct omap_aess *abe, u32 *firmware)
+int omap_aess_reload_fw(struct omap_aess *abe, const void *firmware)
{
omap_aess_load_fw_param(abe, firmware);
omap_aess_init_gain_ramp(abe);
index 3b90ee2a5309a646e502c8ff46c13a0c03ab5b7a..89ba09f1642348ae208106bce4eb97f8cb0e3755 100644 (file)
#ifndef _ABE_MEM_H_
#define _ABE_MEM_H_
-#ifdef __KERNEL__
#include <asm/io.h>
-#endif
-
-#define OMAP_ABE_DMEM 0
-#define OMAP_ABE_CMEM 1
-#define OMAP_ABE_SMEM 2
-#define OMAP_ABE_PMEM 3
-#define OMAP_ABE_AESS 4
-
-struct omap_aess_addr {
- int bank;
- unsigned int offset;
- unsigned int bytes;
-};
-
-#define OMAP_AESS_DMEM_MULTIFRAME_ID 0
-#define OMAP_AESS_DMEM_DMIC_UL_FIFO_ID 1
-#define OMAP_AESS_DMEM_MCPDM_UL_FIFO_ID 2
-#define OMAP_AESS_DMEM_BT_UL_FIFO_ID 3
-#define OMAP_AESS_DMEM_MM_UL_FIFO_ID 4
-#define OMAP_AESS_DMEM_MM_UL2_FIFO_ID 5
-#define OMAP_AESS_DMEM_VX_UL_FIFO_ID 6
-#define OMAP_AESS_DMEM_MM_DL_FIFO_ID 7
-#define OMAP_AESS_DMEM_VX_DL_FIFO_ID 8
-#define OMAP_AESS_DMEM_TONES_DL_FIFO_ID 9
-#define OMAP_AESS_DMEM_MCASP_DL_FIFO_ID 10
-#define OMAP_AESS_DMEM_BT_DL_FIFO_ID 11
-#define OMAP_AESS_DMEM_MCPDM_DL_FIFO_ID 12
-#define OMAP_AESS_DMEM_MM_EXT_OUT_FIFO_ID 13
-#define OMAP_AESS_DMEM_MM_EXT_IN_FIFO_ID 14
-#define OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID 15
-#define OMAP_AESS_SMEM_DMIC1_96_48_DATA_ID 16
-#define OMAP_AESS_SMEM_DMIC2_96_48_DATA_ID 17
-#define OMAP_AESS_SMEM_AMIC_96_48_DATA_ID 18
-#define OMAP_AESS_SMEM_BT_UL_ID 19
-#define OMAP_AESS_SMEM_BT_UL_8_48_HP_DATA_ID 20
-#define OMAP_AESS_SMEM_BT_UL_8_48_LP_DATA_ID 21
-#define OMAP_AESS_SMEM_BT_UL_16_48_HP_DATA_ID 22
-#define OMAP_AESS_SMEM_BT_UL_16_48_LP_DATA_ID 23
-#define OMAP_AESS_SMEM_MM_UL2_ID 24
-#define OMAP_AESS_SMEM_MM_UL_ID 25
-#define OMAP_AESS_SMEM_VX_UL_ID 26
-#define OMAP_AESS_SMEM_VX_UL_48_8_HP_DATA_ID 27
-#define OMAP_AESS_SMEM_VX_UL_48_8_LP_DATA_ID 28
-#define OMAP_AESS_SMEM_VX_UL_48_16_HP_DATA_ID 29
-#define OMAP_AESS_SMEM_VX_UL_48_16_LP_DATA_ID 30
-#define OMAP_AESS_SMEM_MM_DL_ID 31
-#define OMAP_AESS_SMEM_MM_DL_44P1_ID 32
-#define OMAP_AESS_SMEM_MM_DL_44P1_XK_ID 33
-#define OMAP_AESS_SMEM_VX_DL_ID 34
-#define OMAP_AESS_SMEM_VX_DL_8_48_HP_DATA_ID 35
-#define OMAP_AESS_SMEM_VX_DL_8_48_LP_DATA_ID 36
-#define OMAP_AESS_SMEM_VX_DL_8_48_OSR_LP_DATA_ID 37
-#define OMAP_AESS_SMEM_VX_DL_16_48_HP_DATA_ID 38
-#define OMAP_AESS_SMEM_VX_DL_16_48_LP_DATA_ID 39
-#define OMAP_AESS_SMEM_TONES_ID 40
-#define OMAP_AESS_SMEM_TONES_44P1_ID 41
-#define OMAP_AESS_SMEM_TONES_44P1_XK_ID 42
-#define OMAP_AESS_SMEM_MCASP1_ID 43
-#define OMAP_AESS_SMEM_BT_DL_ID 44
-#define OMAP_AESS_SMEM_BT_DL_8_48_OSR_LP_DATA_ID 45
-#define OMAP_AESS_SMEM_BT_DL_48_8_HP_DATA_ID 46
-#define OMAP_AESS_SMEM_BT_DL_48_8_LP_DATA_ID 47
-#define OMAP_AESS_SMEM_BT_DL_48_16_HP_DATA_ID 48
-#define OMAP_AESS_SMEM_BT_DL_48_16_LP_DATA_ID 49
-#define OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID 50
-#define OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID 51
-#define OMAP_AESS_SMEM_EARP_48_96_LP_DATA_ID 52
-#define OMAP_AESS_SMEM_IHF_48_96_LP_DATA_ID 53
-#define OMAP_AESS_SMEM_DC_HS_ID 54
-#define OMAP_AESS_SMEM_DC_HF_ID 55
-#define OMAP_AESS_SMEM_SDT_F_DATA_ID 56
-#define OMAP_AESS_SMEM_GTARGET1_ID 57
-#define OMAP_AESS_SMEM_GCURRENT_ID 58
-#define OMAP_AESS_CMEM_DL1_COEFS_ID 59
-#define OMAP_AESS_CMEM_DL2_L_COEFS_ID 60
-#define OMAP_AESS_CMEM_DL2_R_COEFS_ID 61
-#define OMAP_AESS_CMEM_SDT_COEFS_ID 62
-#define OMAP_AESS_CMEM_96_48_AMIC_COEFS_ID 63
-#define OMAP_AESS_CMEM_96_48_DMIC_COEFS_ID 64
-#define OMAP_AESS_CMEM_1_ALPHA_ID 65
-#define OMAP_AESS_CMEM_ALPHA_ID 66
-#define OMAP_AESS_DMEM_SLOT23_CTRL_ID 67
-#define OMAP_AESS_DMEM_AUPLINKROUTING_ID 68
-#define OMAP_AESS_DMEM_MAXTASKBYTESINSLOT_ID 69
-#define OMAP_AESS_DMEM_PINGPONGDESC_ID 70
-#define OMAP_AESS_DMEM_IODESCR_ID 71
-#define OMAP_AESS_DMEM_MCUIRQFIFO_ID 72
-#define OMAP_AESS_DMEM_PING_ID 73
-#define OMAP_AESS_DMEM_DEBUG_FIFO_ID 74
-#define OMAP_AESS_DMEM_DEBUG_FIFO_HAL_ID 75
-#define OMAP_AESS_DMEM_DEBUG_HAL_TASK_ID 76
-#define OMAP_AESS_DMEM_LOOPCOUNTER_ID 77
-#define OMAP_AESS_DMEM_FWMEMINITDESCR_ID 78
-
-#ifdef __KERNEL__
+#include <linux/pm_runtime.h>
/* Distinction between Read and Write from/to ABE memory
* is useful for simulation tool */
static inline void omap_abe_mem_write(struct omap_aess *abe, int bank,
u32 offset, u32 *src, size_t bytes)
{
+ pm_runtime_get_sync(abe->dev);
memcpy((void __force *)(abe->io_base[bank] + offset), src, bytes);
+ pm_runtime_put_sync(abe->dev);
}
static inline void omap_abe_mem_read(struct omap_aess *abe, int bank,
u32 offset, u32 *dest, size_t bytes)
{
+ pm_runtime_get_sync(abe->dev);
memcpy(dest, (void __force *)(abe->io_base[bank] + offset), bytes);
+ pm_runtime_put_sync(abe->dev);
}
static inline u32 omap_aess_reg_readl(struct omap_aess *abe, u32 offset)
{
- return __raw_readl(abe->io_base[OMAP_ABE_AESS] + offset);
+ u32 ret;
+ pm_runtime_get_sync(abe->dev);
+ ret = __raw_readl(abe->io_base[OMAP_ABE_AESS] + offset);
+ pm_runtime_put_sync(abe->dev);
+ return ret;
}
static inline void omap_aess_reg_writel(struct omap_aess *abe,
u32 offset, u32 val)
{
+ pm_runtime_get_sync(abe->dev);
__raw_writel(val, (abe->io_base[OMAP_ABE_AESS] + offset));
+ pm_runtime_put_sync(abe->dev);
}
static inline void *omap_abe_reset_mem(struct omap_aess *abe, int bank,
u32 offset, size_t bytes)
{
- return memset((u32 *)(abe->io_base[bank] + offset), 0, bytes);
+ void *ret;
+ pm_runtime_get_sync(abe->dev);
+ ret = memset((u32 *)(abe->io_base[bank] + offset), 0, bytes);
+ pm_runtime_put_sync(abe->dev);
+ return ret;
}
static inline void omap_aess_mem_write(struct omap_aess *abe,
struct omap_aess_addr addr, u32 *src)
{
- memcpy((void __force *)(abe->io_base[addr.bank] + addr.offset), src, addr.bytes);
+ pm_runtime_get_sync(abe->dev);
+ memcpy((void __force *)(abe->io_base[addr.bank] + addr.offset),
+ src, addr.bytes);
+ pm_runtime_put_sync(abe->dev);
}
static inline void omap_aess_mem_read(struct omap_aess *abe,
struct omap_aess_addr addr, u32 *dest)
{
- memcpy(dest, (void __force *)(abe->io_base[addr.bank] + addr.offset), addr.bytes);
+ pm_runtime_get_sync(abe->dev);
+ memcpy(dest, (void __force *)(abe->io_base[addr.bank] + addr.offset),
+ addr.bytes);
+ pm_runtime_put_sync(abe->dev);
}
static inline void *omap_aess_reset_mem(struct omap_aess *abe,
struct omap_aess_addr addr)
{
- return memset((void __force *)(abe->io_base[addr.bank] + addr.offset), 0, addr.bytes);
+ void *ret;
+ pm_runtime_get_sync(abe->dev);
+ ret = memset((void __force *)(abe->io_base[addr.bank] + addr.offset),
+ 0, addr.bytes);
+ pm_runtime_put_sync(abe->dev);
+ return ret;
}
-#endif /* __KERNEL__ */
#endif /*_ABE_MEM_H_*/
index 2fcc382471c4bf7178b24028aecf9665c0a83bd3..02a903502a85396278250fecb25e48903cce63d2 100644 (file)
*
* GPL LICENSE SUMMARY
*
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
#include <linux/err.h>
#include <linux/slab.h>
-#include "abe_typ.h"
+#include "aess-fw.h"
#include "abe.h"
#include "abe_port.h"
#include "abe_dbg.h"
#include "abe_mem.h"
#include "abe_gain.h"
-#include "abe_seq.h"
-
-#include "abe_def.h"
+#include "abe_aess.h"
/*
* GLOBAL DEFINITION
*/
+#define ABE_ATC_DMIC_DMA_REQ 1
+#define ABE_ATC_MCPDMDL_DMA_REQ 2
+#define ABE_ATC_MCPDMUL_DMA_REQ 3
+
+/* nb of samples to route */
+#define NBROUTE_UL 16
+
+/* ATC REGISTERS SIZE in bytes */
+#define ABE_ATC_DESC_SIZE 512
+
#define ATC_SIZE 8 /* 8 bytes per descriptors */
struct omap_abe_atc_desc {
unsigned desen:1;
};
-struct ABE_SPingPongDescriptor {
+struct omap_aess_pingpong_desc {
/* 0: [W] asrc output used for the next ASRC call (+/- 1 / 0) */
u16 drift_ASRC;
/* 2: [W] asrc output used for controlling the number of
static u32 abe_dma_port_iter_factor(struct omap_aess_data_format *f);
static u32 abe_dma_port_iteration(struct omap_aess_data_format *f);
-void omap_aess_decide_main_port(struct omap_aess *abe);
-int omap_aess_init_io_tasks(struct omap_aess *abe, u32 id,
+void omap_aess_decide_main_port(struct omap_aess *aess);
+int omap_aess_init_io_tasks(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *format,
struct omap_aess_port_protocol *prot);
void abe_init_dma_t(u32 id, struct omap_aess_port_protocol *prot);
-extern void omap_aess_init_asrc_vx_dl(struct omap_aess *abe, s32 dppm);
-extern void omap_aess_init_asrc_vx_ul(struct omap_aess *abe, s32 dppm);
+extern void omap_aess_init_asrc_vx_dl(struct omap_aess *aess, s32 dppm);
+extern void omap_aess_init_asrc_vx_ul(struct omap_aess *aess, s32 dppm);
/**
* omap_aess_reset_port
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* Stop the port activity and reload default parameters on the associated
* processing features.
* Clears the internal AE buffers.
*/
-int omap_aess_reset_port(struct omap_aess *abe, u32 id)
+int omap_aess_reset_port(struct omap_aess *aess, u32 id)
{
- struct omap_aess_port *port = abe->fw_info->port;
+ struct omap_aess_port *port = aess->fw_info->port;
- abe_port[id] = port[id];
+ memcpy(&abe_port[id], &port[id], sizeof(struct omap_aess_port));
return 0;
}
-static void omap_aess_update_scheduling_table(struct omap_aess *abe,
+static void omap_aess_update_scheduling_table(struct omap_aess *aess,
struct omap_aess_init_task *init_task,
int enable)
{
for (i = 0; i < init_task->nb_task; i++) {
task = &init_task->task[i];
if (enable)
- abe->MultiFrame[task->frame][task->slot] = task->task;
- else
- abe->MultiFrame[task->frame][task->slot] = 0;
- }
-}
-
-static void omap_aess_update_scheduling_table1(struct omap_aess *abe,
- struct omap_aess_init_task1 *init_task,
- int enable)
-{
- int i;
- struct omap_aess_task *task;
-
- for (i = 0; i < init_task->nb_task; i++) {
- task = &init_task->task[i];
- if (enable)
- abe->MultiFrame[task->frame][task->slot] = task->task;
+ aess->MultiFrame[task->frame][task->slot] = task->task;
else
- abe->MultiFrame[task->frame][task->slot] = 0;
+ aess->MultiFrame[task->frame][task->slot] = 0;
}
}
-static u32 omap_aess_update_io_task(struct omap_aess *abe,
+static u32 omap_aess_update_io_task(struct omap_aess *aess,
struct omap_aess_io_task *io_task,
int enable)
{
for (i = 0; i < io_task->nb_task; i++) {
task = &io_task->task[i];
if (enable)
- abe->MultiFrame[task->frame][task->slot] = task->task;
+ aess->MultiFrame[task->frame][task->slot] = task->task;
else
- abe->MultiFrame[task->frame][task->slot] = 0;
+ aess->MultiFrame[task->frame][task->slot] = 0;
}
return io_task->smem;
}
-static u32 omap_aess_update_io_task1(struct omap_aess *abe,
+static u32 omap_aess_update_io_task1(struct omap_aess *aess,
struct omap_aess_io_task1 *io_task,
int enable)
{
for (i = 0; i < io_task->nb_task; i++) {
task = &io_task->task[i];
if (enable)
- abe->MultiFrame[task->frame][task->slot] = task->task;
+ aess->MultiFrame[task->frame][task->slot] = task->task;
else
- abe->MultiFrame[task->frame][task->slot] = 0;
+ aess->MultiFrame[task->frame][task->slot] = 0;
}
return io_task->smem;
}
/**
- * abe_build_scheduler_table
- * @abe: Pointer on aess handle
+ * omap_aess_build_scheduler_table
+ * @aess: Pointer on aess handle
*
* Initialize Audio Engine scheduling table for ABE internal
* processing. The content of the scheduling table is provided
* by the firmware header. It can be changed according to the
* ABE graph.
*/
-void omap_aess_build_scheduler_table(struct omap_aess *abe)
+void omap_aess_build_scheduler_table(struct omap_aess *aess)
{
- u16 i, n;
+ struct omap_aess_task *task;
u16 aUplinkMuxing[NBROUTE_UL];
+ int i, n;
/* Initialize default scheduling table */
- memset(abe->MultiFrame, 0, sizeof(abe->MultiFrame));
- omap_aess_update_scheduling_table(abe, abe->fw_info->init_table, 1);
+ memset(aess->MultiFrame, 0, sizeof(aess->MultiFrame));
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
- (u32 *)abe->MultiFrame);
+ for (i = 0; i < aess->fw_info->nb_init_task; i++) {
+ task = &aess->fw_info->init_table[i];
+ aess->MultiFrame[task->frame][task->slot] = task->task;
+ }
+
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
+ (u32 *)aess->MultiFrame);
/* reset the uplink router */
- n = abe->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID].bytes >> 1;
+ n = aess->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID].bytes >> 1;
for (i = 0; i < n; i++)
- aUplinkMuxing[i] = abe->fw_info->label_id[OMAP_AESS_BUFFER_ZERO_ID];
+ aUplinkMuxing[i] = aess->fw_info->label_id[OMAP_AESS_BUFFER_ZERO_ID];
- omap_aess_mem_write(abe,
- abe->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID],
+ omap_aess_mem_write(aess,
+ aess->fw_info->map[OMAP_AESS_DMEM_AUPLINKROUTING_ID],
(u32 *)aUplinkMuxing);
}
/**
* abe_dma_port_copy_subroutine_id
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @port_id: ABE port ID
*
* returns the index of the function doing the copy in I/O tasks
*/
-static u32 abe_dma_port_copy_subroutine_id(struct omap_aess *abe, u32 port_id)
+static u32 abe_dma_port_copy_subroutine_id(struct omap_aess *aess, u32 port_id)
{
u32 sub_id;
if (abe_port[port_id].protocol.direction == ABE_ATC_DIRECTION_IN) {
switch (abe_port[port_id].format.samp_format) {
- case MONO_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_MSB_ID];
+ case OMAP_AESS_FORMAT_MONO_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_MSB_ID];
break;
- case MONO_RSHIFTED_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_RSHIFTED_16_ID];
+ case OMAP_AESS_FORMAT_MONO_RSHIFTED_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_RSHIFTED_16_ID];
break;
- case STEREO_RSHIFTED_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_RSHIFTED_16_ID];
+ case OMAP_AESS_FORMAT_STEREO_RSHIFTED_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_RSHIFTED_16_ID];
break;
- case STEREO_16_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_16_16_ID];
+ case OMAP_AESS_FORMAT_STEREO_16_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_16_16_ID];
break;
- case MONO_16_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_16_16_ID];
+ case OMAP_AESS_FORMAT_MONO_16_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_MONO_16_16_ID];
break;
- case STEREO_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_MSB_ID];
+ case OMAP_AESS_FORMAT_STEREO_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_D2S_STEREO_MSB_ID];
break;
- case SIX_MSB:
+ case OMAP_AESS_FORMAT_SIX_MSB:
if (port_id == OMAP_ABE_DMIC_PORT) {
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_DMIC_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_DMIC_ID];
break;
}
default:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
break;
}
} else {
switch (abe_port[port_id].format.samp_format) {
- case MONO_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_MSB_ID];
+ case OMAP_AESS_FORMAT_MONO_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_MSB_ID];
break;
- case MONO_RSHIFTED_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_RSHIFTED_16_ID];
+ case OMAP_AESS_FORMAT_MONO_RSHIFTED_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_RSHIFTED_16_ID];
break;
- case STEREO_RSHIFTED_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_RSHIFTED_16_ID];
+ case OMAP_AESS_FORMAT_STEREO_RSHIFTED_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_RSHIFTED_16_ID];
break;
- case STEREO_16_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_16_16_ID];
+ case OMAP_AESS_FORMAT_STEREO_16_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_16_16_ID];
break;
- case MONO_16_16:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_16_16_ID];
+ case OMAP_AESS_FORMAT_MONO_16_16:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_MONO_16_16_ID];
break;
- case STEREO_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_MSB_ID];
+ case OMAP_AESS_FORMAT_STEREO_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_S2D_STEREO_MSB_ID];
break;
- case SIX_MSB:
+ case OMAP_AESS_FORMAT_SIX_MSB:
if (port_id == OMAP_ABE_PDM_DL_PORT) {
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_MCPDM_DL_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_MCPDM_DL_ID];
break;
}
if (port_id == OMAP_ABE_MM_UL_PORT) {
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
break;
}
- case THREE_MSB:
- case FOUR_MSB:
- case FIVE_MSB:
- case SEVEN_MSB:
- case EIGHT_MSB:
- case NINE_MSB:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
+ case OMAP_AESS_FORMAT_THREE_MSB:
+ case OMAP_AESS_FORMAT_FOUR_MSB:
+ case OMAP_AESS_FORMAT_FIVE_MSB:
+ case OMAP_AESS_FORMAT_SEVEN_MSB:
+ case OMAP_AESS_FORMAT_EIGHT_MSB:
+ case OMAP_AESS_FORMAT_NINE_MSB:
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
break;
default:
- sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
break;
}
}
@@ -415,161 +412,161 @@ static u32 abe_dma_port_copy_subroutine_id(struct omap_aess *abe, u32 port_id)
/**
* abe_clean_temporay buffers
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* clear temporary buffers according to the port ID.
*/
-static void omap_aess_clean_temporary_buffers(struct omap_aess *abe, u32 id)
+static void omap_aess_clean_temporary_buffers(struct omap_aess *aess, u32 id)
{
switch (id) {
case OMAP_ABE_DMIC_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_DMIC_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DMIC1_96_48_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DMIC2_96_48_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_DMIC_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DMIC1_96_48_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DMIC2_96_48_DATA_ID]);
/* reset working values of the gain, target gain is preserved */
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC1_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC1_RIGHT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC2_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC2_RIGHT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC3_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DMIC3_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC1_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC1_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC2_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC2_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC3_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DMIC3_RIGHT);
break;
case OMAP_ABE_PDM_UL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MCPDM_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_AMIC_96_48_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MCPDM_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_AMIC_96_48_DATA_ID]);
/* reset working values of the gain, target gain is preserved */
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_AMIC_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_AMIC_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_AMIC_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_AMIC_RIGHT);
break;
case OMAP_ABE_BT_VX_UL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_BT_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_8_48_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_8_48_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_16_48_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_UL_16_48_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_BT_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_8_48_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_8_48_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_16_48_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_UL_16_48_LP_DATA_ID]);
/* reset working values of the gain, target gain is preserved */
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_BTUL_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_BTUL_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_BTUL_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_BTUL_RIGHT);
break;
case OMAP_ABE_MM_UL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_UL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_UL_ID]);
break;
case OMAP_ABE_MM_UL2_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_UL2_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_UL2_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_UL2_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_UL2_ID]);
break;
case OMAP_ABE_VX_UL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_VX_UL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_8_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_8_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_16_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_16_LP_DATA_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXAUDUL_UPLINK);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_VX_UL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_8_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_8_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_16_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_UL_48_16_LP_DATA_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXAUDUL_UPLINK);
break;
case OMAP_ABE_MM_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_DL_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_DL_44P1_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MM_DL_44P1_XK_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL1_MM_DL);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL2_MM_DL);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_DL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_DL_44P1_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MM_DL_44P1_XK_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL1_MM_DL);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL2_MM_DL);
break;
case OMAP_ABE_VX_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_VX_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_OSR_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_16_48_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_VX_DL_16_48_LP_DATA_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL1_VX_DL);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL2_VX_DL);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_VX_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_8_48_OSR_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_16_48_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_VX_DL_16_48_LP_DATA_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL1_VX_DL);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL2_VX_DL);
break;
case OMAP_ABE_TONES_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_TONES_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_TONES_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_TONES_44P1_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_TONES_44P1_XK_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL1_TONES);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXDL2_TONES);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_TONES_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_TONES_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_TONES_44P1_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_TONES_44P1_XK_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL1_TONES);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXDL2_TONES);
break;
case OMAP_ABE_MCASP_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MCASP_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_MCASP1_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MCASP_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_MCASP1_ID]);
break;
case OMAP_ABE_BT_VX_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_BT_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_BT_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_ID]);
#if !defined(CONFIG_SND_OMAP4_ABE_USE_ALT_FW)
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_8_48_OSR_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_8_48_OSR_LP_DATA_ID]);
#endif
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_8_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_8_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_16_HP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_16_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_8_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_8_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_16_HP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_BT_DL_48_16_LP_DATA_ID]);
break;
case OMAP_ABE_PDM_DL_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MCPDM_DL_FIFO_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_EARP_48_96_LP_DATA_ID]);
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_SMEM_IHF_48_96_LP_DATA_ID]);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DL1_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DL1_RIGHT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DL2_LEFT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_GAIN_DL2_RIGHT);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXSDT_UL);
- omap_aess_reset_gain_mixer(abe, OMAP_AESS_MIXSDT_DL);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MCPDM_DL_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_EARP_48_96_LP_DATA_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_SMEM_IHF_48_96_LP_DATA_ID]);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DL1_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DL1_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DL2_LEFT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_GAIN_DL2_RIGHT);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXSDT_UL);
+ omap_aess_reset_gain_mixer(aess, OMAP_AESS_MIXSDT_DL);
break;
case OMAP_ABE_MM_EXT_OUT_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_EXT_OUT_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_EXT_OUT_FIFO_ID]);
break;
case OMAP_ABE_MM_EXT_IN_PORT:
- omap_aess_reset_mem(abe, abe->fw_info->map[OMAP_AESS_DMEM_MM_EXT_IN_FIFO_ID]);
+ omap_aess_reset_mem(aess, aess->fw_info->map[OMAP_AESS_DMEM_MM_EXT_IN_FIFO_ID]);
break;
}
}
/**
* omap_aess_disable_enable_dma_request
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
* @on_off: Enable/Disable
*
* Enable/Disable DMA request associated to a port.
*/
-static void omap_aess_disable_enable_dma_request(struct omap_aess *abe, u32 id,
+static void omap_aess_disable_enable_dma_request(struct omap_aess *aess, u32 id,
u32 on_off)
{
u8 desc_third_word[4], irq_dmareq_field;
- struct ABE_SIODescriptor sio_desc;
- struct ABE_SPingPongDescriptor desc_pp;
+ struct omap_aess_io_desc sio_desc;
+ struct omap_aess_pingpong_desc desc_pp;
struct omap_aess_addr addr;
- if (abe_port[id].protocol.protocol_switch == PINGPONG_PORT_PROT) {
+ if (abe_port[id].protocol.protocol_switch == OMAP_AESS_PORT_PINGPONG) {
irq_dmareq_field = (u8) (on_off *
abe_port[id].protocol.p.prot_pingpong.irq_data);
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
addr.offset += (u32)&(desc_pp.data_size) - (u32)&(desc_pp);
addr.bytes = 4;
- omap_aess_mem_read(abe, addr, (u32 *)desc_third_word);
+ omap_aess_mem_read(aess, addr, (u32 *)desc_third_word);
desc_third_word[2] = irq_dmareq_field;
- omap_aess_mem_write(abe, addr, (u32 *)desc_third_word);
+ omap_aess_mem_write(aess, addr, (u32 *)desc_third_word);
} else {
/* serial interface: sync ATC with Firmware activity */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID],
sizeof(struct omap_aess_addr));
- addr.offset += id * sizeof(struct ABE_SIODescriptor);
- addr.bytes = sizeof(struct ABE_SIODescriptor);
- omap_aess_mem_read(abe, addr, (u32 *)&sio_desc);
+ addr.offset += id * sizeof(struct omap_aess_io_desc);
+ addr.bytes = sizeof(struct omap_aess_io_desc);
+ omap_aess_mem_read(aess, addr, (u32 *)&sio_desc);
if (on_off) {
- if (abe_port[id].protocol.protocol_switch != SERIAL_PORT_PROT)
+ if (abe_port[id].protocol.protocol_switch != OMAP_AESS_PORT_SERIAL)
sio_desc.atc_irq_data =
(u8) abe_port[id].protocol.p.prot_dmareq.
dma_data;
@@ -578,45 +575,45 @@ static void omap_aess_disable_enable_dma_request(struct omap_aess *abe, u32 id,
sio_desc.atc_irq_data = 0;
sio_desc.on_off = 0;
}
- omap_aess_mem_write(abe, addr, (u32 *)&sio_desc);
+ omap_aess_mem_write(aess, addr, (u32 *)&sio_desc);
}
}
/**
* omap_aess_enable_dma_request
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* Enable DMA request associated to the port ID
*/
-static void omap_aess_enable_dma_request(struct omap_aess *abe, u32 id)
+static void omap_aess_enable_dma_request(struct omap_aess *aess, u32 id)
{
- omap_aess_disable_enable_dma_request(abe, id, 1);
+ omap_aess_disable_enable_dma_request(aess, id, 1);
}
/**
* omap_aess_disable_dma_request
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* Disable DMA request associated to the port ID
*/
-static void omap_aess_disable_dma_request(struct omap_aess *abe, u32 id)
+static void omap_aess_disable_dma_request(struct omap_aess *aess, u32 id)
{
- omap_aess_disable_enable_dma_request(abe, id, 0);
+ omap_aess_disable_enable_dma_request(aess, id, 0);
}
/**
* omap_aess_init_atc
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
*
* load the DMEM ATC/AESS descriptor associated to the port ID.
* ATC is describing the internal flexible FIFO inside the DMEM
* connected to HW IP (eg McBSP/DMIC/...)
*/
-static void omap_aess_init_atc(struct omap_aess *abe, u32 id)
+static void omap_aess_init_atc(struct omap_aess *aess, u32 id)
{
u8 iter;
s32 datasize;
atc_desc.wrpt = 0 + ((JITTER_MARGIN+1) * datasize);
switch ((abe_port[id]).protocol.protocol_switch) {
- case SERIAL_PORT_PROT:
+ case OMAP_AESS_PORT_SERIAL:
atc_desc.cbdir = (abe_port[id]).protocol.direction;
atc_desc.cbsize =
(abe_port[id]).protocol.p.prot_serial.buf_size;
atc_desc.destid =
abe_atc_dstid[(abe_port[id]).protocol.p.prot_serial.
desc_addr >> 3];
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_serial.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
break;
- case DMIC_PORT_PROT:
+ case OMAP_AESS_PORT_DMIC:
atc_desc.cbdir = ABE_ATC_DIRECTION_IN;
atc_desc.cbsize = (abe_port[id]).protocol.p.prot_dmic.buf_size;
atc_desc.badd =
((abe_port[id]).protocol.p.prot_dmic.buf_addr) >> 4;
atc_desc.iter = DMIC_ITER;
atc_desc.srcid = abe_atc_srcid[ABE_ATC_DMIC_DMA_REQ];
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(ABE_ATC_DMIC_DMA_REQ*ATC_SIZE),
(u32 *)&atc_desc, sizeof(atc_desc));
break;
- case MCPDMDL_PORT_PROT:
+ case OMAP_AESS_PORT_MCPDMDL:
atc_desc.cbdir = ABE_ATC_DIRECTION_OUT;
atc_desc.cbsize =
(abe_port[id]).protocol.p.prot_mcpdmdl.buf_size;
((abe_port[id]).protocol.p.prot_mcpdmdl.buf_addr) >> 4;
atc_desc.iter = MCPDM_DL_ITER;
atc_desc.destid = abe_atc_dstid[ABE_ATC_MCPDMDL_DMA_REQ];
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE),
(u32 *)&atc_desc, sizeof(atc_desc));
break;
- case MCPDMUL_PORT_PROT:
+ case OMAP_AESS_PORT_MCPDMUL:
atc_desc.cbdir = ABE_ATC_DIRECTION_IN;
atc_desc.cbsize =
(abe_port[id]).protocol.p.prot_mcpdmul.buf_size;
((abe_port[id]).protocol.p.prot_mcpdmul.buf_addr) >> 4;
atc_desc.iter = MCPDM_UL_ITER;
atc_desc.srcid = abe_atc_srcid[ABE_ATC_MCPDMUL_DMA_REQ];
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE),
(u32 *)&atc_desc, sizeof(atc_desc));
break;
- case PINGPONG_PORT_PROT:
+ case OMAP_AESS_PORT_PINGPONG:
/* software protocol, nothing to do on ATC */
break;
- case DMAREQ_PORT_PROT:
+ case OMAP_AESS_PORT_DMAREQ:
atc_desc.cbdir = (abe_port[id]).protocol.direction;
atc_desc.cbsize =
(abe_port[id]).protocol.p.prot_dmareq.buf_size;
[(abe_port[id]).protocol.p.prot_dmareq.
desc_addr >> 3];
}
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
break;
/**
* omap_aess_disable_data_transfer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port id
*
* disables the ATC descriptor and stop IO/port activities
* disable the IO task (@f = 0)
* clear ATC DMEM buffer, ATC enabled
*/
-int omap_aess_disable_data_transfer(struct omap_aess *abe, u32 id)
+int omap_aess_disable_data_transfer(struct omap_aess *aess, u32 id)
{
switch (id) {
case OMAP_ABE_MM_DL_PORT:
- abe->MultiFrame[18][1] = 0;
+ aess->MultiFrame[18][1] = 0;
break;
default:
break;
/* local host variable status= "port is running" */
abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_IDLE;
/* disable DMA requests */
- omap_aess_disable_dma_request(abe, id);
+ omap_aess_disable_dma_request(aess, id);
/* disable ATC transfers */
- omap_aess_init_atc(abe, id);
- omap_aess_clean_temporary_buffers(abe, id);
+ omap_aess_init_atc(aess, id);
+ omap_aess_clean_temporary_buffers(aess, id);
/* select the main port based on the desactivation of this port */
- omap_aess_decide_main_port(abe);
+ omap_aess_decide_main_port(aess);
return 0;
}
/**
* omap_aess_enable_data_transfer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port id
*
* enables the ATC descriptor
* reset ATC pointers
* enable the IO task (@f <> 0)
*/
-int omap_aess_enable_data_transfer(struct omap_aess *abe, u32 id)
+int omap_aess_enable_data_transfer(struct omap_aess *aess, u32 id)
{
struct omap_aess_port_protocol *protocol;
struct omap_aess_data_format format;
- omap_aess_clean_temporary_buffers(abe, id);
+ omap_aess_clean_temporary_buffers(aess, id);
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].task), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].task), 1);
switch (id) {
case OMAP_ABE_PDM_UL_PORT:
/* initializes the ABE ATC descriptors in DMEM for BE ports */
protocol = &(abe_port[id].protocol);
format = abe_port[id].format;
- omap_aess_init_atc(abe, id);
- omap_aess_init_io_tasks(abe, id, &format, protocol);
+ omap_aess_init_atc(aess, id);
+ omap_aess_init_io_tasks(aess, id, &format, protocol);
break;
case OMAP_ABE_MM_DL_PORT:
protocol = &(abe_port[OMAP_ABE_MM_DL_PORT].protocol);
- if (protocol->protocol_switch == PINGPONG_PORT_PROT)
- omap_aess_update_scheduling_table1(abe, &abe->fw_info->ping_pong->task, 1);
+ if (protocol->protocol_switch == OMAP_AESS_PORT_PINGPONG)
+ omap_aess_update_scheduling_table(aess, &aess->fw_info->ping_pong->task, 1);
break;
default:
break;
}
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
- (u32 *)abe->MultiFrame);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
+ (u32 *)aess->MultiFrame);
/* local host variable status= "port is running" */
abe_port[id].status = OMAP_ABE_PORT_ACTIVITY_RUNNING;
/* enable DMA requests */
- omap_aess_enable_dma_request(abe, id);
+ omap_aess_enable_dma_request(aess, id);
/* select the main port based on the activation of this new port */
- omap_aess_decide_main_port(abe);
+ omap_aess_decide_main_port(aess);
return 0;
}
EXPORT_SYMBOL(omap_aess_enable_data_transfer);
+/**
+ * omap_aess_read_port_address
+ * @aess: Pointer on aess handle
+ * @port: port name
+ * @aess_dma: output pointer to the DMA iteration and data destination pointer
+ *
+ * This API returns the address of the DMA register used on this audio port.
+ * Depending on the protocol being used, adds the base address offset L3
+ * (DMA) or MPU (ARM)
+ */
+static void omap_aess_read_port_address(struct omap_aess *aess, u32 port,
+ struct omap_aess_dma *aess_dma)
+{
+ struct omap_aess_dma_offset *dma_offset = &abe_port[port].dma;
+
+ switch (abe_port[port].protocol.protocol_switch) {
+ case OMAP_AESS_PORT_PINGPONG:
+ /* return the base address of the buffer in L3 and L4 spaces */
+ aess_dma->data = (void *)(dma_offset->data +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
+ break;
+ case OMAP_AESS_PORT_DMAREQ:
+ /* return the CBPr(L3), DMEM(L3), DMEM(L4) address */
+ aess_dma->data = (void *)(dma_offset->data +
+ ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_ATC_BASE_OFFSET_MPU);
+ break;
+ default:
+ break;
+ }
+ aess_dma->iter = dma_offset->iter;
+}
+
/**
* omap_aess_connect_cbpr_dmareq_port
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
* @f: desired data format
* @d: desired dma_request line (0..7)
- * @returned_dma_t: returned pointer to the base address of the CBPr register and number of
- * samples to exchange during a DMA_request.
+ * @aess_dma: returned pointer to the base address of the CBPr register and
+ * number of samples to exchange during a DMA_request.
*
* enables the data echange between a DMA and the ABE through the
* CBPr registers of AESS.
*/
-int omap_aess_connect_cbpr_dmareq_port(struct omap_aess *abe,
- u32 id, struct omap_aess_data_format *f,
- u32 d,
- struct omap_aess_dma *returned_dma_t)
+void omap_aess_connect_cbpr_dmareq_port(struct omap_aess *aess, u32 id,
+ struct omap_aess_data_format *f, u32 d,
+ struct omap_aess_dma *aess_dma)
{
- abe_port[id] = ((struct omap_aess_port *)abe->fw_info->port)[id];
- (abe_port[id]).format = (*f);
- abe_port[id].protocol.protocol_switch = DMAREQ_PORT_PROT;
+ omap_aess_reset_port(aess, id);
+
+ memcpy(&abe_port[id].format, f, sizeof(*f));
+
+ abe_port[id].protocol.protocol_switch = OMAP_AESS_PORT_DMAREQ;
abe_port[id].protocol.p.prot_dmareq.iter = abe_dma_port_iteration(f);
- abe_port[id].protocol.p.prot_dmareq.dma_addr = ABE_DMASTATUS_RAW;
+ abe_port[id].protocol.p.prot_dmareq.dma_addr = OMAP_AESS_DMASTATUS_RAW;
abe_port[id].protocol.p.prot_dmareq.dma_data = (1 << d);
+
/* load the dma_t with physical information from AE memory mapping */
- abe_init_dma_t(id, &((abe_port[id]).protocol));
+ abe_init_dma_t(id, &abe_port[id].protocol);
/* load the ATC descriptors - disabled */
- omap_aess_init_atc(abe, id);
+ omap_aess_init_atc(aess, id);
/* load the micro-task parameters */
- omap_aess_init_io_tasks(abe, id, &((abe_port[id]).format),
- &((abe_port[id]).protocol));
+ omap_aess_init_io_tasks(aess, id, &abe_port[id].format,
+ &abe_port[id].protocol);
abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
- /* return the dma pointer address */
- omap_aess_read_port_address(abe, id, returned_dma_t);
- return 0;
+ if (aess_dma)
+ omap_aess_read_port_address(aess, id, aess_dma);
}
EXPORT_SYMBOL(omap_aess_connect_cbpr_dmareq_port);
/**
* omap_aess_connect_serial_port()
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
* @f: data format
* @mcbsp_id: peripheral ID (McBSP #1, #2, #3)
+ * @aess_dma: returned pointer to the base address of the CBPr register and
+ * number of samples to exchange during a DMA_request.
*
* Operations : enables the data echanges between a McBSP and an ATC buffer in
* DMEM. This API is used connect 48kHz McBSP streams to MM_DL and 8/16kHz
* voice streams to VX_UL, VX_DL, BT_VX_UL, BT_VX_DL. It abstracts the
* abe_write_port API.
*/
-int omap_aess_connect_serial_port(struct omap_aess *abe,
- u32 id, struct omap_aess_data_format *f,
- u32 mcbsp_id)
+void omap_aess_connect_serial_port(struct omap_aess *aess, u32 id,
+ struct omap_aess_data_format *f,
+ u32 mcbsp_id, struct omap_aess_dma *aess_dma)
{
- abe_port[id] = ((struct omap_aess_port *)abe->fw_info->port)[id];
- (abe_port[id]).format = (*f);
- (abe_port[id]).protocol.protocol_switch = SERIAL_PORT_PROT;
+ omap_aess_reset_port(aess, id);
+
+ memcpy(&abe_port[id].format, f, sizeof(*f));
+
+ abe_port[id].protocol.protocol_switch = OMAP_AESS_PORT_SERIAL;
/* McBSP peripheral connected to ATC */
- (abe_port[id]).protocol.p.prot_serial.desc_addr = mcbsp_id*ATC_SIZE;
+ abe_port[id].protocol.p.prot_serial.desc_addr = mcbsp_id * ATC_SIZE;
/* check the iteration of ATC */
- (abe_port[id]).protocol.p.prot_serial.iter =
- abe_dma_port_iter_factor(f);
+ abe_port[id].protocol.p.prot_serial.iter = abe_dma_port_iter_factor(f);
/* load the ATC descriptors - disabled */
- omap_aess_init_atc(abe, id);
+ omap_aess_init_atc(aess, id);
/* load the micro-task parameters */
- omap_aess_init_io_tasks(abe, id, &((abe_port[id]).format),
- &((abe_port[id]).protocol));
+ omap_aess_init_io_tasks(aess, id, &abe_port[id].format,
+ &abe_port[id].protocol);
abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
- return 0;
+ if (aess_dma)
+ omap_aess_read_port_address(aess, id, aess_dma);
}
EXPORT_SYMBOL(omap_aess_connect_serial_port);
-/**
- * omap_aess_read_port_address
- * @abe: Pointer on aess handle
- * @port: port name
- * @dma2: output pointer to the DMA iteration and data destination pointer
- *
- * This API returns the address of the DMA register used on this audio port.
- * Depending on the protocol being used, adds the base address offset L3
- * (DMA) or MPU (ARM)
- */
-int omap_aess_read_port_address(struct omap_aess *abe,
- u32 port, struct omap_aess_dma *dma2)
-{
- struct omap_aess_dma_offset dma1;
- u32 protocol_switch;
-
- dma1 = (abe_port[port]).dma;
- protocol_switch = abe_port[port].protocol.protocol_switch;
- switch (protocol_switch) {
- case PINGPONG_PORT_PROT:
- /* return the base address of the buffer in L3 and L4 spaces */
- (*dma2).data = (void *)(dma1.data +
- ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
- (*dma2).l3_dmem = (void *)(dma1.data +
- ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
- (*dma2).l4_dmem = (void *)(dma1.data +
- ABE_DEFAULT_BASE_ADDRESS_L4 + ABE_DMEM_BASE_OFFSET_MPU);
- break;
- case DMAREQ_PORT_PROT:
- /* return the CBPr(L3), DMEM(L3), DMEM(L4) address */
- (*dma2).data = (void *)(dma1.data +
- ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_ATC_BASE_OFFSET_MPU);
- (*dma2).l3_dmem =
- (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr +
- ABE_DEFAULT_BASE_ADDRESS_L3 + ABE_DMEM_BASE_OFFSET_MPU);
- (*dma2).l4_dmem =
- (void *)((abe_port[port]).protocol.p.prot_dmareq.buf_addr +
- ABE_DEFAULT_BASE_ADDRESS_L4 + ABE_DMEM_BASE_OFFSET_MPU);
- break;
- default:
- break;
- }
- (*dma2).iter = (dma1.iter);
-
- return 0;
-}
-EXPORT_SYMBOL(omap_aess_read_port_address);
-
/**
* abe_init_dma_t
* @id: ABE port ID
dma.data = 0;
dma.iter = 0;
switch (prot->protocol_switch) {
- case PINGPONG_PORT_PROT:
+ case OMAP_AESS_PORT_PINGPONG:
for (idx = 0; idx < 32; idx++) {
if (((prot->p).prot_pingpong.irq_data) ==
(u32) (1 << idx))
dma.data = (prot->p).prot_pingpong.buf_addr >> 2;
dma.iter = (prot->p).prot_pingpong.buf_size >> 2;
break;
- case DMAREQ_PORT_PROT:
+ case OMAP_AESS_PORT_DMAREQ:
for (idx = 0; idx < 32; idx++) {
if (((prot->p).prot_dmareq.dma_data) ==
(u32) (1 << idx))
(prot->p).prot_dmareq.desc_addr =
((CBPr_DMA_RTX0 + idx)*ATC_SIZE);
break;
- case SLIMBUS_PORT_PROT:
- case SERIAL_PORT_PROT:
- case DMIC_PORT_PROT:
- case MCPDMDL_PORT_PROT:
- case MCPDMUL_PORT_PROT:
+ case OMAP_AESS_PORT_SERIAL:
+ case OMAP_AESS_PORT_DMIC:
+ case OMAP_AESS_PORT_MCPDMDL:
+ case OMAP_AESS_PORT_MCPDMUL:
default:
break;
}
/**
* omap_aess_enable_atc
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
*
* Enable ATC associated to the port ID
*/
-static void omap_aess_enable_atc(struct omap_aess *abe, u32 id)
+static void omap_aess_enable_atc(struct omap_aess *aess, u32 id)
{
struct omap_abe_atc_desc atc_desc;
- omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_read(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
atc_desc.desen = 1;
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
/**
* omap_aess_disable_atc
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
*
* Enable ATC associated to the port ID
*/
-static void omap_aess_disable_atc(struct omap_aess *abe, u32 id)
+static void omap_aess_disable_atc(struct omap_aess *aess, u32 id)
{
struct omap_abe_atc_desc atc_desc;
- omap_abe_mem_read(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_read(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
atc_desc.desen = 0;
- omap_abe_mem_write(abe, OMAP_ABE_DMEM,
+ omap_abe_mem_write(aess, OMAP_ABE_DMEM,
(abe_port[id]).protocol.p.prot_dmareq.desc_addr,
(u32 *)&atc_desc, sizeof(atc_desc));
/**
* omap_aess_init_io_tasks
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
* @format: data format being used
* @prot: protocol being used
* For Write to DMEM usually THR1/THR2 = 2/0
* UP_1/2 =X+1/X-1
*/
-int omap_aess_init_io_tasks(struct omap_aess *abe, u32 id,
+int omap_aess_init_io_tasks(struct omap_aess *aess, u32 id,
struct omap_aess_data_format *format,
struct omap_aess_port_protocol *prot)
{
u32 copy_func_index2, atc_desc_address1, atc_desc_address2;
struct omap_aess_addr addr;
- if (prot->protocol_switch == PINGPONG_PORT_PROT) {
- struct ABE_SPingPongDescriptor desc_pp;
+ if (prot->protocol_switch == OMAP_AESS_PORT_PINGPONG) {
+ struct omap_aess_pingpong_desc desc_pp;
memset(&desc_pp, 0, sizeof(desc_pp));
return -AESS_EINVAL;
}
if (abe_port[id].format.f == 44100)
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->ping_pong->tsk_freq[2].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->ping_pong->tsk_freq[2].task), 1);
else
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->ping_pong->tsk_freq[3].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->ping_pong->tsk_freq[3].task), 1);
/* able interrupt to be generated at the first frame */
desc_pp.split_addr1 = 1;
- copy_func_index = (u8) abe_dma_port_copy_subroutine_id(abe, id);
+ copy_func_index = (u8) abe_dma_port_copy_subroutine_id(aess, id);
dmareq_addr = abe_port[id].protocol.p.prot_pingpong.irq_addr;
dmareq_field = abe_port[id].protocol.p.prot_pingpong.irq_data;
datasize = abe_dma_port_iter_factor(format);
desc_pp.data_size = (u8) datasize;
/* address comunicated in Bytes */
desc_pp.workbuff_BaseAddr =
- (u16) (abe->base_address_pingpong[1]);
+ (u16) (aess->base_address_pingpong[1]);
/* size comunicated in XIO sample */
desc_pp.workbuff_Samples = 0;
desc_pp.nextbuff0_BaseAddr =
- (u16) (abe->base_address_pingpong[0]);
+ (u16) (aess->base_address_pingpong[0]);
desc_pp.nextbuff1_BaseAddr =
- (u16) (abe->base_address_pingpong[1]);
- if (dmareq_addr == ABE_DMASTATUS_RAW) {
+ (u16) (aess->base_address_pingpong[1]);
+ if (dmareq_addr == OMAP_AESS_DMASTATUS_RAW) {
desc_pp.nextbuff0_Samples =
- (u16) ((abe->size_pingpong >> 2) / datasize);
+ (u16) ((aess->size_pingpong >> 2) / datasize);
desc_pp.nextbuff1_Samples =
- (u16) ((abe->size_pingpong >> 2) / datasize);
+ (u16) ((aess->size_pingpong >> 2) / datasize);
} else {
desc_pp.nextbuff0_Samples = 0;
desc_pp.nextbuff1_Samples = 0;
/* send a DMA req to fill B0 with N samples
abe_block_copy (COPY_FROM_HOST_TO_ABE,
ABE_ATC,
- ABE_DMASTATUS_RAW,
+ OMAP_AESS_DMASTATUS_RAW,
&(abe_port[id].protocol.p.prot_pingpong.irq_data),
4); */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
addr.bytes = sizeof(desc_pp);
- omap_aess_mem_write(abe, addr, (u32 *)&desc_pp);
+ omap_aess_mem_write(aess, addr, (u32 *)&desc_pp);
} else {
- struct ABE_SIODescriptor sio_desc;
+ struct omap_aess_io_desc sio_desc;
int idx;
switch (abe_port[id].format.f) {
memset(&sio_desc, 0, sizeof(sio_desc));
- io_sub_id = ABE_DMASTATUS_RAW;
- dmareq_addr = ABE_DMASTATUS_RAW;
+ io_sub_id = OMAP_AESS_DMASTATUS_RAW;
+ dmareq_addr = OMAP_AESS_DMASTATUS_RAW;
dmareq_field = 0;
atc_desc_address1 = 0;
atc_desc_address2 = 0;
datasize = abe_dma_port_iter_factor(format);
x_io = (u8) abe_dma_port_iteration(format);
nsamp = (x_io / datasize);
- atc_ptr_saved2 = abe->fw_info->label_id[OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID] + id;
- atc_ptr_saved = abe->fw_info->label_id[OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID] + id;
+ atc_ptr_saved2 = aess->fw_info->label_id[OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID] + id;
+ atc_ptr_saved = aess->fw_info->label_id[OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID] + id;
smem1 = abe_port[id].smem_buffer1;
smem2 = abe_port[id].smem_buffer2;
smem3 = abe_port[id].smem_buffer2;
- copy_func_index1 = (u8) abe_dma_port_copy_subroutine_id(abe, id);
+ copy_func_index1 = (u8) abe_dma_port_copy_subroutine_id(aess, id);
- before_func_index = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
- after_func_index = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
- copy_func_index2 = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ before_func_index = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ after_func_index = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
+ copy_func_index2 = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
switch (prot->protocol_switch) {
- case DMIC_PORT_PROT:
+ case OMAP_AESS_PORT_DMIC:
/* DMIC port is read in two steps */
x_io = x_io >> 1;
nsamp = nsamp >> 1;
atc_desc_address1 = (ABE_ATC_DMIC_DMA_REQ*ATC_SIZE);
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
- case MCPDMDL_PORT_PROT:
+ case OMAP_AESS_PORT_MCPDMDL:
/* PDMDL port is written to in two steps */
x_io = x_io >> 1;
atc_desc_address1 = (ABE_ATC_MCPDMDL_DMA_REQ*ATC_SIZE);
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
- case MCPDMUL_PORT_PROT:
+ case OMAP_AESS_PORT_MCPDMUL:
atc_desc_address1 = (ABE_ATC_MCPDMUL_DMA_REQ*ATC_SIZE);
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
- break;
- case SLIMBUS_PORT_PROT:
- atc_desc_address1 = abe_port[id].protocol.p.prot_slimbus.desc_addr1;
- atc_desc_address2 = abe_port[id].protocol.p.prot_slimbus.desc_addr2;
- copy_func_index2 = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_NULL_ID];
- /* @@@@@@
- #define SPLIT_SMEM_CFPID 9
- #define MERGE_SMEM_CFPID 10
- #define SPLIT_TDM_12_CFPID 11
- #define MERGE_TDM_12_CFPID 12
- */
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
- case SERIAL_PORT_PROT: /* McBSP/McASP */
+ case OMAP_AESS_PORT_SERIAL: /* McBSP/McASP */
atc_desc_address1 = (s16) abe_port[id].protocol.p.prot_serial.desc_addr;
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
- case DMAREQ_PORT_PROT: /* DMA w/wo CBPr */
+ case OMAP_AESS_PORT_DMAREQ: /* DMA w/wo CBPr */
dmareq_addr = abe_port[id].protocol.p.prot_dmareq.dma_addr;
dmareq_field = 0;
atc_desc_address1 = abe_port[id].protocol.p.prot_dmareq.desc_addr;
- io_sub_id = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
+ io_sub_id = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_IO_IP_ID];
break;
}
/* special situation of the PING_PONG protocol which
*/
switch (id) {
case OMAP_ABE_VX_DL_PORT:
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].task), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].task), 1);
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->port[id].tsk_freq[idx].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->port[id].tsk_freq[idx].task), 1);
/* check for 8kHz/16kHz */
if (idx < 2) {
/* ASRC set only for McBSP */
- if ((prot->protocol_switch == SERIAL_PORT_PROT)) {
+ if ((prot->protocol_switch == OMAP_AESS_PORT_SERIAL)) {
if ((abe_port[OMAP_ABE_VX_DL_PORT].status ==
OMAP_ABE_PORT_ACTIVITY_IDLE) &&
(abe_port[OMAP_ABE_VX_UL_PORT].status ==
/* the 1st opened port is VX_DL_PORT
* both VX_UL ASRC and VX_DL ASRC will add/remove sample
* referring to VX_DL flow_counter */
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].tsk_freq[idx].asrc.serial), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].tsk_freq[idx].asrc.serial), 1);
/* Init VX_UL ASRC & VX_DL ASRC and enable its adaptation */
- omap_aess_init_asrc_vx_ul(abe, -250);
- omap_aess_init_asrc_vx_dl(abe, 250);
+ omap_aess_init_asrc_vx_ul(aess, -250);
+ omap_aess_init_asrc_vx_dl(aess, 250);
} else {
/* Do nothing, Scheduling Table has already been patched */
}
} else {
/* Enable only ASRC on VXDL port*/
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].tsk_freq[idx].asrc.cbpr), 1);
- omap_aess_init_asrc_vx_dl(abe, 0);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].tsk_freq[idx].asrc.cbpr), 1);
+ omap_aess_init_asrc_vx_dl(aess, 0);
}
}
break;
case OMAP_ABE_VX_UL_PORT:
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].task), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].task), 1);
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->port[id].tsk_freq[idx].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->port[id].tsk_freq[idx].task), 1);
/* check for 8kHz/16kHz */
if (idx < 2) {
/* ASRC set only for McBSP */
- if ((prot->protocol_switch == SERIAL_PORT_PROT)) {
+ if ((prot->protocol_switch == OMAP_AESS_PORT_SERIAL)) {
if ((abe_port[OMAP_ABE_VX_DL_PORT].status ==
OMAP_ABE_PORT_ACTIVITY_IDLE) &&
(abe_port[OMAP_ABE_VX_UL_PORT].status ==
/* the 1st opened port is VX_UL_PORT
* both VX_UL ASRC and VX_DL ASRC will add/remove sample
* referring to VX_UL flow_counter */
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].tsk_freq[idx].asrc.serial), 1);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].tsk_freq[idx].asrc.serial), 1);
/* Init VX_UL ASRC & VX_DL ASRC and enable its adaptation */
- omap_aess_init_asrc_vx_ul(abe, -250);
- omap_aess_init_asrc_vx_dl(abe, 250);
+ omap_aess_init_asrc_vx_ul(aess, -250);
+ omap_aess_init_asrc_vx_dl(aess, 250);
} else {
/* Do nothing, Scheduling Table has already been patched */
}
} else {
/* Enable only ASRC on VXUL port*/
- omap_aess_update_scheduling_table1(abe, &(abe->fw_info->port[id].tsk_freq[idx].asrc.cbpr), 1);
- omap_aess_init_asrc_vx_ul(abe, 0);
+ omap_aess_update_scheduling_table(aess, &(aess->fw_info->port[id].tsk_freq[idx].asrc.cbpr), 1);
+ omap_aess_init_asrc_vx_ul(aess, 0);
}
}
break;
case OMAP_ABE_BT_VX_UL_PORT:
case OMAP_ABE_MM_DL_PORT:
case OMAP_ABE_TONES_DL_PORT:
- smem1 = omap_aess_update_io_task1(abe, &(abe->fw_info->port[id].tsk_freq[idx].task), 1);
+ smem1 = omap_aess_update_io_task1(aess, &(aess->fw_info->port[id].tsk_freq[idx].task), 1);
break;
case OMAP_ABE_MM_UL_PORT:
- copy_func_index1 = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
- before_func_index = abe->fw_info->fct_id[OMAP_AESS_COPY_FCT_ROUTE_MM_UL_ID];
+ copy_func_index1 = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_MM_UL_ID];
+ before_func_index = aess->fw_info->fct_id[OMAP_AESS_COPY_FCT_ROUTE_MM_UL_ID];
break;
case OMAP_ABE_MM_EXT_IN_PORT:
/* set the SMEM buffer -- programming sequence */
- smem1 = abe->fw_info->label_id[OMAP_AESS_BUFFER_MM_EXT_IN_ID];
+ smem1 = aess->fw_info->label_id[OMAP_AESS_BUFFER_MM_EXT_IN_ID];
break;
case OMAP_ABE_PDM_DL_PORT:
case OMAP_ABE_PDM_UL_PORT:
sio_desc.data_size2 = (u8) datasize2;
sio_desc.copy_f_index2 = (u8) copy_func_index2;
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID],
sizeof(struct omap_aess_addr));
- addr.bytes = sizeof(struct ABE_SIODescriptor);
- addr.offset += (id * sizeof(struct ABE_SIODescriptor));
+ addr.bytes = sizeof(struct omap_aess_io_desc);
+ addr.offset += (id * sizeof(struct omap_aess_io_desc));
- omap_aess_mem_write(abe, addr, (u32 *)&sio_desc);
+ omap_aess_mem_write(aess, addr, (u32 *)&sio_desc);
}
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
- (u32 *)abe->MultiFrame);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
+ (u32 *)aess->MultiFrame);
return 0;
}
/**
* omap_aess_select_main_port - Select stynchronization port for Event generator.
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
*
* tells the FW which is the reference stream for adjusting
* the processing on 23/24/25 slots
*/
-int omap_aess_select_main_port(struct omap_aess *abe, u32 id)
+int omap_aess_select_main_port(struct omap_aess *aess, u32 id)
{
u32 selection;
/* flow control */
- selection = abe->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID].offset + id * sizeof(struct ABE_SIODescriptor) +
- offsetof(struct ABE_SIODescriptor, flow_counter);
+ selection = aess->fw_info->map[OMAP_AESS_DMEM_IODESCR_ID].offset + id * sizeof(struct omap_aess_io_desc) +
+ offsetof(struct omap_aess_io_desc, flow_counter);
/* when the main port is a sink port from AESS point of view
the sign the firmware task analysis must be changed */
selection &= 0xFFFFL;
if (abe_port[id].protocol.direction == ABE_ATC_DIRECTION_IN)
selection |= 0x80000;
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_SLOT23_CTRL_ID],
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_SLOT23_CTRL_ID],
&selection);
return 0;
}
*/
static u32 abe_valid_port_for_synchro(u32 id)
{
- if ((abe_port[id].protocol.protocol_switch == DMAREQ_PORT_PROT) ||
- (abe_port[id].protocol.protocol_switch == PINGPONG_PORT_PROT) ||
+ if ((abe_port[id].protocol.protocol_switch == OMAP_AESS_PORT_DMAREQ) ||
+ (abe_port[id].protocol.protocol_switch == OMAP_AESS_PORT_PINGPONG) ||
(abe_port[id].status != OMAP_ABE_PORT_ACTIVITY_RUNNING))
return 0;
else
/**
* omap_aess_decide_main_port() - Decide main port selection for synchronization.
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* Lock up on all ABE port in order to find out the correct port for the
* Audio Engine synchronization.
*/
-void omap_aess_decide_main_port(struct omap_aess *abe)
+void omap_aess_decide_main_port(struct omap_aess *aess)
{
u32 id, id_not_found;
/* if no port is currently activated, the default one is PDM_DL */
if (id_not_found)
- omap_aess_select_main_port(abe, OMAP_ABE_PDM_DL_PORT);
+ omap_aess_select_main_port(aess, OMAP_ABE_PDM_DL_PORT);
else
- omap_aess_select_main_port(abe, abe_port_priority[id]);
+ omap_aess_select_main_port(aess, abe_port_priority[id]);
}
/**
@@ -1468,34 +1441,34 @@ static void abe_format_switch(struct omap_aess_data_format *f, u32 *iter, u32 *m
}
switch (f->samp_format) {
- case MONO_MSB:
- case MONO_RSHIFTED_16:
- case STEREO_16_16:
+ case OMAP_AESS_FORMAT_MONO_MSB:
+ case OMAP_AESS_FORMAT_MONO_RSHIFTED_16:
+ case OMAP_AESS_FORMAT_STEREO_16_16:
*mulfac = 1;
break;
- case STEREO_MSB:
- case STEREO_RSHIFTED_16:
+ case OMAP_AESS_FORMAT_STEREO_MSB:
+ case OMAP_AESS_FORMAT_STEREO_RSHIFTED_16:
*mulfac = 2;
break;
- case THREE_MSB:
+ case OMAP_AESS_FORMAT_THREE_MSB:
*mulfac = 3;
break;
- case FOUR_MSB:
+ case OMAP_AESS_FORMAT_FOUR_MSB:
*mulfac = 4;
break;
- case FIVE_MSB:
+ case OMAP_AESS_FORMAT_FIVE_MSB:
*mulfac = 5;
break;
- case SIX_MSB:
+ case OMAP_AESS_FORMAT_SIX_MSB:
*mulfac = 6;
break;
- case SEVEN_MSB:
+ case OMAP_AESS_FORMAT_SEVEN_MSB:
*mulfac = 7;
break;
- case EIGHT_MSB:
+ case OMAP_AESS_FORMAT_EIGHT_MSB:
*mulfac = 8;
break;
- case NINE_MSB:
+ case OMAP_AESS_FORMAT_NINE_MSB:
*mulfac = 9;
break;
default:
@@ -1503,7 +1476,7 @@ static void abe_format_switch(struct omap_aess_data_format *f, u32 *iter, u32 *m
break;
}
*iter = (n_freq * (*mulfac));
- if (f->samp_format == MONO_16_16)
+ if (f->samp_format == OMAP_AESS_FORMAT_MONO_16_16)
*iter /= 2;
}
/**
* omap_aess_dma_port_iter_factor
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @f: port format
*
* returns the multiplier factor to apply during data move with DMEM
*/
-static u32 omap_aess_dma_port_iter_factor(struct omap_aess *abe, struct omap_aess_data_format *f)
+static u32 omap_aess_dma_port_iter_factor(struct omap_aess *aess, struct omap_aess_data_format *f)
{
u32 iter, mulfac;
@@ -1552,36 +1525,36 @@ static u32 omap_aess_dma_port_iter_factor(struct omap_aess *abe, struct omap_aes
/**
* omap_aess_mono_mixer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: name of the mixer (MIXDL1, MIXDL2 or MIXAUDUL)
* @on_off: enable/disable flag
*
* This API Programs DL1Mixer or DL2Mixer to output mono data
* on both left and right data paths.
*/
-int omap_aess_mono_mixer(struct omap_aess *abe, u32 id, u32 on_off)
+int omap_aess_mono_mixer(struct omap_aess *aess, u32 id, u32 on_off)
{
struct omap_aess_task *task;
switch (id) {
case MIXDL1:
- task = &abe->fw_info->dl1_mono_mixer[on_off];
+ task = &aess->fw_info->dl1_mono_mixer[on_off];
break;
case MIXDL2:
- task = &abe->fw_info->dl2_mono_mixer[on_off];
+ task = &aess->fw_info->dl2_mono_mixer[on_off];
break;
case MIXAUDUL:
- task = &abe->fw_info->audul_mono_mixer[on_off];
+ task = &aess->fw_info->audul_mono_mixer[on_off];
break;
default:
return 0;
break;
}
- abe->MultiFrame[task->frame][task->slot] = task->task;
+ aess->MultiFrame[task->frame][task->slot] = task->task;
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
- (u32 *)abe->MultiFrame);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_DMEM_MULTIFRAME_ID],
+ (u32 *)aess->MultiFrame);
return 0;
}
/**
* omap_aess_check_activity - Check if some ABE activity.
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
*
* Check if any ABE ports are running.
* return 1: still activity on ABE
* return 0: no more activity on ABE. Event generator can be stopped
*
*/
-int omap_aess_check_activity(struct omap_aess *abe)
+int omap_aess_check_activity(struct omap_aess *aess)
{
int i, ret = 0;
/**
* abe_write_pdmdl_offset - write the desired offset on the DL1/DL2 paths
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @path: DL1 or DL2 port
* @offset_left: integer value that will be added on all PDM left samples
* @offset_right: integer value that will be added on all PDM right samples
* Set ABE internal DC offset cancellation parameter for McPDM IP. Value
* depends on TWL604x triming parameters.
*/
-void omap_aess_write_pdmdl_offset(struct omap_aess *abe, u32 path,
+void omap_aess_write_pdmdl_offset(struct omap_aess *aess, u32 path,
u32 offset_left, u32 offset_right)
{
u32 offset[2];
switch (path) {
case 1:
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_SMEM_DC_HS_ID], offset);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_SMEM_DC_HS_ID], offset);
break;
case 2:
- omap_aess_mem_write(abe, abe->fw_info->map[OMAP_AESS_SMEM_DC_HF_ID], offset);
+ omap_aess_mem_write(aess, aess->fw_info->map[OMAP_AESS_SMEM_DC_HF_ID], offset);
break;
default:
break;
/**
* oamp_abe_set_ping_pong_buffer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @port: ABE port ID
* @n_bytes: Size of Ping/Pong buffer
*
* Updates the next ping-pong buffer with "size" bytes copied from the
* host processor. This API notifies the FW that the data transfer is done.
*/
-int omap_aess_set_ping_pong_buffer(struct omap_aess *abe, u32 port, u32 n_bytes)
+int omap_aess_set_ping_pong_buffer(struct omap_aess *aess, u32 port, u32 n_bytes)
{
u32 struct_offset, n_samples, datasize, base_and_size;
- struct ABE_SPingPongDescriptor desc_pp;
+ struct omap_aess_pingpong_desc desc_pp;
struct omap_aess_addr addr;
/* ping_pong is only supported on MM_DL */
@@ -1664,14 +1637,14 @@ int omap_aess_set_ping_pong_buffer(struct omap_aess *abe, u32 port, u32 n_bytes)
}
/* translates the number of bytes in samples */
/* data size in DMEM words */
- datasize = omap_aess_dma_port_iter_factor(abe, (struct omap_aess_data_format *)&((abe_port[port]).format));
+ datasize = omap_aess_dma_port_iter_factor(aess, (struct omap_aess_data_format *)&((abe_port[port]).format));
/* data size in bytes */
datasize = datasize << 2;
n_samples = n_bytes / datasize;
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
- addr.bytes = sizeof(struct ABE_SPingPongDescriptor);
- omap_aess_mem_read(abe, addr, (u32 *)&desc_pp);
+ addr.bytes = sizeof(struct omap_aess_pingpong_desc);
+ omap_aess_mem_read(aess, addr, (u32 *)&desc_pp);
/*
* read the port SIO descriptor and extract the current pointer
* address after reading the counter
@@ -1686,14 +1659,14 @@ int omap_aess_set_ping_pong_buffer(struct omap_aess *abe, u32 port, u32 n_bytes)
base_and_size = desc_pp.nextbuff1_BaseAddr;
}
- base_and_size = abe->pp_buf_addr[abe->pp_buf_id_next];
- abe->pp_buf_id_next = (abe->pp_buf_id_next + 1) & 0x03;
+ base_and_size = aess->pp_buf_addr[aess->pp_buf_id_next];
+ aess->pp_buf_id_next = (aess->pp_buf_id_next + 1) & 0x03;
base_and_size = (base_and_size & 0xFFFFL) + (n_samples << 16);
addr.offset += struct_offset;
addr.bytes = 4;
- omap_aess_mem_write(abe, addr, (u32 *)&base_and_size);
+ omap_aess_mem_write(aess, addr, (u32 *)&base_and_size);
return 0;
}
/**
* omap_aess_read_offset_from_ping_buffer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
* @n: returned address of the offset
* from the ping buffer start address (in samples)
* Computes the current firmware ping pong read pointer location,
* expressed in samples, as the offset from the start address of ping buffer.
*/
-int omap_aess_read_offset_from_ping_buffer(struct omap_aess *abe,
+int omap_aess_read_offset_from_ping_buffer(struct omap_aess *aess,
u32 id, u32 *n)
{
- struct ABE_SPingPongDescriptor desc_pp;
+ struct omap_aess_pingpong_desc desc_pp;
struct omap_aess_addr addr;
/* ping_pong is only supported on MM_DL */
return -AESS_EINVAL;
} else {
/* read the port SIO ping pong descriptor */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
- addr.bytes = sizeof(struct ABE_SPingPongDescriptor);
- omap_aess_mem_read(abe, addr, (u32 *)&desc_pp);
+ addr.bytes = sizeof(struct omap_aess_pingpong_desc);
+ omap_aess_mem_read(aess, addr, (u32 *)&desc_pp);
/* extract the current ping pong buffer read pointer based on
the value of the counter */
if ((desc_pp.counter & 0x1) == 0) {
desc_pp.workbuff_Samples;
}
switch (abe_port[OMAP_ABE_MM_DL_PORT].format.samp_format) {
- case MONO_MSB:
- case MONO_RSHIFTED_16:
- case STEREO_16_16:
- *n += abe->pp_buf_id * abe->size_pingpong / 4;
+ case OMAP_AESS_FORMAT_MONO_MSB:
+ case OMAP_AESS_FORMAT_MONO_RSHIFTED_16:
+ case OMAP_AESS_FORMAT_STEREO_16_16:
+ *n += aess->pp_buf_id * aess->size_pingpong / 4;
break;
- case STEREO_MSB:
- case STEREO_RSHIFTED_16:
- *n += abe->pp_buf_id * abe->size_pingpong / 8;
+ case OMAP_AESS_FORMAT_STEREO_MSB:
+ case OMAP_AESS_FORMAT_STEREO_RSHIFTED_16:
+ *n += aess->pp_buf_id * aess->size_pingpong / 8;
break;
default:
aess_err("Bad data format for Ping-pong buffer");
}
EXPORT_SYMBOL(omap_aess_read_offset_from_ping_buffer);
-/**
- * omap_aess_irq_ping_pong
- * @abe: Pointer on aess handle
- *
- * Call the respective subroutine depending on the IRQ FIFO content:
- * APS interrupts : IRQ_FIFO[31:28] = IRQtag_APS,
- * IRQ_FIFO[27:16] = APS_IRQs, IRQ_FIFO[15:0] = loopCounter
- * SEQ interrupts : IRQ_FIFO[31:28] = IRQtag_COUNT,
- * IRQ_FIFO[27:16] = Count_IRQs, IRQ_FIFO[15:0] = loopCounter
- * Ping-Pong Interrupts : IRQ_FIFO[31:28] = IRQtag_PP,
- * IRQ_FIFO[27:16] = PP_MCU_IRQ, IRQ_FIFO[15:0] = loopCounter
- */
-void omap_aess_irq_ping_pong(struct omap_aess *abe)
-{
- /* first IRQ doesn't represent a buffer transference completion */
- if (abe->pp_first_irq)
- abe->pp_first_irq = 0;
- else
- abe->pp_buf_id = (abe->pp_buf_id + 1) & 0x03;
-
- omap_aess_call_subroutine(abe, abe->seq.irq_pingpong_player_id,
- NOPARAMETER, NOPARAMETER,
- NOPARAMETER, NOPARAMETER);
-}
-
/**
* omap_aess_read_next_ping_pong_buffer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @port: ABE portID
* @p: Next buffer address (pointer)
* @n: Next buffer size (pointer)
*
* Tell the next base address of the next ping_pong Buffer and its size
*/
-int omap_aess_read_next_ping_pong_buffer(struct omap_aess *abe, u32 port,
+int omap_aess_read_next_ping_pong_buffer(struct omap_aess *aess, u32 port,
u32 *p, u32 *n)
{
- struct ABE_SPingPongDescriptor desc_pp;
+ struct omap_aess_pingpong_desc desc_pp;
struct omap_aess_addr addr;
/* ping_pong is only supported on MM_DL */
}
/* read the port SIO descriptor and extract the current pointer
address after reading the counter */
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PINGPONGDESC_ID],
sizeof(struct omap_aess_addr));
- addr.bytes = sizeof(struct ABE_SPingPongDescriptor);
- omap_aess_mem_read(abe, addr, (u32 *)&desc_pp);
+ addr.bytes = sizeof(struct omap_aess_pingpong_desc);
+ omap_aess_mem_read(aess, addr, (u32 *)&desc_pp);
if ((desc_pp.counter & 0x1) == 0)
*p = desc_pp.nextbuff0_BaseAddr;
*p = desc_pp.nextbuff1_BaseAddr;
/* translates the number of samples in bytes */
- *n = abe->size_pingpong;
+ *n = aess->size_pingpong;
return 0;
}
/**
* omap_aess_init_ping_pong_buffer
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: ABE port ID
* @size_bytes:size of the ping pong
* @n_buffers:number of buffers (2 = ping/pong)
*
* Computes the base address of the ping_pong buffers
*/
-static int omap_aess_init_ping_pong_buffer(struct omap_aess *abe,
+static int omap_aess_init_ping_pong_buffer(struct omap_aess *aess,
u32 id, u32 size_bytes,
u32 n_buffers, u32 *p)
{
return -AESS_EINVAL;
}
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PING_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PING_ID],
sizeof(struct omap_aess_addr));
for (i = 0; i < n_buffers; i++) {
dmem_addr = addr.offset + (i * size_bytes);
/* base addresses of the ping pong buffers in U8 unit */
- abe->base_address_pingpong[i] = dmem_addr;
+ aess->base_address_pingpong[i] = dmem_addr;
}
for (i = 0; i < 4; i++)
- abe->pp_buf_addr[i] = addr.offset + (i * size_bytes);
- abe->pp_buf_id = 0;
- abe->pp_buf_id_next = 0;
- abe->pp_first_irq = 1;
+ aess->pp_buf_addr[i] = addr.offset + (i * size_bytes);
+ aess->pp_buf_id = 0;
+ aess->pp_buf_id_next = 0;
+ aess->pp_first_irq = 1;
/* global data */
- abe->size_pingpong = size_bytes;
+ aess->size_pingpong = size_bytes;
*p = (u32)addr.offset;
return 0;
}
/**
* omap_aess_connect_irq_ping_pong_port
- * @abe: Pointer on aess handle
+ * @aess: Pointer on aess handle
* @id: port name
* @f: desired data format
* @subroutine_id: index of the call-back subroutine to call
* "abe_set_ping_pong_buffer" to notify the new amount of samples in the
* pong buffer.
*/
-int omap_aess_connect_irq_ping_pong_port(struct omap_aess *abe,
+int omap_aess_connect_irq_ping_pong_port(struct omap_aess *aess,
u32 id, struct omap_aess_data_format *f,
u32 subroutine_id, u32 size,
u32 *sink, u32 dsp_mcu_flag)
return -AESS_EINVAL;
}
- memcpy(&addr, &abe->fw_info->map[OMAP_AESS_DMEM_PING_ID],
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_PING_ID],
sizeof(struct omap_aess_addr));
- abe_port[id] = ((struct omap_aess_port *)abe->fw_info->port)[id];
+ abe_port[id] = ((struct omap_aess_port *)aess->fw_info->port)[id];
(abe_port[id]).format = (*f);
- (abe_port[id]).protocol.protocol_switch = PINGPONG_PORT_PROT;
+ (abe_port[id]).protocol.protocol_switch = OMAP_AESS_PORT_PINGPONG;
(abe_port[id]).protocol.p.prot_pingpong.buf_addr = addr.offset;
(abe_port[id]).protocol.p.prot_pingpong.buf_size = size;
(abe_port[id]).protocol.p.prot_pingpong.irq_data = (1);
- omap_aess_init_ping_pong_buffer(abe, OMAP_ABE_MM_DL_PORT, size, 2, sink);
+ omap_aess_init_ping_pong_buffer(aess, OMAP_ABE_MM_DL_PORT, size, 2, sink);
if (dsp_mcu_flag == PING_PONG_WITH_MCU_IRQ)
(abe_port[id]).protocol.p.prot_pingpong.irq_addr =
- ABE_MCU_IRQSTATUS_RAW;
+ OMAP_AESS_MCU_IRQSTATUS_RAW;
if (dsp_mcu_flag == PING_PONG_WITH_DSP_IRQ)
(abe_port[id]).protocol.p.prot_pingpong.irq_addr =
- ABE_DSP_IRQSTATUS_RAW;
+ OMAP_AESS_DSP_IRQSTATUS_RAW;
abe_port[id].status = OMAP_ABE_PORT_INITIALIZED;
/* load the ATC descriptors - disabled */
- omap_aess_init_atc(abe, id);
+ omap_aess_init_atc(aess, id);
/* load the micro-task parameters */
- omap_aess_init_io_tasks(abe, id, &((abe_port[id]).format),
+ omap_aess_init_io_tasks(aess, id, &((abe_port[id]).format),
&((abe_port[id]).protocol));
*sink = (abe_port[id]).protocol.p.prot_pingpong.buf_addr;
index 42d31f785698733c9a37b06ee0e097512846d6ea..c80d67d39dc2fcd396a22e22a5b2549e7a0c9cce 100644 (file)
#ifndef _ABE_PORT_H_
#define _ABE_PORT_H_
-struct ABE_STask {
- /* 0 ... Index of called function */
- u16 iF;
- /* 2 ... for INITPTR of A0 */
- u16 A0;
- /* 4 ... for INITPTR of A1 */
- u16 A1;
- /* 6 ... for INITPTR of A2 & A3 */
- u16 A2_3;
- /* 8 ... for INITPTR of A4 & A5 */
- u16 A4_5;
- /* 10 ... for INITREG of R0, R1, R2, R3 */
- u16 R;
- /* 12 */
- u16 misc0;
- /* 14 */
- u16 misc1;
-};
-
-#define ABE_TASK_ID(ID) (OMAP_ABE_D_TASKSLIST_ADDR + sizeof(struct ABE_STask)*(ID))
-
-struct ABE_SIODescriptor {
- /* 0 */
- u16 drift_asrc;
- /* 2 */
- u16 drift_io;
- /* 4 "Function index" of XLS sheet "Functions" */
- u8 io_type_idx;
- /* 5 1 = MONO or Stereo1616, 2= STEREO, ... */
- u8 samp_size;
- /* 6 drift "issues" for ASRC */
- s16 flow_counter;
- /* 8 address for IRQ or DMArequests */
- u16 hw_ctrl_addr;
- /* 10 DMA request bit-field or IRQ (DSP/MCU) */
- u8 atc_irq_data;
- /* 11 0 = Read, 3 = Write */
- u8 direction_rw;
- /* 12 */
- u8 repeat_last_samp;
- /* 13 12 at 48kHz, ... */
- u8 nsamp;
- /* 14 nsamp x samp_size */
- u8 x_io;
- /* 15 ON = 0x80, OFF = 0x00 */
- u8 on_off;
- /* 16 For Slimbus and TDM purpose */
- u16 split_addr1;
- /* 18 */
- u16 split_addr2;
- /* 20 */
- u16 split_addr3;
- /* 22 */
- u8 before_f_index;
- /* 23 */
- u8 after_f_index;
- /* 24 SM/CM INITPTR field */
- u16 smem_addr1;
- /* 26 in bytes */
- u16 atc_address1;
- /* 28 DMIC_ATC_PTR, MCPDM_UL_ATC_PTR, ... */
- u16 atc_pointer_saved1;
- /* 30 samp_size (except in TDM or Slimbus) */
- u8 data_size1;
- /* 31 "Function index" of XLS sheet "Functions" */
- u8 copy_f_index1;
- /* 32 For Slimbus and TDM purpose */
- u16 smem_addr2;
- /* 34 */
- u16 atc_address2;
- /* 36 */
- u16 atc_pointer_saved2;
- /* 38 */
- u8 data_size2;
- /* 39 */
- u8 copy_f_index2;
-};
-
-#ifdef __KERNEL__
int omap_aess_select_main_port(struct omap_aess *abe, u32 id);
void omap_aess_build_scheduler_table(struct omap_aess *abe);
int omap_aess_reset_port(struct omap_aess *abe, u32 id);
void omap_aess_irq_ping_pong(struct omap_aess *abe);
-#endif
#endif /* _ABE_PORT_H_ */
diff --git a/sound/soc/omap/aess/abe_seq.c b/sound/soc/omap/aess/abe_seq.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include "abe.h"
-#include "abe_dbg.h"
-
-/* Maximun subroutines for ABE sequences */
-#define OMAP_ABE_MAX_SUB_ROUTINE 10
-
-struct omap_aess_subroutine {
- u32 sub_id;
- s32 param[4];
-};
-
-
-/* table of new subroutines called in the sequence */
-static abe_subroutine2 abe_all_subsubroutine[OMAP_ABE_MAX_SUB_ROUTINE];
-/* number of parameters per calls */
-static u32 abe_all_subsubroutine_nparam[OMAP_ABE_MAX_SUB_ROUTINE];
-/* paramters of the subroutine (if any) */
-static u32 abe_all_subroutine_params[OMAP_ABE_MAX_SUB_ROUTINE][4];
-
-/**
- * omap_aess_dummy_subroutine
- *
- */
-void omap_aess_dummy_subroutine(void)
-{
-}
-
-/**
- * omap_aess_add_subroutine
- * @abe: Pointer on aess handle
- * @id: ABE port id
- * @f: pointer to the subroutines
- * @nparam: number of parameters
- * @params: pointer to the parameters
- *
- * add one function pointer more and returns the index to it
- */
-int omap_aess_add_subroutine(struct omap_aess *abe, u32 *id, abe_subroutine2 f, u32 nparam, u32 *params)
-{
- u32 i, i_found;
-
- if ((abe->seq.write_pointer >= OMAP_ABE_MAX_SUB_ROUTINE) ||
- ((u32) f == 0)) {
- aess_err("Too many subroutine Plugged");
- return -AESS_EINVAL;
- } else {
- /* search if this subroutine address was not already
- * declared, then return the previous index
- */
- for (i_found = abe->seq.write_pointer, i = 0;
- i < abe->seq.write_pointer; i++) {
- if (f == abe_all_subsubroutine[i])
- i_found = i;
- }
-
- if (i_found == abe->seq.write_pointer) {
- /* Sub routine not listed - Add it */
- *id = abe->seq.write_pointer;
- abe_all_subsubroutine[i_found] = (f);
- for (i = 0; i < nparam; i++)
- abe_all_subroutine_params[i_found][i] = params[i];
- abe_all_subsubroutine_nparam[i_found] = nparam;
- abe->seq.write_pointer++;
- } else {
- /* Sub routine listed - Update parameters */
- for (i = 0; i < nparam; i++)
- abe_all_subroutine_params[i_found][i] = params[i];
- abe_all_subsubroutine_nparam[i_found] = nparam;
- *id = i_found;
- }
- }
- return 0;
-}
-
-/**
- * omap_aess_init_subroutine_table
- * @abe: Pointer on aess handle
- *
- * initializes the default table of pointers to subroutines
- *
- */
-void omap_aess_init_subroutine_table(struct omap_aess *abe)
-{
- u32 id;
-
- /* reset the table's pointers */
- abe->seq.write_pointer = 0;
-
- /* the first index is the NULL task */
- omap_aess_add_subroutine(abe, &id,
- (abe_subroutine2)omap_aess_dummy_subroutine,
- 0, (u32 *)0);
-
- omap_aess_add_subroutine(abe, &abe->seq.irq_pingpong_player_id,
- (abe_subroutine2)omap_aess_dummy_subroutine,
- 0, (u32 *)0);
-}
-
-/**
- * omap_aess_reset_all_sequence
- * @abe: Pointer on aess handle
- *
- * load default configuration for all sequences
- * kill any running activities
- */
-void omap_aess_reset_all_sequence(struct omap_aess *abe)
-{
- omap_aess_init_subroutine_table(abe);
-}
-
-/**
- * omap_aess_call_subroutine
- * @abe: Pointer on aess handle
- * @idx: index to the table of all registered Call-backs and subroutines
- * @p1: first parameter
- * @p2: second parameter
- * @p3: 3rd parameter
- * @p4: 4th parameter
- *
- * run and log a subroutine
- */
-void omap_aess_call_subroutine(struct omap_aess *abe, u32 idx, u32 p1, u32 p2, u32 p3, u32 p4)
-{
- abe_subroutine0 f0;
- abe_subroutine1 f1;
- abe_subroutine2 f2;
- abe_subroutine3 f3;
- abe_subroutine4 f4;
- u32 *params;
-
- if (idx > OMAP_ABE_MAX_SUB_ROUTINE)
- return;
-
- switch (idx) {
- default:
- switch (abe_all_subsubroutine_nparam[idx]) {
- case 0:
- f0 = (abe_subroutine0)abe_all_subsubroutine[idx];
- (*f0)();
- break;
- case 1:
- f1 = (abe_subroutine1)abe_all_subsubroutine[idx];
- params = abe_all_subroutine_params[idx];
- if (params != (u32 *)0)
- p1 = params[0];
- (*f1)(p1);
- break;
- case 2:
- f2 = abe_all_subsubroutine[idx];
- params = abe_all_subroutine_params[idx];
- if (params != (u32 *)0) {
- p1 = params[0];
- p2 = params[1];
- }
- (*f2)(p1, p2);
- break;
- case 3:
- f3 = (abe_subroutine3) abe_all_subsubroutine[idx];
- params = abe_all_subroutine_params[idx];
- if (params != (u32 *)0) {
- p1 = params[0];
- p2 = params[1];
- p3 = params[2];
- }
- (*f3)(p1, p2, p3);
- break;
- case 4:
- f4 = (abe_subroutine4) abe_all_subsubroutine[idx];
- params = abe_all_subroutine_params[idx];
- if (params != (u32 *)0) {
- p1 = params[0];
- p2 = params[1];
- p3 = params[2];
- p4 = params[3];
- }
- (*f4)(p1, p2, p3, p4);
- break;
- default:
- break;
- }
- }
-}
-
-/**
- * omap_aess_plug_subroutine
- * @abe: Pointer on aess handle
- * @id: returned sequence index after plugging a new subroutine
- * @f: subroutine address to be inserted
- * @n: number of parameters of this subroutine
- * @params: pointer on parameters
- *
- * register a list of subroutines for call-back purpose
- */
-int omap_aess_plug_subroutine(struct omap_aess *abe, u32 *id,
- abe_subroutine2 f, u32 n, u32 *params)
-{
- omap_aess_add_subroutine(abe, id, (abe_subroutine2)f, n,
- (u32 *)params);
- return 0;
-}
-EXPORT_SYMBOL(omap_aess_plug_subroutine);
diff --git a/sound/soc/omap/aess/abe_seq.h b/sound/soc/omap/aess/abe_seq.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#ifndef _ABE_SEQ_H_
-#define _ABE_SEQ_H_
-
-void omap_aess_reset_all_sequence(struct omap_aess *abe);
-void omap_aess_call_subroutine(struct omap_aess *abe, u32 idx, u32 p1, u32 p2, u32 p3, u32 p4);
-
-#endif /* _ABE_SEQ_H_ */
diff --git a/sound/soc/omap/aess/abe_typ.h b/sound/soc/omap/aess/abe_typ.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/*
- *
- * This file is provided under a dual BSD/GPLv2 license. When using or
- * redistributing this file, you may do so under either license.
- *
- * GPL LICENSE SUMMARY
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of version 2 of the GNU General Public License as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- * The full GNU General Public License is included in this distribution
- * in the file called LICENSE.GPL.
- *
- * BSD LICENSE
- *
- * Copyright(c) 2010-2012 Texas Instruments Incorporated,
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include "abe_def.h"
-
-#ifndef _ABE_TYP_H_
-#define _ABE_TYP_H_
-
-/*
- * BASIC TYPES
- */
-#define MAX_UINT8 ((((1L << 7) - 1) << 1) + 1)
-#define MAX_UINT16 ((((1L << 15) - 1) << 1) + 1)
-#define MAX_UINT32 ((((1L << 31) - 1) << 1) + 1)
-#include <linux/types.h>
-
-/* subroutine types */
-typedef void (*abe_subroutine0) (void);
-typedef void (*abe_subroutine1) (u32);
-typedef void (*abe_subroutine2) (u32, u32);
-typedef void (*abe_subroutine3) (u32, u32, u32);
-typedef void (*abe_subroutine4) (u32, u32, u32, u32);
-/*
- * OPP TYPE
- *
- * 0: Ultra Lowest power consumption audio player
- * 1: OPP 25% (simple multimedia features)
- * 2: OPP 50% (multimedia and voice calls)
- * 3: OPP100% (multimedia complex use-cases)
- */
-#define ABE_OPP0 0
-#define ABE_OPP25 1
-#define ABE_OPP50 2
-#define ABE_OPP100 3
-
-/*
- * SAMPLES TYPE
- *
- * mono 16 bit sample LSB aligned, 16 MSB bits are unused;
- * mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP
- * TX purpose;
- * mono sample MSB aligned (16/24/32bits);
- * two successive mono samples in one 32bits container;
- * Two L/R 16bits samples in a 32bits container;
- * Two channels defined with two MSB aligned samples;
- * Three channels defined with three MSB aligned samples (MIC);
- * Four channels defined with four MSB aligned samples (MIC);
- * . . .
- * Eight channels defined with eight MSB aligned samples (MIC);
- */
-#define MONO_MSB 1
-#define MONO_RSHIFTED_16 2
-#define STEREO_RSHIFTED_16 3
-#define STEREO_16_16 4
-#define STEREO_MSB 5
-#define THREE_MSB 6
-#define FOUR_MSB 7
-#define FIVE_MSB 8
-#define SIX_MSB 9
-#define SEVEN_MSB 10
-#define EIGHT_MSB 11
-#define NINE_MSB 12
-#define TEN_MSB 13
-#define MONO_16_16 14
-
-/*
- * PORT PROTOCOL TYPE - abe_port_protocol_switch_id
- */
-#define SLIMBUS_PORT_PROT 1
-#define SERIAL_PORT_PROT 2
-#define TDM_SERIAL_PORT_PROT 3
-#define DMIC_PORT_PROT 4
-#define MCPDMDL_PORT_PROT 5
-#define MCPDMUL_PORT_PROT 6
-#define PINGPONG_PORT_PROT 7
-#define DMAREQ_PORT_PROT 8
-
-/*
- * PORT IDs, this list is aligned with the FW data mapping
- */
-#define OMAP_ABE_DMIC_PORT 0
-#define OMAP_ABE_PDM_UL_PORT 1
-#define OMAP_ABE_BT_VX_UL_PORT 2
-#define OMAP_ABE_MM_UL_PORT 3
-#define OMAP_ABE_MM_UL2_PORT 4
-#define OMAP_ABE_VX_UL_PORT 5
-#define OMAP_ABE_MM_DL_PORT 6
-#define OMAP_ABE_VX_DL_PORT 7
-#define OMAP_ABE_TONES_DL_PORT 8
-#define OMAP_ABE_MCASP_DL_PORT 9
-#define OMAP_ABE_BT_VX_DL_PORT 10
-#define OMAP_ABE_PDM_DL_PORT 11
-#define OMAP_ABE_MM_EXT_OUT_PORT 12
-#define OMAP_ABE_MM_EXT_IN_PORT 13
-#define TDM_DL_PORT 14
-#define TDM_UL_PORT 15
-#define DEBUG_PORT 16
-#define LAST_PORT_ID 17
-
-#define FEAT_MIXDL1 14
-#define FEAT_MIXDL2 15
-#define FEAT_MIXAUDUL 16
-#define FEAT_GAINS 21
-#define FEAT_GAINS_DMIC1 22
-#define FEAT_GAINS_DMIC2 23
-#define FEAT_GAINS_DMIC3 24
-#define FEAT_GAINS_AMIC 25
-#define FEAT_GAIN_BTUL 29
-
-/* abe_mixer_id */
-#define MIXDL1 FEAT_MIXDL1
-#define MIXDL2 FEAT_MIXDL2
-#define MIXAUDUL FEAT_MIXAUDUL
-/*
- * GAIN IDs
- */
-#define GAINS_DMIC1 FEAT_GAINS_DMIC1
-#define GAINS_DMIC2 FEAT_GAINS_DMIC2
-#define GAINS_DMIC3 FEAT_GAINS_DMIC3
-#define GAINS_AMIC FEAT_GAINS_AMIC
-#define GAINS_BTUL FEAT_GAIN_BTUL
-
-/*
- * EVENT GENERATORS - abe_event_id
- */
-#define EVENT_TIMER 0
-#define EVENT_44100 1
-/*
- * SERIAL PORTS IDs - abe_mcbsp_id
- */
-#define MCBSP1_TX MCBSP1_DMA_TX
-#define MCBSP1_RX MCBSP1_DMA_RX
-#define MCBSP2_TX MCBSP2_DMA_TX
-#define MCBSP2_RX MCBSP2_DMA_RX
-#define MCBSP3_TX MCBSP3_DMA_TX
-#define MCBSP3_RX MCBSP3_DMA_RX
-
-/*
- * SERIAL PORTS IDs - abe_mcasp_id
- */
-#define MCASP1_TX McASP1_AXEVT
-#define MCASP1_RX McASP1_AREVT
-
-/*
- * DATA_FORMAT_T
- *
- * used in port declaration
- */
-struct omap_aess_data_format {
- /* Sampling frequency of the stream */
- u32 f;
- /* Sample format type */
- u32 samp_format;
-};
-
-/*
- * PORT_PROTOCOL_T
- *
- * port declaration
- */
-struct omap_aess_port_protocol {
- /* Direction=0 means input from AESS point of view */
- u32 direction;
- /* Protocol type (switch) during the data transfers */
- u32 protocol_switch;
- union {
- /* Slimbus peripheral connected to ATC */
- struct {
- /* Address of ATC Slimbus descriptor's index */
- u32 desc_addr1;
- /* DMEM address 1 in bytes */
- u32 buf_addr1;
- /* DMEM buffer size size in bytes */
- u32 buf_size;
- /* ITERation on each DMAreq signals */
- u32 iter;
- /* Second ATC index for SlimBus reception (or NULL) */
- u32 desc_addr2;
- /* DMEM address 2 in bytes */
- u32 buf_addr2;
- } prot_slimbus;
- /* McBSP/McASP peripheral connected to ATC */
- struct {
- u32 desc_addr;
- /* Address of ATC McBSP/McASP descriptor's in bytes */
- u32 buf_addr;
- /* DMEM address in bytes */
- u32 buf_size;
- /* ITERation on each DMAreq signals */
- u32 iter;
- } prot_serial;
- /* DMIC peripheral connected to ATC */
- struct {
- /* DMEM address in bytes */
- u32 buf_addr;
- /* DMEM buffer size in bytes */
- u32 buf_size;
- /* Number of activated DMIC */
- u32 nbchan;
- } prot_dmic;
- /* McPDMDL peripheral connected to ATC */
- struct {
- /* DMEM address in bytes */
- u32 buf_addr;
- /* DMEM size in bytes */
- u32 buf_size;
- /* Control allowed on McPDM DL */
- u32 control;
- } prot_mcpdmdl;
- /* McPDMUL peripheral connected to ATC */
- struct {
- /* DMEM address size in bytes */
- u32 buf_addr;
- /* DMEM buffer size size in bytes */
- u32 buf_size;
- } prot_mcpdmul;
- /* Ping-Pong interface to the Host using cache-flush */
- struct {
- /* Address of ATC descriptor's */
- u32 desc_addr;
- /* DMEM buffer base address in bytes */
- u32 buf_addr;
- /* DMEM size in bytes for each ping and pong buffers */
- u32 buf_size;
- /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */
- u32 irq_addr;
- /* IRQ data content loaded in the AESS IRQ register */
- u32 irq_data;
- /* Call-back function upon IRQ reception */
- u32 callback;
- } prot_pingpong;
- /* DMAreq line to CBPr */
- struct {
- /* Address of ATC descriptor's */
- u32 desc_addr;
- /* DMEM buffer address in bytes */
- u32 buf_addr;
- /* DMEM buffer size size in bytes */
- u32 buf_size;
- /* ITERation on each DMAreq signals */
- u32 iter;
- /* DMAreq address */
- u32 dma_addr;
- /* DMA/AESS = 1 << #DMA */
- u32 dma_data;
- } prot_dmareq;
- /* Circular buffer - direct addressing to DMEM */
- struct {
- /* DMEM buffer base address in bytes */
- u32 buf_addr;
- /* DMEM buffer size in bytes */
- u32 buf_size;
- /* DMAreq address */
- u32 dma_addr;
- /* DMA/AESS = 1 << #DMA */
- u32 dma_data;
- } prot_circular_buffer;
- } p;
-};
-
-struct omap_aess_dma_offset {
- /* Offset to the first address of the */
- u32 data;
- /* number of iterations for the DMA data moves. */
- u32 iter;
-};
-
-/*
- * ABE_PORT_T status / format / sampling / protocol(call_back) /
- * features / gain / name ..
- *
- */
-
-struct omap_aess_task {
- u8 frame;
- u8 slot;
- u16 task;
-};
-
-struct omap_aess_init_task1 {
- u32 nb_task;
- struct omap_aess_task task[2];
-};
-
-struct omap_aess_init_task {
- u32 nb_task;
- struct omap_aess_task *task;
-};
-
-struct omap_aess_io_task {
- u32 nb_task;
- u32 smem;
- struct omap_aess_task *task;
-};
-
-struct omap_aess_io_task1 {
- u32 nb_task;
- u32 smem;
- struct omap_aess_task task[2];
-};
-
-struct omap_aess_port_type {
- struct omap_aess_init_task1 serial;
- struct omap_aess_init_task1 cbpr;
-};
-
-struct omap_aess_asrc_port {
- struct omap_aess_io_task1 task;
- struct omap_aess_port_type asrc;
-};
-
-struct omap_aess_port {
- /* running / idled */
- u16 status;
- /* Sample format type */
- struct omap_aess_data_format format;
- /* API : for ASRC */
- s32 drift;
- /* optionnal call-back index for errors and ack */
- u16 callback;
- /* IO tasks buffers */
- u16 smem_buffer1;
- u16 smem_buffer2;
- struct omap_aess_port_protocol protocol;
- /* pointer and iteration counter of the xDMA */
- struct omap_aess_dma_offset dma;
- struct omap_aess_init_task1 task;
- struct omap_aess_asrc_port tsk_freq[4];
-};
-
-/*
- * ROUTER_T
- *
- * table of indexes in unsigned bytes
- */
-typedef u16 abe_router_t;
-/*
- * DRIFT_T abe_drift_t = s32
- *
- * ASRC drift parameter in [ppm] value
- */
-/*
- * -------------------- INTERNAL DATA TYPES ---------------------
- */
-/*
- * ABE_IRQ_DATA_T
- *
- * IRQ FIFO content declaration
- * APS interrupts : IRQ_FIFO[31:28] = IRQtag_APS,
- * IRQ_FIFO[27:16] = APS_IRQs, IRQ_FIFO[15:0] = loopCounter
- * SEQ interrupts : IRQ_FIFO[31:28] IRQtag_COUNT,
- * IRQ_FIFO[27:16] = Count_IRQs, IRQ_FIFO[15:0] = loopCounter
- * Ping-Pong Interrupts : IRQ_FIFO[31:28] = IRQtag_PP,
- * IRQ_FIFO[27:16] = PP_MCU_IRQ, IRQ_FIFO[15:0] = loopCounter
- */
-struct omap_aess_irq_data {
- unsigned int counter:16;
- unsigned int data:12;
- unsigned int tag:4;
-};
-
-#endif /* ifndef _ABE_TYP_H_ */
diff --git a/sound/soc/omap/aess/aess-fw.h b/sound/soc/omap/aess/aess-fw.h
--- /dev/null
@@ -0,0 +1,716 @@
+/*
+ *
+ * This file is provided under a dual BSD/GPLv2 license. When using or
+ * redistributing this file, you may do so under either license.
+ *
+ * GPL LICENSE SUMMARY
+ *
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
+ * All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ * The full GNU General Public License is included in this distribution
+ * in the file called LICENSE.GPL.
+ *
+ * BSD LICENSE
+ *
+ * Copyright(c) 2010-2013 Texas Instruments Incorporated,
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _AESS_FW_H_
+#define _AESS_FW_H_
+
+/*
+ * HARDWARE AND PERIPHERAL DEFINITIONS
+ */
+/* holds the DMA req lines to the sDMA */
+#define ABE_DMASTATUS_RAW 0x84
+
+/* Direction=0 means input from ABE point of view */
+#define ABE_ATC_DIRECTION_IN 0
+/* Direction=1 means output from ABE point of view */
+#define ABE_ATC_DIRECTION_OUT 1
+
+/*
+ * DMA requests
+ */
+/*Internal connection doesn't connect at ABE boundary */
+#define External_DMA_0 0
+/*Transmit request digital microphone */
+#define DMIC_DMA_REQ 1
+/*Multichannel PDM downlink */
+#define McPDM_DMA_DL 2
+/*Multichannel PDM uplink */
+#define McPDM_DMA_UP 3
+/*MCBSP module 1 - transmit request */
+#define MCBSP1_DMA_TX 4
+/*MCBSP module 1 - receive request */
+#define MCBSP1_DMA_RX 5
+/*MCBSP module 2 - transmit request */
+#define MCBSP2_DMA_TX 6
+/*MCBSP module 2 - receive request */
+#define MCBSP2_DMA_RX 7
+/*MCBSP module 3 - transmit request */
+#define MCBSP3_DMA_TX 8
+/*MCBSP module 3 - receive request */
+#define MCBSP3_DMA_RX 9
+/*McASP - Data transmit DMA request line */
+#define McASP1_AXEVT 26
+/*McASP - Data receive DMA request line */
+#define McASP1_AREVT 29
+/*DUMMY FIFO @@@ */
+#define _DUMMY_FIFO_ 30
+/*DMA of the Circular buffer peripheral 0 */
+#define CBPr_DMA_RTX0 32
+/*DMA of the Circular buffer peripheral 1 */
+#define CBPr_DMA_RTX1 33
+/*DMA of the Circular buffer peripheral 2 */
+#define CBPr_DMA_RTX2 34
+/*DMA of the Circular buffer peripheral 3 */
+#define CBPr_DMA_RTX3 35
+/*DMA of the Circular buffer peripheral 4 */
+#define CBPr_DMA_RTX4 36
+/*DMA of the Circular buffer peripheral 5 */
+#define CBPr_DMA_RTX5 37
+/*DMA of the Circular buffer peripheral 6 */
+#define CBPr_DMA_RTX6 38
+/*DMA of the Circular buffer peripheral 7 */
+#define CBPr_DMA_RTX7 39
+
+/*
+ * HARDWARE AND PERIPHERAL DEFINITIONS
+ */
+/* MM_DL */
+#define ABE_CBPR0_IDX 0
+/* VX_DL */
+#define ABE_CBPR1_IDX 1
+/* VX_UL */
+#define ABE_CBPR2_IDX 2
+/* MM_UL */
+#define ABE_CBPR3_IDX 3
+/* MM_UL2 */
+#define ABE_CBPR4_IDX 4
+/* TONES */
+#define ABE_CBPR5_IDX 5
+/* TDB */
+#define ABE_CBPR6_IDX 6
+/* DEBUG/CTL */
+#define ABE_CBPR7_IDX 7
+#define CIRCULAR_BUFFER_PERIPHERAL_R__0 (0x100 + ABE_CBPR0_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__1 (0x100 + ABE_CBPR1_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__2 (0x100 + ABE_CBPR2_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__3 (0x100 + ABE_CBPR3_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__4 (0x100 + ABE_CBPR4_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__5 (0x100 + ABE_CBPR5_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__6 (0x100 + ABE_CBPR6_IDX*4)
+#define CIRCULAR_BUFFER_PERIPHERAL_R__7 (0x100 + ABE_CBPR7_IDX*4)
+#define PING_PONG_WITH_MCU_IRQ 1
+#define PING_PONG_WITH_DSP_IRQ 2
+/*
+ * INTERNAL DEFINITIONS
+ */
+/* 24 Q6.26 coefficients */
+#define NBEQ1 25
+/* 2x12 Q6.26 coefficients */
+#define NBEQ2 13
+
+/* sink / input port from Host point of view (or AESS for DMIC/McPDM/.. */
+#define SNK_P ABE_ATC_DIRECTION_IN
+/* source / ouptut port */
+#define SRC_P ABE_ATC_DIRECTION_OUT
+
+/* number of task/slot depending on the OPP value */
+#define DOPPMODE32_OPP100 (0x00000010)
+#define DOPPMODE32_OPP50 (0x0000000C)
+#define DOPPMODE32_OPP25 (0x0000004)
+
+/*
+ * ABE CONST AREA FOR PERIPHERAL TUNING
+ */
+/* port idled IDLE_P */
+#define OMAP_ABE_PORT_ACTIVITY_IDLE 1
+/* port initialized, ready to be activated */
+#define OMAP_ABE_PORT_INITIALIZED 3
+/* port activated RUN_P */
+#define OMAP_ABE_PORT_ACTIVITY_RUNNING 2
+
+#define NOPARAMETER 0
+/* number of ATC access upon AMIC DMArequests, all the FIFOs are enabled */
+#define MCPDM_UL_ITER 4
+/* All the McPDM FIFOs are enabled simultaneously */
+#define MCPDM_DL_ITER 24
+/* All the DMIC FIFOs are enabled simultaneously */
+#define DMIC_ITER 12
+/* TBD later if needed */
+#define MAX_PINGPONG_BUFFERS 2
+
+/* OLD WAY */
+#define c_feat_init_eq 1
+#define c_feat_read_eq1 2
+#define c_write_eq1 3
+#define c_feat_read_eq2 4
+#define c_write_eq2 5
+#define c_feat_read_eq3 6
+#define c_write_eq3 7
+/* max number of gain to be controlled by HAL */
+#define MAX_NBGAIN_CMEM 36
+
+
+#define OMAP_ABE_DMEM 0
+#define OMAP_ABE_CMEM 1
+#define OMAP_ABE_SMEM 2
+#define OMAP_ABE_PMEM 3
+#define OMAP_ABE_AESS 4
+
+struct omap_aess_addr {
+ int bank;
+ unsigned int offset;
+ unsigned int bytes;
+};
+
+/* ABE memory IDs */
+#define OMAP_AESS_DMEM_MULTIFRAME_ID 0
+#define OMAP_AESS_DMEM_DMIC_UL_FIFO_ID 1
+#define OMAP_AESS_DMEM_MCPDM_UL_FIFO_ID 2
+#define OMAP_AESS_DMEM_BT_UL_FIFO_ID 3
+#define OMAP_AESS_DMEM_MM_UL_FIFO_ID 4
+#define OMAP_AESS_DMEM_MM_UL2_FIFO_ID 5
+#define OMAP_AESS_DMEM_VX_UL_FIFO_ID 6
+#define OMAP_AESS_DMEM_MM_DL_FIFO_ID 7
+#define OMAP_AESS_DMEM_VX_DL_FIFO_ID 8
+#define OMAP_AESS_DMEM_TONES_DL_FIFO_ID 9
+#define OMAP_AESS_DMEM_MCASP_DL_FIFO_ID 10
+#define OMAP_AESS_DMEM_BT_DL_FIFO_ID 11
+#define OMAP_AESS_DMEM_MCPDM_DL_FIFO_ID 12
+#define OMAP_AESS_DMEM_MM_EXT_OUT_FIFO_ID 13
+#define OMAP_AESS_DMEM_MM_EXT_IN_FIFO_ID 14
+#define OMAP_AESS_SMEM_DMIC0_96_48_DATA_ID 15
+#define OMAP_AESS_SMEM_DMIC1_96_48_DATA_ID 16
+#define OMAP_AESS_SMEM_DMIC2_96_48_DATA_ID 17
+#define OMAP_AESS_SMEM_AMIC_96_48_DATA_ID 18
+#define OMAP_AESS_SMEM_BT_UL_ID 19
+#define OMAP_AESS_SMEM_BT_UL_8_48_HP_DATA_ID 20
+#define OMAP_AESS_SMEM_BT_UL_8_48_LP_DATA_ID 21
+#define OMAP_AESS_SMEM_BT_UL_16_48_HP_DATA_ID 22
+#define OMAP_AESS_SMEM_BT_UL_16_48_LP_DATA_ID 23
+#define OMAP_AESS_SMEM_MM_UL2_ID 24
+#define OMAP_AESS_SMEM_MM_UL_ID 25
+#define OMAP_AESS_SMEM_VX_UL_ID 26
+#define OMAP_AESS_SMEM_VX_UL_48_8_HP_DATA_ID 27
+#define OMAP_AESS_SMEM_VX_UL_48_8_LP_DATA_ID 28
+#define OMAP_AESS_SMEM_VX_UL_48_16_HP_DATA_ID 29
+#define OMAP_AESS_SMEM_VX_UL_48_16_LP_DATA_ID 30
+#define OMAP_AESS_SMEM_MM_DL_ID 31
+#define OMAP_AESS_SMEM_MM_DL_44P1_ID 32
+#define OMAP_AESS_SMEM_MM_DL_44P1_XK_ID 33
+#define OMAP_AESS_SMEM_VX_DL_ID 34
+#define OMAP_AESS_SMEM_VX_DL_8_48_HP_DATA_ID 35
+#define OMAP_AESS_SMEM_VX_DL_8_48_LP_DATA_ID 36
+#define OMAP_AESS_SMEM_VX_DL_8_48_OSR_LP_DATA_ID 37
+#define OMAP_AESS_SMEM_VX_DL_16_48_HP_DATA_ID 38
+#define OMAP_AESS_SMEM_VX_DL_16_48_LP_DATA_ID 39
+#define OMAP_AESS_SMEM_TONES_ID 40
+#define OMAP_AESS_SMEM_TONES_44P1_ID 41
+#define OMAP_AESS_SMEM_TONES_44P1_XK_ID 42
+#define OMAP_AESS_SMEM_MCASP1_ID 43
+#define OMAP_AESS_SMEM_BT_DL_ID 44
+#define OMAP_AESS_SMEM_BT_DL_8_48_OSR_LP_DATA_ID 45
+#define OMAP_AESS_SMEM_BT_DL_48_8_HP_DATA_ID 46
+#define OMAP_AESS_SMEM_BT_DL_48_8_LP_DATA_ID 47
+#define OMAP_AESS_SMEM_BT_DL_48_16_HP_DATA_ID 48
+#define OMAP_AESS_SMEM_BT_DL_48_16_LP_DATA_ID 49
+#define OMAP_AESS_SMEM_DL2_M_LR_EQ_DATA_ID 50
+#define OMAP_AESS_SMEM_DL1_M_EQ_DATA_ID 51
+#define OMAP_AESS_SMEM_EARP_48_96_LP_DATA_ID 52
+#define OMAP_AESS_SMEM_IHF_48_96_LP_DATA_ID 53
+#define OMAP_AESS_SMEM_DC_HS_ID 54
+#define OMAP_AESS_SMEM_DC_HF_ID 55
+#define OMAP_AESS_SMEM_SDT_F_DATA_ID 56
+#define OMAP_AESS_SMEM_GTARGET1_ID 57
+#define OMAP_AESS_SMEM_GCURRENT_ID 58
+#define OMAP_AESS_CMEM_DL1_COEFS_ID 59
+#define OMAP_AESS_CMEM_DL2_L_COEFS_ID 60
+#define OMAP_AESS_CMEM_DL2_R_COEFS_ID 61
+#define OMAP_AESS_CMEM_SDT_COEFS_ID 62
+#define OMAP_AESS_CMEM_96_48_AMIC_COEFS_ID 63
+#define OMAP_AESS_CMEM_96_48_DMIC_COEFS_ID 64
+#define OMAP_AESS_CMEM_1_ALPHA_ID 65
+#define OMAP_AESS_CMEM_ALPHA_ID 66
+#define OMAP_AESS_DMEM_SLOT23_CTRL_ID 67
+#define OMAP_AESS_DMEM_AUPLINKROUTING_ID 68
+#define OMAP_AESS_DMEM_MAXTASKBYTESINSLOT_ID 69
+#define OMAP_AESS_DMEM_PINGPONGDESC_ID 70
+#define OMAP_AESS_DMEM_IODESCR_ID 71
+#define OMAP_AESS_DMEM_MCUIRQFIFO_ID 72
+#define OMAP_AESS_DMEM_PING_ID 73
+#define OMAP_AESS_DMEM_DEBUG_FIFO_ID 74
+#define OMAP_AESS_DMEM_DEBUG_FIFO_HAL_ID 75
+#define OMAP_AESS_DMEM_DEBUG_HAL_TASK_ID 76
+#define OMAP_AESS_DMEM_LOOPCOUNTER_ID 77
+#define OMAP_AESS_DMEM_FWMEMINITDESCR_ID 78
+
+/* ABE copy function IDs */
+#define OMAP_AESS_COPY_FCT_NULL_ID 0
+#define OMAP_AESS_COPY_FCT_S2D_STEREO_16_16_ID 1
+#define OMAP_AESS_COPY_FCT_S2D_MONO_MSB_ID 2
+#define OMAP_AESS_COPY_FCT_S2D_STEREO_MSB_ID 3
+#define OMAP_AESS_COPY_FCT_S2D_STEREO_RSHIFTED_16_ID 4
+#define OMAP_AESS_COPY_FCT_S2D_MONO_RSHIFTED_16_ID 5
+#define OMAP_AESS_COPY_FCT_D2S_STEREO_16_16_ID 6
+#define OMAP_AESS_COPY_FCT_D2S_MONO_MSB_ID 7
+#define OMAP_AESS_COPY_FCT_D2S_MONO_RSHIFTED_16_ID 8
+#define OMAP_AESS_COPY_FCT_D2S_STEREO_RSHIFTED_16_ID 9
+#define OMAP_AESS_COPY_FCT_D2S_STEREO_MSB_ID 10
+#define OMAP_AESS_COPY_FCT_DMIC_ID 11
+#define OMAP_AESS_COPY_FCT_MCPDM_DL_ID 12
+#define OMAP_AESS_COPY_FCT_MM_UL_ID 13
+#define OMAP_AESS_COPY_FCT_SPLIT_SMEM_ID 14
+#define OMAP_AESS_COPY_FCT_MERGE_SMEM_ID 15
+#define OMAP_AESS_COPY_FCT_SPLIT_TDM_ID 16
+#define OMAP_AESS_COPY_FCT_MERGE_TDM_ID 17
+#define OMAP_AESS_COPY_FCT_ROUTE_MM_UL_ID 18
+#define OMAP_AESS_COPY_FCT_IO_IP_ID 19
+#define OMAP_AESS_COPY_FCT_COPY_UNDERFLOW_ID 20
+#define OMAP_AESS_COPY_FCT_COPY_MCPDM_DL_HF_PDL1_ID 21
+#define OMAP_AESS_COPY_FCT_COPY_MCPDM_DL_HF_PDL2_ID 22
+#define OMAP_AESS_COPY_FCT_S2D_MONO_16_16_ID 23
+#define OMAP_AESS_COPY_FCT_D2S_MONO_16_16_ID 24
+#define OMAP_AESS_COPY_FCT_DMIC_NO_PRESCALE_ID 25
+
+/* ABE buffer IDs */
+#define OMAP_AESS_BUFFER_ZERO_ID 0
+#define OMAP_AESS_BUFFER_DMIC1_L_ID 1
+#define OMAP_AESS_BUFFER_DMIC1_R_ID 2
+#define OMAP_AESS_BUFFER_DMIC2_L_ID 3
+#define OMAP_AESS_BUFFER_DMIC2_R_ID 4
+#define OMAP_AESS_BUFFER_DMIC3_L_ID 5
+#define OMAP_AESS_BUFFER_DMIC3_R_ID 6
+#define OMAP_AESS_BUFFER_BT_UL_L_ID 7
+#define OMAP_AESS_BUFFER_BT_UL_R_ID 8
+#define OMAP_AESS_BUFFER_MM_EXT_IN_L_ID 9
+#define OMAP_AESS_BUFFER_MM_EXT_IN_R_ID 10
+#define OMAP_AESS_BUFFER_AMIC_L_ID 11
+#define OMAP_AESS_BUFFER_AMIC_R_ID 12
+#define OMAP_AESS_BUFFER_VX_REC_L_ID 13
+#define OMAP_AESS_BUFFER_VX_REC_R_ID 14
+#define OMAP_AESS_BUFFER_MCU_IRQ_FIFO_PTR_ID 15
+#define OMAP_AESS_BUFFER_DMIC_ATC_PTR_ID 16
+#define OMAP_AESS_BUFFER_MM_EXT_IN_ID 17
+
+struct omap_aess_io_desc {
+ /* 0 */
+ u16 drift_asrc;
+ /* 2 */
+ u16 drift_io;
+ /* 4 "Function index" of XLS sheet "Functions" */
+ u8 io_type_idx;
+ /* 5 1 = MONO or Stereo1616, 2= STEREO, ... */
+ u8 samp_size;
+ /* 6 drift "issues" for ASRC */
+ s16 flow_counter;
+ /* 8 address for IRQ or DMArequests */
+ u16 hw_ctrl_addr;
+ /* 10 DMA request bit-field or IRQ (DSP/MCU) */
+ u8 atc_irq_data;
+ /* 11 0 = Read, 3 = Write */
+ u8 direction_rw;
+ /* 12 */
+ u8 repeat_last_samp;
+ /* 13 12 at 48kHz, ... */
+ u8 nsamp;
+ /* 14 nsamp x samp_size */
+ u8 x_io;
+ /* 15 ON = 0x80, OFF = 0x00 */
+ u8 on_off;
+ /* 16 For TDM purpose */
+ u16 split_addr1;
+ /* 18 */
+ u16 split_addr2;
+ /* 20 */
+ u16 split_addr3;
+ /* 22 */
+ u8 before_f_index;
+ /* 23 */
+ u8 after_f_index;
+ /* 24 SM/CM INITPTR field */
+ u16 smem_addr1;
+ /* 26 in bytes */
+ u16 atc_address1;
+ /* 28 DMIC_ATC_PTR, MCPDM_UL_ATC_PTR, ... */
+ u16 atc_pointer_saved1;
+ /* 30 samp_size (except in TDM) */
+ u8 data_size1;
+ /* 31 "Function index" of XLS sheet "Functions" */
+ u8 copy_f_index1;
+ /* 32 For TDM purpose */
+ u16 smem_addr2;
+ /* 34 */
+ u16 atc_address2;
+ /* 36 */
+ u16 atc_pointer_saved2;
+ /* 38 */
+ u8 data_size2;
+ /* 39 */
+ u8 copy_f_index2;
+};
+
+/*
+ * OPP TYPE
+ *
+ * 0: Ultra Lowest power consumption audio player
+ * 1: OPP 25% (simple multimedia features)
+ * 2: OPP 50% (multimedia and voice calls)
+ * 3: OPP100% (multimedia complex use-cases)
+ */
+#define ABE_OPP0 0
+#define ABE_OPP25 1
+#define ABE_OPP50 2
+#define ABE_OPP100 3
+
+/*
+ * SAMPLES TYPE
+ *
+ * mono 16 bit sample LSB aligned, 16 MSB bits are unused;
+ * mono right shifted to 16bits LSBs on a 32bits DMEM FIFO for McBSP
+ * TX purpose;
+ * mono sample MSB aligned (16/24/32bits);
+ * two successive mono samples in one 32bits container;
+ * Two L/R 16bits samples in a 32bits container;
+ * Two channels defined with two MSB aligned samples;
+ * Three channels defined with three MSB aligned samples (MIC);
+ * Four channels defined with four MSB aligned samples (MIC);
+ * . . .
+ * Eight channels defined with eight MSB aligned samples (MIC);
+ */
+#define OMAP_AESS_FORMAT_MONO_MSB 1
+#define OMAP_AESS_FORMAT_MONO_RSHIFTED_16 2
+#define OMAP_AESS_FORMAT_STEREO_RSHIFTED_16 3
+#define OMAP_AESS_FORMAT_STEREO_16_16 4
+#define OMAP_AESS_FORMAT_STEREO_MSB 5
+#define OMAP_AESS_FORMAT_THREE_MSB 6
+#define OMAP_AESS_FORMAT_FOUR_MSB 7
+#define OMAP_AESS_FORMAT_FIVE_MSB 8
+#define OMAP_AESS_FORMAT_SIX_MSB 9
+#define OMAP_AESS_FORMAT_SEVEN_MSB 10
+#define OMAP_AESS_FORMAT_EIGHT_MSB 11
+#define OMAP_AESS_FORMAT_NINE_MSB 12
+#define OMAP_AESS_FORMAT_TEN_MSB 13
+#define OMAP_AESS_FORMAT_MONO_16_16 14
+
+/*
+ * PORT PROTOCOL TYPE - abe_port_protocol_switch_id
+ */
+#define OMAP_AESS_PORT_SERIAL 2
+#define OMAP_AESS_PORT_TDM 3
+#define OMAP_AESS_PORT_DMIC 4
+#define OMAP_AESS_PORT_MCPDMDL 5
+#define OMAP_AESS_PORT_MCPDMUL 6
+#define OMAP_AESS_PORT_PINGPONG 7
+#define OMAP_AESS_PORT_DMAREQ 8
+
+/*
+ * PORT IDs, this list is aligned with the FW data mapping
+ */
+#define OMAP_ABE_DMIC_PORT 0
+#define OMAP_ABE_PDM_UL_PORT 1
+#define OMAP_ABE_BT_VX_UL_PORT 2
+#define OMAP_ABE_MM_UL_PORT 3
+#define OMAP_ABE_MM_UL2_PORT 4
+#define OMAP_ABE_VX_UL_PORT 5
+#define OMAP_ABE_MM_DL_PORT 6
+#define OMAP_ABE_VX_DL_PORT 7
+#define OMAP_ABE_TONES_DL_PORT 8
+#define OMAP_ABE_MCASP_DL_PORT 9
+#define OMAP_ABE_BT_VX_DL_PORT 10
+#define OMAP_ABE_PDM_DL_PORT 11
+#define OMAP_ABE_MM_EXT_OUT_PORT 12
+#define OMAP_ABE_MM_EXT_IN_PORT 13
+#define TDM_DL_PORT 14
+#define TDM_UL_PORT 15
+#define DEBUG_PORT 16
+#define LAST_PORT_ID 17
+
+#define FEAT_MIXDL1 14
+#define FEAT_MIXDL2 15
+#define FEAT_MIXAUDUL 16
+#define FEAT_GAINS 21
+#define FEAT_GAINS_DMIC1 22
+#define FEAT_GAINS_DMIC2 23
+#define FEAT_GAINS_DMIC3 24
+#define FEAT_GAINS_AMIC 25
+#define FEAT_GAIN_BTUL 29
+
+/* abe_mixer_id */
+#define MIXDL1 FEAT_MIXDL1
+#define MIXDL2 FEAT_MIXDL2
+#define MIXAUDUL FEAT_MIXAUDUL
+/*
+ * GAIN IDs
+ */
+#define GAINS_DMIC1 FEAT_GAINS_DMIC1
+#define GAINS_DMIC2 FEAT_GAINS_DMIC2
+#define GAINS_DMIC3 FEAT_GAINS_DMIC3
+#define GAINS_AMIC FEAT_GAINS_AMIC
+#define GAINS_BTUL FEAT_GAIN_BTUL
+
+/*
+ * EVENT GENERATORS - abe_event_id
+ */
+#define EVENT_TIMER 0
+#define EVENT_44100 1
+/*
+ * SERIAL PORTS IDs - abe_mcbsp_id
+ */
+#define MCBSP1_TX MCBSP1_DMA_TX
+#define MCBSP1_RX MCBSP1_DMA_RX
+#define MCBSP2_TX MCBSP2_DMA_TX
+#define MCBSP2_RX MCBSP2_DMA_RX
+#define MCBSP3_TX MCBSP3_DMA_TX
+#define MCBSP3_RX MCBSP3_DMA_RX
+
+/*
+ * SERIAL PORTS IDs - abe_mcasp_id
+ */
+#define MCASP1_TX McASP1_AXEVT
+#define MCASP1_RX McASP1_AREVT
+
+/*
+ * DATA_FORMAT_T
+ *
+ * used in port declaration
+ */
+struct omap_aess_data_format {
+ /* Sampling frequency of the stream */
+ u32 f;
+ /* Sample format type */
+ u32 samp_format;
+};
+
+/*
+ * PORT_PROTOCOL_T
+ *
+ * port declaration
+ */
+struct omap_aess_port_protocol {
+ /* Direction=0 means input from AESS point of view */
+ u32 direction;
+ /* Protocol type (switch) during the data transfers */
+ u32 protocol_switch;
+ union {
+ /* McBSP/McASP peripheral connected to ATC */
+ struct {
+ u32 desc_addr;
+ /* Address of ATC McBSP/McASP descriptor's in bytes */
+ u32 buf_addr;
+ /* DMEM address in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ } prot_serial;
+ /* DMIC peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* Number of activated DMIC */
+ u32 nbchan;
+ } prot_dmic;
+ /* McPDMDL peripheral connected to ATC */
+ struct {
+ /* DMEM address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes */
+ u32 buf_size;
+ /* Control allowed on McPDM DL */
+ u32 control;
+ } prot_mcpdmdl;
+ /* McPDMUL peripheral connected to ATC */
+ struct {
+ /* DMEM address size in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ } prot_mcpdmul;
+ /* Ping-Pong interface to the Host using cache-flush */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM size in bytes for each ping and pong buffers */
+ u32 buf_size;
+ /* IRQ address (either DMA (0) MCU (1) or DSP(2)) */
+ u32 irq_addr;
+ /* IRQ data content loaded in the AESS IRQ register */
+ u32 irq_data;
+ /* Call-back function upon IRQ reception */
+ u32 callback;
+ } prot_pingpong;
+ /* DMAreq line to CBPr */
+ struct {
+ /* Address of ATC descriptor's */
+ u32 desc_addr;
+ /* DMEM buffer address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size size in bytes */
+ u32 buf_size;
+ /* ITERation on each DMAreq signals */
+ u32 iter;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } prot_dmareq;
+ /* Circular buffer - direct addressing to DMEM */
+ struct {
+ /* DMEM buffer base address in bytes */
+ u32 buf_addr;
+ /* DMEM buffer size in bytes */
+ u32 buf_size;
+ /* DMAreq address */
+ u32 dma_addr;
+ /* DMA/AESS = 1 << #DMA */
+ u32 dma_data;
+ } prot_circular_buffer;
+ } p;
+};
+
+struct omap_aess_dma_offset {
+ /* Offset to the first address of the */
+ u32 data;
+ /* number of iterations for the DMA data moves. */
+ u32 iter;
+};
+
+/*
+ * ABE_PORT_T status / format / sampling / protocol(call_back) /
+ * features / gain / name ..
+ *
+ */
+
+struct omap_aess_task {
+ u8 frame;
+ u8 slot;
+ u16 task;
+};
+
+struct omap_aess_init_task {
+ u32 nb_task;
+ struct omap_aess_task task[2];
+};
+
+struct omap_aess_io_task {
+ u32 nb_task;
+ u32 smem;
+ struct omap_aess_task *task;
+};
+
+struct omap_aess_io_task1 {
+ u32 nb_task;
+ u32 smem;
+ struct omap_aess_task task[2];
+};
+
+struct omap_aess_port_type {
+ struct omap_aess_init_task serial;
+ struct omap_aess_init_task cbpr;
+};
+
+struct omap_aess_asrc_port {
+ struct omap_aess_io_task1 task;
+ struct omap_aess_port_type asrc;
+};
+
+struct omap_aess_port {
+ /* running / idled */
+ u16 status;
+ /* Sample format type */
+ struct omap_aess_data_format format;
+ /* IO tasks buffers */
+ u16 smem_buffer1;
+ u16 smem_buffer2;
+ struct omap_aess_port_protocol protocol;
+ /* pointer and iteration counter of the xDMA */
+ struct omap_aess_dma_offset dma;
+ struct omap_aess_init_task task;
+ struct omap_aess_asrc_port tsk_freq[4];
+};
+
+#define OMAP_AESS_GAIN_DMIC1_LEFT 0
+#define OMAP_AESS_GAIN_DMIC1_RIGHT 1
+#define OMAP_AESS_GAIN_DMIC2_LEFT 2
+#define OMAP_AESS_GAIN_DMIC2_RIGHT 3
+#define OMAP_AESS_GAIN_DMIC3_LEFT 4
+#define OMAP_AESS_GAIN_DMIC3_RIGHT 5
+#define OMAP_AESS_GAIN_AMIC_LEFT 6
+#define OMAP_AESS_GAIN_AMIC_RIGHT 7
+#define OMAP_AESS_GAIN_DL1_LEFT 8
+#define OMAP_AESS_GAIN_DL1_RIGHT 9
+#define OMAP_AESS_GAIN_DL2_LEFT 10
+#define OMAP_AESS_GAIN_DL2_RIGHT 11
+#define OMAP_AESS_GAIN_SPLIT_LEFT 12
+#define OMAP_AESS_GAIN_SPLIT_RIGHT 13
+#define OMAP_AESS_MIXDL1_MM_DL 14
+#define OMAP_AESS_MIXDL1_MM_UL2 15
+#define OMAP_AESS_MIXDL1_VX_DL 16
+#define OMAP_AESS_MIXDL1_TONES 17
+#define OMAP_AESS_MIXDL2_MM_DL 18
+#define OMAP_AESS_MIXDL2_MM_UL2 19
+#define OMAP_AESS_MIXDL2_VX_DL 20
+#define OMAP_AESS_MIXDL2_TONES 21
+#define OMAP_AESS_MIXECHO_DL1 22
+#define OMAP_AESS_MIXECHO_DL2 23
+#define OMAP_AESS_MIXSDT_UL 24
+#define OMAP_AESS_MIXSDT_DL 25
+#define OMAP_AESS_MIXVXREC_MM_DL 26
+#define OMAP_AESS_MIXVXREC_TONES 27
+#define OMAP_AESS_MIXVXREC_VX_UL 28
+#define OMAP_AESS_MIXVXREC_VX_DL 29
+#define OMAP_AESS_MIXAUDUL_MM_DL 30
+#define OMAP_AESS_MIXAUDUL_TONES 31
+#define OMAP_AESS_MIXAUDUL_UPLINK 32
+#define OMAP_AESS_MIXAUDUL_VX_DL 33
+#define OMAP_AESS_GAIN_BTUL_LEFT 34
+#define OMAP_AESS_GAIN_BTUL_RIGHT 35
+
+#endif /* _AESS_FW_H_ */
index bf346c5075d5eeef94828c5ffc62d65a6abab2c8..23fdb026cf2373c8f685d0e0a60a437ba5cc4b33 100644 (file)
#include <sound/soc.h>
#include <sound/soc-fw.h>
-#include <plat/cpu.h>
#include "../../../arch/arm/mach-omap2/omap-pm.h"
#include "omap-abe-priv.h"
int abe_pm_suspend(struct snd_soc_dai *dai);
int abe_pm_resume(struct snd_soc_dai *dai);
-int abe_mixer_write(struct snd_soc_platform *platform, unsigned int reg,
- unsigned int val);
-unsigned int abe_mixer_read(struct snd_soc_platform *platform,
- unsigned int reg);
irqreturn_t abe_irq_handler(int irq, void *dev_id);
void abe_init_debugfs(struct omap_abe *abe);
void abe_cleanup_debugfs(struct omap_abe *abe);
"mpu"
};
+/* TODO: map IO directly into ABE memories */
+static unsigned int omap_abe_oppwidget_read(struct snd_soc_platform *platform,
+ unsigned int reg)
+{
+ struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
+
+ if (reg > OMAP_ABE_NUM_DAPM_REG)
+ return 0;
+
+ dev_dbg(platform->dev, "read R%d (Ox%x) = 0x%x\n",
+ reg, reg, abe->opp.widget[reg]);
+ return abe->opp.widget[reg];
+}
+
+static int omap_abe_oppwidget_write(struct snd_soc_platform *platform, unsigned int reg,
+ unsigned int val)
+{
+ struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
+
+ if (reg > OMAP_ABE_NUM_DAPM_REG)
+ return 0;
+
+ abe->opp.widget[reg] = val;
+ dev_dbg(platform->dev, "write R%d (Ox%x) = 0x%x\n", reg, reg, val);
+ return 0;
+}
+
+
static void abe_init_gains(struct omap_aess *abe)
{
/* Uplink gains */
struct snd_soc_fw_hdr *hdr)
{
struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
- const u8 *fw_data = snd_soc_fw_get_data(hdr);
+ const void *fw_data = snd_soc_fw_get_data(hdr);
/* get firmware and coefficients header info */
memcpy(&abe->hdr, fw_data, sizeof(struct fw_header));
}
#endif
/* store ABE firmware for later context restore */
- abe->fw_text = kzalloc(hdr->size, GFP_KERNEL);
- if (abe->fw_text == NULL)
- return -ENOMEM;
-
- memcpy(abe->fw_text, fw_data, hdr->size);
+ abe->fw_data = fw_data;
return 0;
}
struct snd_soc_fw_hdr *hdr)
{
struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
- const u8 *fw_data = snd_soc_fw_get_data(hdr);
+ const void *fw_data = snd_soc_fw_get_data(hdr);
/* store ABE config for later context restore */
- abe->fw_config = kzalloc(hdr->size, GFP_KERNEL);
- if (abe->fw_config == NULL)
- return -ENOMEM;
-
dev_info(abe->dev, "ABE Config size %d bytes\n", hdr->size);
- memcpy(abe->fw_config, fw_data, hdr->size);
+ abe->fw_config = fw_data;
return 0;
}
static void abe_free_fw(struct omap_abe *abe)
{
- kfree(abe->fw_text);
- kfree(abe->fw_config);
-
/* This below should be done in HAL - oposite of init_mem()*/
if (!abe->aess)
return;
if (abe->aess->fw_info) {
- kfree(abe->aess->fw_info->init_table);
kfree(abe->aess->fw_info);
}
}
goto err_fw;
}
- ret = request_threaded_irq(abe->irq, NULL, abe_irq_handler,
- IRQF_ONESHOT, "ABE", (void *)abe);
+ ret = devm_request_threaded_irq(abe->dev, abe->irq, NULL, abe_irq_handler,
+ IRQF_ONESHOT, "ABE", (void *)abe);
if (ret) {
dev_err(platform->dev, "request for ABE IRQ %d failed %d\n",
abe->irq, ret);
for (i = 0; i < OMAP_ABE_ROUTES_UL + 2; i++)
abe->mixer.route_ul[i] = abe->aess->fw_info->label_id[OMAP_AESS_BUFFER_ZERO_ID];
- omap_aess_load_fw(abe->aess, abe->fw_text);
+ omap_aess_load_fw(abe->aess, abe->fw_data);
/* "tick" of the audio engine */
omap_aess_write_event_generator(abe->aess, EVENT_TIMER);
return ret;
-err_opp:
- free_irq(abe->irq, (void *)abe);
err_irq:
abe_free_fw(abe);
err_fw:
struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
abe_cleanup_debugfs(abe);
- free_irq(abe->irq, (void *)abe);
abe_free_fw(abe);
pm_runtime_disable(abe->dev);
.remove = abe_remove,
.suspend = abe_pm_suspend,
.resume = abe_pm_resume,
- .read = abe_mixer_read,
- .write = abe_mixer_write,
+ .read = omap_abe_oppwidget_read,
+ .write = omap_abe_oppwidget_write,
.stream_event = abe_opp_stream_event,
};
{
struct resource *res;
struct omap_abe *abe;
- int ret = -EINVAL, i;
+ int ret, i;
abe = devm_kzalloc(&pdev->dev, sizeof(struct omap_abe), GFP_KERNEL);
if (abe == NULL)
return -ENOMEM;
- dev_set_drvdata(&pdev->dev, abe);
for (i = 0; i < OMAP_ABE_IO_RESOURCES; i++) {
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
if (res == NULL) {
dev_err(&pdev->dev, "no resource %s\n",
abe_memory_bank[i]);
- goto err;
+ return -ENODEV;
}
- abe->io_base[i] = ioremap(res->start, resource_size(res));
- if (!abe->io_base[i]) {
- ret = -ENOMEM;
- goto err;
+ if (!devm_request_mem_region(&pdev->dev, res->start,
+ resource_size(res), abe_memory_bank[i]))
+ return -EBUSY;
+
+ abe->io_base[i] = devm_ioremap(&pdev->dev, res->start,
+ resource_size(res));
+ if (!abe->io_base[i])
+ return -ENOMEM;
+ }
+
+ for (i = 0; i < OMAP_ABE_DMA_RESOURCES; i++) {
+ char name[8];
+
+ sprintf(name, "fifo%d", i);
+ res = platform_get_resource_byname(pdev, IORESOURCE_DMA, name);
+ if (res == NULL) {
+ dev_err(&pdev->dev, "no resource %s\n", name);
+ return -ENODEV;
}
+ abe->dma_lines[i] = res->start;
}
abe->irq = platform_get_irq(pdev, 0);
- if (abe->irq < 0) {
- ret = abe->irq;
- goto err;
- }
+ if (abe->irq < 0)
+ return abe->irq;
+
+ dev_set_drvdata(&pdev->dev, abe);
#ifdef CONFIG_PM
abe->get_context_lost_count = omap_pm_get_dev_context_loss_count;
abe->device_scale = NULL;
#endif
abe->dev = &pdev->dev;
+
mutex_init(&abe->mutex);
mutex_init(&abe->opp.mutex);
mutex_init(&abe->opp.req_mutex);
put_device(abe->dev);
ret = request_firmware_nowait(THIS_MODULE, 1, "omap4_abe_new", abe->dev,
- GFP_KERNEL, pdev, abe_fw_ready);
- if (ret != 0) {
+ GFP_KERNEL, pdev, abe_fw_ready);
+ if (!ret)
dev_err(abe->dev, "Failed to load firmware %d\n", ret);
- goto err;
- }
-
- return ret;
-
-err:
- for (--i; i >= 0; i--)
- iounmap(abe->io_base[i]);
return ret;
}
static int abe_engine_remove(struct platform_device *pdev)
{
struct omap_abe *abe = dev_get_drvdata(&pdev->dev);
- int i;
snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(omap_abe_dai));
snd_soc_unregister_platform(&pdev->dev);
+
+ abe->fw_data = NULL;
+ abe->fw_config = NULL;
release_firmware(abe->fw);
- for (i = 0; i < OMAP_ABE_IO_RESOURCES; i++)
- iounmap(abe->io_base[i]);
return 0;
}
index 33abb0e9ec98336826601d1d6374e2490bbf5059..3d15c831a4bf44f283924f1cbae809ac558ede90 100644 (file)
#define abe_val_to_gain(val) \
(-OMAP_ABE_MAX_GAIN + (val * OMAP_ABE_GAIN_SCALE))
-/* TODO: map IO directly into ABE memories */
-unsigned int abe_mixer_read(struct snd_soc_platform *platform,
- unsigned int reg)
-{
- struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
-
- if (reg > OMAP_ABE_NUM_DAPM_REG)
- return 0;
-
- dev_dbg(platform->dev, "read R%d (Ox%x) = 0x%x\n",
- reg, reg, abe->opp.widget[reg]);
- return abe->opp.widget[reg];
-}
-
-int abe_mixer_write(struct snd_soc_platform *platform, unsigned int reg,
- unsigned int val)
-{
- struct omap_abe *abe = snd_soc_platform_get_drvdata(platform);
-
- if (reg > OMAP_ABE_NUM_DAPM_REG)
- return 0;
-
- abe->opp.widget[reg] = val;
- dev_dbg(platform->dev, "write R%d (Ox%x) = 0x%x\n", reg, reg, val);
- return 0;
-}
-
void omap_abe_dc_set_hs_offset(struct snd_soc_platform *platform,
int left, int right, int step_mV)
{
index 86b98c273c851bb99229728f8db9f37f7ce22803..bed4d47556970130d1a70889a58a334c9801d22d 100644 (file)
.buffer_bytes_max = 24 * 1024 * 2,
};
-static void abe_irq_pingpong_subroutine(u32 *sub, u32 *data)
+/*
+ * omap_aess_irq_data
+ *
+ * IRQ FIFO content declaration
+ * APS interrupts : IRQ_FIFO[31:28] = IRQtag_APS,
+ * IRQ_FIFO[27:16] = APS_IRQs, IRQ_FIFO[15:0] = loopCounter
+ * SEQ interrupts : IRQ_FIFO[31:28] OMAP_ABE_IRQTAG_COUNT,
+ * IRQ_FIFO[27:16] = Count_IRQs, IRQ_FIFO[15:0] = loopCounter
+ * Ping-Pong Interrupts : IRQ_FIFO[31:28] = OMAP_ABE_IRQTAG_PP,
+ * IRQ_FIFO[27:16] = PP_MCU_IRQ, IRQ_FIFO[15:0] = loopCounter
+ */
+struct omap_aess_irq_data {
+ unsigned int counter:16;
+ unsigned int data:12;
+ unsigned int tag:4;
+};
+
+#define OMAP_ABE_IRQTAG_COUNT 0x000c
+#define OMAP_ABE_IRQTAG_PP 0x000d
+#define OMAP_ABE_IRQ_FIFO_MASK ((OMAP_ABE_D_MCUIRQFIFO_SIZE >> 2) - 1)
+
+static void abe_irq_pingpong_subroutine(struct snd_pcm_substream *substream, struct omap_abe *abe)
{
- struct snd_pcm_substream *substream = (struct snd_pcm_substream *)sub;
- struct omap_abe *abe = (struct omap_abe *)data;
u32 dst, n_bytes;
omap_aess_read_next_ping_pong_buffer(abe->aess, OMAP_ABE_MM_DL_PORT, &dst, &n_bytes);
}
}
+
irqreturn_t abe_irq_handler(int irq, void *dev_id)
{
struct omap_abe *abe = dev_id;
+ struct omap_aess_addr addr;
+ struct omap_aess *aess = abe->aess;
+ struct omap_aess_irq_data IRQ_data;
+ u32 abe_irq_dbg_write_ptr, i, cmem_src, sm_cm;
pm_runtime_get_sync(abe->dev);
omap_aess_clear_irq(abe->aess);
- omap_aess_irq_processing(abe->aess);
+
+ /* extract the write pointer index from CMEM memory (INITPTR format) */
+ /* CMEM address of the write pointer in bytes */
+ cmem_src = aess->fw_info->label_id[OMAP_AESS_BUFFER_MCU_IRQ_FIFO_PTR_ID] << 2;
+ omap_abe_mem_read(aess, OMAP_ABE_CMEM, cmem_src,
+ &sm_cm, sizeof(abe_irq_dbg_write_ptr));
+ /* AESS left-pointer index located on MSBs */
+ abe_irq_dbg_write_ptr = sm_cm >> 16;
+ abe_irq_dbg_write_ptr &= 0xFF;
+ /* loop on the IRQ FIFO content */
+ for (i = 0; i < OMAP_ABE_D_MCUIRQFIFO_SIZE; i++) {
+ /* stop when the FIFO is empty */
+ if (abe_irq_dbg_write_ptr == aess->irq_dbg_read_ptr)
+ break;
+ /* read the IRQ/DBG FIFO */
+ memcpy(&addr, &aess->fw_info->map[OMAP_AESS_DMEM_MCUIRQFIFO_ID],
+ sizeof(struct omap_aess_addr));
+ addr.offset += (aess->irq_dbg_read_ptr << 2);
+ addr.bytes = sizeof(IRQ_data);
+ omap_aess_mem_read(aess, addr, (u32 *)&IRQ_data);
+ aess->irq_dbg_read_ptr = (aess->irq_dbg_read_ptr + 1) & OMAP_ABE_IRQ_FIFO_MASK;
+ /* select the source of the interrupt */
+ switch (IRQ_data.tag) {
+ case OMAP_ABE_IRQTAG_PP:
+ /* first IRQ doesn't represent a buffer transference completion */
+ if (aess->pp_first_irq)
+ aess->pp_first_irq = 0;
+ else
+ aess->pp_buf_id = (aess->pp_buf_id + 1) & 0x03;
+
+ abe_irq_pingpong_subroutine(abe->dai.port[OMAP_ABE_FE_PORT_MM_DL_LP]->substream,
+ abe);
+
+ break;
+ case OMAP_ABE_IRQTAG_COUNT:
+ /*omap_aess_monitoring(aess);*/
+ break;
+ default:
+ break;
+ }
+
+ }
+
pm_runtime_put_sync_suspend(abe->dev);
return IRQ_HANDLED;
}
-static int omap_abe_hwrule_period_step(struct snd_pcm_hw_params *params,
+static int omap_abe_hwrule_size_step(struct snd_pcm_hw_params *params,
struct snd_pcm_hw_rule *rule)
{
- struct snd_interval *period_size = hw_param_interval(params,
- SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
unsigned int rate = params_rate(params);
/* 44.1kHz has the same iteration number as 48kHz */
rate = (rate == 44100) ? 48000 : rate;
/* ABE requires chunks of 250us worth of data */
- return snd_interval_step(period_size, 0, rate / 4000);
+ return snd_interval_step(hw_param_interval(params, rule->var), 0,
+ rate / 4000);
}
static int aess_open(struct snd_pcm_substream *substream)
break;
default:
/*
- * Period size must be aligned with the Audio Engine
+ * Period and buffer size must be aligned with the Audio Engine
* processing loop which is 250 us long
*/
ret = snd_pcm_hw_rule_add(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
- omap_abe_hwrule_period_step,
+ omap_abe_hwrule_size_step,
NULL,
SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
+ ret = snd_pcm_hw_rule_add(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
+ omap_abe_hwrule_size_step,
+ NULL,
+ SNDRV_PCM_HW_PARAM_BUFFER_SIZE, -1);
break;
}
struct snd_soc_dai *dai = rtd->cpu_dai;
struct omap_aess_data_format format;
size_t period_size;
- u32 dst, param[2];
+ u32 dst;
int ret = 0;
mutex_lock(&abe->mutex);
format.f = params_rate(params);
if (params_format(params) == SNDRV_PCM_FORMAT_S32_LE)
- format.samp_format = STEREO_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_MSB;
else
- format.samp_format = STEREO_16_16;
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_16_16;
period_size = params_period_bytes(params);
- param[0] = (u32)substream;
- param[1] = (u32)abe;
-
- /* Adding ping pong buffer subroutine */
- omap_aess_plug_subroutine(abe->aess, &abe->aess->seq.irq_pingpong_player_id,
- (abe_subroutine2) abe_irq_pingpong_subroutine,
- 2, param);
-
/* Connect a Ping-Pong cache-flush protocol to MM_DL port */
omap_aess_connect_irq_ping_pong_port(abe->aess, OMAP_ABE_MM_DL_PORT, &format,
- abe->aess->seq.irq_pingpong_player_id,
+ 0,
period_size, &dst,
PING_PONG_WITH_MCU_IRQ);
index 0444bc403b942162bcb2c87b1a7fb8c5bba2bc5f..ac16aa644bd58e30a2fbdd77f4631771a810f835 100644 (file)
/* BT_DL connection to McBSP 1 ports */
format.f = 8000;
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_BT_VX_DL_PORT, &format, MCBSP1_TX);
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+ omap_aess_connect_serial_port(abe->aess, OMAP_ABE_BT_VX_DL_PORT, &format, MCBSP1_TX, NULL);
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_BE_PORT_BT_VX_DL]);
} else {
/* BT_UL connection to McBSP 1 ports */
format.f = 8000;
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_BT_VX_UL_PORT, &format, MCBSP1_RX);
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+ omap_aess_connect_serial_port(abe->aess, OMAP_ABE_BT_VX_UL_PORT, &format, MCBSP1_RX, NULL);
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_BE_PORT_BT_VX_UL]);
}
/* MM_EXT connection to McBSP 2 ports */
format.f = 48000;
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_MM_EXT_OUT_PORT, &format, MCBSP2_TX);
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+ omap_aess_connect_serial_port(abe->aess, OMAP_ABE_MM_EXT_OUT_PORT, &format, MCBSP2_TX, NULL);
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_BE_PORT_MM_EXT_DL]);
} else {
/* MM_EXT connection to McBSP 2 ports */
format.f = 48000;
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_MM_EXT_IN_PORT, &format, MCBSP2_RX);
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+ omap_aess_connect_serial_port(abe->aess, OMAP_ABE_MM_EXT_IN_PORT, &format, MCBSP2_RX, NULL);
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_BE_PORT_MM_EXT_UL]);
}
abe->dai.port[OMAP_ABE_FE_PORT_MM_UL1]);
break;
case OMAP_ABE_FRONTEND_DAI_LP_MEDIA:
- if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+ if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
omap_abe_port_enable(abe->aess,
abe->dai.port[OMAP_ABE_FE_PORT_MM_DL_LP]);
+ abe->dai.port[OMAP_ABE_FE_PORT_MM_DL_LP]->substream = substream;
+ }
break;
case OMAP_ABE_FRONTEND_DAI_MEDIA_CAPTURE:
if (stream == SNDRV_PCM_STREAM_CAPTURE)
struct omap_abe *abe = snd_soc_dai_get_drvdata(dai);
struct omap_pcm_dma_data *dma_data;
struct omap_aess_data_format format;
- struct omap_aess_dma dma_sink;
struct omap_aess_dma dma_params;
dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
switch (params_channels(params)) {
case 1:
if (params_format(params) == SNDRV_PCM_FORMAT_S16_LE)
- format.samp_format = MONO_16_16;
+ format.samp_format = OMAP_AESS_FORMAT_MONO_16_16;
else
- format.samp_format = MONO_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_MONO_MSB;
break;
case 2:
if (params_format(params) == SNDRV_PCM_FORMAT_S16_LE)
- format.samp_format = STEREO_16_16;
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_16_16;
else
- format.samp_format = STEREO_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_MSB;
break;
case 3:
- format.samp_format = THREE_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_THREE_MSB;
break;
case 4:
- format.samp_format = FOUR_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_FOUR_MSB;
break;
case 5:
- format.samp_format = FIVE_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_FIVE_MSB;
break;
case 6:
- format.samp_format = SIX_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_SIX_MSB;
break;
case 7:
- format.samp_format = SEVEN_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_SEVEN_MSB;
break;
case 8:
- format.samp_format = EIGHT_MSB;
+ format.samp_format = OMAP_AESS_FORMAT_EIGHT_MSB;
break;
default:
dev_err(dai->dev, "%d channels not supported",
switch (dai->id) {
case OMAP_ABE_FRONTEND_DAI_MEDIA:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_MM_DL_PORT, &format, ABE_CBPR0_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_MM_DL_PORT, &dma_params);
- } else {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_MM_UL_PORT, &format, ABE_CBPR3_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_MM_UL_PORT, &dma_params);
- }
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_MM_DL_PORT, &format,
+ ABE_CBPR0_IDX, &dma_params);
+ else
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_MM_UL_PORT, &format,
+ ABE_CBPR3_IDX, &dma_params);
break;
case OMAP_ABE_FRONTEND_DAI_LP_MEDIA:
return 0;
case OMAP_ABE_FRONTEND_DAI_MEDIA_CAPTURE:
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
return -EINVAL;
- else {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_MM_UL2_PORT, &format, ABE_CBPR4_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_MM_UL2_PORT, &dma_params);
- }
+ else
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_MM_UL2_PORT, &format,
+ ABE_CBPR4_IDX, &dma_params);
break;
case OMAP_ABE_FRONTEND_DAI_VOICE:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_VX_DL_PORT, &format, ABE_CBPR1_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_VX_DL_PORT, &dma_params);
- } else {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_VX_UL_PORT, &format, ABE_CBPR2_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_VX_UL_PORT, &dma_params);
- }
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_VX_DL_PORT, &format,
+ ABE_CBPR1_IDX, &dma_params);
+ else
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_VX_UL_PORT, &format,
+ ABE_CBPR2_IDX, &dma_params);
break;
case OMAP_ABE_FRONTEND_DAI_TONES:
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- omap_aess_connect_cbpr_dmareq_port(abe->aess, OMAP_ABE_TONES_DL_PORT, &format, ABE_CBPR5_IDX,
- &dma_sink);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_TONES_DL_PORT, &dma_params);
- } else
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ omap_aess_connect_cbpr_dmareq_port(abe->aess,
+ OMAP_ABE_TONES_DL_PORT, &format,
+ ABE_CBPR5_IDX, &dma_params);
+ else
return -EINVAL;
break;
case OMAP_ABE_FRONTEND_DAI_MODEM:
/* MODEM is special case where data IO is performed by McBSP2
* directly onto VX_DL and VX_UL (instead of SDMA).
*/
- if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
- /* Vx_DL connection to McBSP 2 ports */
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_VX_DL_PORT, &format, MCBSP2_RX);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_VX_DL_PORT, &dma_params);
- } else {
- /* Vx_UL connection to McBSP 2 ports */
- format.samp_format = STEREO_RSHIFTED_16;
- omap_aess_connect_serial_port(abe->aess, OMAP_ABE_VX_UL_PORT, &format, MCBSP2_TX);
- omap_aess_read_port_address(abe->aess, OMAP_ABE_VX_UL_PORT, &dma_params);
- }
+ format.samp_format = OMAP_AESS_FORMAT_STEREO_RSHIFTED_16;
+
+ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+ omap_aess_connect_serial_port(abe->aess,
+ OMAP_ABE_VX_DL_PORT, &format,
+ MCBSP2_RX, &dma_params);
+ else
+ omap_aess_connect_serial_port(abe->aess,
+ OMAP_ABE_VX_UL_PORT, &format,
+ MCBSP2_TX, &dma_params);
break;
default:
dev_err(dai->dev, "port %d not supported\n", dai->id);
index c4cf0a57487d624be3eec444e44dd00b0c285098..284e73fac76eab8d30f2b1d80082a2cc025bd5a9 100644 (file)
}
}
- omap_aess_reload_fw(abe->aess, abe->fw_text);
+ omap_aess_reload_fw(abe->aess, abe->fw_data);
switch (dai->id) {
case OMAP_ABE_DAI_PDM_UL:
index ff0379582d62deac2c5b0970878343fb40c4fc77..d6763c7511d9b5f59890427e0bcad819dc8ff3af 100644 (file)
OMAP_ABE_MIXER_VOLUME, \
SOC_CONTROL_TYPE_VOLSW)
+#define OMAP_ABE_DMA_RESOURCES 8
#ifdef __KERNEL__
struct clk *clk;
void __iomem *io_base[OMAP_ABE_IO_RESOURCES];
+ int dma_lines[OMAP_ABE_DMA_RESOURCES];
int irq;
int active;
struct mutex mutex;
/* firmware */
struct fw_header hdr;
u32 *fw_config;
- u32 *fw_text;
+ const void *fw_data;
const struct firmware *fw;
int num_equ;
index 597e83b2fa430223bfe70b07c3e5003d7b357e19..b7c687a9421f166c8388b5b7aa1c6bb8809b42c9 100644 (file)
static const struct snd_soc_dapm_route dmic_audio_map[] = {
/* Digital Mics: DMic0, DMic1, DMic2 with bias */
- {"DMIC0", NULL, "omap-dmic-abe.0 Capture"},
- {"omap-dmic-abe.0 Capture", NULL, "Digital Mic1 Bias"},
+ {"DMIC0", NULL, "omap-dmic-abe Capture"},
+ {"omap-dmic-abe Capture", NULL, "Digital Mic1 Bias"},
{"Digital Mic1 Bias", NULL, "Digital Mic 0"},
- {"DMIC1", NULL, "omap-dmic-abe.1 Capture"},
- {"omap-dmic-abe.1 Capture", NULL, "Digital Mic1 Bias"},
+ {"DMIC1", NULL, "omap-dmic-abe Capture"},
+ {"omap-dmic-abe Capture", NULL, "Digital Mic1 Bias"},
{"Digital Mic1 Bias", NULL, "Digital Mic 1"},
- {"DMIC2", NULL, "omap-dmic-abe.2 Capture"},
- {"omap-dmic-abe.2 Capture", NULL, "Digital Mic1 Bias"},
+ {"DMIC2", NULL, "omap-dmic-abe Capture"},
+ {"omap-dmic-abe Capture", NULL, "Digital Mic1 Bias"},
{"Digital Mic1 Bias", NULL, "Digital Mic 2"},
};
{
/* McPDM DL1 - Headset */
SND_SOC_DAI_CONNECT("McPDM-DL1", "twl6040-codec", "aess",
- "twl6040-dl1", "mcpdm-dl1"),
+ "twl6040-dl1", "mcpdm-abe"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_PDM_DL1, mcpdm_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_mcpdm_ops, omap_abe_twl6040_init),
SND_SOC_DAI_IGNORE_SUSPEND, SND_SOC_DAI_IGNORE_PMDOWN,
{
/* McPDM UL1 - Analog Capture */
SND_SOC_DAI_CONNECT("McPDM-UL1", "twl6040-codec", "aess",
- "twl6040-ul", "mcpdm-ul1"),
+ "twl6040-ul", "mcpdm-abe"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_PDM_UL, mcpdm_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_mcpdm_ops, NULL),
SND_SOC_DAI_IGNORE_SUSPEND, SND_SOC_DAI_IGNORE_PMDOWN,
{
/* McPDM DL2 - Handsfree */
SND_SOC_DAI_CONNECT("McPDM-DL2", "twl6040-codec", "aess",
- "twl6040-dl2", "mcpdm-dl2"),
+ "twl6040-dl2", "mcpdm-abe"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_PDM_DL2, mcpdm_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_mcpdm_ops, omap_abe_twl6040_dl2_init),
SND_SOC_DAI_IGNORE_SUSPEND, SND_SOC_DAI_IGNORE_PMDOWN,
{
/* DMIC0 */
SND_SOC_DAI_CONNECT("DMIC-0", "dmic-codec", "aess",
- "dmic-hifi", "omap-dmic-abe-dai-0"),
+ "dmic-hifi", "omap-dmic-abe-dai"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_DMIC0, dmic_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_dmic_ops, NULL),
},
{
/* DMIC1 */
SND_SOC_DAI_CONNECT("DMIC-1", "dmic-codec", "aess",
- "dmic-hifi", "omap-dmic-abe-dai-1"),
+ "dmic-hifi", "omap-dmic-abe-dai"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_DMIC1, dmic_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_dmic_ops, NULL),
},
{
/* DMIC2 */
SND_SOC_DAI_CONNECT("DMIC-2", "dmic-codec", "aess",
- "dmic-hifi", "omap-dmic-abe-dai-2"),
+ "dmic-hifi", "omap-dmic-abe-dai"),
SND_SOC_DAI_BE_LINK(OMAP_ABE_DAI_DMIC2, dmic_be_hw_params_fixup),
SND_SOC_DAI_OPS(&omap_abe_dmic_ops, NULL),
},
index 6e5c7b8a9678ff2fc3410f1d1a92f0186714924b..56738100e09fb15ac1e096c4bdd8b6a63d2507a3 100644 (file)
#include "omap-pcm.h"
#include "omap-dmic.h"
-#define OMAP_DMIC_LEGACY_MODE 0x0
-#define OMAP_DMIC_ABE_MODE 0x1
-
-#define OMAP_DMIC_DAI_MODE_MASK 0x0f
+#define OMAP_DMIC_LEGACY_DAI 0
+#define OMAP_DMIC_ABE_DAI 1
struct omap_dmic {
struct device *dev;
int threshold;
u32 ch_enabled;
int active;
- bool abe_mode;
+ bool active_dai;
int running;
struct mutex mutex;
};
struct snd_soc_dai *dai)
{
struct omap_dmic *dmic = snd_soc_dai_get_drvdata(dai);
- int dai_abe_mode = dai->id & OMAP_DMIC_DAI_MODE_MASK;
int ret = 0;
mutex_lock(&dmic->mutex);
if (!dmic->active++) {
- dmic->abe_mode = dai_abe_mode;
+ dmic->active_dai = dai->id;
/* DMIC FIFO configuration */
- if (dmic->abe_mode == OMAP_DMIC_LEGACY_MODE)
+ if (dai->id == OMAP_DMIC_LEGACY_DAI)
dmic->threshold = OMAP_DMIC_THRES_MAX - 3;
else
dmic->threshold = 2;
- } else if (dmic->abe_mode != dai_abe_mode) {
+ } else if (dmic->active_dai != dai->id) {
dev_err(dmic->dev, "Trying %s, while DMIC is in %s.\n",
- dai_abe_mode ? "ABE mode" : "Legacy mode",
- dmic->abe_mode ? "ABE mode" : "Legacy mode");
+ dai->id ? "ABE mode" : "Legacy mode",
+ dmic->active_dai ? "ABE mode" : "Legacy mode");
dmic->active--;
ret = -EINVAL;
}
dmic->ch_enabled = 0;
channels = params_channels(params);
- if (dmic->abe_mode == OMAP_DMIC_LEGACY_MODE)
+ if (dai->id == OMAP_DMIC_LEGACY_DAI)
select_channels = channels;
else
select_channels = 6;
return 0;
}
-#define DMIC_LEGACY_DAI (OMAP_DMIC_LEGACY_MODE | (0 << 4))
-#define DMIC_ABE_DAI_1 (OMAP_DMIC_ABE_MODE | (1 << 4))
-#define DMIC_ABE_DAI_2 (OMAP_DMIC_ABE_MODE | (2 << 4))
-#define DMIC_ABE_DAI_3 (OMAP_DMIC_ABE_MODE | (3 << 4))
-
static struct snd_soc_dai_driver omap_dmic_dai[] = {
{
.name = "omap-dmic",
- .id = DMIC_LEGACY_DAI,
+ .id = OMAP_DMIC_LEGACY_DAI,
.probe = omap_dmic_probe,
.remove = omap_dmic_remove,
.capture = {
.ops = &omap_dmic_dai_ops,
},
{
- .name = "omap-dmic-abe-dai-0",
- .id = DMIC_ABE_DAI_1,
- .capture = {
- .stream_name = "omap-dmic-abe.0 Capture",
- .channels_min = 2,
- .channels_max = 2,
- .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
- .formats = SNDRV_PCM_FMTBIT_S32_LE,
- },
- .ops = &omap_dmic_dai_ops,
-},
-{
- .name = "omap-dmic-abe-dai-1",
- .id = DMIC_ABE_DAI_2,
- .capture = {
- .stream_name = "omap-dmic-abe.1 Capture",
- .channels_min = 2,
- .channels_max = 2,
- .rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
- .formats = SNDRV_PCM_FMTBIT_S32_LE,
- },
- .ops = &omap_dmic_dai_ops,
-},
-{
- .name = "omap-dmic-abe-dai-2",
- .id = DMIC_ABE_DAI_3,
+ .name = "omap-dmic-abe-dai",
+ .id = OMAP_DMIC_ABE_DAI,
.capture = {
- .stream_name = "omap-dmic-abe.2 Capture",
+ .stream_name = "omap-dmic-abe Capture",
.channels_min = 2,
.channels_max = 2,
.rates = SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000,
{
struct omap_dmic *dmic;
struct resource *res;
- int ret;
+ int ret, nr_dai;
dmic = devm_kzalloc(&pdev->dev, sizeof(struct omap_dmic), GFP_KERNEL);
if (!dmic)
goto err_put_clk;
}
- if (!devm_request_mem_region(&pdev->dev, res->start,
- resource_size(res), pdev->name)) {
- dev_err(dmic->dev, "memory region already claimed\n");
- ret = -ENODEV;
- goto err_put_clk;
- }
-
- dmic->io_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
+ dmic->io_base = devm_request_and_ioremap(&pdev->dev, res);
if (!dmic->io_base) {
+ dev_err(&pdev->dev, "cannot remap\n");
ret = -ENOMEM;
goto err_put_clk;
}
- ret = snd_soc_register_dais(&pdev->dev, omap_dmic_dai,
- ARRAY_SIZE(omap_dmic_dai));
+#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
+ defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
+ nr_dai = ARRAY_SIZE(omap_dmic_dai);
+#else
+ nr_dai = 1;
+#endif
+ ret = snd_soc_register_dais(&pdev->dev, omap_dmic_dai, nr_dai);
if (ret)
goto err_put_clk;
index 84e16f053bb16f85fb3279d0af7930082b0e47ad..4b0ea194bf745646c8e99a2dce845d9a01fce189 100644 (file)
.ops = &omap_mcasp_dai_ops,
};
-static int omap_mcasp_probe(struct platform_device *pdev)
+static int asoc_mcasp_probe(struct platform_device *pdev)
{
struct omap_mcasp *mcasp;
struct resource *res;
return mcasp->irq;
}
- ret = request_threaded_irq(mcasp->irq, NULL, omap_mcasp_irq_handler,
- IRQF_ONESHOT, "McASP", mcasp);
+ ret = devm_request_threaded_irq(&pdev->dev, mcasp->irq, NULL,
+ omap_mcasp_irq_handler,
+ IRQF_ONESHOT, "McASP", mcasp);
if (ret) {
dev_err(mcasp->dev, "IRQ request failed\n");
return ret;
mcasp->fclk = clk_get(&pdev->dev, "fck");
if (!mcasp->fclk) {
dev_err(mcasp->dev, "cant get fck\n");
- ret = -ENODEV;
- goto err_clk;
+ return -ENODEV;
}
pm_runtime_enable(&pdev->dev);
err_dai:
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
-err_clk:
- free_irq(mcasp->irq, (void *)mcasp);
return ret;
}
-static int omap_mcasp_remove(struct platform_device *pdev)
+static int asoc_mcasp_remove(struct platform_device *pdev)
{
struct omap_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
snd_soc_unregister_dai(&pdev->dev);
pm_runtime_disable(&pdev->dev);
clk_put(mcasp->fclk);
- free_irq(mcasp->irq, (void *)mcasp);
return 0;
}
MODULE_DEVICE_TABLE(of, omap_mcasp_of_match);
static struct platform_driver omap_mcasp_driver = {
- .probe = omap_mcasp_probe,
- .remove = omap_mcasp_remove,
.driver = {
.name = "omap-mcasp",
.owner = THIS_MODULE,
.of_match_table = omap_mcasp_of_match,
},
+ .probe = asoc_mcasp_probe,
+ .remove = asoc_mcasp_remove,
};
static int __init omap_mcasp_init(void)
index 4c5345ad976c0fcb3d4c3fa11fc4690daed7640a..ee7fabe9e82c3d8cc314c8454574928fe6443bc5 100644 (file)
#include "omap-abe-priv.h"
-#define MCPDM_LEGACY_MODE 0x0
-#define MCPDM_ABE_MODE 0x1
-
-#define MCPDM_DAI_MODE_MASK 0x0f
+#define OMAP_MCPDM_LEGACY_DAI 0
+#define OMAP_MCPDM_ABE_DAI 1
struct omap_mcpdm {
struct device *dev;
u32 dn_rx_offset;
int active;
- int abe_mode;
+ int active_dai;
- struct omap_aess *abe;
+ struct omap_aess *aess;
struct omap_abe_port *dl_port;
struct omap_abe_port *ul_port;
};
struct snd_soc_dai *dai)
{
struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
- int dai_abe_mode = dai->id & MCPDM_DAI_MODE_MASK;
int ret = 0;
mutex_lock(&mcpdm->mutex);
omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
- mcpdm->abe_mode = dai_abe_mode;
+ mcpdm->active_dai = dai->id;
/* McPDM FIFO configuration */
mcpdm->dn_threshold = 2;
- if (mcpdm->abe_mode == MCPDM_LEGACY_MODE)
+ if (dai->id == OMAP_MCPDM_LEGACY_DAI)
mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
else
mcpdm->up_threshold = 2;
- } else if (mcpdm->abe_mode != dai_abe_mode) {
+ } else if (mcpdm->active_dai != dai->id) {
dev_err(mcpdm->dev, "Trying %s, while McPDM is in %s.\n",
- dai_abe_mode ? "ABE mode" : "Legacy mode",
- mcpdm->abe_mode ? "ABE mode" : "Legacy mode");
+ dai->id ? "ABE mode" : "Legacy mode",
+ mcpdm->active_dai ? "ABE mode" : "Legacy mode");
ret = -EINVAL;
}
if (!dai->active) {
if (omap_mcpdm_active(mcpdm)) {
- if (mcpdm->abe_mode == MCPDM_LEGACY_MODE) {
+ if (dai->id == OMAP_MCPDM_LEGACY_DAI) {
omap_mcpdm_stop(mcpdm);
omap_mcpdm_close_streams(mcpdm);
} else {
- omap_abe_port_disable(mcpdm->abe,
+ omap_abe_port_disable(mcpdm->aess,
mcpdm->dl_port);
- omap_abe_port_disable(mcpdm->abe,
+ omap_abe_port_disable(mcpdm->aess,
mcpdm->ul_port);
usleep_range(250, 300);
omap_mcpdm_stop(mcpdm);
dma_data = snd_soc_dai_get_dma_data(dai, substream);
/* ABE DAIs have fixed channels */
- if ((dai->id & MCPDM_DAI_MODE_MASK) == MCPDM_ABE_MODE) {
+ if (dai->id == OMAP_MCPDM_ABE_DAI) {
mcpdm->dn_channels = MCPDM_PDM_DN_MASK | MCPDM_CMD_INT;
mcpdm->up_channels = MCPDM_PDM_UPLINK_EN(1) |
MCPDM_PDM_UPLINK_EN(2);
if (omap_mcpdm_active(mcpdm))
return 0;
- if (mcpdm->abe_mode == MCPDM_ABE_MODE) {
+ if (dai->id == OMAP_MCPDM_ABE_DAI) {
/* Check if ABE McPDM DL is already started */
- if ((omap_abe_port_is_enabled(mcpdm->abe, mcpdm->dl_port)) ||
- (omap_abe_port_is_enabled(mcpdm->abe, mcpdm->ul_port)))
+ if ((omap_abe_port_is_enabled(mcpdm->aess, mcpdm->dl_port)) ||
+ (omap_abe_port_is_enabled(mcpdm->aess, mcpdm->ul_port)))
return 0;
omap_abe_pm_get(platform);
/* start ATC before McPDM IP */
- omap_abe_port_enable(mcpdm->abe, mcpdm->dl_port);
- omap_abe_port_enable(mcpdm->abe, mcpdm->ul_port);
+ omap_abe_port_enable(mcpdm->aess, mcpdm->dl_port);
+ omap_abe_port_enable(mcpdm->aess, mcpdm->ul_port);
/* wait 250us for ABE tick */
usleep_range(250, 300);
struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
int ret;
+ mcpdm->aess = omap_abe_port_mgr_get();
+
+ mcpdm->dl_port = omap_abe_port_open(mcpdm->aess,
+ OMAP_ABE_BE_PORT_PDM_DL1);
+ if (mcpdm->dl_port == NULL) {
+ omap_abe_port_mgr_put(mcpdm->aess);
+ return -EINVAL;
+ }
+
+ mcpdm->ul_port = omap_abe_port_open(mcpdm->aess,
+ OMAP_ABE_BE_PORT_PDM_UL1);
+ if (mcpdm->ul_port == NULL) {
+ omap_abe_port_close(mcpdm->aess, mcpdm->dl_port);
+ omap_abe_port_mgr_put(mcpdm->aess);
+ return -EINVAL;
+ }
+
pm_runtime_enable(mcpdm->dev);
/* Disable lines while request is ongoing */
pm_runtime_get_sync(mcpdm->dev);
omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
- ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
+ ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
0, "McPDM", (void *)mcpdm);
pm_runtime_put_sync(mcpdm->dev);
if (ret) {
dev_err(mcpdm->dev, "Request for IRQ failed\n");
pm_runtime_disable(mcpdm->dev);
+
+ omap_abe_port_close(mcpdm->aess, mcpdm->dl_port);
+ omap_abe_port_close(mcpdm->aess, mcpdm->ul_port);
+ omap_abe_port_mgr_put(mcpdm->aess);
}
/* Configure McPDM threshold values */
{
struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
- free_irq(mcpdm->irq, (void *)mcpdm);
pm_runtime_disable(mcpdm->dev);
+ omap_abe_port_close(mcpdm->aess, mcpdm->dl_port);
+ omap_abe_port_close(mcpdm->aess, mcpdm->ul_port);
+ omap_abe_port_mgr_put(mcpdm->aess);
+
return 0;
}
#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
-#define MCPDM_LEGACY_DAI (MCPDM_LEGACY_MODE | (0 << 4))
-#define MCPDM_ABE_DAI_DL1 (MCPDM_ABE_MODE | (1 << 4))
-#define MCPDM_ABE_DAI_DL2 (MCPDM_ABE_MODE | (2 << 4))
-#define MCPDM_ABE_DAI_UL1 (MCPDM_ABE_MODE | (4 << 4))
-
static struct snd_soc_dai_driver omap_mcpdm_dai[] = {
{
.name = "mcpdm-legacy",
- .id = MCPDM_LEGACY_DAI,
+ .id = OMAP_MCPDM_LEGACY_DAI,
.probe = omap_mcpdm_probe,
.remove = omap_mcpdm_remove,
.probe_order = SND_SOC_COMP_ORDER_LATE,
},
.ops = &omap_mcpdm_dai_ops,
},
-#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
- defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
{
- .name = "mcpdm-dl1",
- .id = MCPDM_ABE_DAI_DL1,
+ .name = "mcpdm-abe",
+ .id = OMAP_MCPDM_ABE_DAI,
.probe_order = SND_SOC_COMP_ORDER_LATE,
.remove_order = SND_SOC_COMP_ORDER_EARLY,
.playback = {
.rates = OMAP_MCPDM_RATES,
.formats = OMAP_MCPDM_FORMATS,
},
- .ops = &omap_mcpdm_dai_ops,
-},
-{
- .name = "mcpdm-dl2",
- .id = MCPDM_ABE_DAI_DL2,
- .probe_order = SND_SOC_COMP_ORDER_LATE,
- .remove_order = SND_SOC_COMP_ORDER_EARLY,
- .playback = {
- .channels_min = 1,
- .channels_max = 2,
- .rates = OMAP_MCPDM_RATES,
- .formats = OMAP_MCPDM_FORMATS,
- },
- .ops = &omap_mcpdm_dai_ops,
-},
-{
- .name = "mcpdm-ul1",
- .id = MCPDM_ABE_DAI_UL1,
- .probe_order = SND_SOC_COMP_ORDER_LATE,
- .remove_order = SND_SOC_COMP_ORDER_EARLY,
.capture = {
.channels_min = 1,
.channels_max = 2,
},
.ops = &omap_mcpdm_dai_ops,
},
-#endif
};
void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
{
struct omap_mcpdm *mcpdm;
struct resource *res;
- int ret;
+ int ret, nr_dai;
mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
if (!mcpdm)
omap_mcpdm_dai_dma_params[0].port_addr = res->start + MCPDM_REG_DN_DATA;
omap_mcpdm_dai_dma_params[1].port_addr = res->start + MCPDM_REG_UP_DATA;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (res == NULL)
- return -ENOMEM;
-
res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
if (!res)
return -ENODEV;
if (res == NULL)
return -ENOMEM;
- if (!devm_request_mem_region(&pdev->dev, res->start,
- resource_size(res), "McPDM"))
- return -EBUSY;
-
- mcpdm->io_base = devm_ioremap(&pdev->dev, res->start,
- resource_size(res));
- if (!mcpdm->io_base)
+ mcpdm->io_base = devm_request_and_ioremap(&pdev->dev, res);
+ if (!mcpdm->io_base) {
+ dev_err(&pdev->dev, "cannot remap\n");
return -ENOMEM;
+ }
mcpdm->irq = platform_get_irq(pdev, 0);
if (mcpdm->irq < 0)
#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
-
- mcpdm->abe = omap_abe_port_mgr_get();
-
- mcpdm->dl_port = omap_abe_port_open(mcpdm->abe,
- OMAP_ABE_BE_PORT_PDM_DL1);
- if (mcpdm->dl_port == NULL) {
- omap_abe_port_mgr_put(mcpdm->abe);
- return -EINVAL;
- }
-
- mcpdm->ul_port = omap_abe_port_open(mcpdm->abe,
- OMAP_ABE_BE_PORT_PDM_UL1);
- if (mcpdm->ul_port == NULL) {
- omap_abe_port_close(mcpdm->abe, mcpdm->dl_port);
- omap_abe_port_mgr_put(mcpdm->abe);
- return -EINVAL;
- }
+ nr_dai = ARRAY_SIZE(omap_mcpdm_dai);
+#else
+ nr_dai = 1;
#endif
- ret = snd_soc_register_dais(&pdev->dev, omap_mcpdm_dai,
- ARRAY_SIZE(omap_mcpdm_dai));
- if (!ret)
- return 0;
+ ret = snd_soc_register_dais(&pdev->dev, omap_mcpdm_dai, nr_dai);
-#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
- defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
- omap_abe_port_close(mcpdm->abe, mcpdm->dl_port);
- omap_abe_port_close(mcpdm->abe, mcpdm->ul_port);
- omap_abe_port_mgr_put(mcpdm->abe);
-#endif
return ret;
}
static int asoc_mcpdm_remove(struct platform_device *pdev)
{
- struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
-
snd_soc_unregister_dai(&pdev->dev);
-#if defined(CONFIG_SND_OMAP_SOC_ABE) ||\
- defined(CONFIG_SND_OMAP_SOC_ABE_MODULE)
- omap_abe_port_close(mcpdm->abe, mcpdm->dl_port);
- omap_abe_port_close(mcpdm->abe, mcpdm->ul_port);
- omap_abe_port_mgr_put(mcpdm->abe);
-#endif
-
return 0;
}
diff --git a/sound/usb/6fire/pcm.c b/sound/usb/6fire/pcm.c
index e2ca12fe92e946f662d47ae39983e176f7a50402..40dd50a80f55de653ffc30c2c4a4960c4d868025 100644 (file)
--- a/sound/usb/6fire/pcm.c
+++ b/sound/usb/6fire/pcm.c
urb->instance.pipe = in ? usb_rcvisocpipe(chip->dev, ep)
: usb_sndisocpipe(chip->dev, ep);
urb->instance.interval = 1;
- urb->instance.transfer_flags = URB_ISO_ASAP;
urb->instance.complete = handler;
urb->instance.context = urb;
urb->instance.number_of_packets = PCM_N_PACKETS_PER_URB;
index fde9a7a29cb6e670ba2d58e49b8b9e39a5cd7f15..b45e29b8c675f557ceb818ede6b90bd45809c415 100644 (file)
--- a/sound/usb/caiaq/audio.c
+++ b/sound/usb/caiaq/audio.c
if (send_it) {
out->number_of_packets = outframe;
- out->transfer_flags = URB_ISO_ASAP;
usb_submit_urb(out, GFP_ATOMIC);
} else {
struct snd_usb_caiaq_cb_info *oinfo = out->context;
}
urb->number_of_packets = FRAMES_PER_URB;
- urb->transfer_flags = URB_ISO_ASAP;
usb_submit_urb(urb, GFP_ATOMIC);
}
* BYTES_PER_FRAME;
urbs[i]->context = &dev->data_cb_info[i];
urbs[i]->interval = 1;
- urbs[i]->transfer_flags = URB_ISO_ASAP;
urbs[i]->number_of_packets = FRAMES_PER_URB;
urbs[i]->complete = (dir == SNDRV_PCM_STREAM_CAPTURE) ?
read_completed : write_completed;
diff --git a/sound/usb/card.c b/sound/usb/card.c
index ccf95cfe186f324a7a7b95dc4c71e118df063706..a9d57799c5e543fc6d33aa842bb59f587b80af5b 100644 (file)
--- a/sound/usb/card.c
+++ b/sound/usb/card.c
int err = -ENODEV;
down_read(&chip->shutdown_rwsem);
- if (!chip->shutdown && !chip->probing)
+ if (chip->probing)
+ err = 0;
+ else if (!chip->shutdown)
err = usb_autopm_get_interface(chip->pm_intf);
up_read(&chip->shutdown_rwsem);
diff --git a/sound/usb/card.h b/sound/usb/card.h
index 8a751b4887ea87043fb34483a652f0d444145d5a..d32ea411545a2ccccccfe100bdebb801c2fa1979 100644 (file)
--- a/sound/usb/card.h
+++ b/sound/usb/card.h
unsigned int altset_idx; /* USB data format: index of alternate setting */
unsigned int txfr_quirk:1; /* allow sub-frame alignment */
unsigned int fmt_type; /* USB audio format type (1-3) */
+ unsigned int pkt_offset_adj; /* Bytes to drop from beginning of packets (for non-compliant devices) */
unsigned int running: 1; /* running status */
diff --git a/sound/usb/endpoint.c b/sound/usb/endpoint.c
index 21049b882ee6445d47714074fddbcb550cf5eef8..63cca3a219c9e10c5104bda9c5a4b03a4f35f795 100644 (file)
--- a/sound/usb/endpoint.c
+++ b/sound/usb/endpoint.c
if (!u->urb->transfer_buffer)
goto out_of_memory;
u->urb->pipe = ep->pipe;
- u->urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP;
+ u->urb->transfer_flags = URB_NO_TRANSFER_DMA_MAP;
u->urb->interval = 1 << ep->datainterval;
u->urb->context = u;
u->urb->complete = snd_complete_urb;
u->urb->transfer_dma = ep->sync_dma + i * 4;
u->urb->transfer_buffer_length = 4;
u->urb->pipe = ep->pipe;
- u->urb->transfer_flags = URB_ISO_ASAP |
- URB_NO_TRANSFER_DMA_MAP;
+ u->urb->transfer_flags = URB_NO_TRANSFER_DMA_MAP;
u->urb->number_of_packets = 1;
u->urb->interval = 1 << ep->syncinterval;
u->urb->context = u;
diff --git a/sound/usb/midi.c b/sound/usb/midi.c
index 34b9bb7fe87c8eabed83df8b7b77f510bedbc2b1..e5fee1800a4fbc37174e100cca49533038fa266f 100644 (file)
--- a/sound/usb/midi.c
+++ b/sound/usb/midi.c
struct snd_usb_midi_in_endpoint *in;
} endpoints[MIDI_MAX_ENDPOINTS];
unsigned long input_triggered;
- bool autopm_reference;
unsigned int opened[2];
unsigned char disconnected;
unsigned char input_running;
{
struct snd_usb_midi* umidi = substream->rmidi->private_data;
struct snd_kcontrol *ctl;
- int err;
down_read(&umidi->disc_rwsem);
if (umidi->disconnected) {
mutex_lock(&umidi->mutex);
if (open) {
if (!umidi->opened[0] && !umidi->opened[1]) {
- err = usb_autopm_get_interface(umidi->iface);
- umidi->autopm_reference = err >= 0;
- if (err < 0 && err != -EACCES) {
- mutex_unlock(&umidi->mutex);
- up_read(&umidi->disc_rwsem);
- return -EIO;
- }
if (umidi->roland_load_ctl) {
ctl = umidi->roland_load_ctl;
ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
snd_ctl_notify(umidi->card,
SNDRV_CTL_EVENT_MASK_INFO, &ctl->id);
}
- if (umidi->autopm_reference)
- usb_autopm_put_interface(umidi->iface);
}
}
mutex_unlock(&umidi->mutex);
return err;
}
+ usb_autopm_get_interface_no_resume(umidi->iface);
+
list_add_tail(&umidi->list, midi_list);
return 0;
}
diff --git a/sound/usb/misc/ua101.c b/sound/usb/misc/ua101.c
index 8b81cb54026f9877d5c83a9a91b95ff1a8abde55..6ad617b947321b438d3ae1b1071364109747d379 100644 (file)
--- a/sound/usb/misc/ua101.c
+++ b/sound/usb/misc/ua101.c
usb_init_urb(&urb->urb);
urb->urb.dev = ua->dev;
urb->urb.pipe = stream->usb_pipe;
- urb->urb.transfer_flags = URB_ISO_ASAP |
- URB_NO_TRANSFER_DMA_MAP;
+ urb->urb.transfer_flags = URB_NO_TRANSFER_DMA_MAP;
urb->urb.transfer_buffer = addr;
urb->urb.transfer_dma = dma;
urb->urb.transfer_buffer_length = max_packet_size;
diff --git a/sound/usb/pcm.c b/sound/usb/pcm.c
index d82e378d37cbb7202aaa487b6003b6b171b79eab..bcc50ed275a4278af124bb1da34c8eeb469bcac4 100644 (file)
--- a/sound/usb/pcm.c
+++ b/sound/usb/pcm.c
stride = runtime->frame_bits >> 3;
for (i = 0; i < urb->number_of_packets; i++) {
- cp = (unsigned char *)urb->transfer_buffer + urb->iso_frame_desc[i].offset;
+ cp = (unsigned char *)urb->transfer_buffer + urb->iso_frame_desc[i].offset + subs->pkt_offset_adj;
if (urb->iso_frame_desc[i].status && printk_ratelimit()) {
snd_printdd(KERN_ERR "frame %d active: %d\n", i, urb->iso_frame_desc[i].status);
// continue;
diff --git a/sound/usb/quirks.c b/sound/usb/quirks.c
index b9ca776705af71c24438182ca7c249f26ff8c6e2..f581c3e226fbd427cd8da07e4c8c8486bc65da20 100644 (file)
--- a/sound/usb/quirks.c
+++ b/sound/usb/quirks.c
break;
}
snd_emuusb_set_samplerate(subs->stream->chip, emu_samplerate_id);
+ subs->pkt_offset_adj = (emu_samplerate_id >= EMU_QUIRK_SR_176400HZ) ? 4 : 0;
}
void snd_usb_set_format_quirk(struct snd_usb_substream *subs,
diff --git a/sound/usb/stream.c b/sound/usb/stream.c
index ad181d538bd9658edd79fec07d2fae125c9ebd38..cfc4d4eaf42b706e1d64aff76cc908b9c3d84046 100644 (file)
--- a/sound/usb/stream.c
+++ b/sound/usb/stream.c
subs->dev = as->chip->dev;
subs->txfr_quirk = as->chip->txfr_quirk;
subs->speed = snd_usb_get_speed(subs->dev);
+ subs->pkt_offset_adj = 0;
snd_usb_set_pcm_ops(as->pcm, stream);
if (!csep && altsd->bNumEndpoints >= 2)
csep = snd_usb_find_desc(alts->endpoint[1].extra, alts->endpoint[1].extralen, NULL, USB_DT_CS_ENDPOINT);
+ /*
+ * If we can't locate the USB_DT_CS_ENDPOINT descriptor in the extra
+ * bytes after the first endpoint, go search the entire interface.
+ * Some devices have it directly *before* the standard endpoint.
+ */
+ if (!csep)
+ csep = snd_usb_find_desc(alts->extra, alts->extralen, NULL, USB_DT_CS_ENDPOINT);
+
if (!csep || csep->bLength < 7 ||
csep->bDescriptorSubtype != UAC_EP_GENERAL) {
snd_printk(KERN_WARNING "%d:%u:%d : no or invalid"
index 1e7a47a86605078d2934720f168da85cbf8145ce..bf618e1500acb3488193b90e6e7dc4469e22509d 100644 (file)
++u, transfer += transfer_length) {
struct urb *urb = urbs[u];
struct usb_iso_packet_descriptor *desc;
- urb->transfer_flags = URB_ISO_ASAP;
urb->transfer_buffer = transfer;
urb->dev = dev;
urb->pipe = pipe;
index 520ef96d7c75f14094c12ce4cc950e72c846c5d2..b37653247ef4e035b096153253b69ca0fd1e9a8b 100644 (file)
if (0 == i)
atomic_set(&subs->state, state_STARTING3);
urb->dev = usX2Y->dev;
- urb->transfer_flags = URB_ISO_ASAP;
for (pack = 0; pack < nr_of_packs(); pack++) {
urb->iso_frame_desc[pack].offset = subs->maxpacksize * pack;
urb->iso_frame_desc[pack].length = subs->maxpacksize;
index cc56007791e02192bd6176050a252b1eed2fc53a..f2a1acdc4d839f22eb7fa83d63b5f35ce367c5cd 100644 (file)
if (0 == u)
atomic_set(&subs->state, state_STARTING3);
urb->dev = usX2Y->dev;
- urb->transfer_flags = URB_ISO_ASAP;
for (pack = 0; pack < nr_of_packs(); pack++) {
urb->iso_frame_desc[pack].offset = subs->maxpacksize * (pack + u * nr_of_packs());
urb->iso_frame_desc[pack].length = subs->maxpacksize;
diff --git a/virt/kvm/ioapic.c b/virt/kvm/ioapic.c
index cfb7e4d52dc26d1c832eb2a554d8a8ed1d9d23c3..52058f0defb4a842ef3a24cc9220b52e017ecdbc 100644 (file)
--- a/virt/kvm/ioapic.c
+++ b/virt/kvm/ioapic.c
u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
u64 redir_content;
- ASSERT(redir_index < IOAPIC_NUM_PINS);
+ if (redir_index < IOAPIC_NUM_PINS)
+ redir_content =
+ ioapic->redirtbl[redir_index].bits;
+ else
+ redir_content = ~0ULL;
- redir_content = ioapic->redirtbl[redir_index].bits;
result = (ioapic->ioregsel & 0x1) ?
(redir_content >> 32) & 0xffffffff :
redir_content & 0xffffffff;
diff --git a/virt/kvm/kvm_main.c b/virt/kvm/kvm_main.c
index 1cd693a76a510c34a2d563d9fe68072802d28620..10afa343baafac498abd43072c74713b576dc7f7 100644 (file)
--- a/virt/kvm/kvm_main.c
+++ b/virt/kvm/kvm_main.c
}
int kvm_gfn_to_hva_cache_init(struct kvm *kvm, struct gfn_to_hva_cache *ghc,
- gpa_t gpa)
+ gpa_t gpa, unsigned long len)
{
struct kvm_memslots *slots = kvm_memslots(kvm);
int offset = offset_in_page(gpa);
- gfn_t gfn = gpa >> PAGE_SHIFT;
+ gfn_t start_gfn = gpa >> PAGE_SHIFT;
+ gfn_t end_gfn = (gpa + len - 1) >> PAGE_SHIFT;
+ gfn_t nr_pages_needed = end_gfn - start_gfn + 1;
+ gfn_t nr_pages_avail;
ghc->gpa = gpa;
ghc->generation = slots->generation;
- ghc->memslot = gfn_to_memslot(kvm, gfn);
- ghc->hva = gfn_to_hva_many(ghc->memslot, gfn, NULL);
- if (!kvm_is_error_hva(ghc->hva))
+ ghc->len = len;
+ ghc->memslot = gfn_to_memslot(kvm, start_gfn);
+ ghc->hva = gfn_to_hva_many(ghc->memslot, start_gfn, &nr_pages_avail);
+ if (!kvm_is_error_hva(ghc->hva) && nr_pages_avail >= nr_pages_needed) {
ghc->hva += offset;
- else
- return -EFAULT;
-
+ } else {
+ /*
+ * If the requested region crosses two memslots, we still
+ * verify that the entire region is valid here.
+ */
+ while (start_gfn <= end_gfn) {
+ ghc->memslot = gfn_to_memslot(kvm, start_gfn);
+ ghc->hva = gfn_to_hva_many(ghc->memslot, start_gfn,
+ &nr_pages_avail);
+ if (kvm_is_error_hva(ghc->hva))
+ return -EFAULT;
+ start_gfn += nr_pages_avail;
+ }
+ /* Use the slow path for cross page reads and writes. */
+ ghc->memslot = NULL;
+ }
return 0;
}
EXPORT_SYMBOL_GPL(kvm_gfn_to_hva_cache_init);
struct kvm_memslots *slots = kvm_memslots(kvm);
int r;
+ BUG_ON(len > ghc->len);
+
if (slots->generation != ghc->generation)
- kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa);
+ kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa, ghc->len);
+
+ if (unlikely(!ghc->memslot))
+ return kvm_write_guest(kvm, ghc->gpa, data, len);
if (kvm_is_error_hva(ghc->hva))
return -EFAULT;
struct kvm_memslots *slots = kvm_memslots(kvm);
int r;
+ BUG_ON(len > ghc->len);
+
if (slots->generation != ghc->generation)
- kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa);
+ kvm_gfn_to_hva_cache_init(kvm, ghc, ghc->gpa, ghc->len);
+
+ if (unlikely(!ghc->memslot))
+ return kvm_read_guest(kvm, ghc->gpa, data, len);
if (kvm_is_error_hva(ghc->hva))
return -EFAULT;