| author | Praneeth Bajjuri <praneeth@ti.com> | |
| Thu, 13 Jun 2013 23:22:51 +0000 (18:22 -0500) | ||
| committer | Praneeth Bajjuri <praneeth@ti.com> | |
| Thu, 13 Jun 2013 23:22:51 +0000 (18:22 -0500) |
* p-ti-linux-3.8.y: (406 commits)
ARM: OMAP4+: omap2plus_defconfig: Enable audio via TWL6040 as module
ASoC: OMAP4+: AESS: aess_mem: Activate AESS for memory/register access
ARM: dts: OMAP5: AESS: Fix AESS L3 Interconnect address
ASoC: OMAP: ABE: Pick working ABE support from LDC audio branch
TI-Integration: ARM: OMAP2+: Fix merege by restoring omap_mcasp_init() call
omapdss: TFCS panel: Check for successful TLC driver registration before using it
omapdss: DSS DPLLs: Ignore PLL_PWR_STATUS on DRA7
ARM: DRA7: dts: Add the sdma dt node and corresponding dma request lines for mmc
ARM: dra7: dts: Add a fixed regulator node needed for eMMC
arm/dts: dra7: Add ldo regulator for mmc1
arm/dts: dra7: Add mmc controller nodes and board data
ARM: DRA: hwmod: Correct the dma line names for mmc
arch: arm: configs: Add support for DRA7 evm in omap2plus_defconfig
arm: dts: dra7-evm: Add pinmux configs needed for display
HACK: pinctrl: pinctrl single: Make pinctrl-single init early
OMAPDSS:HDMI: Change PLL calculations
omapdss: hdmi: fix deepcolor mode configuration
ARM: dts: DRA7x: Add DMM bindings
omapdrm: hack: Assign managers/channel to outputs in a more trivial way
gpu: drm: omap: Use bitmaps for placement
...
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
ARM: OMAP4+: omap2plus_defconfig: Enable audio via TWL6040 as module
ASoC: OMAP4+: AESS: aess_mem: Activate AESS for memory/register access
ARM: dts: OMAP5: AESS: Fix AESS L3 Interconnect address
ASoC: OMAP: ABE: Pick working ABE support from LDC audio branch
TI-Integration: ARM: OMAP2+: Fix merege by restoring omap_mcasp_init() call
omapdss: TFCS panel: Check for successful TLC driver registration before using it
omapdss: DSS DPLLs: Ignore PLL_PWR_STATUS on DRA7
ARM: DRA7: dts: Add the sdma dt node and corresponding dma request lines for mmc
ARM: dra7: dts: Add a fixed regulator node needed for eMMC
arm/dts: dra7: Add ldo regulator for mmc1
arm/dts: dra7: Add mmc controller nodes and board data
ARM: DRA: hwmod: Correct the dma line names for mmc
arch: arm: configs: Add support for DRA7 evm in omap2plus_defconfig
arm: dts: dra7-evm: Add pinmux configs needed for display
HACK: pinctrl: pinctrl single: Make pinctrl-single init early
OMAPDSS:HDMI: Change PLL calculations
omapdss: hdmi: fix deepcolor mode configuration
ARM: dts: DRA7x: Add DMM bindings
omapdrm: hack: Assign managers/channel to outputs in a more trivial way
gpu: drm: omap: Use bitmaps for placement
...
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
495 files changed:
diff --git a/Documentation/devicetree/bindings/arm/omap/dmm.txt b/Documentation/devicetree/bindings/arm/omap/dmm.txt
--- /dev/null
@@ -0,0 +1,17 @@
+OMAP Dynamic Memory Manager (DMM) bindings
+
+Required properties:
+- compatible: Must be "ti,omap4-dmm" for OMAP4 family
+ Must be "ti,omap5-dmm" for OMAP5 family
+- reg: Contains timer register address range (base address and length)
+- interrupts: Contains interrupt information (source, etc) for the DMM IRQ
+- ti,hwmods: Name of the hwmod associated to the counter, which is typically
+ "dmm"
+
+Example:
+
+dmm: dmm@4e000000 {
+ compatible = "ti,omap4-dmm";
+ reg = <0x4e000000 0x800>;
+ ti,hwmods = "dmm";
+};
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index d0051a7505873e14d17c5a8718179f19475a78bc..4f87488af6cb7e402126b8a766d482fa38492638 100644 (file)
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
+
+- DRA7 EVM: Software Developement Board for DRA7XX
+ compatible = "ti,dra7-evm", "ti,dra7"
diff --git a/Documentation/devicetree/bindings/clock/palmas-clk.txt b/Documentation/devicetree/bindings/clock/palmas-clk.txt
--- /dev/null
@@ -0,0 +1,27 @@
+* palmas and palmas-charger resource clock IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-clk
+ ti,twl6036-clk
+ ti,twl6037-clk
+ ti,tps65913-clk
+ ti,tps65914-clk
+ ti,tps80036-clk
+and also the generic series names
+ ti,palmas-clk
+
+Optional properties:
+- ti,clk32g-mode-sleep - mode to adopt in pmic sleep 0 - off, 1 - on
+- ti,clkg32kgaudio-mode-sleep - see above
+
+Example:
+
+clk {
+ compatible = "ti,twl6035-clk", "ti,palmas-clk";
+ ti,clk32kg-mode-sleep = <0>;
+ ti,clk32kgaudio-mode-sleep = <0>;
+ #clock-cells = <1>;
+ clock-frequency = <32000000>;
+ clock-names = "clk32kg", "clk32kgaudio";
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-palmas.txt b/Documentation/devicetree/bindings/gpio/gpio-palmas.txt
--- /dev/null
@@ -0,0 +1,35 @@
+* palmas and palmas charger GPIO IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-gpio
+ ti,twl6036-gpio
+ ti,twl6037-gpio
+ ti,tps65913-gpio
+ ti,tps65914-gpio
+ ti,tps80036-gpio
+
+and also the generic series names
+
+ ti,palmas-gpio
+
+- gpio-controller: mark the device as a GPIO controller
+- gpio-cells = <1>: GPIO lines are provided.
+- interrupt-controller : palmas has its own internal IRQs
+- #interrupt-cells : should be set to 2 for IRQ number and flags
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as the trigger masks from
+ Documentation/devicetree/bindings/interrupts.txt
+- interrupt-parent : The parent interrupt controller.
+
+Example:
+
+gpio {
+ compatible = "ti,twl6035-gpio", "ti,palmas-gpio";
+
+ gpio-controller;
+ #gpio-cells = <1>;
+ interrupt-parent = <&palmas>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt b/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt
--- /dev/null
@@ -0,0 +1,26 @@
+* palmas and palmas-charger Button IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-pwrbutton
+ ti,twl6036-pwrbutton
+ ti,twl6037-pwrbutton
+ ti,tps65913-pwrbutton
+ ti,tps65914-pwrbutton
+ ti,tps80036-pwrbutton
+and also the generic series names
+ ti,palmas-pwrbutton
+
+- interrupts: the interrupt outputs of the controller.
+- interrupt-names : Should be the name of irq resource. Each interrupt
+ binds its interrupt-name.
+- interrupt-parent : The parent interrupt controller.
+
+Example:
+
+pwrbutton {
+ compatible = "ti,twl6035-pwrbutton", "ti,palmas-pwrbutton";
+ interrupt-parent = <&palmas>;
+ interrupts = <1 0>;
+ interrupt-names = "pwron-irq";
+};
diff --git a/Documentation/devicetree/bindings/leds/leds-palmas.txt b/Documentation/devicetree/bindings/leds/leds-palmas.txt
--- /dev/null
@@ -0,0 +1,36 @@
+* palmas and palmas-charger LED IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-leds
+ ti,twl6036-leds
+ ti,twl6037-leds
+ ti,tps65913-leds
+ ti,tps65914-leds
+ ti,tps80036-leds
+and also the generic series names
+ ti,palmas-leds
+
+Optional properties:
+-ti,led1-current - sink current setting 0 - 0mA, 1 - 25mA, 2 - 5mA,
+ 3 - 0mA, 4 - 5mA, 5 - 5mA, 6 - 10.0mA, 7 - 0mA
+-ti,led2-current - see above
+-ti,led3-current - see above
+-ti,led4-current - see above
+-ti,chrg-led-mode - only valid for charger - mode for charging led operation
+ 0 - Charging indicator
+ 1 - controlled as a general purpose LED
+-ti,chrg-led-vbat-low - only valid for charger - blinking of low battery led
+ 0 - blinking is enabled,
+ 1 - blinking is disabled
+
+Example:
+leds {
+ compatible = "ti,twl6035-leds", "ti,palmas-leds";
+ ti,led1-current = <0>;
+ ti,led2-current = <0>;
+ ti,led3-current = <0>;
+ ti,led4-current = <0>;
+ ti,chrg-led-mode = <0>;
+ ti,chrg-led-vbat-low = <0>;
+};
diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt
index 94a0c12789461f399244d206f130adf2081b564a..3defba700eed5a3414689396325ca73049bd007f 100644 (file)
-Texas Instruments Palmas family
-
-The Palmas familly are Integrated Power Management Chips.
-These chips are connected to an i2c bus.
+* palmas and palmas-charger device tree bindings
+The TI palmas family current members :-
+twl6035 (palmas)
+twl6036 (palmas-charger)
+twl6037 (palmas)
+tps65913 (palmas)
+tps65914 (palmas)
+tps80036 (palmas-charger)
Required properties:
-- compatible : Must be "ti,palmas";
- For Integrated power-management in the palmas series, twl6035, twl6037,
- tps65913
-- interrupts : This i2c device has an IRQ line connected to the main SoC
-- interrupt-controller : Since the palmas support several interrupts internally,
- it is considered as an interrupt controller cascaded to the SoC one.
-- #interrupt-cells = <1>;
+- compatible : Should be from the list
+ ti,twl6035
+ ti,twl6036
+ ti,twl6037
+ ti,tps65913
+ ti,tps65914
+ ti,tps80036
+ ti,tps659038
+and also the generic series names
+ ti,palmas
+ ti,palmas-charger
+- interrupt-controller : palmas has its own internal IRQs
+- #interrupt-cells : should be set to 2 for IRQ number and flags
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as the trigger masks from
+ Documentation/devicetree/bindings/interrupts.txt
- interrupt-parent : The parent interrupt controller.
-Optional node:
-- Child nodes contain in the palmas. The palmas family is made of several
- variants that support a different number of features.
- The child nodes will thus depend of the capability of the variant.
-- mux_pad1 if a value is given it will be used for the pad1 mux
-- mux_pad2 if a value us given it will be used for the pad2 mux
-- power_ctrl if a value is given it will be written to the POWER_CTRL register
+Optional properties:
+ ti,mux_padX : set the pad register X (1-2) to the correct muxing for the
+ hardware, if not set will use muxing in OTP.
Example:
-/*
- * Integrated Power Management Chip Palmas
- */
-palmas@48 {
- compatible = "ti,palmas";
- reg = <0x48>;
- interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,mux_pad1 = <0x00>;
- ti,mux_pad2 = <0x00>;
- ti,power_ctrl = <0x03>;
+palmas {
+ compatible = "ti,twl6035", "ti,palmas";
+ reg = <0x48>
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,mux-pad1 = <0>;
+ ti,mux-pad2 = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic {
+ compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+ ....
+ }
+
+ gpio {
+ compatible = "ti,twl6035-gpio", "ti,palmas-gpio";
+ ....
+ };
+
+ wdt {
+ compatible = "ti,twl6035-wdt", "ti,palmas-wdt";
+ ....
+ };
+
+ rtc {
+ compatible = "ti,twl6035-rtc", "ti,palmas-rtc";
+ ....
+ };
- palmas_pmic {
- compatible = "ti,palmas_pmic";
- regulators {
- smps12_reg: smps12 {
- regulator-min-microvolt = < 600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- ti,warm_sleep = <0>;
- ti,roof_floor = <0>;
- ti,mode_sleep = <0>;
- ti,warm_reset = <0>;
- ti,tstep = <0>;
- ti,vsel = <0>;
- };
- };
- ti,ldo6_vibrator = <0>;
+ pwrbutton {
+ compatible = "ti,twl6035-pwrbutton", "ti,palmas-pwrbutton";
+ ....
};
- palmas_rtc {
- compatible = "ti,palmas_rtc";
- interrupts = <8 9>;
- reg = <0>;
- };
-};
+ leds {
+ compatible = "ti,twl6035-leds", "ti-palmas-leds";
+ }
+
+ clk {
+ compatible = "ti,twl6035-clk", "ti,palmas-clk";
+ ....
+ };
+}
diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
--- /dev/null
@@ -0,0 +1,169 @@
+* palmas and palmas-charger regulator IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-pmic
+ ti,twl6036-pmic
+ ti,twl6037-pmic
+ ti,tps65913-pmic
+ ti,tps65914-pmic
+ ti,tps80036-pmic
+ ti,tps659038-pmic
+and also the generic series names
+ ti,palmas-pmic
+
+Optional properties:
+- ti,ldo6-vibrator : ldo6 is in vibrator mode
+
+Optional nodes:
+- regulators : should contain the constrains and init information for the
+ regulators. It should contain a subnode per regulator from the
+ list.
+ For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
+ smps45, smps457, smps7 depending on varient, smps6, smps[8-10],
+ ldo[1-9], ldoln, ldousb
+ For ti,palmas-charger-pmic - smps12, smps123, smps3 depending on OTP,
+ smps[6-9], boost, ldo[1-14], ldoln, ldousb
+
+ optional chip specific regulator fields :-
+ ti,warm-reset - maintain voltage during warm reset
+ ti,roof-floor - control voltage selection by pin
+ ti,sleep-mode - mode to adopt in pmic sleep 0 - off, 1 - auto,
+ 2 - eco, 3 - forced pwm
+ ti,tstep - slope control 0 - Jump, 1 10mV/us, 2 5mV/us, 3 2.5mV/us
+ ti,smps-range - OTP has the wrong range set for the hardware so override
+ 0 - low range, 1 - high range
+
+Example:
+
+pmic@0 {
+ compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+ interrupt-parent = <&palmas>;
+ interrupts = <14 0>;
+ interrupt-name = "short-irq";
+
+ ti,ldo6_vibrator;
+
+ regulators {
+ smps12_reg : smps12 {
+ regulator-name = "smps12";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,warm-reset;
+ ti,roof-floor;
+ ti,mode-sleep = <0>;
+ ti,tstep = <0>;
+ ti,smps-range = <1>;
+ };
+
+ smps3_reg: smps3 {
+ regulator-name = "smps3";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ };
+
+ smps45_reg: smps45 {
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ };
+
+ smps6_reg: smps6 {
+ regulator-name = "smps6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ smps7_reg: smps7 {
+ regulator-name = "smps7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ smps8_reg: smps8 {
+ regulator-name = "smps8";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ };
+
+ smps9_reg: smps9 {
+ regulator-name = "smps9";
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ smps10_reg: smps10 {
+ regulator-name = "smps10";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldoln_reg: ldoln {
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldousb_reg: ldousb {
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3250000>;
+ regulator-max-microvolt = <3250000>;
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/regulator/ti-avs-class0.txt b/Documentation/devicetree/bindings/regulator/ti-avs-class0.txt
--- /dev/null
@@ -0,0 +1,66 @@
+Texas Instrument SmartReflex AVS Class 0 Regulator
+
+Required properties:
+- compatible: "ti,avsclass0"
+- reg: Should contain Efuse registers location and length
+- avs-supply: The supply for AVS block
+- efuse-settings: An array of 2-tuples items, and each item consists
+ of Voltage index and efuse offset(from reg) like: <voltage offset>
+ voltage: Voltage index in microvolts (also called nominal voltage)
+ offset: ofset in bytes from base provided in reg
+ NOTE: min_uV, max_uV are pickedup from this list
+
+Optional properties:
+- voltage-tolerance: Specify the voltage tolerance in percentage
+- ti,avsclass0-microvolt-values: Boolean property indicating that the efuse
+ values are in microvolts
+
+Example #1: single rails:
+soc.dtsi:
+avs_mpu: regulator-avs@0x40200000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40200000 0x20>;
+ efuse-settings = <975000 0
+ 1075000 4
+ 1200000 8>;
+};
+
+avs_core: regulator-avs@0x40300000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40300000 0x20>;
+ efuse-settings = <975000 0
+ 1050000 4>;
+};
+
+board.dtsi:
+&avs_mpu {
+ avs-supply = <&vcc>;
+};
+&avs_core {
+ avs-supply = <&smps2>;
+};
+
+Example #2: Ganged (combined) rails:
+soc.dtsi:
+avs_mpu: regulator-avs@0x40200000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40200000 0x20>;
+ efuse-settings = <975000 0
+ 1075000 4
+ 1200000 8>;
+};
+
+avs_core: regulator-avs@0x40300000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40300000 0x20>;
+ efuse-settings = <975000 0
+ 1050000 4>;
+};
+
+board.dtsi:
+&avs_mpu {
+ avs-supply = <&smps3>;
+};
+&avs_core {
+ avs-supply = <&smps3>;
+};
diff --git a/Documentation/devicetree/bindings/rtc/palmas-rtc.txt b/Documentation/devicetree/bindings/rtc/palmas-rtc.txt
--- /dev/null
@@ -0,0 +1,21 @@
+* palmas and palmas-charger RTC IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-rtc
+ ti,twl6036-rtc
+ ti,twl6037-rtc
+ ti,tps65913-rtc
+ ti,tps65914-rtc
+ ti,tps80036-rtc
+and also the generic series names
+ ti,palmas-rtc
+
+Examples:
+
+rtc {
+ compatible = "ti,twl6035-rtc", "ti,palmas-rtc";
+ interrupt-parent = <&palmas>;
+ interrupts = <8 0 9 0>;
+ interrupt-name = "alarm-irq", "timer-irq";
+};
diff --git a/Documentation/devicetree/bindings/watchdog/palmas-wdt.txt b/Documentation/devicetree/bindings/watchdog/palmas-wdt.txt
--- /dev/null
@@ -0,0 +1,21 @@
+* palmas and palmas-charger Watchdog IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-wdt
+ ti,twl6036-wdt
+ ti,twl6037-wdt
+ ti,tps65913-wdt
+ ti,tps65914-wdt
+ ti,tps80036-wdt
+and also the generic series names
+ ti,palmas-wdt
+
+Examples:
+
+wdt {
+ compatible = "ti,twl6035-wdt", "ti,palmas-wdt";
+ interrupt-parent = <&palmas>;
+ interrupts = <10 0>;
+ interrupt-name = "watchdog-irq";
+};
diff --git a/Makefile b/Makefile
index 7684f9518e04a14956f9975a725a49d25f340594..183eff3e92d3c226481af48f42e1bf217f81ef27 100644 (file)
--- a/Makefile
+++ b/Makefile
VERSION = 3
PATCHLEVEL = 8
-SUBLEVEL = 8
+SUBLEVEL = 13
EXTRAVERSION =
NAME = Displaced Humerus Anterior
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5f23fb1ef9c886845d0a77417e9e2f04baadfc77..1def7c896b50902dc72b60cd61706fef9416bad1 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 355 if ARCH_U8500
default 264 if MACH_H4700
- default 512 if SOC_OMAP5
+ default 512 if SOC_OMAP5 || SOC_DRA7XX
default 288 if ARCH_VT8500
default 0
help
index 5cad8a6dadb021fd2aef0a4ef1a77c40173041e7..dfe56872a7a997e88fff99bab5ce42de077e3614 100644 (file)
endif
ccflags-y := -fpic -fno-builtin -I$(obj)
-asflags-y := -Wa,-march=all -DZIMAGE
+asflags-y := -DZIMAGE
# Supply kernel BSS size to the decompressor via a linker symbol.
KBSS_SZ = $(shell $(CROSS_COMPILE)size $(obj)/../../../../vmlinux | \
index 4324416e26d5aa56664676c69f52209e15e3b567..0ccfd668bd8fd2cde51ad96dc79116e27837142a 100644 (file)
* to cover all 32bit address and cacheable and bufferable.
*/
__armv4_mpu_cache_on:
+ .arch armv4
mov r0, #0x3f @ 4G, the whole
mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
mcr p15, 0, r0, c6, c7, 1
@ Enable unaligned access on v6, to allow better code generation
@ for the decompressor C code:
__armv6_mmu_cache_on:
+ .arch armv6
mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
bic r0, r0, #2 @ A (no unaligned access fault)
orr r0, r0, #1 << 22 @ U (v6 unaligned access model)
__arm926ejs_mmu_cache_on:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+ .arch armv5
mov r0, #4 @ put dcache in WT mode
mcr p15, 7, r0, c15, c0, 0
#endif
__armv4_mmu_cache_on:
+ .arch armv4
mov r12, lr
#ifdef CONFIG_MMU
mov r6, #CB_BITS | 0x12 @ U
mov pc, r12
__armv7_mmu_cache_on:
+ .arch armv7-a
mov r12, lr
#ifdef CONFIG_MMU
mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
mov r3, #16
b call_cache_fn
+ .arch armv4
__armv4_mpu_cache_flush:
mov r2, #1
mov r3, #0
mov pc, lr
__armv6_mmu_cache_flush:
+ .arch armv6
mov r1, #0
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
mcr p15, 0, r1, c7, c10, 4 @ drain WB
mov pc, lr
+ .arch armv7-a
__armv7_mmu_cache_flush:
mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
mcr p15, 0, r10, c7, c5, 4 @ ISB
mov pc, lr
+ .arch armv5
__armv5tej_mmu_cache_flush:
1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
bne 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
+ .arch armv4
__armv4_mmu_cache_flush:
mov r2, #64*1024 @ default: 32K dcache size (*2)
mov r11, #32 @ default: 32 byte line size
mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
mov pc, lr
+ .arch armv4
+
/*
* Various debugging routines for printing hex characters and
* memory, which again must be relocatable.
index 55ce4dff88b46bc91e15713807585724458aeaed..101fed319815346ee54a96bae8f30fd0131a9ffa 100644 (file)
omap5-sevm.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
- am335x-bone.dtb
+ am335x-bone.dtb \
+ am335x-boneblack.dtb \
+ dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
index ecac1e7b0b4913959d05858ccba4a49aba9e0734..725aa632b5bc9f3bea8d058500616e803d92339f 100644 (file)
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <>;
+ pinctrl-0 = <&clkout2_pin>;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN | MODE0 */
>;
};
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ >;
+ };
};
ocp {
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
--- /dev/null
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "am33xx.dtsi"
+
+/ {
+ model = "TI AM335x BeagleBone Black";
+ compatible = "ti,am335x-boneblack", "ti,am335x-bone", "ti,am33xx";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&dcdc2_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ am33xx_pinmux: pinmux@44e10800 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkout2_pin>;
+
+ userled_pins: pinmux_userled_pins {
+ pinctrl-single,pins = <
+ 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
+ 0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
+ 0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
+ 0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
+ >;
+ };
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ 0x188 0x70 /* i2c0_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */
+ 0x18c 0x70 /* i2c0_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE0 */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x170 0x30 /* uart0_rxd.uart0_rxd PULLUP |INPUTENABLE | MODE0 */
+ 0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN | MODE0 */
+ >;
+ };
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ >;
+ };
+ };
+
+ ocp: ocp {
+ uart0: serial@44e09000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+ };
+
+ i2c0: i2c@44e0b000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@24 {
+ reg = <0x24>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "at,24c256";
+ reg = <0x50>;
+ };
+ };
+
+ rtc@44e3e000 {
+ ti,system-power-controller;
+ };
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&userled_pins>;
+
+ compatible = "gpio-leds";
+
+ led0 {
+ label = "beaglebone:green:heartbeat";
+ gpios = <&gpio1 21 0>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led1 {
+ label = "beaglebone:green:mmc0";
+ gpios = <&gpio1 22 0>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led2 {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio1 23 0>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio1 24 0>;
+ linux,default-trigger = "mmc1";
+ default-state = "off";
+ };
+ };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+ ti,pmic-shutdown-controller;
+
+ regulators {
+ dcdc1_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1325000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@3 {
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@6 {
+ regulator-always-on;
+ };
+ };
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+};
index ae4189be800568bd509d564dee82b1f34bbc7a28..b0ca6277212dfa228b5848f7f3b253878dfb588b 100644 (file)
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
+ pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
matrix_keypad_s0: matrix_keypad_s0 {
pinctrl-single,pins = <
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN | MODE0 */
>;
};
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ >;
+ };
};
ocp {
&aes {
status = "okay";
};
+
+&tscadc {
+ tsc {
+ ti,wires = <4>;
+ ti,x-plate-resistance = <200>;
+ ti,steps-to-configure = <5>;
+ ti,wire-config = <0x00 0x11 0x22 0x33>;
+ };
+
+ adc {
+ ti,adc-channels = <4>;
+ };
+};
index b7c9e68c112d462b46a76a4485ac012b922b75e3..caa7f9a75efa9e68358eeac9c68d00b203d17ae8 100644 (file)
am33xx_pinmux: pinmux@44e10800 {
pinctrl-names = "default";
- pinctrl-0 = <&gpio_keys_s0>;
+ pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
0x174 0x00 /* uart0_txd.uart0_txd PULLDOWN | MODE0 */
>;
};
+
+ clkout2_pin: pinumx_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 0x03 /* xdma_event_intr1.clkout2 OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
+ >;
+ };
};
ocp {
index 970c015acb83a318b0564dd4e1fd6816072e7640..8b6ae5765591af656d17f3719e23a1e16796124f 100644 (file)
&edma 5>;
dma-names = "tx", "rx";
};
+
+ tscadc: tscadc@44e0d000 {
+ compatible = "ti,ti-tscadc";
+ reg = <0x44e0d000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <16>;
+ ti,hwmods = "adc_tsc";
+ status = "disabled";
+ };
};
};
index cb7bcc51608d81cd51bba98ec29455973ca9daf0..02b70a404a1fafbd951423a697f28e64cfc6958c 100644 (file)
usart1 {
pinctrl_usart1: usart1-0 {
atmel,pins =
- <2 6 0x1 0x1 /* PB6 periph A with pullup */
- 2 7 0x1 0x0>; /* PB7 periph A */
+ <1 6 0x1 0x1 /* PB6 periph A with pullup */
+ 1 7 0x1 0x0>; /* PB7 periph A */
};
pinctrl_usart1_rts: usart1_rts-0 {
usart3 {
pinctrl_usart3: usart3-0 {
atmel,pins =
- <2 10 0x1 0x1 /* PB10 periph A with pullup */
- 2 11 0x1 0x0>; /* PB11 periph A */
+ <1 10 0x1 0x1 /* PB10 periph A with pullup */
+ 1 11 0x1 0x0>; /* PB11 periph A */
};
pinctrl_usart3_rts: usart3_rts-0 {
atmel,pins =
- <3 8 0x2 0x0>; /* PB8 periph B */
+ <2 8 0x2 0x0>; /* PC8 periph B */
};
pinctrl_usart3_cts: usart3_cts-0 {
atmel,pins =
- <3 10 0x2 0x0>; /* PB10 periph B */
+ <2 10 0x2 0x0>; /* PC10 periph B */
};
};
uart1 {
pinctrl_uart1: uart1-0 {
atmel,pins =
- <2 12 0x1 0x1 /* PB12 periph A with pullup */
- 2 13 0x1 0x0>; /* PB13 periph A */
+ <1 12 0x1 0x1 /* PB12 periph A with pullup */
+ 1 13 0x1 0x0>; /* PB13 periph A */
};
};
index fbe7a7089c2adbc82da7d3ef995b6506c1089d1d..28467fd6bf9689901d6d41e59369bb5278079630 100644 (file)
/ {
model = "Atmel AT91SAM9G15 SoC";
- compatible = "atmel, at91sam9g15, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9g15", "atmel,at91sam9x5";
ahb {
apb {
index 86dd3f6d938ff272334102894fd4e2d9e17c4457..5427b2dba87e34150e1fb2f4dd0e60652fcf5d2d 100644 (file)
/include/ "at91sam9x5ek.dtsi"
/ {
- model = "Atmel AT91SAM9G25-EK";
+ model = "Atmel AT91SAM9G15-EK";
compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
};
index 05a718fb83c49b4cfa1fcb35be13b4e9ff2d2ec6..5fd32df03f25d9551494fd40b5793882b6a966c3 100644 (file)
/ {
model = "Atmel AT91SAM9G25 SoC";
- compatible = "atmel, at91sam9g25, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9g25", "atmel,at91sam9x5";
ahb {
apb {
index f9d14a722794eb0f927ecb03eeac0d790f0efff7..d6fa8af50724ab6bb37b96426950bf7aa86fccca 100644 (file)
/ {
model = "Atmel AT91SAM9G35 SoC";
- compatible = "atmel, at91sam9g35, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9g35", "atmel,at91sam9x5";
ahb {
apb {
index 54eb33ba6d22ba6e308d756518e8481056a19890..9ac2bc2b4f07cd36eca29c2172607d4e84c631bb 100644 (file)
/ {
model = "Atmel AT91SAM9X25 SoC";
- compatible = "atmel, at91sam9x25, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9x25", "atmel,at91sam9x5";
ahb {
apb {
index fb102d6126ce696234133a2869c7f84a5db888ee..ba67d83d17ac5d3821f5018773a54a0342f98081 100644 (file)
/ {
model = "Atmel AT91SAM9X35 SoC";
- compatible = "atmel, at91sam9x35, atmel,at91sam9x5";
+ compatible = "atmel,at91sam9x35", "atmel,at91sam9x5";
ahb {
apb {
index 8a7cf1d9cf5db6f71ee002725151a6d968da40fa..ccab2568b0d7921ecb972db631b20d8f785d9299 100644 (file)
compatible = "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
chosen {
- bootargs = "128M console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
+ bootargs = "console=ttyS0,115200 root=/dev/mtdblock1 rw rootfstype=ubifs ubi.mtd=1 root=ubi0:rootfs";
};
ahb {
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
--- /dev/null
@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "dra7.dtsi"
+
+/ {
+ model = "TI DRA7";
+ compatible = "ti,dra7-evm", "ti,dra7";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&avs_mpu>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+
+ vmmc2_fixed: fixedregulator-mmc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmc2_fixed";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+};
+
+&dra7_pmx_core {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &vout1_pins
+ >;
+
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ 0x408 0x60000 /* i2c2_sda INPUT | MODE0 */
+ 0x40C 0x60000 /* i2c2_scl INPUT | MODE0 */
+ >;
+ };
+
+ vout1_pins: pinmux_vout1_pins {
+ pinctrl-single,pins = <
+ 0x1C8 0x0 /* vout1_clk OUTPUT | MODE0 */
+ 0x1CC 0x0 /* vout1_de OUTPUT | MODE0 */
+ 0x1D0 0x0 /* vout1_fld OUTPUT | MODE0 */
+ 0x1D4 0x0 /* vout1_hsync OUTPUT | MODE0 */
+ 0x1D8 0x0 /* vout1_vsync OUTPUT | MODE0 */
+ 0x1DC 0x0 /* vout1_d0 OUTPUT | MODE0 */
+ 0x1E0 0x0 /* vout1_d1 OUTPUT | MODE0 */
+ 0x1E4 0x0 /* vout1_d2 OUTPUT | MODE0 */
+ 0x1E8 0x0 /* vout1_d3 OUTPUT | MODE0 */
+ 0x1EC 0x0 /* vout1_d4 OUTPUT | MODE0 */
+ 0x1F0 0x0 /* vout1_d5 OUTPUT | MODE0 */
+ 0x1F4 0x0 /* vout1_d6 OUTPUT | MODE0 */
+ 0x1F8 0x0 /* vout1_d7 OUTPUT | MODE0 */
+ 0x1FC 0x0 /* vout1_d8 OUTPUT | MODE0 */
+ 0x200 0x0 /* vout1_d9 OUTPUT | MODE0 */
+ 0x204 0x0 /* vout1_d10 OUTPUT | MODE0 */
+ 0x208 0x0 /* vout1_d11 OUTPUT | MODE0 */
+ 0x20C 0x0 /* vout1_d12 OUTPUT | MODE0 */
+ 0x210 0x0 /* vout1_d13 OUTPUT | MODE0 */
+ 0x214 0x0 /* vout1_d14 OUTPUT | MODE0 */
+ 0x218 0x0 /* vout1_d15 OUTPUT | MODE0 */
+ 0x21C 0x0 /* vout1_d16 OUTPUT | MODE0 */
+ 0x220 0x0 /* vout1_d17 OUTPUT | MODE0 */
+ 0x224 0x0 /* vout1_d18 OUTPUT | MODE0 */
+ 0x228 0x0 /* vout1_d19 OUTPUT | MODE0 */
+ 0x22C 0x0 /* vout1_d20 OUTPUT | MODE0 */
+ 0x230 0x0 /* vout1_d21 OUTPUT | MODE0 */
+ 0x234 0x0 /* vout1_d22 OUTPUT | MODE0 */
+ 0x238 0x0 /* vout1_d23 OUTPUT | MODE0 */
+ >;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+
+ tps659038: tps659038@58 {
+ reg = <0x58>;
+ };
+
+ pcf_lcd: pcf8575@20 {
+ compatible = "ti,pcf8575";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ /* TLC chip for LCD panel power and backlight */
+ tlc59108: tlc59108@40 {
+ compatible = "ti,tlc59108";
+ reg = <0x40>;
+ gpios = <&pcf_lcd 15 0>; /* P15, CON_LCD_PWR_DN */
+ };
+};
+
+/include/ "tps659038.dtsi"
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ clock-frequency = <400000>;
+
+ pcf_hdmi: pcf8575@26 {
+ compatible = "ti,pcf8575";
+ reg = <0x26>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+};
+
+&mmc1 {
+ vmmc-supply = <&ldo1_reg>;
+ bus-width = <4>;
+};
+
+&mmc2 {
+ vmmc-supply = <&vmmc2_fixed>;
+ bus-width = <8>;
+ ti,non-removable;
+};
+
+&mmc3 {
+ bus-width = <8>;
+ ti,non-removable;
+ status = "disabled";
+};
+
+&mmc4 {
+ bus-width = <4>;
+ status = "disabled";
+};
+
+&avs_mpu {
+ avs-supply = <&smps123_reg>;
+};
+
+&avs_core {
+ avs-supply = <&smps7_reg>;
+};
+
+&avs_gpu {
+ avs-supply = <&smps6_reg>;
+};
+
+&avs_dspeve {
+ avs-supply = <&smps45_reg>;
+};
+
+&avs_iva {
+ avs-supply = <&smps8_reg>;
+};
+
+&dpi1 {
+ lcd {
+ compatible = "ti,tfc_s9700";
+ tlc = <&tlc59108>;
+ data-lines = <24>;
+ };
+};
+
+&hdmi {
+ tpd12s015: tpd12s015 {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&pcf_hdmi 4 0>, /* pcf8575@22 P4, CT_CP_HDP */
+ <&pcf_hdmi 5 0>, /* pcf8575@22 P5, LS_OE */
+ <&gpio7 12 0>; /* gpio7_12/sp1_cs2, HPD */
+
+ hdmi_ddc = <&i2c2>;
+
+ hdmi-monitor {
+ compatible = "ti,hdmi_panel";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
--- /dev/null
@@ -0,0 +1,536 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "ti,dra7xx";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ operating-points = <
+ /* kHz uV */
+ /* The OPP_HIGH Only for DVFS enabled Samples Hence commenting*/
+ 1000000 1090000
+ /* 1176000 1210000 */
+ >;
+ clocks = <&dpll_mpu>;
+ clock-names = "cpu";
+ timer {
+ compatible = "arm,armv7-timer";
+ /*
+ * PPI secure/nonsecure IRQ,
+ * active low level-sensitive
+ */
+ interrupts = <1 13 0x308>,
+ <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /*
+ * PPI secure/nonsecure IRQ,
+ * active low level-sensitive
+ */
+ interrupts = <1 13 0x308>,
+ <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
+ };
+ };
+
+ gic: interrupt-controller@48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48211000 0x1000>,
+ <0x48212000 0x1000>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is uses for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap5-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the SOC interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since that will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap4-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2";
+
+ counter32k: counter@4ae04000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4ae04000 0x40>;
+ ti,hwmods = "counter_32k";
+ };
+
+ dra7_pmx_core: pinmux@4a003400 {
+ compatible = "pinctrl-single";
+ reg = <0x4a003400 0x0464>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x3fffffff>;
+ };
+
+ dpll_mpu: dpll_mpu {
+ #clock-cells = <0>;
+ compatible = "ti,omap-clock";
+ };
+
+ sdma: dma-controller@4a056000 {
+ compatible = "ti,omap4430-sdma";
+ reg = <0x4a056000 0x1000>;
+ interrupts = <0 12 0x4>,
+ <0 13 0x4>,
+ <0 14 0x4>,
+ <0 15 0x4>;
+ #dma-cells = <1>;
+ #dma-channels = <32>;
+ #dma-requests = <127>;
+ };
+
+ gpio1: gpio@4ae10000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4ae10000 0x200>;
+ interrupts = <0 29 0x4>;
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio2: gpio@48055000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48055000 0x200>;
+ interrupts = <0 30 0x4>;
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio3: gpio@48057000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48057000 0x200>;
+ interrupts = <0 31 0x4>;
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio4: gpio@48059000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48059000 0x200>;
+ interrupts = <0 32 0x4>;
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio5: gpio@4805b000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805b000 0x200>;
+ interrupts = <0 33 0x4>;
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio6: gpio@4805d000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805d000 0x200>;
+ interrupts = <0 34 0x4>;
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio7: gpio@48051000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48051000 0x200>;
+ interrupts = <0 35 0x4>;
+ ti,hwmods = "gpio7";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio8: gpio@48053000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48053000 0x200>;
+ interrupts = <0 121 0x4>;
+ ti,hwmods = "gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806a000 0x100>;
+ interrupts = <0 72 0x4>;
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806c000 0x100>;
+ interrupts = <0 73 0x4>;
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@48020000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48020000 0x100>;
+ interrupts = <0 74 0x4>;
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ uart4: serial@4806e000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806e000 0x100>;
+ interrupts = <0 70 0x4>;
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
+
+ uart5: serial@48066000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48066000 0x100>;
+ interrupts = <0 105 0x4>;
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ };
+
+ uart6: serial@48068000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48068000 0x100>;
+ interrupts = <0 106 0x4>;
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ };
+
+ timer1: timer@4ae18000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4ae18000 0x80>;
+ interrupts = <0 37 0x4>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer@48032000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48032000 0x80>;
+ interrupts = <0 38 0x4>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@48034000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48034000 0x80>;
+ interrupts = <0 39 0x4>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer@48036000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48036000 0x80>;
+ interrupts = <0 40 0x4>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer@48820000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48820000 0x80>;
+ interrupts = <0 41 0x4>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer@48822000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48822000 0x80>;
+ interrupts = <0 42 0x4>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer7: timer@48824000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48824000 0x80>;
+ interrupts = <0 43 0x4>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer@48826000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48826000 0x80>;
+ interrupts = <0 44 0x4>;
+ ti,hwmods = "timer8";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer9: timer@4803e000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4803e000 0x80>;
+ interrupts = <0 45 0x4>;
+ ti,hwmods = "timer9";
+ };
+
+ timer10: timer@48086000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48086000 0x80>;
+ interrupts = <0 46 0x4>;
+ ti,hwmods = "timer10";
+ };
+
+ timer11: timer@48088000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48088000 0x80>;
+ interrupts = <0 47 0x4>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
+
+ wdt2: wdt@4ae14000 {
+ compatible = "ti,omap4-wdt";
+ reg = <0x4ae14000 0x80>;
+ interrupts = <0 80 0x4>;
+ ti,hwmods = "wd_timer2";
+ };
+
+ dmm: dmm@4e000000 {
+ compatible = "ti,omap5-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
+ bandgap {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50>;
+ compatible = "ti,dra752-bandgap";
+ interrupts = <0 126 4>; /* talert */
+ };
+
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48070000 0x100>;
+ interrupts = <0 56 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48072000 0x100>;
+ interrupts = <0 57 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48060000 0x100>;
+ interrupts = <0 61 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ };
+
+ i2c4: i2c@4807a000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807a000 0x100>;
+ interrupts = <0 62 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c4";
+ };
+
+ i2c5: i2c@4807c000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807c000 0x100>;
+ interrupts = <0 60 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c5";
+ };
+
+ mmc1: mmc@4809c000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x4809c000 0x400>;
+ interrupts = <0 83 0x4>;
+ ti,hwmods = "mmc1";
+ ti,dual-volt;
+ ti,needs-special-reset;
+ dmas = <&sdma 61>, <&sdma 62>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc2: mmc@480b4000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480b4000 0x400>;
+ interrupts = <0 86 0x4>;
+ ti,hwmods = "mmc2";
+ ti,needs-special-reset;
+ dmas = <&sdma 47>, <&sdma 48>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc3: mmc@480ad000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480ad000 0x400>;
+ interrupts = <0 94 0x4>;
+ ti,hwmods = "mmc3";
+ ti,needs-special-reset;
+ dmas = <&sdma 77>, <&sdma 78>;
+ dma-names = "tx", "rx";
+ };
+
+ mmc4: mmc@480d1000 {
+ compatible = "ti,omap4-hsmmc";
+ reg = <0x480d1000 0x400>;
+ interrupts = <0 96 0x4>;
+ ti,hwmods = "mmc4";
+ ti,needs-special-reset;
+ dmas = <&sdma 57>, <&sdma 58>;
+ dma-names = "tx", "rx";
+ };
+
+ avs_mpu: regulator-avs@0x4A003B18 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A003B18 0x20>;
+ efuse-settings = <1090000 8
+ 1210000 12
+ 1280000 16>;
+ };
+
+ avs_core: regulator-avs@0x4A0025EC {
+ compatible = "ti,avsclass0";
+ reg = <0x4A0025EC 0x20>;
+ efuse-settings = <1030000 8>;
+ };
+
+ avs_gpu: regulator-avs@0x4A003B00 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A003B00 0x20>;
+ efuse-settings = <1090000 8
+ 1210000 12
+ 1280000 16>;
+ };
+
+ avs_dspeve: regulator-avs@0x4A0025D8 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A0025D8 0x20>;
+ efuse-settings = <1055000 8
+ 1150000 12
+ 1250000 16>;
+ };
+
+ avs_iva: regulator-avs@0x4A0025C4 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A0025C4 0x20>;
+ efuse-settings = <1055000 8
+ 1150000 12
+ 1250000 16>;
+ };
+
+ dss {
+ compatible = "ti,omap4-dss";
+ ti,hwmods = "dss_core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ vdda_video-supply = <&ldoln_reg>;
+
+ dispc {
+ compatible = "ti,omap4-dispc";
+ ti,hwmods = "dss_dispc";
+ };
+
+ dpi1: dpi@1 {
+ compatible = "ti,dra7xx-dpi";
+ reg = <0>;
+ video-source = <0>;
+ };
+
+ dpi2: dpi@2 {
+ compatible = "ti,dra7xx-dpi";
+ reg = <1>;
+ video-source = <2>;
+ };
+
+ dpi3: dpi@3 {
+ compatible = "ti,dra7xx-dpi";
+ reg = <2>;
+ video-source = <3>;
+ };
+
+ hdmi: hdmi {
+ compatible = "ti,omap4-hdmi", "simple-bus";
+ ti,hwmods = "dss_hdmi";
+ vdda_hdmi_dac-supply = <&ldo3_reg>;
+ video-source = <1>;
+ };
+ };
+ };
+};
index 122fd99f7bf82d021403882561ef21e20f892e71..1676973af1c0b63e118971beddff9dde6a62b213 100644 (file)
reg = <0x80000000 0x40000000>; /* 1 GB */
};
- leds {
+ leds: leds {
compatible = "gpio-leds";
heartbeat {
label = "pandaboard::status1";
ti,mclk-freq = <38400000>;
ti,mcpdm = <&mcpdm>;
+ ti,mcbsp1 = <&mcbsp1>;
+ ti,mcbsp2 = <&mcbsp2>;
+ ti,aess = <&aess>;
ti,twl6040 = <&twl6040>;
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"AFML", "Line In",
- "AFMR", "Line In";
+ "AFMR", "Line In",
+ "Headset Playback", "PDM_DL1",
+ "Handsfree Playback", "PDM_DL2",
+ "PDM_UL1", "Capture",
+ "40122000.mcbsp Playback", "BT_VX_DL",
+ "BT_VX_UL", "40122000.mcbsp Capture",
+ "40124000.mcbsp Playback", "MM_EXT_DL",
+ "MM_EXT_UL", "40124000.mcbsp Capture";
+ };
+
+ sound_hdmi {
+ compatible = "ti,omap-hdmi-tpd12s015-audio";
+ ti,model = "OMAP4HDMI";
+
+ ti,hdmi_audio = <&hdmi>;
+ ti,level_shifter = <&tpd12s015>;
+ };
+
+ /* HS USB Port 1 RESET */
+ hsusb1_reset: hsusb1_reset_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb1_reset";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 30 0>; /* gpio_62 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ /* HS USB Port 1 Power */
+ hsusb1_power: hsusb1_power_reg {
+ compatible = "regulator-fixed";
+ regulator-name = "hsusb1_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 1 0>; /* gpio_1 */
+ startup-delay-us = <70000>;
+ enable-active-high;
+ };
+
+ /* HS USB Host PHY on PORT 1 */
+ hsusb1_phy: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ reset-supply = <&hsusb1_reset>;
+ vcc-supply = <&hsusb1_power>;
+ };
+
+ /* hsusb1_phy is clocked by FREF_CLK3 i.e. auxclk3 */
+ clock_alias {
+ clock-name = "auxclk3_ck";
+ clock-alias = "main_clk";
+ device = <&hsusb1_phy>;
};
};
&mcbsp1_pins
&dss_hdmi_pins
&tpd12s015_pins
+ &hsusbb1_pins
+ &led_gpio_pins
>;
twl6040_pins: pinmux_twl6040_pins {
>;
};
+ hsusbb1_pins: pinmux_hsusbb1_pins {
+ pinctrl-single,pins = <
+ 0x82 0x10C /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk INPUT | PULLDOWN */
+ 0x84 0x4 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
+ 0x86 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
+ 0x88 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
+ 0x8a 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
+ 0x8c 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
+ 0x8e 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
+ 0x90 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
+ 0x92 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
+ 0x94 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
+ 0x96 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
+ 0x98 0x104 /* USBB1_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
+ >;
+ };
+
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0xe2 0x118 /* i2c1_scl PULLUP | INPUTENABLE | MODE0 */
0xf0 0x118 /* i2c4_sda PULLUP | INPUTENABLE | MODE0 */
>;
};
+
+ led_gpio_pins: pinmux_leds_pins {
+ pinctrl-single,pins = <
+ >;
+ };
+};
+
+&omap4_pmx_wkup {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &led_wkgpio_pins
+ >;
+
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins = <
+ 0x1a 0x3 /* gpio_wk7 OUTPUT | MODE 3 */
+ 0x1c 0x3 /* gpio_wk8 OUTPUT | MODE 3 */
+ >;
+ };
};
&i2c1 {
twl6040: twl@4b {
compatible = "ti,twl6040";
- reg = <0x4b>;
/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
interrupt-parent = <&gic>;
};
/include/ "twl6030.dtsi"
+/include/ "twl6040.dtsi"
&i2c2 {
pinctrl-names = "default";
device-handle = <&elpida_ECB240ABACN>;
};
-&mcbsp2 {
- status = "disabled";
-};
-
&mcbsp3 {
status = "disabled";
};
status = "disabled";
};
+&dpi {
+ dvi {
+ compatible = "ti,tfp410";
+ data-lines = <24>;
+ gpios = <&gpio1 0 0>; /* 0, power-down */
+ i2c-bus = <&i2c3>;
+ };
+};
+
+&hdmi {
+ tpd12s015: tpd12s015 {
+ compatible = "ti,tpd12s015";
+
+ gpios = <&gpio2 28 0>, /* 60, CT CP HPD */
+ <&gpio2 9 0>, /* 41, LS OE */
+ <&gpio2 31 0>; /* 63, HPD */
+
+ hdmi {
+ compatible = "ti,hdmi_panel";
+ };
+
+ };
+};
+
&twl_usb_comparator {
usb-supply = <&vusb>;
};
+
+&usbhshost {
+ port1-mode = "ehci-phy";
+};
+
+&usbhsehci {
+ phys = <&hsusb1_phy>;
+};
+
+&usb_otg_hs {
+ interface-type = <1>;
+ mode = <3>;
+ power = <50>;
+};
index b1195f70225f88ae4224ba18e28898de55697f01..c9ba4372a7ed9d434c4346e6424ce4edd776edaf 100644 (file)
/include/ "omap4460.dtsi"
/include/ "omap4-panda-common.dtsi"
+&leds {
+ compatible = "gpio-leds";
+ heartbeat {
+ label = "pandaboard::status1";
+ gpios = <&gpio4 14 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ mmc {
+ label = "pandaboard::status2";
+ gpios = <&gpio1 8 0>;
+ linux,default-trigger = "gpio";
+ };
+};
+
+&led_gpio_pins {
+ pinctrl-single,pins = <
+ 0xb6 0x3 /* gpio_110 OUTPUT | MODE 3 */
+ >;
+};
+
+&omap4_pmx_wkup {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &led_wkgpio_pins
+ >;
+
+ led_wkgpio_pins: pinmux_leds_wkpins {
+ pinctrl-single,pins = <
+ 0x1c 0x3 /* gpio_wk8 OUTPUT | MODE 3 */
+ >;
+ };
+};
+
/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
&sound {
ti,model = "PandaBoardES";
index f8b221f0168ee05920c8f4e2d91a905f3362ab62..1a23f5a7b362c0ee5bb240c97f35b0d077d51571 100644 (file)
*/
/dts-v1/;
-/include/ "omap443x.dtsi"
+/include/ "omap4.dtsi"
/include/ "omap4-panda-common.dtsi"
index 587b6651dfb334f44f7f1fc25582c7419e004aaa..403b879c6d87f4eecc84da59db971cf644190c1b 100644 (file)
pinctrl-single,function-mask = <0x7fff>;
};
+ sdma: dma-controller@4a056000 {
+ compatible = "ti,omap4430-sdma";
+ reg = <0x4a056000 0x1000>;
+ interrupts = <0 12 0x4>,
+ <0 13 0x4>,
+ <0 14 0x4>,
+ <0 15 0x4>;
+ #dma-cells = <1>;
+ #dma-channels = <32>;
+ #dma-requests = <127>;
+ };
+
+ dmm: dmm@4e000000 {
+ compatible = "ti,omap4-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
dss {
compatible = "ti,omap4-dss";
ti,hwmods = "dss_core";
vdda_hdmi_dac-supply = <&vdac>;
video-source = <1>;
};
- };
-
- sdma: dma-controller@4a056000 {
- compatible = "ti,omap4430-sdma";
- reg = <0x4a056000 0x1000>;
- interrupts = <0 12 0x4>,
- <0 13 0x4>,
- <0 14 0x4>,
- <0 15 0x4>;
- #dma-cells = <1>;
- #dma-channels = <32>;
- #dma-requests = <127>;
};
gpio1: gpio@4a310000 {
index b7a80eae30d39772876c3a8c335b8cf13d73319b..7b7b5347ef15df576b93d0c27864171bd8ca1a81 100644 (file)
ti,hdmi_audio = <&hdmi>;
ti,level_shifter = <&tpd12s015>;
};
+
+ leds {
+ compatible = "gpio-leds";
+ led@1 {
+ label = "omap5:blue:usr1";
+ gpios = <&gpio5 25 0>; /* gpio5_153 D1 LED */
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+ };
};
&omap5_pmx_core {
&tpd12s015_pins
&tca6424a_pins
&palmas_pins
+ &led_gpio_pins
>;
twl6040_pins: pinmux_twl6040_pins {
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
0x0fc 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
- 0x100 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
- 0x102 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
+ 0x100 0x106 /* GPIO7_194, DDC-SCL */
+ 0x102 0x106 /* GPIO7_195, DDC-SDA */
>;
};
0x140 0x11f /* MSLEEP INPUT | PULLUP | MODE7 */
>;
};
+
+ led_gpio_pins: pinmux_led_gpio_pins {
+ pinctrl-single,pins = <
+ 0x196 0x6 /* uart3_cts_rctx.gpio5_153 OUTPUT | MODE6 */
+ >;
+ };
};
&omap5_pmx_wkup {
gpios = <&tca6424a 0 0>, /* TCA6424A P01, CT_CP_HDP */
<&tca6424a 1 0>, /* TCA6424A P00, LS_OE*/
- <&gpio7 1 0>; /* 193, HPD */
+ <&gpio7 1 0>, /* 193, HPD */
+ <&gpio7 2 0>, /* 194, SCL */
+ <&gpio7 3 0>; /* 195, SDA */
+
hdmi-monitor {
compatible = "ti,hdmi_panel";
index f20e10ebfdc03d64e930d16592ec62469088b85e..3f1846ae98a6827208e9bf7b60db6f0dff05187f 100644 (file)
<0x401a0000 0x1fff>, /* CMEM - MPU */
<0x401c0000 0x5fff>, /* SMEM - MPU */
<0x401e0000 0x1fff>, /* PMEM - MPU */
- <0x4901f000 0x3ff>, /* L3 Interconnect */
+ <0x490f1000 0x3ff>, /* L3 Interconnect */
<0x49080000 0xffff>, /* DMEM - MPU */
<0x490a0000 0x1fff>, /* CMEM - MPU */
<0x490ce000 0x5fff>, /* SMEM - MPU */
ti,timer-pwm;
};
+ dmm: dmm@4e000000 {
+ compatible = "ti,omap5-dmm";
+ reg = <0x4e000000 0x800>;
+ interrupts = <0 113 0x4>;
+ ti,hwmods = "dmm";
+ };
+
emif1: emif@0x4c000000 {
compatible = "ti,emif-4d5";
ti,hwmods = "emif1";
diff --git a/arch/arm/boot/dts/tps659038.dtsi b/arch/arm/boot/dts/tps659038.dtsi
--- /dev/null
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/*
+ * TPS659038 is an Integrated Power Management Chip from Texas Instruments
+ * Data Manual - TPS659039-Q1 POWER MANAGEMENT UNIT (PMU) FOR PROCESSOR Data Manual
+ * Register Manual - TPS659038/39-Q1 Functional Register Descriptions.
+ */
+
+&tps659038 {
+ compatible = "ti,tps659038";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+ ti,ldo6_vibrator = <0>;
+ ti,smps10 = <0>;
+
+ regulators {
+ smps123_reg: smps123 {
+ regulator-name = "smps123";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps45_reg: smps45 {
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps6_reg: smps6 {
+ regulator-name = "smps6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps7_reg: smps7 {
+ regulator-name = "smps7";
+ regulator-min-microvolt = <1030000>;
+ regulator-max-microvolt = <1030000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps8_reg: smps8 {
+ regulator-name = "smps8";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps9_reg: smps9 {
+ regulator-name = "smps9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldoln_reg: ldoln {
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3250000>;
+ regulator-max-microvolt = <3250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
index 606d48f3b8f81c10370b718d7b2b3475818b9a03..8aab786863dfabac6854bf6ce1c6054074f61a28 100644 (file)
# CONFIG_MMC_BLOCK_BOUNCE is not set
CONFIG_SDIO_UART=m
CONFIG_MMC_ATMELMCI=y
-CONFIG_MMC_ATMELMCI_DMA=y
CONFIG_LEDS_ATMEL_PWM=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGER_TIMER=y
index 15cd735d9259635b4fbb4e9e4109d0706c0bc324..8edf3b640a9df3e8ffe3020744b3821edecbceb6 100644 (file)
CONFIG_OMAP_RESET_CLOCKS=y
CONFIG_OMAP_MUX_DEBUG=y
CONFIG_SOC_OMAP5=y
+CONFIG_SOC_DRA7XX=y
CONFIG_ARM_THUMBEE=y
CONFIG_ARM_ERRATA_411920=y
CONFIG_SMP=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_GENERIC_CPUFREQ_CPU0=y
# CONFIG_ARM_OMAP2PLUS_CPUFREQ is not set
CONFIG_FPE_NWFPE=y
# CONFIG_INET_LRO is not set
# CONFIG_IPV6 is not set
CONFIG_NETFILTER=y
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_C_CAN=m
+CONFIG_CAN_C_CAN_PLATFORM=m
CONFIG_BT=m
CONFIG_BT_HCIUART=m
CONFIG_BT_HCIUART_H4=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_SENSORS_TSL2550=m
+CONFIG_SENSORS_LIS3_I2C=m
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_INPUT_JOYDEV=y
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_MATRIX=m
CONFIG_KEYBOARD_TWL4030=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=y
CONFIG_PINCTRL_SINGLE=y
CONFIG_DEBUG_GPIO=y
CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCF857X=y
CONFIG_GPIO_TWL4030=y
CONFIG_W1=y
CONFIG_POWER_SUPPLY=y
-CONFIG_WATCHDOG=y
+CONFIG_SENSORS_LM75=m
CONFIG_THERMAL=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_FAIR_SHARE=y
-CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_GOV_USER_SPACE=y
CONFIG_CPU_THERMAL=y
+CONFIG_WATCHDOG=y
CONFIG_OMAP_WATCHDOG=y
CONFIG_TWL4030_WATCHDOG=y
CONFIG_PALMAS_WATCHDOG=y
CONFIG_MFD_TPS65217=y
+CONFIG_TWL6040_CORE=y
CONFIG_REGULATOR_TWL4030=y
CONFIG_MFD_PALMAS=y
CONFIG_MFD_PALMAS_GPADC=y
CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
CONFIG_USB_GSPCA=m
CONFIG_DRM=y
+CONFIG_DRM_OMAP=y
+CONFIG_DRM_OMAP_NUM_CRTCS=3
CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
CONFIG_OMAP2_DSS=y
+CONFIG_OMAP2_DSS_DRA7XX_DPI=y
CONFIG_OMAP2_DSS_RFBI=y
CONFIG_OMAP2_DSS_SDI=y
CONFIG_OMAP2_DSS_DSI=y
-CONFIG_FB_OMAP_LCD_VGA=y
-CONFIG_FB_OMAP2=m
-CONFIG_PANEL_GENERIC_DPI=m
-CONFIG_PANEL_SHARP_LS037V7DW01=m
-CONFIG_PANEL_NEC_NL8048HL11_01B=m
-CONFIG_PANEL_TAAL=m
-CONFIG_PANEL_TPO_TD043MTEA1=m
-CONFIG_PANEL_ACX565AKM=m
+CONFIG_PANEL_GENERIC_DPI=y
+CONFIG_PANEL_TFP410=y
+CONFIG_PANEL_LGPHILIPS_LB035Q02=y
+CONFIG_PANEL_SHARP_LS037V7DW01=y
+CONFIG_PANEL_NEC_NL8048HL11_01B=y
+CONFIG_PANEL_PICODLP=y
+CONFIG_PANEL_TFCS9700=y
+CONFIG_PANEL_TAAL=y
+CONFIG_PANEL_LG4591=y
+CONFIG_PANEL_TPO_TD043MTEA1=y
+CONFIG_PANEL_ACX565AKM=y
+CONFIG_PANEL_N8X0=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FONTS=y
CONFIG_SND_SOC=m
CONFIG_SND_OMAP_SOC=m
CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
+CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
CONFIG_USB=y
CONFIG_USB_DEBUG=y
CONFIG_SDIO_UART=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_OMAP=y
+CONFIG_RTC_DRV_PALMAS=y
CONFIG_RTC_DRV_TWL92330=y
CONFIG_RTC_DRV_TWL4030=y
-CONFIG_RTC_DRV_PALMAS=y
+CONFIG_RTC_DRV_OMAP=y
CONFIG_DMADEVICES=y
CONFIG_TI_EDMA=y
CONFIG_DMA_OMAP=y
CONFIG_STAGING=y
-CONFIG_DRM_OMAP=y
-CONFIG_DRM_OMAP_NUM_CRTCS=3
CONFIG_TI_SOC_THERMAL=y
CONFIG_TI_THERMAL=y
CONFIG_OMAP4_THERMAL=y
CONFIG_OMAP5_THERMAL=y
+CONFIG_DRA752_THERMAL=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DAVINCI_CPDMA=y
index 02fe2fbe2477078b4fa8da59c6f2a416fdb71913..ed94b1a366ae62d9535c66847ebe85abf4f4f0c0 100644 (file)
* IOP3XX processor registers
*/
#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
-#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
+#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfedfe000
#define IOP3XX_PERIPHERAL_SIZE 0x00002000
#define IOP3XX_PERIPHERAL_UPPER_PA (IOP3XX_PERIPHERAL_PHYS_BASE +\
IOP3XX_PERIPHERAL_SIZE - 1)
index f9e8657dd24122cf67362e4def103d41cfd25329..23fa6a21e228d15da6698d41a3bff2aae63ff5b9 100644 (file)
struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
struct pmu *leader_pmu = event->group_leader->pmu;
- if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
+ if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
+ return 1;
+
+ if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
return 1;
return armpmu->get_event_idx(hw_events, event) >= 0;
index bd6f56b9ec2101534b7477c11c9f6ef0a3a6e68b..59d2adb764a995f9174a6494bd2bcc1974c10e73 100644 (file)
static u32 __read_mostly (*read_sched_clock)(void) = jiffy_sched_clock_read;
-static inline u64 cyc_to_ns(u64 cyc, u32 mult, u32 shift)
+static inline u64 notrace cyc_to_ns(u64 cyc, u32 mult, u32 shift)
{
return (cyc * mult) >> shift;
}
-static unsigned long long cyc_to_sched_clock(u32 cyc, u32 mask)
+static unsigned long long notrace cyc_to_sched_clock(u32 cyc, u32 mask)
{
u64 epoch_ns;
u32 epoch_cyc;
index 4b678478cf95d9f60d6a4484b4a490ee46228d45..6b4608d58da284bba765701ddc06a0ddbd57b443 100644 (file)
of_id = of_match_node(rstc_ids, np);
if (!of_id)
- panic("AT91: rtsc no restart function availlable\n");
+ panic("AT91: rtsc no restart function available\n");
arm_pm_restart = of_id->data;
index 0edce4bf3ae7a8328445783f8d35dd0176867325..5e3ca7a10438d3cae3c25db73acfb2be61a3efee 100644 (file)
clk_prepare_enable(clk[gpio3_gate]);
clk_prepare_enable(clk[iim_gate]);
clk_prepare_enable(clk[emi_gate]);
+ clk_prepare_enable(clk[max_gate]);
+ clk_prepare_enable(clk[iomuxc_gate]);
/*
* SCC is needed to boot via mmc after a watchdog reset. The clock code
index 6cf9c1cc2bef3cf3fa7749d134a0edb64bdf8644..612bd1cc257c147255eb9baefb86ff6d0a6a2497 100644 (file)
#define cpu_is_omap34xx() 0
#define cpu_is_omap44xx() 0
#define soc_is_omap54xx() 0
+#define soc_is_dra7xx() 0
#define soc_is_am33xx() 0
#define cpu_class_is_omap1() 1
#define cpu_class_is_omap2() 0
index 3ceda910e4b98ac1c369fed8c79c4e0d043b428f..ed1b71e10663cf37731410e6e89562e20eac8326 100644 (file)
select I2C
select I2C_OMAP
select MENELAUS if ARCH_OMAP2
- select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
+ select NEON if CPU_V7
select PM_RUNTIME
select REGULATOR
select SERIAL_OMAP
config SOC_HAS_REALTIME_COUNTER
bool "Real time free running counter"
- depends on SOC_OMAP5
+ depends on SOC_OMAP5 || SOC_DRA7XX
default y
config ARCH_OMAP2
config SOC_OMAP5
bool "TI OMAP5"
select ARCH_HAS_BANDGAP
+ select ARCH_HAS_OPP
select ARM_ARCH_TIMER
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ARCH_HAS_XHCI if USB_SUPPORT
select ARCH_NEEDS_CPU_IDLE_COUPLED
+ select PM_OPP if PM
+
+config SOC_DRA7XX
+ bool "TI DRA7XX"
+ select ARCH_HAS_BANDGAP
+ select ARM_ARCH_TIMER
+ select CPU_V7
+ select ARM_GIC
+ select HAVE_SMP
+ select COMMON_CLK
comment "OMAP Core Type"
depends on ARCH_OMAP2
index b123e80ad730b9fd7f4abd8f3a0d7740ac42668b..af35320f7bfe332be5e13cd7fa696378a896c28a 100644 (file)
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common)
ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
obj-y += mcbsp.o
sleep_omap4plus.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common)
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_SOC_OMAP5) += $(omap4plus-common-pm)
obj-$(CONFIG_SOC_AM33XX) += pm33xx.o sleep33xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
+obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
vc44xx_data.o vp44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common)
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
+obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
+obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clock-common) cclock54xx_data.o
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
+obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX) += cclock7xx_data.o
# OMAP2 clock rate set data (old "OPP" data)
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
index 02c55e7b523380e2c3a0a8dbe3346a5ae3df3a6f..d60b2059954e3b56ba772cba5638655e9c6312d9 100644 (file)
.restart = omap44xx_restart,
MACHINE_END
#endif
+
+#ifdef CONFIG_SOC_DRA7XX
+static const char *dra7xx_boards_compat[] __initdata = {
+ "ti,dra7",
+ NULL,
+};
+
+DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
+ .reserve = omap_reserve,
+ .smp = smp_ops(omap4_smp_ops),
+ .map_io = omap5_map_io,
+ .init_early = dra7xx_init_early,
+ .init_irq = omap_gic_of_init,
+ .handle_irq = gic_handle_irq,
+ .init_machine = omap_generic_init,
+ .init_late = dra7xx_init_late,
+ .timer = &omap5_timer,
+ .dt_compat = dra7xx_boards_compat,
+ .restart = omap44xx_restart,
+MACHINE_END
+#endif
index da15beadda41771a5759c14fb1c17c7041dbce6e..30dadcdcd1fd40933c671bfe7a7e5fe63e1a620c 100644 (file)
CLK(NULL, "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck, CK_AM33XX),
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_AM33XX),
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_AM33XX),
+ CLK(NULL, "clkout2_ck", &clkout2_ck, CK_AM33XX),
};
"l4hs_gclk",
"l4fw_gclk",
"l4ls_gclk",
+ "clkout2_ck", /* Required for external peripherals like, Audio codecs */
};
static struct reparent_init_clks reparent_clks[] = {
diff --git a/arch/arm/mach-omap2/cclock7xx_data.c b/arch/arm/mach-omap2/cclock7xx_data.c
--- /dev/null
@@ -0,0 +1,2149 @@
+/*
+ * DRA7xx Clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Mike Turquette (mturquette@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock7xx.h"
+#include "cm1_7xx.h"
+#include "cm2_7xx.h"
+#include "cm-regbits-7xx.h"
+#include "prm7xx.h"
+#include "prm-regbits-7xx.h"
+#include "control.h"
+
+#define DRA7_DPLL_ABE_DEFFREQ 361267200
+#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
+
+/* Root clocks */
+
+DEFINE_CLK_FIXED_RATE(atl_clkin0_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(atl_clkin1_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(atl_clkin2_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(atlclkin3_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(hdmi_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mlb_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mlbp_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(pciesref_acs_clk_ck, CLK_IS_ROOT, 100000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin0_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin1_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin2_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin3_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(rmii_clk_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(sdvenc_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_20000000_ck, CLK_IS_ROOT, 20000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
+
+static const struct clksel_rate div_1_8_rates[] = {
+ { .div = 1, .val = 8, .flags = RATE_IN_7XX },
+ { .div = 0 },
+};
+
+
+static const char *sys_clkin1_parents[] = {
+ "virt_12000000_ck", "virt_20000000_ck",
+ "virt_16800000_ck", "virt_19200000_ck", "virt_26000000_ck",
+ "virt_27000000_ck", "virt_38400000_ck",
+};
+
+DEFINE_CLK_MUX(sys_clkin1, sys_clkin1_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_SYS,
+ DRA7XX_SYS_CLKSEL_SHIFT, DRA7XX_SYS_CLKSEL_WIDTH,
+ CLK_MUX_INDEX_ONE, NULL);
+
+
+DEFINE_CLK_FIXED_RATE(sys_clkin2, CLK_IS_ROOT, 22579200, 0x0);
+
+DEFINE_CLK_FIXED_RATE(usb_otg_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video1_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video1_m2_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video2_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video2_m2_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+/* Module clocks and DPLL outputs */
+
+static const char *abe_dpll_sys_clk_mux_parents[] = {
+ "sys_clkin1", "sys_clkin2",
+};
+
+DEFINE_CLK_MUX(abe_dpll_sys_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_PLL_SYS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *abe_dpll_bypass_clk_mux_parents[] = {
+ "abe_dpll_sys_clk_mux", "sys_32k_ck",
+};
+
+DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL,
+ 0x0, DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(abe_dpll_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_PLL_REF, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+/* DPLL_ABE */
+static struct dpll_data dpll_abe_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_ABE,
+ .clk_bypass = &abe_dpll_bypass_clk_mux,
+ .clk_ref = &abe_dpll_clk_mux,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_ABE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_ABE,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_ABE,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .m4xen_mask = DRA7XX_DPLL_REGM4XEN_MASK,
+ .lpmode_mask = DRA7XX_DPLL_LPMODE_EN_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_abe_ck_parents[] = {
+ "abe_dpll_clk_mux", "abe_dpll_bypass_clk_mux"
+};
+
+static struct clk dpll_abe_ck;
+
+static const struct clk_ops dpll_abe_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap4_dpll_regm4xen_recalc,
+ .round_rate = &omap4_dpll_regm4xen_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_abe_ck_hw = {
+ .hw = {
+ .clk = &dpll_abe_ck,
+ },
+ .dpll_data = &dpll_abe_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
+
+static const char *dpll_abe_x2_ck_parents[] = {
+ "dpll_abe_ck",
+};
+
+static struct clk dpll_abe_x2_ck;
+
+static const struct clk_ops dpll_abe_x2_ck_ops = {
+ .recalc_rate = &omap3_clkoutx2_recalc,
+};
+
+static struct clk_hw_omap dpll_abe_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_abe_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+static const struct clk_ops omap_hsdivider_ops = {
+ .set_rate = &omap2_clksel_set_rate,
+ .recalc_rate = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M2_DPLL_ABE, DRA7XX_DIVHS_MASK);
+
+static const struct clk_div_table abe_24m_fclk_rates[] = {
+ { .div = 8, .val = 0 },
+ { .div = 16, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_ABE_24M, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, abe_24m_fclk_rates,
+ NULL);
+
+DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_ABE, DRA7XX_CLKSEL_OPP_SHIFT,
+ DRA7XX_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
+ DRA7XX_CM_CLKSEL_AESS_FCLK_DIV, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(abe_giclk_div, "aess_fclk", &aess_fclk, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_GICLK_DIV, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const struct clk_div_table abe_lp_clk_div_rates[] = {
+ { .div = 16, .val = 0 },
+ { .div = 32, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(abe_lp_clk_div, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_ABE_LP_CLK,
+ DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0,
+ abe_lp_clk_div_rates, NULL);
+
+DEFINE_CLK_DIVIDER(abe_sys_clk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_SYS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *adc_gfclk_mux_parents[] = {
+ "sys_clkin1", "sys_clkin2", "sys_32k_ck",
+};
+
+DEFINE_CLK_MUX(adc_gfclk_mux, adc_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_ADC_GFCLK, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+/* DPLL_PCIE_REF */
+static struct dpll_data dpll_pcie_ref_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PCIE_REF,
+ .clk_bypass = &sys_clkin1,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_PCIE_REF,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PCIE_REF,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+};
+
+static const char *dpll_pcie_ref_ck_parents[] = {
+ "sys_clkin1",
+};
+
+static struct clk dpll_pcie_ref_ck;
+
+static const struct clk_ops dpll_pcie_ref_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_pcie_ref_ck_hw = {
+ .hw = {
+ .clk = &dpll_pcie_ref_ck,
+ },
+ .dpll_data = &dpll_pcie_ref_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_pcie_ref_ck, dpll_pcie_ref_ck_parents,
+ dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_pcie_ref_m2ldo_ck, "dpll_pcie_ref_ck",
+ &dpll_pcie_ref_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_PCIE_REF,
+ DRA7XX_DIVHS_MASK);
+
+/* APLL_PCIE */
+static struct dpll_data apll_pcie_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PCIE_REF,
+ .clk_bypass = &dpll_pcie_ref_ck,
+ .clk_ref = &dpll_pcie_ref_ck,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_PCIE_REF,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PCIE_REF,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = -1,
+ .max_divider = 0,
+ .min_divider = 1,
+};
+
+static const char *apll_pcie_ck_parents[] = {
+ "BUGGED",
+};
+
+static struct clk apll_pcie_ck;
+
+static struct clk_hw_omap apll_pcie_ck_hw = {
+ .hw = {
+ .clk = &apll_pcie_ck,
+ },
+ .dpll_data = &apll_pcie_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(apll_pcie_ck, apll_pcie_ck_parents, dpll_pcie_ref_ck_ops);
+
+static const char *apll_pcie_clkvcoldo_parents[] = {
+ "apll_pcie_ck",
+};
+
+static struct clk apll_pcie_clkvcoldo;
+
+static const struct clk_ops apll_pcie_clkvcoldo_ops = {
+};
+
+static struct clk_hw_omap apll_pcie_clkvcoldo_hw = {
+ .hw = {
+ .clk = &apll_pcie_clkvcoldo,
+ },
+ .clksel_reg = DRA7XX_CM_CLKVCOLDO_APLL_PCIE,
+};
+
+DEFINE_STRUCT_CLK(apll_pcie_clkvcoldo, apll_pcie_clkvcoldo_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk apll_pcie_clkvcoldo_div;
+
+static struct clk_hw_omap apll_pcie_clkvcoldo_div_hw = {
+ .hw = {
+ .clk = &apll_pcie_clkvcoldo_div,
+ },
+ .clksel_reg = DRA7XX_CM_CLKVCOLDO_APLL_PCIE,
+};
+
+DEFINE_STRUCT_CLK(apll_pcie_clkvcoldo_div, apll_pcie_clkvcoldo_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(apll_pcie_m2_ck, "apll_pcie_ck", &apll_pcie_ck, 0x0,
+ DRA7XX_CM_DIV_M2_APLL_PCIE, DRA7XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_DIVIDER(sys_clk1_dclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(sys_clk2_dclk_div, "sys_clkin2", &sys_clkin2, 0x0,
+ DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_ABE, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(per_abe_x1_dclk_div, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M3_DPLL_ABE, DRA7XX_DIVHS_MASK);
+
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_CORE,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_CORE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_CORE,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_CORE,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_core_ck_parents[] = {
+ "sys_clkin1", "dpll_abe_m3x2_ck"
+};
+
+static struct clk dpll_core_ck;
+
+static const struct clk_ops dpll_core_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_core_ck_hw = {
+ .hw = {
+ .clk = &dpll_core_ck,
+ },
+ .dpll_data = &dpll_core_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
+
+static const char *dpll_core_x2_ck_parents[] = {
+ "dpll_core_ck",
+};
+
+static struct clk dpll_core_x2_ck;
+
+static struct clk_hw_omap dpll_core_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_core_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h12x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+static const char *mpu_dpll_hs_clk_div_parents[] = {
+ "dpll_core_h12x2_ck",
+};
+
+static struct clk mpu_dpll_hs_clk_div;
+
+static struct clk_hw_omap mpu_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &mpu_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(mpu_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_MPU,
+ .clk_bypass = &mpu_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_MPU,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_MPU,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_MPU,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_mpu_ck_parents[] = {
+ "sys_clkin1", "mpu_dpll_hs_clk_div"
+};
+
+static struct clk dpll_mpu_ck;
+
+static const struct clk_ops dpll_mpu_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap5_mpu_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_mpu_ck_hw = {
+ .hw = {
+ .clk = &dpll_mpu_ck,
+ },
+ .dpll_data = &dpll_mpu_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_mpu_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_MPU, DRA7XX_DIVHS_MASK);
+
+static const char *mpu_dclk_div_parents[] = {
+ "dpll_mpu_m2_ck",
+};
+
+static struct clk mpu_dclk_div;
+
+static struct clk_hw_omap mpu_dclk_div_hw = {
+ .hw = {
+ .clk = &mpu_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(mpu_dclk_div, mpu_dclk_div_parents, apll_pcie_clkvcoldo_ops);
+
+static struct clk dsp_dpll_hs_clk_div;
+
+static struct clk_hw_omap dsp_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &dsp_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(dsp_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_DSP */
+static struct dpll_data dpll_dsp_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_DSP,
+ .clk_bypass = &dsp_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_DSP,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_DSP,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_DSP,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_dsp_ck_parents[] = {
+ "sys_clkin1", "dsp_dpll_hs_clk_div"
+};
+
+static struct clk dpll_dsp_ck;
+
+static struct clk_hw_omap dpll_dsp_ck_hw = {
+ .hw = {
+ .clk = &dpll_dsp_ck,
+ },
+ .dpll_data = &dpll_dsp_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_dsp_ck, dpll_dsp_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_dsp_m2_ck, "dpll_dsp_ck", &dpll_dsp_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_DSP, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(dsp_gclk_div, "dpll_dsp_m2_ck", &dpll_dsp_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk iva_dpll_hs_clk_div;
+
+static struct clk_hw_omap iva_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &iva_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(iva_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_IVA */
+static struct dpll_data dpll_iva_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_IVA,
+ .clk_bypass = &iva_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_IVA,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_IVA,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_IVA,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_iva_ck_parents[] = {
+ "sys_clkin1", "iva_dpll_hs_clk_div"
+};
+
+static struct clk dpll_iva_ck;
+
+static struct clk_hw_omap dpll_iva_ck_hw = {
+ .hw = {
+ .clk = &dpll_iva_ck,
+ },
+ .dpll_data = &dpll_iva_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_iva_m2_ck, "dpll_iva_ck", &dpll_iva_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_IVA, DRA7XX_DIVHS_MASK);
+
+static const char *iva_dclk_parents[] = {
+ "dpll_iva_m2_ck",
+};
+
+static struct clk iva_dclk;
+
+static struct clk_hw_omap iva_dclk_hw = {
+ .hw = {
+ .clk = &iva_dclk,
+ },
+};
+
+DEFINE_STRUCT_CLK(iva_dclk, iva_dclk_parents, apll_pcie_clkvcoldo_ops);
+
+/* DPLL_GPU */
+static struct dpll_data dpll_gpu_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_GPU,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_GPU,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_GPU,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_GPU,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static struct clk dpll_gpu_ck;
+
+static struct clk_hw_omap dpll_gpu_ck_hw = {
+ .hw = {
+ .clk = &dpll_gpu_ck,
+ },
+ .dpll_data = &dpll_gpu_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_gpu_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gpu_m2_ck, "dpll_gpu_ck", &dpll_gpu_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_GPU, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(gpu_dclk, "dpll_gpu_m2_ck", &dpll_gpu_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_CORE, DRA7XX_DIVHS_MASK);
+
+static const char *core_dpll_out_dclk_div_parents[] = {
+ "dpll_core_m2_ck",
+};
+
+static struct clk core_dpll_out_dclk_div;
+
+static struct clk_hw_omap core_dpll_out_dclk_div_hw = {
+ .hw = {
+ .clk = &core_dpll_out_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(core_dpll_out_dclk_div, core_dpll_out_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_DDR */
+static struct dpll_data dpll_ddr_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_DDR,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_DDR,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_DDR,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_DDR,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static struct clk dpll_ddr_ck;
+
+static struct clk_hw_omap dpll_ddr_ck_hw = {
+ .hw = {
+ .clk = &dpll_ddr_ck,
+ },
+ .dpll_data = &dpll_ddr_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_DDR, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(emif_phy_dclk_div, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+/* DPLL_GMAC */
+static struct dpll_data dpll_gmac_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_GMAC,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_GMAC,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_GMAC,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_GMAC,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static struct clk dpll_gmac_ck;
+
+static struct clk_hw_omap dpll_gmac_ck_hw = {
+ .hw = {
+ .clk = &dpll_gmac_ck,
+ },
+ .dpll_data = &dpll_gmac_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_gmac_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_m2_ck, "dpll_gmac_ck", &dpll_gmac_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_GMAC, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(gmac_250m_dclk_div, "dpll_gmac_m2_ck", &dpll_gmac_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static const char *video2_dclk_div_parents[] = {
+ "video2_m2_clkin",
+};
+
+static struct clk video2_dclk_div;
+
+static struct clk_hw_omap video2_dclk_div_hw = {
+ .hw = {
+ .clk = &video2_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video2_dclk_div, video2_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const char *video1_dclk_div_parents[] = {
+ "video1_m2_clkin",
+};
+
+static struct clk video1_dclk_div;
+
+static struct clk_hw_omap video1_dclk_div_hw = {
+ .hw = {
+ .clk = &video1_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video1_dclk_div, video1_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const char *hdmi_dclk_div_parents[] = {
+ "hdmi_clkin",
+};
+
+static struct clk hdmi_dclk_div;
+
+static struct clk_hw_omap hdmi_dclk_div_hw = {
+ .hw = {
+ .clk = &hdmi_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(hdmi_dclk_div, hdmi_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_FIXED_FACTOR(per_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
+ &dpll_abe_m3x2_ck, 0x0, 1, 2);
+
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PER,
+ .clk_bypass = &per_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_PER,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PER,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PER,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_per_ck_parents[] = {
+ "sys_clkin1", "per_dpll_hs_clk_div"
+};
+
+static struct clk dpll_per_ck;
+
+static struct clk_hw_omap dpll_per_ck_hw = {
+ .hw = {
+ .clk = &dpll_per_ck,
+ },
+ .dpll_data = &dpll_per_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_PER, DRA7XX_DIVHS_MASK);
+
+static const char *func_96m_aon_dclk_div_parents[] = {
+ "dpll_per_m2_ck",
+};
+
+static struct clk func_96m_aon_dclk_div;
+
+static struct clk_hw_omap func_96m_aon_dclk_div_hw = {
+ .hw = {
+ .clk = &func_96m_aon_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(func_96m_aon_dclk_div, func_96m_aon_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_FIXED_FACTOR(usb_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
+ &dpll_abe_m3x2_ck, 0x0, 1, 3);
+
+/* DPLL_USB */
+static struct dpll_data dpll_usb_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_USB,
+ .clk_bypass = &usb_dpll_hs_clk_div,
+ .flags = DPLL_J_TYPE,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_USB,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_USB,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_USB,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .sddiv_mask = DRA7XX_DPLL_SD_DIV_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+};
+
+static const char *dpll_usb_ck_parents[] = {
+ "sys_clkin1", "usb_dpll_hs_clk_div"
+};
+
+static struct clk dpll_usb_ck;
+
+static const struct clk_ops dpll_usb_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+ .init = &omap2_init_clk_clkdm,
+};
+
+static struct clk_hw_omap dpll_usb_ck_hw = {
+ .hw = {
+ .clk = &dpll_usb_ck,
+ },
+ .dpll_data = &dpll_usb_dd,
+ .clkdm_name = "coreaon_clkdm",
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_USB, DRA7XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_DIVIDER(l3init_480m_dclk_div, "dpll_usb_m2_ck", &dpll_usb_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(usb_otg_dclk_div, "usb_otg_clkin_ck", &usb_otg_clkin_ck, 0x0,
+ DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(sata_dclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_pcie_ref_m2_ck, "dpll_pcie_ref_ck",
+ &dpll_pcie_ref_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_PCIE_REF,
+ DRA7XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_DIVIDER(pcie2_dclk_div, "dpll_pcie_ref_m2_ck", &dpll_pcie_ref_m2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(pcie_dclk_div, "apll_pcie_m2_ck", &apll_pcie_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(emu_dclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(secure_32k_dclk_div, "secure_32k_clk_src_ck",
+ &secure_32k_clk_src_ck, 0x0,
+ DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk eve_dpll_hs_clk_div;
+
+static struct clk_hw_omap eve_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &eve_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(eve_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_EVE */
+static struct dpll_data dpll_eve_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_EVE,
+ .clk_bypass = &eve_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_EVE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_EVE,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_EVE,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_eve_ck_parents[] = {
+ "sys_clkin1", "eve_dpll_hs_clk_div"
+};
+
+static struct clk dpll_eve_ck;
+
+static struct clk_hw_omap dpll_eve_ck_hw = {
+ .hw = {
+ .clk = &dpll_eve_ck,
+ },
+ .dpll_data = &dpll_eve_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_eve_ck, dpll_eve_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_eve_m2_ck, "dpll_eve_ck", &dpll_eve_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_EVE, DRA7XX_DIVHS_MASK);
+
+static const char *eve_dclk_div_parents[] = {
+ "dpll_eve_m2_ck",
+};
+
+static struct clk eve_dclk_div;
+
+static struct clk_hw_omap eve_dclk_div_hw = {
+ .hw = {
+ .clk = &eve_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(eve_dclk_div, eve_dclk_div_parents, apll_pcie_clkvcoldo_ops);
+
+static const char *clkoutmux0_clk_mux_parents[] = {
+ "sys_clk1_dclk_div", "sys_clk2_dclk_div", "per_abe_x1_dclk_div",
+ "mpu_dclk_div", "dsp_gclk_div", "iva_dclk",
+ "gpu_dclk", "core_dpll_out_dclk_div", "emif_phy_dclk_div",
+ "gmac_250m_dclk_div", "video2_dclk_div", "video1_dclk_div",
+ "hdmi_dclk_div", "func_96m_aon_dclk_div", "l3init_480m_dclk_div",
+ "usb_otg_dclk_div", "sata_dclk_div", "pcie2_dclk_div",
+ "pcie_dclk_div", "emu_dclk_div", "secure_32k_dclk_div",
+ "eve_dclk_div",
+};
+
+DEFINE_CLK_MUX(clkoutmux0_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_CLKOUTMUX0, DRA7XX_CLKSEL_0_4_SHIFT,
+ DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(clkoutmux1_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_CLKOUTMUX1, DRA7XX_CLKSEL_0_4_SHIFT,
+ DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(clkoutmux2_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_CLKOUTMUX2, DRA7XX_CLKSEL_0_4_SHIFT,
+ DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_FIXED_FACTOR(custefuse_sys_gfclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ 1, 2);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h13x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h14x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H14_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h22x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H22_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h23x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H23_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h24x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H24_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+static const char *dpll_ddr_x2_ck_parents[] = {
+ "dpll_ddr_ck",
+};
+
+static struct clk dpll_ddr_x2_ck;
+
+static struct clk_hw_omap dpll_ddr_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_ddr_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_ddr_x2_ck, dpll_ddr_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_ddr_h11x2_ck, "dpll_ddr_x2_ck",
+ &dpll_ddr_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_DDR,
+ DRA7XX_DIVHS_0_5_MASK);
+
+static const char *dpll_dsp_x2_ck_parents[] = {
+ "dpll_dsp_ck",
+};
+
+static struct clk dpll_dsp_x2_ck;
+
+static struct clk_hw_omap dpll_dsp_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_dsp_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_dsp_x2_ck, dpll_dsp_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_dsp_m3x2_ck, "dpll_dsp_x2_ck", &dpll_dsp_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M3_DPLL_DSP, DRA7XX_DIVHS_MASK);
+
+static const char *dpll_gmac_x2_ck_parents[] = {
+ "dpll_gmac_ck",
+};
+
+static struct clk dpll_gmac_x2_ck;
+
+static struct clk_hw_omap dpll_gmac_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_gmac_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_gmac_x2_ck, dpll_gmac_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h11x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_GMAC,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h12x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_GMAC,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h13x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_GMAC,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_m3x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_M3_DPLL_GMAC,
+ DRA7XX_DIVHS_MASK);
+
+static const char *dpll_per_x2_ck_parents[] = {
+ "dpll_per_ck",
+};
+
+static struct clk dpll_per_x2_ck;
+
+static struct clk_hw_omap dpll_per_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_per_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h11x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h12x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h13x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h14x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H14_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M2_DPLL_PER, DRA7XX_DIVHS_MASK);
+
+static const char *dpll_usb_clkdcoldo_parents[] = {
+ "dpll_usb_ck",
+};
+
+static struct clk dpll_usb_clkdcoldo;
+
+static struct clk_hw_omap dpll_usb_clkdcoldo_hw = {
+ .hw = {
+ .clk = &dpll_usb_clkdcoldo,
+ },
+ .clksel_reg = DRA7XX_CM_CLKDCOLDO_DPLL_USB,
+};
+
+DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo, dpll_usb_clkdcoldo_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const char *eve_clk_parents[] = {
+ "dpll_eve_m2_ck", "dpll_dsp_m3x2_ck",
+};
+
+DEFINE_CLK_MUX(eve_clk, eve_clk_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_EVE_CLK,
+ DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_FIXED_FACTOR(func_128m_clk, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck,
+ 0x0, 1, 2);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 16);
+
+DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
+ 4);
+
+DEFINE_CLK_FIXED_FACTOR(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 4);
+
+DEFINE_CLK_FIXED_FACTOR(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 2);
+
+DEFINE_CLK_FIXED_FACTOR(gmii_m_clk_div, "dpll_gmac_h11x2_ck",
+ &dpll_gmac_h11x2_ck, 0x0, 1, 2);
+
+static struct clk hdmi_clk2_div;
+
+static struct clk_hw_omap hdmi_clk2_div_hw = {
+ .hw = {
+ .clk = &hdmi_clk2_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(hdmi_clk2_div, hdmi_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk hdmi_div_clk;
+
+static struct clk_hw_omap hdmi_div_clk_hw = {
+ .hw = {
+ .clk = &hdmi_div_clk,
+ },
+};
+
+DEFINE_STRUCT_CLK(hdmi_div_clk, hdmi_dclk_div_parents, apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_MUX(hdmi_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static struct clk l3_iclk_div;
+
+static struct clk_hw_omap l3_iclk_div_hw = {
+ .hw = {
+ .clk = &l3_iclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(l3_iclk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const struct clk_div_table l3init_60m_fclk_rates[] = {
+ { .div = 1, .val = 0 },
+ { .div = 8, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(l3init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_USB_60MHZ,
+ DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0,
+ l3init_60m_fclk_rates, NULL);
+
+static const char *l4_root_clk_div_parents[] = {
+ "l3_iclk_div",
+};
+
+static struct clk l4_root_clk_div;
+
+static struct clk_hw_omap l4_root_clk_div_hw = {
+ .hw = {
+ .clk = &l4_root_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(l4_root_clk_div, l4_root_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_DIVIDER(mlb_clk, "mlb_clkin_ck", &mlb_clkin_ck, 0x0,
+ DRA7XX_CM_CLKSEL_MLB_MCASP, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(mlbp_clk, "mlbp_clkin_ck", &mlbp_clkin_ck, 0x0,
+ DRA7XX_CM_CLKSEL_MLBP_MCASP, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(per_abe_x1_gfclk2_div, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(timer_sys_clk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_TIMER_SYS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *video1_clk2_div_parents[] = {
+ "video1_clkin",
+};
+
+static struct clk video1_clk2_div;
+
+static struct clk_hw_omap video1_clk2_div_hw = {
+ .hw = {
+ .clk = &video1_clk2_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video1_clk2_div, video1_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk video1_div_clk;
+
+static struct clk_hw_omap video1_div_clk_hw = {
+ .hw = {
+ .clk = &video1_div_clk,
+ },
+};
+
+DEFINE_STRUCT_CLK(video1_div_clk, video1_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_MUX(video1_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static const char *video2_clk2_div_parents[] = {
+ "video2_clkin",
+};
+
+static struct clk video2_clk2_div;
+
+static struct clk_hw_omap video2_clk2_div_hw = {
+ .hw = {
+ .clk = &video2_clk2_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video2_clk2_div, video2_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk video2_div_clk;
+
+static struct clk_hw_omap video2_div_clk_hw = {
+ .hw = {
+ .clk = &video2_div_clk,
+ },
+};
+
+DEFINE_STRUCT_CLK(video2_div_clk, video2_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_MUX(video2_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static const char *wkupaon_iclk_mux_parents[] = {
+ "sys_clkin1", "abe_lp_clk_div",
+};
+
+DEFINE_CLK_MUX(wkupaon_iclk_mux, wkupaon_iclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_WKUPAON, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+/* Leaf clocks controlled by modules */
+
+DEFINE_CLK_GATE(dss_32khz_clk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_32KHZ_CLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(dss_48mhz_clk, "func_48m_fclk", &func_48m_fclk, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_48MHZ_CLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_DSSCLK_SHIFT, 0x0,
+ NULL);
+
+DEFINE_CLK_GATE(dss_hdmi_clk, "hdmi_dpll_clk_mux", &hdmi_dpll_clk_mux, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_HDMI_CLK_SHIFT, 0x0,
+ NULL);
+
+DEFINE_CLK_GATE(dss_video1_clk, "video1_dpll_clk_mux", &video1_dpll_clk_mux,
+ 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL,
+ DRA7XX_OPTFCLKEN_VIDEO1_CLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(dss_video2_clk, "video2_dpll_clk_mux", &video2_dpll_clk_mux,
+ 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL,
+ DRA7XX_OPTFCLKEN_VIDEO2_CLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO2_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO3_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO4_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO5_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO6_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio7_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO7_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio8_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO8_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc1_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc2_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc3_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc4_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(sata_ref_clk, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_L3INIT_SATA_CLKCTRL, DRA7XX_OPTFCLKEN_REF_CLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_otg_ss1_refclk960m, "dpll_usb_clkdcoldo",
+ &dpll_usb_clkdcoldo, 0x0, DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL,
+ DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_otg_ss2_refclk960m, "dpll_usb_clkdcoldo",
+ &dpll_usb_clkdcoldo, 0x0, DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL,
+ DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_phy1_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL,
+ DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_phy2_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL,
+ DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_phy3_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL,
+ DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+
+/* Remaining optional clocks */
+static const char *atl_dpll_clk_mux_parents[] = {
+ "sys_32k_ck", "video1_clkin", "video2_clkin",
+ "hdmi_clkin",
+};
+
+DEFINE_CLK_MUX(atl_dpll_clk_mux, atl_dpll_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_ATL_ATL_CLKCTRL, DRA7XX_CLKSEL_SOURCE1_SHIFT,
+ DRA7XX_CLKSEL_SOURCE1_WIDTH, 0x0, NULL);
+
+static const char *atl_gfclk_mux_parents[] = {
+ "l3_iclk_div", "dpll_abe_m2_ck", "atl_dpll_clk_mux",
+};
+
+DEFINE_CLK_MUX(atl_gfclk_mux, atl_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_ATL_ATL_CLKCTRL, DRA7XX_CLKSEL_SOURCE2_SHIFT,
+ DRA7XX_CLKSEL_SOURCE2_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(dcan1_sys_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+static const struct clk_div_table gmac_gmii_ref_clk_div_rates[] = {
+ { .div = 2, .val = 0 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(gmac_gmii_ref_clk_div, "dpll_gmac_m2_ck",
+ &dpll_gmac_m2_ck, 0x0, DRA7XX_CM_GMAC_GMAC_CLKCTRL,
+ DRA7XX_CLKSEL_REF_SHIFT, DRA7XX_CLKSEL_REF_WIDTH, 0x0,
+ gmac_gmii_ref_clk_div_rates, NULL);
+
+static const char *gmac_rft_clk_mux_parents[] = {
+ "video1_clkin", "video2_clkin", "dpll_abe_m2_ck",
+ "hdmi_clkin", "l3_iclk_div",
+};
+
+DEFINE_CLK_MUX(gmac_rft_clk_mux, gmac_rft_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_GMAC_GMAC_CLKCTRL, DRA7XX_CLKSEL_RFT_SHIFT,
+ DRA7XX_CLKSEL_RFT_WIDTH, 0x0, NULL);
+
+static const char *gpu_core_gclk_mux_parents[] = {
+ "dpll_core_h14x2_ck", "dpll_per_h14x2_ck", "dpll_gpu_m2_ck",
+};
+
+DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_CORE_CLK_SHIFT,
+ DRA7XX_CLKSEL_CORE_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_HYD_CLK_SHIFT,
+ DRA7XX_CLKSEL_HYD_CLK_WIDTH, 0x0, NULL);
+
+static const char *ipu1_gfclk_mux_parents[] = {
+ "dpll_abe_m2x2_ck", "dpll_core_h22x2_ck",
+};
+
+DEFINE_CLK_MUX(ipu1_gfclk_mux, ipu1_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU1_IPU1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+static const struct clk_div_table l3instr_ts_gclk_div_rates[] = {
+ { .div = 8, .val = 0 },
+ { .div = 16, .val = 1 },
+ { .div = 32, .val = 2 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(l3instr_ts_gclk_div, "wkupaon_iclk_mux",
+ &wkupaon_iclk_mux, 0x0,
+ DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ DRA7XX_CLKSEL_24_25_SHIFT, DRA7XX_CLKSEL_24_25_WIDTH,
+ 0x0, l3instr_ts_gclk_div_rates, NULL);
+
+static const char *mcasp1_ahclkr_mux_parents[] = {
+ "abe_24m_fclk", "abe_sys_clk_div", "func_24m_clk",
+ "atlclkin3", "atl_clkin2", "atl_clkin1",
+ "atl_clkin0", "sys_clkin2", "ref_clkin0",
+ "ref_clkin1", "ref_clkin2", "ref_clkin3",
+ "mlb_clk", "mlbp_clk",
+};
+
+DEFINE_CLK_MUX(mcasp1_ahclkr_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT,
+ DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp1_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+static const char *mcasp1_aux_gfclk_mux_parents[] = {
+ "per_abe_x1_gfclk2_div", "video1_clk2_div", "video2_clk2_div",
+ "hdmi_clk2_div",
+};
+
+DEFINE_CLK_MUX(mcasp1_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp2_ahclkr_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT,
+ DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp2_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT,
+ DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp2_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp3_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP3_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp3_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP3_CLKCTRL,