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raw | patch | inline | side by side (parent: 72d90c3)
raw | patch | inline | side by side (parent: 72d90c3)
author | Suman Anna <s-anna@ti.com> | |
Fri, 28 Jun 2013 00:10:37 +0000 (17:10 -0700) | ||
committer | Suman Anna <s-anna@ti.com> | |
Fri, 29 Aug 2014 02:50:56 +0000 (21:50 -0500) |
The DRA7xx family of SoCs can have up to two identical DSP
processor subsystems, with most of them having a single DSP
processor subsystem. The second DSP is present only on DRA74x
variants currently. The relevant hwmod class and data structures
are added for this second DSP only for DRA74x SoC variants.
The hwmod data for this DSP2 is very similar to the data on
DSP1.
Signed-off-by: Suman Anna <s-anna@ti.com>
processor subsystems, with most of them having a single DSP
processor subsystem. The second DSP is present only on DRA74x
variants currently. The relevant hwmod class and data structures
are added for this second DSP only for DRA74x SoC variants.
The hwmod data for this DSP2 is very similar to the data on
DSP1.
Signed-off-by: Suman Anna <s-anna@ti.com>
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | patch | blob | history |
index 4d8cc902c455bf51c4ac814e398ef4a26a62e41e..a8dec76648f94671c6a8c16b2b9dc10c10a12a34 100644 (file)
},
};
+/* dsp2 processor */
+static struct omap_hwmod dra7xx_dsp2_hwmod = {
+ .name = "dsp2",
+ .class = &dra7xx_dsp_hwmod_class,
+ .clkdm_name = "dsp2_clkdm",
+ .rst_lines = dra7xx_dsp_resets,
+ .rst_lines_cnt = ARRAY_SIZE(dra7xx_dsp_resets),
+ .main_clk = "dpll_dsp_m2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET,
+ .rstctrl_offs = DRA7XX_RM_DSP2_RSTCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET,
+ },
+ },
+};
+
/*
* 'dss' class
*
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* dsp2 -> l3_main_1 */
+static struct omap_hwmod_ocp_if dra7xx_dsp2__l3_main_1 = {
+ .master = &dra7xx_dsp2_hwmod,
+ .slave = &dra7xx_l3_main_1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
{
.name = "family",
&dra7xx_l4_per3__usb_otg_ss4,
&dra7xx_l3_main_1__mmu0_dsp2,
&dra7xx_l3_main_1__mmu1_dsp2,
+ &dra7xx_dsp2__l3_main_1,
NULL,
};