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raw | patch | inline | side by side (parent: a6d50f3)
raw | patch | inline | side by side (parent: a6d50f3)
author | Misael Lopez Cruz <misael.lopez@ti.com> | |
Mon, 21 Sep 2015 18:20:43 +0000 (13:20 -0500) | ||
committer | Vishal Mahaveer <vishalm@ti.com> | |
Tue, 13 Oct 2015 02:30:14 +0000 (21:30 -0500) |
Use the same timeout for the software implementation as the
hardware approach would do.
Change-Id: Idd87f943746d9bafccd3b07669284f599bbf7535
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
hardware approach would do.
Change-Id: Idd87f943746d9bafccd3b07669284f599bbf7535
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
drivers/mmc/host/omap_hsmmc.c | patch | blob | history |
index 8879410e45915bf06d41948a251bb96edd3a202a..942daf5e6898b2fb7af61636a18bfb09572ff4a9 100644 (file)
if (clkd == 0)
clkd = 1;
- if (host->need_i834_errata) {
- unsigned long delta;
-
- delta = (timeout_clks / (host->clk_rate / clkd));
-
- /*
- * We should really be using just timeout_ns + delta,
- * however we have no control over when DMA will
- * actually start transferring; due to that we will add
- * an extra slack to make sure we don't expire too
- * early.
- */
- host->data_timeout = timeout_ns + delta + MMC_SOFT_TIMER_SLACK;
- return;
- }
-
cycle_ns = 1000000000 / (host->clk_rate / clkd);
timeout = timeout_ns / cycle_ns;
timeout += timeout_clks;
dto -= 13;
else
dto = 0;
+ }
+
+ if (host->need_i834_errata) {
+ host->data_timeout = (1 << (dto + 13)) * cycle_ns;
+ } else {
if (dto > 14)
dto = 14;
+ reg &= ~DTO_MASK;
+ reg |= dto << DTO_SHIFT;
+ OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
}
-
- reg &= ~DTO_MASK;
- reg |= dto << DTO_SHIFT;
- OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
}
static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)