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raw | patch | inline | side by side (parent: e34f080)
author | Archit Taneja <archit@ti.com> | |
Tue, 25 Oct 2011 06:12:55 +0000 (11:42 +0530) | ||
committer | Archit Taneja <archit@ti.com> | |
Thu, 28 Feb 2013 09:50:05 +0000 (15:20 +0530) |
Create functions which configure registers related to video packetizer,
color space converter and video sampler to add deep color support.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Mythri P K <mythripk@ti.com>
color space converter and video sampler to add deep color support.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Mythri P K <mythripk@ti.com>
drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c | patch | blob | history | |
drivers/video/omap2/dss/ti_hdmi_5xxx_ip.c | patch | blob | history |
index a0259ae915b1c2f425d55c778b0409358ea1e047..947ec62aec58270ab9c366f0e892e21e5bb8bec9 100644 (file)
r = FLD_MOD(r, vsync_pol, 7, 7);
r = FLD_MOD(r, hsync_pol, 6, 6);
r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
- r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
+ r = FLD_MOD(r, ip_data->cfg.deep_color + 1 , 1, 0);
hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
}
index d062e432747ac45e8a11c3a67f9accf5ecb7611e..16c2d62821e935ab530b2df8719189892e569a69 100644 (file)
cfg->v_fc_config.cm.mode, 3, 3);
}
+static void hdmi_core_config_video_packetizer(struct hdmi_ip_data *ip_data)
+{
+ void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
+ struct hdmi_config *cfg = &ip_data->cfg;
+ int clr_depth;
+
+ switch (cfg->deep_color) {
+ case HDMI_DEEP_COLOR_30BIT:
+ clr_depth = 5;
+ break;
+ case HDMI_DEEP_COLOR_36BIT:
+ clr_depth = 6;
+ break;
+ case HDMI_DEEP_COLOR_24BIT:
+ default:
+ clr_depth = 0;
+ break;
+ }
+
+ /* COLOR_DEPTH */
+ REG_FLD_MOD(core_sys_base, HDMI_CORE_VP_PR_CD, clr_depth, 7, 4);
+
+ /* BYPASS_EN */
+ REG_FLD_MOD(core_sys_base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 1, 6, 6);
+
+ /* PP_EN */
+ REG_FLD_MOD(core_sys_base, HDMI_CORE_VP_CONF, clr_depth ? 1 : 0, 5, 5);
+
+ /* YCC422_EN */
+ REG_FLD_MOD(core_sys_base, HDMI_CORE_VP_CONF, 0, 3, 3);
+
+ /* PP_STUFFING */
+ REG_FLD_MOD(core_sys_base, HDMI_CORE_VP_STUFF, clr_depth ? 1 : 0, 1, 1);
+
+ /* YCC422_STUFFING */
+ REG_FLD_MOD(core_sys_base, HDMI_CORE_VP_STUFF, 1, 2, 2);
+
+ /* OUTPUT_SELECTOR */
+ REG_FLD_MOD(core_sys_base, HDMI_CORE_VP_CONF, clr_depth ? 0 : 2, 1, 0);
+}
+
+static void hdmi_core_config_csc(struct hdmi_ip_data *ip_data)
+{
+ void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
+ struct hdmi_config *cfg = &ip_data->cfg;
+ int clr_depth;
+
+ switch (cfg->deep_color) {
+ case HDMI_DEEP_COLOR_30BIT:
+ clr_depth = 5;
+ break;
+ case HDMI_DEEP_COLOR_36BIT:
+ clr_depth = 6;
+ break;
+ case HDMI_DEEP_COLOR_24BIT:
+ default:
+ clr_depth = 0;
+ break;
+ }
+
+ /* CSC_COLORDEPTH */
+ REG_FLD_MOD(core_sys_base, HDMI_CORE_CSC_SCALE, clr_depth, 7, 4);
+}
+
+static void hdmi_core_config_video_sampler(struct hdmi_ip_data *ip_data)
+{
+ void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
+ struct hdmi_config *cfg = &ip_data->cfg;
+ int video_mapping;
+
+ switch (cfg->deep_color) {
+ case HDMI_DEEP_COLOR_30BIT:
+ video_mapping = 3;
+ break;
+ case HDMI_DEEP_COLOR_36BIT:
+ video_mapping = 5;
+ break;
+ case HDMI_DEEP_COLOR_24BIT:
+ default:
+ video_mapping = 1;
+ break;
+ }
+
+ /* VIDEO_MAPPING */
+ REG_FLD_MOD(core_sys_base, HDMI_CORE_TX_INVID0, video_mapping, 4, 0);
+}
+
static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data)
{
void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
hdmi_core_video_config(ip_data, &v_core_cfg);
+ hdmi_core_config_video_packetizer(ip_data);
+ hdmi_core_config_csc(ip_data);
+ hdmi_core_config_video_sampler(ip_data);
+
/*
* configure packet
* info frame video see doc CEA861-D page 65