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raw | patch | inline | side by side (parent: dc0555d)
author | Suman Anna <s-anna@ti.com> | |
Wed, 27 May 2015 03:00:51 +0000 (22:00 -0500) | ||
committer | Suman Anna <s-anna@ti.com> | |
Sat, 30 May 2015 00:15:09 +0000 (19:15 -0500) |
The IPU1 MMU has been using common IOMMU pdata quirks defined and
used by all IPU IOMMU devices on OMAP4 and beyond. Separate out the
pdata for IPU1 MMU with the additional .set_pwrdm_constraint ops
plugged in, so that the IPU1 power domain can be restricted to ON
state during the boot and active period of the IPU1 remote processor.
This eliminates the pre-conditions for the IPU1 boot issue as
described in [1].
NOTE:
The fix is currently applied only to IPU1 on DRA7xx SoC, as the
other affected processors on OMAP4/OMAP5/DRA7 are in domains that
are not entering RET. The fix can be easily scaled if these domains
do hit RET in the future.
[1] http://git.ti.com/gitweb/?p=rpmsg/rpmsg.git;a=commit;h=6d6dd44c55638d54a151bf2ae6cc77b2f4e459d0
Signed-off-by: Suman Anna <s-anna@ti.com>
used by all IPU IOMMU devices on OMAP4 and beyond. Separate out the
pdata for IPU1 MMU with the additional .set_pwrdm_constraint ops
plugged in, so that the IPU1 power domain can be restricted to ON
state during the boot and active period of the IPU1 remote processor.
This eliminates the pre-conditions for the IPU1 boot issue as
described in [1].
NOTE:
The fix is currently applied only to IPU1 on DRA7xx SoC, as the
other affected processors on OMAP4/OMAP5/DRA7 are in domains that
are not entering RET. The fix can be easily scaled if these domains
do hit RET in the future.
[1] http://git.ti.com/gitweb/?p=rpmsg/rpmsg.git;a=commit;h=6d6dd44c55638d54a151bf2ae6cc77b2f4e459d0
Signed-off-by: Suman Anna <s-anna@ti.com>
arch/arm/mach-omap2/pdata-quirks.c | patch | blob | history |
index ec7e6df8d0c67fa12f5aa5b8b1f1bb67a2e5eabd..1d4dd1212678d16e58e59c581771f74fa5bf8cf6 100644 (file)
struct of_dev_auxdata omap_auxdata_lookup[];
static struct twl4030_gpio_platform_data twl_gpio_auxdata;
+#if IS_ENABLED(CONFIG_OMAP_IOMMU)
+int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev, bool request,
+ u8 *pwrst);
+#else
+static inline int omap_iommu_set_pwrdm_constraint(struct platform_device *pdev,
+ bool request, u8 *pwrst)
+{
+ return 0;
+}
+#endif
+
#if IS_ENABLED(CONFIG_WL12XX)
static struct wl12xx_platform_data wl12xx __initdata;
.device_enable = omap_device_enable,
.device_idle = omap_device_idle,
};
+
+static struct iommu_platform_data dra7_ipu1_iommu_pdata = {
+ .reset_name = "mmu_cache",
+ .assert_reset = omap_device_assert_hardreset,
+ .deassert_reset = omap_device_deassert_hardreset,
+ .device_enable = omap_device_enable,
+ .device_idle = omap_device_idle,
+ .set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint,
+};
#endif
#ifdef CONFIG_SOC_AM33XX
OF_DEV_AUXDATA("ti,dra7-iommu", 0x55082000, "55082000.mmu",
&omap4_iommu_pdata),
OF_DEV_AUXDATA("ti,dra7-iommu", 0x58882000, "58882000.mmu",
- &omap4_iommu_pdata),
+ &dra7_ipu1_iommu_pdata),
#endif
{ /* sentinel */ },
};