| author | Dan Murphy <dmurphy@ti.com> | |
| Thu, 30 May 2013 10:44:11 +0000 (05:44 -0500) | ||
| committer | Dan Murphy <dmurphy@ti.com> | |
| Thu, 30 May 2013 10:44:11 +0000 (05:44 -0500) |
TI-Feature: power_management
TI-Tree: git://git.ti.com/~kristo/ti-linux-kernel/pm-linux-feature-tree.git
TI-Branch: pm-linux-3.8.y
* 'pm-linux-3.8.y' of git://git.ti.com/~kristo/ti-linux-kernel/pm-linux-feature-tree: (60 commits)
ARM: DRA7: dts: Remove the non existent l3_main_3 entry
ARM: DRA7: dpll: No freqsel on DRA7
ARM: DRA7: dpll: Lock GMAC PLL at boot
ARM: DRA7: dpll: Lock ABE PLL according to ATL needs
ARM: DRA7: id: Change control_id_code register address
thermal: consider emul_temperature while computing trend
ARM: OMAP5: Add select tuples to enable CPUFREQ on OMAP5
ARM: DRA7XX: PM: add soc_is_dra7xx check to take care of freqsel absence
ARM: dts: dra7: add clock nodes for CPU and link avs_mpu regulator to cpu
Arm: DRA7XX: Clock: Update dpll_mpu_ck_ops
ARM: DTS: DRA7: Link the actual TPS659038 regulators to
ARM: DTS: DRA7: Add avs class 0 regulator nodes
regulator: ti-avs-class0: use regulator name based on device instance
regulator: ti-avs-class0: dont reserve efuse memory offsets
cpufreq: cpufreq-cpu0: defer probe when regulator is not ready(v2)
regulator: core: return err value for regulator_get if there is no DT binding
ARM/dts: dra7-evm: Enable tps659038 on i2c1 bus
arm: dts: dra7: add I2C devices to dra7 DeviceTree file
arm: omap2plus_defconfig: enable DRA752 thermal support by default
arm: mach-omap2: flag DRA7 as having bandgap
...
Conflicts:
arch/arm/configs/omap2plus_defconfig
Signed-off-by: Dan Murphy <dmurphy@ti.com>
TI-Tree: git://git.ti.com/~kristo/ti-linux-kernel/pm-linux-feature-tree.git
TI-Branch: pm-linux-3.8.y
* 'pm-linux-3.8.y' of git://git.ti.com/~kristo/ti-linux-kernel/pm-linux-feature-tree: (60 commits)
ARM: DRA7: dts: Remove the non existent l3_main_3 entry
ARM: DRA7: dpll: No freqsel on DRA7
ARM: DRA7: dpll: Lock GMAC PLL at boot
ARM: DRA7: dpll: Lock ABE PLL according to ATL needs
ARM: DRA7: id: Change control_id_code register address
thermal: consider emul_temperature while computing trend
ARM: OMAP5: Add select tuples to enable CPUFREQ on OMAP5
ARM: DRA7XX: PM: add soc_is_dra7xx check to take care of freqsel absence
ARM: dts: dra7: add clock nodes for CPU and link avs_mpu regulator to cpu
Arm: DRA7XX: Clock: Update dpll_mpu_ck_ops
ARM: DTS: DRA7: Link the actual TPS659038 regulators to
ARM: DTS: DRA7: Add avs class 0 regulator nodes
regulator: ti-avs-class0: use regulator name based on device instance
regulator: ti-avs-class0: dont reserve efuse memory offsets
cpufreq: cpufreq-cpu0: defer probe when regulator is not ready(v2)
regulator: core: return err value for regulator_get if there is no DT binding
ARM/dts: dra7-evm: Enable tps659038 on i2c1 bus
arm: dts: dra7: add I2C devices to dra7 DeviceTree file
arm: omap2plus_defconfig: enable DRA752 thermal support by default
arm: mach-omap2: flag DRA7 as having bandgap
...
Conflicts:
arch/arm/configs/omap2plus_defconfig
Signed-off-by: Dan Murphy <dmurphy@ti.com>
79 files changed:
diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt
index d0051a7505873e14d17c5a8718179f19475a78bc..4f87488af6cb7e402126b8a766d482fa38492638 100644 (file)
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
+
+- DRA7 EVM: Software Developement Board for DRA7XX
+ compatible = "ti,dra7-evm", "ti,dra7"
diff --git a/Documentation/devicetree/bindings/clock/palmas-clk.txt b/Documentation/devicetree/bindings/clock/palmas-clk.txt
--- /dev/null
@@ -0,0 +1,27 @@
+* palmas and palmas-charger resource clock IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-clk
+ ti,twl6036-clk
+ ti,twl6037-clk
+ ti,tps65913-clk
+ ti,tps65914-clk
+ ti,tps80036-clk
+and also the generic series names
+ ti,palmas-clk
+
+Optional properties:
+- ti,clk32g-mode-sleep - mode to adopt in pmic sleep 0 - off, 1 - on
+- ti,clkg32kgaudio-mode-sleep - see above
+
+Example:
+
+clk {
+ compatible = "ti,twl6035-clk", "ti,palmas-clk";
+ ti,clk32kg-mode-sleep = <0>;
+ ti,clk32kgaudio-mode-sleep = <0>;
+ #clock-cells = <1>;
+ clock-frequency = <32000000>;
+ clock-names = "clk32kg", "clk32kgaudio";
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-palmas.txt b/Documentation/devicetree/bindings/gpio/gpio-palmas.txt
--- /dev/null
@@ -0,0 +1,35 @@
+* palmas and palmas charger GPIO IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-gpio
+ ti,twl6036-gpio
+ ti,twl6037-gpio
+ ti,tps65913-gpio
+ ti,tps65914-gpio
+ ti,tps80036-gpio
+
+and also the generic series names
+
+ ti,palmas-gpio
+
+- gpio-controller: mark the device as a GPIO controller
+- gpio-cells = <1>: GPIO lines are provided.
+- interrupt-controller : palmas has its own internal IRQs
+- #interrupt-cells : should be set to 2 for IRQ number and flags
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as the trigger masks from
+ Documentation/devicetree/bindings/interrupts.txt
+- interrupt-parent : The parent interrupt controller.
+
+Example:
+
+gpio {
+ compatible = "ti,twl6035-gpio", "ti,palmas-gpio";
+
+ gpio-controller;
+ #gpio-cells = <1>;
+ interrupt-parent = <&palmas>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
diff --git a/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt b/Documentation/devicetree/bindings/input/palmas-pwrbutton.txt
--- /dev/null
@@ -0,0 +1,26 @@
+* palmas and palmas-charger Button IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-pwrbutton
+ ti,twl6036-pwrbutton
+ ti,twl6037-pwrbutton
+ ti,tps65913-pwrbutton
+ ti,tps65914-pwrbutton
+ ti,tps80036-pwrbutton
+and also the generic series names
+ ti,palmas-pwrbutton
+
+- interrupts: the interrupt outputs of the controller.
+- interrupt-names : Should be the name of irq resource. Each interrupt
+ binds its interrupt-name.
+- interrupt-parent : The parent interrupt controller.
+
+Example:
+
+pwrbutton {
+ compatible = "ti,twl6035-pwrbutton", "ti,palmas-pwrbutton";
+ interrupt-parent = <&palmas>;
+ interrupts = <1 0>;
+ interrupt-names = "pwron-irq";
+};
diff --git a/Documentation/devicetree/bindings/leds/leds-palmas.txt b/Documentation/devicetree/bindings/leds/leds-palmas.txt
--- /dev/null
@@ -0,0 +1,36 @@
+* palmas and palmas-charger LED IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-leds
+ ti,twl6036-leds
+ ti,twl6037-leds
+ ti,tps65913-leds
+ ti,tps65914-leds
+ ti,tps80036-leds
+and also the generic series names
+ ti,palmas-leds
+
+Optional properties:
+-ti,led1-current - sink current setting 0 - 0mA, 1 - 25mA, 2 - 5mA,
+ 3 - 0mA, 4 - 5mA, 5 - 5mA, 6 - 10.0mA, 7 - 0mA
+-ti,led2-current - see above
+-ti,led3-current - see above
+-ti,led4-current - see above
+-ti,chrg-led-mode - only valid for charger - mode for charging led operation
+ 0 - Charging indicator
+ 1 - controlled as a general purpose LED
+-ti,chrg-led-vbat-low - only valid for charger - blinking of low battery led
+ 0 - blinking is enabled,
+ 1 - blinking is disabled
+
+Example:
+leds {
+ compatible = "ti,twl6035-leds", "ti,palmas-leds";
+ ti,led1-current = <0>;
+ ti,led2-current = <0>;
+ ti,led3-current = <0>;
+ ti,led4-current = <0>;
+ ti,chrg-led-mode = <0>;
+ ti,chrg-led-vbat-low = <0>;
+};
diff --git a/Documentation/devicetree/bindings/mfd/palmas.txt b/Documentation/devicetree/bindings/mfd/palmas.txt
index 94a0c12789461f399244d206f130adf2081b564a..3defba700eed5a3414689396325ca73049bd007f 100644 (file)
-Texas Instruments Palmas family
-
-The Palmas familly are Integrated Power Management Chips.
-These chips are connected to an i2c bus.
+* palmas and palmas-charger device tree bindings
+The TI palmas family current members :-
+twl6035 (palmas)
+twl6036 (palmas-charger)
+twl6037 (palmas)
+tps65913 (palmas)
+tps65914 (palmas)
+tps80036 (palmas-charger)
Required properties:
-- compatible : Must be "ti,palmas";
- For Integrated power-management in the palmas series, twl6035, twl6037,
- tps65913
-- interrupts : This i2c device has an IRQ line connected to the main SoC
-- interrupt-controller : Since the palmas support several interrupts internally,
- it is considered as an interrupt controller cascaded to the SoC one.
-- #interrupt-cells = <1>;
+- compatible : Should be from the list
+ ti,twl6035
+ ti,twl6036
+ ti,twl6037
+ ti,tps65913
+ ti,tps65914
+ ti,tps80036
+ ti,tps659038
+and also the generic series names
+ ti,palmas
+ ti,palmas-charger
+- interrupt-controller : palmas has its own internal IRQs
+- #interrupt-cells : should be set to 2 for IRQ number and flags
+ The first cell is the IRQ number.
+ The second cell is the flags, encoded as the trigger masks from
+ Documentation/devicetree/bindings/interrupts.txt
- interrupt-parent : The parent interrupt controller.
-Optional node:
-- Child nodes contain in the palmas. The palmas family is made of several
- variants that support a different number of features.
- The child nodes will thus depend of the capability of the variant.
-- mux_pad1 if a value is given it will be used for the pad1 mux
-- mux_pad2 if a value us given it will be used for the pad2 mux
-- power_ctrl if a value is given it will be written to the POWER_CTRL register
+Optional properties:
+ ti,mux_padX : set the pad register X (1-2) to the correct muxing for the
+ hardware, if not set will use muxing in OTP.
Example:
-/*
- * Integrated Power Management Chip Palmas
- */
-palmas@48 {
- compatible = "ti,palmas";
- reg = <0x48>;
- interrupts = <39>; /* IRQ_SYS_1N cascaded to gic */
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,mux_pad1 = <0x00>;
- ti,mux_pad2 = <0x00>;
- ti,power_ctrl = <0x03>;
+palmas {
+ compatible = "ti,twl6035", "ti,palmas";
+ reg = <0x48>
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ ti,mux-pad1 = <0>;
+ ti,mux-pad2 = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pmic {
+ compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+ ....
+ }
+
+ gpio {
+ compatible = "ti,twl6035-gpio", "ti,palmas-gpio";
+ ....
+ };
+
+ wdt {
+ compatible = "ti,twl6035-wdt", "ti,palmas-wdt";
+ ....
+ };
+
+ rtc {
+ compatible = "ti,twl6035-rtc", "ti,palmas-rtc";
+ ....
+ };
- palmas_pmic {
- compatible = "ti,palmas_pmic";
- regulators {
- smps12_reg: smps12 {
- regulator-min-microvolt = < 600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- ti,warm_sleep = <0>;
- ti,roof_floor = <0>;
- ti,mode_sleep = <0>;
- ti,warm_reset = <0>;
- ti,tstep = <0>;
- ti,vsel = <0>;
- };
- };
- ti,ldo6_vibrator = <0>;
+ pwrbutton {
+ compatible = "ti,twl6035-pwrbutton", "ti,palmas-pwrbutton";
+ ....
};
- palmas_rtc {
- compatible = "ti,palmas_rtc";
- interrupts = <8 9>;
- reg = <0>;
- };
-};
+ leds {
+ compatible = "ti,twl6035-leds", "ti-palmas-leds";
+ }
+
+ clk {
+ compatible = "ti,twl6035-clk", "ti,palmas-clk";
+ ....
+ };
+}
diff --git a/Documentation/devicetree/bindings/regulator/palmas-pmic.txt b/Documentation/devicetree/bindings/regulator/palmas-pmic.txt
--- /dev/null
@@ -0,0 +1,169 @@
+* palmas and palmas-charger regulator IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-pmic
+ ti,twl6036-pmic
+ ti,twl6037-pmic
+ ti,tps65913-pmic
+ ti,tps65914-pmic
+ ti,tps80036-pmic
+ ti,tps659038-pmic
+and also the generic series names
+ ti,palmas-pmic
+
+Optional properties:
+- ti,ldo6-vibrator : ldo6 is in vibrator mode
+
+Optional nodes:
+- regulators : should contain the constrains and init information for the
+ regulators. It should contain a subnode per regulator from the
+ list.
+ For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
+ smps45, smps457, smps7 depending on varient, smps6, smps[8-10],
+ ldo[1-9], ldoln, ldousb
+ For ti,palmas-charger-pmic - smps12, smps123, smps3 depending on OTP,
+ smps[6-9], boost, ldo[1-14], ldoln, ldousb
+
+ optional chip specific regulator fields :-
+ ti,warm-reset - maintain voltage during warm reset
+ ti,roof-floor - control voltage selection by pin
+ ti,sleep-mode - mode to adopt in pmic sleep 0 - off, 1 - auto,
+ 2 - eco, 3 - forced pwm
+ ti,tstep - slope control 0 - Jump, 1 10mV/us, 2 5mV/us, 3 2.5mV/us
+ ti,smps-range - OTP has the wrong range set for the hardware so override
+ 0 - low range, 1 - high range
+
+Example:
+
+pmic@0 {
+ compatible = "ti,twl6035-pmic", "ti,palmas-pmic";
+ interrupt-parent = <&palmas>;
+ interrupts = <14 0>;
+ interrupt-name = "short-irq";
+
+ ti,ldo6_vibrator;
+
+ regulators {
+ smps12_reg : smps12 {
+ regulator-name = "smps12";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ti,warm-reset;
+ ti,roof-floor;
+ ti,mode-sleep = <0>;
+ ti,tstep = <0>;
+ ti,smps-range = <1>;
+ };
+
+ smps3_reg: smps3 {
+ regulator-name = "smps3";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ };
+
+ smps45_reg: smps45 {
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ };
+
+ smps6_reg: smps6 {
+ regulator-name = "smps6";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ smps7_reg: smps7 {
+ regulator-name = "smps7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ smps8_reg: smps8 {
+ regulator-name = "smps8";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ };
+
+ smps9_reg: smps9 {
+ regulator-name = "smps9";
+ regulator-min-microvolt = <2100000>;
+ regulator-max-microvolt = <2100000>;
+ };
+
+ smps10_reg: smps10 {
+ regulator-name = "smps10";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldoln_reg: ldoln {
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ ldousb_reg: ldousb {
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3250000>;
+ regulator-max-microvolt = <3250000>;
+ };
+ };
+};
diff --git a/Documentation/devicetree/bindings/regulator/ti-avs-class0.txt b/Documentation/devicetree/bindings/regulator/ti-avs-class0.txt
--- /dev/null
@@ -0,0 +1,66 @@
+Texas Instrument SmartReflex AVS Class 0 Regulator
+
+Required properties:
+- compatible: "ti,avsclass0"
+- reg: Should contain Efuse registers location and length
+- avs-supply: The supply for AVS block
+- efuse-settings: An array of 2-tuples items, and each item consists
+ of Voltage index and efuse offset(from reg) like: <voltage offset>
+ voltage: Voltage index in microvolts (also called nominal voltage)
+ offset: ofset in bytes from base provided in reg
+ NOTE: min_uV, max_uV are pickedup from this list
+
+Optional properties:
+- voltage-tolerance: Specify the voltage tolerance in percentage
+- ti,avsclass0-microvolt-values: Boolean property indicating that the efuse
+ values are in microvolts
+
+Example #1: single rails:
+soc.dtsi:
+avs_mpu: regulator-avs@0x40200000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40200000 0x20>;
+ efuse-settings = <975000 0
+ 1075000 4
+ 1200000 8>;
+};
+
+avs_core: regulator-avs@0x40300000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40300000 0x20>;
+ efuse-settings = <975000 0
+ 1050000 4>;
+};
+
+board.dtsi:
+&avs_mpu {
+ avs-supply = <&vcc>;
+};
+&avs_core {
+ avs-supply = <&smps2>;
+};
+
+Example #2: Ganged (combined) rails:
+soc.dtsi:
+avs_mpu: regulator-avs@0x40200000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40200000 0x20>;
+ efuse-settings = <975000 0
+ 1075000 4
+ 1200000 8>;
+};
+
+avs_core: regulator-avs@0x40300000 {
+ compatible = "ti,avsclass0";
+ reg = <0x40300000 0x20>;
+ efuse-settings = <975000 0
+ 1050000 4>;
+};
+
+board.dtsi:
+&avs_mpu {
+ avs-supply = <&smps3>;
+};
+&avs_core {
+ avs-supply = <&smps3>;
+};
diff --git a/Documentation/devicetree/bindings/rtc/palmas-rtc.txt b/Documentation/devicetree/bindings/rtc/palmas-rtc.txt
--- /dev/null
@@ -0,0 +1,21 @@
+* palmas and palmas-charger RTC IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-rtc
+ ti,twl6036-rtc
+ ti,twl6037-rtc
+ ti,tps65913-rtc
+ ti,tps65914-rtc
+ ti,tps80036-rtc
+and also the generic series names
+ ti,palmas-rtc
+
+Examples:
+
+rtc {
+ compatible = "ti,twl6035-rtc", "ti,palmas-rtc";
+ interrupt-parent = <&palmas>;
+ interrupts = <8 0 9 0>;
+ interrupt-name = "alarm-irq", "timer-irq";
+};
diff --git a/Documentation/devicetree/bindings/watchdog/palmas-wdt.txt b/Documentation/devicetree/bindings/watchdog/palmas-wdt.txt
--- /dev/null
@@ -0,0 +1,21 @@
+* palmas and palmas-charger Watchdog IP block devicetree bindings
+
+Required properties:
+- compatible : Should be from the list
+ ti,twl6035-wdt
+ ti,twl6036-wdt
+ ti,twl6037-wdt
+ ti,tps65913-wdt
+ ti,tps65914-wdt
+ ti,tps80036-wdt
+and also the generic series names
+ ti,palmas-wdt
+
+Examples:
+
+wdt {
+ compatible = "ti,twl6035-wdt", "ti,palmas-wdt";
+ interrupt-parent = <&palmas>;
+ interrupts = <10 0>;
+ interrupt-name = "watchdog-irq";
+};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0e68a0b23280ac82fe74b903ef924e7d5be092d3..30cd326b5b757866431c7f67ad522bbc5ccd49c2 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 355 if ARCH_U8500
default 264 if MACH_H4700
- default 512 if SOC_OMAP5
+ default 512 if SOC_OMAP5 || SOC_DRA7XX
default 288 if ARCH_VT8500
default 0
help
index 5c0aebbcf0fe89b088b0c33680dceff17f4c9b3f..101fed319815346ee54a96bae8f30fd0131a9ffa 100644 (file)
am335x-evm.dtb \
am335x-evmsk.dtb \
am335x-bone.dtb \
- am335x-boneblack.dtb
+ am335x-boneblack.dtb \
+ dra7-evm.dtb
dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
--- /dev/null
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "dra7.dtsi"
+
+/ {
+ model = "TI DRA7";
+ compatible = "ti,dra7-evm", "ti,dra7";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&avs_mpu>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512 MB */
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ tps659038: tps659038@58 {
+ reg = <0x58>;
+ };
+};
+
+/include/ "tps659038.dtsi"
+
+&i2c2 {
+ clock-frequency = <400000>;
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+};
+
+&i2c4 {
+ clock-frequency = <400000>;
+};
+
+&i2c5 {
+ clock-frequency = <400000>;
+};
+
+&avs_mpu {
+ avs-supply = <&smps123_reg>;
+};
+
+&avs_core {
+ avs-supply = <&smps7_reg>;
+};
+
+&avs_gpu {
+ avs-supply = <&smps6_reg>;
+};
+
+&avs_dspeve {
+ avs-supply = <&smps45_reg>;
+};
+
+&avs_iva {
+ avs-supply = <&smps8_reg>;
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
--- /dev/null
@@ -0,0 +1,439 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+ compatible = "ti,dra7xx";
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ serial3 = &uart4;
+ serial4 = &uart5;
+ serial5 = &uart6;
+ };
+
+ cpus {
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ operating-points = <
+ /* kHz uV */
+ /* The OPP_HIGH Only for DVFS enabled Samples Hence commenting*/
+ 1000000 1090000
+ /* 1176000 1210000 */
+ >;
+ clocks = <&dpll_mpu>;
+ clock-names = "cpu";
+ timer {
+ compatible = "arm,armv7-timer";
+ /*
+ * PPI secure/nonsecure IRQ,
+ * active low level-sensitive
+ */
+ interrupts = <1 13 0x308>,
+ <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
+ };
+ cpu@1 {
+ compatible = "arm,cortex-a15";
+ timer {
+ compatible = "arm,armv7-timer";
+ /*
+ * PPI secure/nonsecure IRQ,
+ * active low level-sensitive
+ */
+ interrupts = <1 13 0x308>,
+ <1 14 0x308>;
+ clock-frequency = <6144000>;
+ };
+ };
+ };
+
+ gic: interrupt-controller@48211000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x48211000 0x1000>,
+ <0x48212000 0x1000>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is uses for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap5-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ /*
+ * XXX: Use a flat representation of the SOC interconnect.
+ * The real OMAP interconnect network is quite complex.
+ * Since that will not bring real advantage to represent that in DT for
+ * the moment, just use a fake OCP bus entry to represent the whole bus
+ * hierarchy.
+ */
+ ocp {
+ compatible = "ti,omap4-l3-noc", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main_1", "l3_main_2";
+
+ counter32k: counter@4ae04000 {
+ compatible = "ti,omap-counter32k";
+ reg = <0x4ae04000 0x40>;
+ ti,hwmods = "counter_32k";
+ };
+
+ dra7_pmx_core: pinmux@4a003400 {
+ compatible = "pinctrl-single";
+ reg = <0x4a003400 0x0464>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x3fffffff>;
+ };
+
+ dpll_mpu: dpll_mpu {
+ #clock-cells = <0>;
+ compatible = "ti,omap-clock";
+ };
+
+ gpio1: gpio@4ae10000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4ae10000 0x200>;
+ interrupts = <0 29 0x4>;
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio2: gpio@48055000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48055000 0x200>;
+ interrupts = <0 30 0x4>;
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio3: gpio@48057000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48057000 0x200>;
+ interrupts = <0 31 0x4>;
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio4: gpio@48059000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48059000 0x200>;
+ interrupts = <0 32 0x4>;
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio5: gpio@4805b000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805b000 0x200>;
+ interrupts = <0 33 0x4>;
+ ti,hwmods = "gpio5";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio6: gpio@4805d000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x4805d000 0x200>;
+ interrupts = <0 34 0x4>;
+ ti,hwmods = "gpio6";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio7: gpio@48051000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48051000 0x200>;
+ interrupts = <0 35 0x4>;
+ ti,hwmods = "gpio7";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gpio8: gpio@48053000 {
+ compatible = "ti,omap4-gpio";
+ reg = <0x48053000 0x200>;
+ interrupts = <0 121 0x4>;
+ ti,hwmods = "gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ uart1: serial@4806a000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806a000 0x100>;
+ interrupts = <0 72 0x4>;
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ };
+
+ uart2: serial@4806c000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806c000 0x100>;
+ interrupts = <0 73 0x4>;
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ };
+
+ uart3: serial@48020000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48020000 0x100>;
+ interrupts = <0 74 0x4>;
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ };
+
+ uart4: serial@4806e000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x4806e000 0x100>;
+ interrupts = <0 70 0x4>;
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ };
+
+ uart5: serial@48066000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48066000 0x100>;
+ interrupts = <0 105 0x4>;
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ };
+
+ uart6: serial@48068000 {
+ compatible = "ti,omap4-uart";
+ reg = <0x48068000 0x100>;
+ interrupts = <0 106 0x4>;
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ };
+
+ timer1: timer@4ae18000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4ae18000 0x80>;
+ interrupts = <0 37 0x4>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer@48032000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48032000 0x80>;
+ interrupts = <0 38 0x4>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@48034000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48034000 0x80>;
+ interrupts = <0 39 0x4>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer@48036000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48036000 0x80>;
+ interrupts = <0 40 0x4>;
+ ti,hwmods = "timer4";
+ };
+
+ timer5: timer@48820000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48820000 0x80>;
+ interrupts = <0 41 0x4>;
+ ti,hwmods = "timer5";
+ ti,timer-dsp;
+ };
+
+ timer6: timer@48822000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48822000 0x80>;
+ interrupts = <0 42 0x4>;
+ ti,hwmods = "timer6";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer7: timer@48824000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48824000 0x80>;
+ interrupts = <0 43 0x4>;
+ ti,hwmods = "timer7";
+ ti,timer-dsp;
+ };
+
+ timer8: timer@48826000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48826000 0x80>;
+ interrupts = <0 44 0x4>;
+ ti,hwmods = "timer8";
+ ti,timer-dsp;
+ ti,timer-pwm;
+ };
+
+ timer9: timer@4803e000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x4803e000 0x80>;
+ interrupts = <0 45 0x4>;
+ ti,hwmods = "timer9";
+ };
+
+ timer10: timer@48086000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48086000 0x80>;
+ interrupts = <0 46 0x4>;
+ ti,hwmods = "timer10";
+ };
+
+ timer11: timer@48088000 {
+ compatible = "ti,omap2-timer";
+ reg = <0x48088000 0x80>;
+ interrupts = <0 47 0x4>;
+ ti,hwmods = "timer11";
+ ti,timer-pwm;
+ };
+
+ wdt2: wdt@4ae14000 {
+ compatible = "ti,omap4-wdt";
+ reg = <0x4ae14000 0x80>;
+ interrupts = <0 80 0x4>;
+ ti,hwmods = "wd_timer2";
+ };
+
+ bandgap {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50>;
+ compatible = "ti,dra752-bandgap";
+ interrupts = <0 126 4>; /* talert */
+ };
+
+ i2c1: i2c@48070000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48070000 0x100>;
+ interrupts = <0 56 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ };
+
+ i2c2: i2c@48072000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48072000 0x100>;
+ interrupts = <0 57 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ };
+
+ i2c3: i2c@48060000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x48060000 0x100>;
+ interrupts = <0 61 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ };
+
+ i2c4: i2c@4807a000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807a000 0x100>;
+ interrupts = <0 62 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c4";
+ };
+
+ i2c5: i2c@4807c000 {
+ compatible = "ti,omap4-i2c";
+ reg = <0x4807c000 0x100>;
+ interrupts = <0 60 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c5";
+ };
+
+ avs_mpu: regulator-avs@0x4A003B18 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A003B18 0x20>;
+ efuse-settings = <1090000 8
+ 1210000 12
+ 1280000 16>;
+ };
+
+ avs_core: regulator-avs@0x4A0025EC {
+ compatible = "ti,avsclass0";
+ reg = <0x4A0025EC 0x20>;
+ efuse-settings = <1030000 8>;
+ };
+
+ avs_gpu: regulator-avs@0x4A003B00 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A003B00 0x20>;
+ efuse-settings = <1090000 8
+ 1210000 12
+ 1280000 16>;
+ };
+
+ avs_dspeve: regulator-avs@0x4A0025D8 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A0025D8 0x20>;
+ efuse-settings = <1055000 8
+ 1150000 12
+ 1250000 16>;
+ };
+
+ avs_iva: regulator-avs@0x4A0025C4 {
+ compatible = "ti,avsclass0";
+ reg = <0x4A0025C4 0x20>;
+ efuse-settings = <1055000 8
+ 1150000 12
+ 1250000 16>;
+ };
+
+ };
+};
diff --git a/arch/arm/boot/dts/tps659038.dtsi b/arch/arm/boot/dts/tps659038.dtsi
--- /dev/null
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+
+/*
+ * TPS659038 is an Integrated Power Management Chip from Texas Instruments
+ * Data Manual - TPS659039-Q1 POWER MANAGEMENT UNIT (PMU) FOR PROCESSOR Data Manual
+ * Register Manual - TPS659038/39-Q1 Functional Register Descriptions.
+ */
+
+&tps659038 {
+ compatible = "ti,tps659038";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ tps659038_pmic {
+ compatible = "ti,tps659038-pmic";
+ ti,ldo6_vibrator = <0>;
+ ti,smps10 = <0>;
+
+ regulators {
+ smps123_reg: smps123 {
+ regulator-name = "smps123";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps45_reg: smps45 {
+ regulator-name = "smps45";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps6_reg: smps6 {
+ regulator-name = "smps6";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps7_reg: smps7 {
+ regulator-name = "smps7";
+ regulator-min-microvolt = <1030000>;
+ regulator-max-microvolt = <1030000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps8_reg: smps8 {
+ regulator-name = "smps8";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1310000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ smps9_reg: smps9 {
+ regulator-name = "smps9";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo1_reg: ldo1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo2_reg: ldo2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo3_reg: ldo3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo4_reg: ldo4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo5_reg: ldo5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo6_reg: ldo6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo7_reg: ldo7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo8_reg: ldo8 {
+ regulator-name = "ldo8";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldo9_reg: ldo9 {
+ regulator-name = "ldo9";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldoln_reg: ldoln {
+ regulator-name = "ldoln";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ ldousb_reg: ldousb {
+ regulator-name = "ldousb";
+ regulator-min-microvolt = <3250000>;
+ regulator-max-microvolt = <3250000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
index 6d3a3e6d0549d7aee35d4c849975cfeae0ef2fcd..6558691216c7e4f5430c341b3587348bceaef1f9 100644 (file)
CONFIG_TI_THERMAL=y
CONFIG_OMAP4_THERMAL=y
CONFIG_OMAP5_THERMAL=y
+CONFIG_DRA752_THERMAL=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
CONFIG_CRC_ITU_T=y
CONFIG_CRC7=y
CONFIG_LIBCRC32C=y
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DAVINCI_CPDMA=y
+CONFIG_SOC_DRA7XX=y
index 6cf9c1cc2bef3cf3fa7749d134a0edb64bdf8644..612bd1cc257c147255eb9baefb86ff6d0a6a2497 100644 (file)
#define cpu_is_omap34xx() 0
#define cpu_is_omap44xx() 0
#define soc_is_omap54xx() 0
+#define soc_is_dra7xx() 0
#define soc_is_am33xx() 0
#define cpu_class_is_omap1() 1
#define cpu_class_is_omap2() 0
index 3ceda910e4b98ac1c369fed8c79c4e0d043b428f..ed1b71e10663cf37731410e6e89562e20eac8326 100644 (file)
select I2C
select I2C_OMAP
select MENELAUS if ARCH_OMAP2
- select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5
+ select NEON if CPU_V7
select PM_RUNTIME
select REGULATOR
select SERIAL_OMAP
config SOC_HAS_REALTIME_COUNTER
bool "Real time free running counter"
- depends on SOC_OMAP5
+ depends on SOC_OMAP5 || SOC_DRA7XX
default y
config ARCH_OMAP2
config SOC_OMAP5
bool "TI OMAP5"
select ARCH_HAS_BANDGAP
+ select ARCH_HAS_OPP
select ARM_ARCH_TIMER
select ARM_CPU_SUSPEND if PM
select ARM_GIC
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ARCH_HAS_XHCI if USB_SUPPORT
select ARCH_NEEDS_CPU_IDLE_COUPLED
+ select PM_OPP if PM
+
+config SOC_DRA7XX
+ bool "TI DRA7XX"
+ select ARCH_HAS_BANDGAP
+ select ARM_ARCH_TIMER
+ select CPU_V7
+ select ARM_GIC
+ select HAVE_SMP
+ select COMMON_CLK
comment "OMAP Core Type"
depends on ARCH_OMAP2
index b123e80ad730b9fd7f4abd8f3a0d7740ac42668b..af35320f7bfe332be5e13cd7fa696378a896c28a 100644 (file)
obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
+obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common)
ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
obj-y += mcbsp.o
sleep_omap4plus.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common)
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
obj-$(CONFIG_SOC_OMAP5) += $(omap4plus-common-pm)
obj-$(CONFIG_SOC_AM33XX) += pm33xx.o sleep33xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
+obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
vc44xx_data.o vp44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
+obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
# OMAP voltage domains
voltagedomain-common := voltage.o vc.o vp.o
obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
obj-$(CONFIG_SOC_OMAP5) += voltagedomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(voltagedomain-common)
# OMAP powerdomain framework
powerdomain-common += powerdomain.o powerdomain-common.o
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
+obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
# PRCM clockdomain control
clockdomain-common += clockdomain.o
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
+obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
# Clock framework
obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
obj-$(CONFIG_SOC_AM33XX) += cclock33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += $(clock-common) cclock54xx_data.o
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX) += $(clock-common)
+obj-$(CONFIG_SOC_DRA7XX) += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX) += cclock7xx_data.o
# OMAP2 clock rate set data (old "OPP" data)
obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
# EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o
index 02c55e7b523380e2c3a0a8dbe3346a5ae3df3a6f..d60b2059954e3b56ba772cba5638655e9c6312d9 100644 (file)
.restart = omap44xx_restart,
MACHINE_END
#endif
+
+#ifdef CONFIG_SOC_DRA7XX
+static const char *dra7xx_boards_compat[] __initdata = {
+ "ti,dra7",
+ NULL,
+};
+
+DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
+ .reserve = omap_reserve,
+ .smp = smp_ops(omap4_smp_ops),
+ .map_io = omap5_map_io,
+ .init_early = dra7xx_init_early,
+ .init_irq = omap_gic_of_init,
+ .handle_irq = gic_handle_irq,
+ .init_machine = omap_generic_init,
+ .init_late = dra7xx_init_late,
+ .timer = &omap5_timer,
+ .dt_compat = dra7xx_boards_compat,
+ .restart = omap44xx_restart,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-omap2/cclock7xx_data.c b/arch/arm/mach-omap2/cclock7xx_data.c
--- /dev/null
@@ -0,0 +1,2149 @@
+/*
+ * DRA7xx Clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Mike Turquette (mturquette@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX Some of the ES1 clocks have been removed/changed; once support
+ * is added for discriminating clocks by ES level, these should be added back
+ * in.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/clk-private.h>
+#include <linux/clkdev.h>
+#include <linux/io.h>
+
+#include "soc.h"
+#include "iomap.h"
+#include "clock.h"
+#include "clock7xx.h"
+#include "cm1_7xx.h"
+#include "cm2_7xx.h"
+#include "cm-regbits-7xx.h"
+#include "prm7xx.h"
+#include "prm-regbits-7xx.h"
+#include "control.h"
+
+#define DRA7_DPLL_ABE_DEFFREQ 361267200
+#define DRA7_DPLL_GMAC_DEFFREQ 1000000000
+
+/* Root clocks */
+
+DEFINE_CLK_FIXED_RATE(atl_clkin0_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(atl_clkin1_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(atl_clkin2_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(atlclkin3_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(hdmi_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mlb_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(mlbp_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(pciesref_acs_clk_ck, CLK_IS_ROOT, 100000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin0_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin1_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin2_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(ref_clkin3_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(rmii_clk_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(sdvenc_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_20000000_ck, CLK_IS_ROOT, 20000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
+
+DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
+
+static const struct clksel_rate div_1_8_rates[] = {
+ { .div = 1, .val = 8, .flags = RATE_IN_7XX },
+ { .div = 0 },
+};
+
+
+static const char *sys_clkin1_parents[] = {
+ "virt_12000000_ck", "virt_20000000_ck",
+ "virt_16800000_ck", "virt_19200000_ck", "virt_26000000_ck",
+ "virt_27000000_ck", "virt_38400000_ck",
+};
+
+DEFINE_CLK_MUX(sys_clkin1, sys_clkin1_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_SYS,
+ DRA7XX_SYS_CLKSEL_SHIFT, DRA7XX_SYS_CLKSEL_WIDTH,
+ CLK_MUX_INDEX_ONE, NULL);
+
+
+DEFINE_CLK_FIXED_RATE(sys_clkin2, CLK_IS_ROOT, 22579200, 0x0);
+
+DEFINE_CLK_FIXED_RATE(usb_otg_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video1_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video1_m2_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video2_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+DEFINE_CLK_FIXED_RATE(video2_m2_clkin_ck, CLK_IS_ROOT, 0, 0x0);
+
+/* Module clocks and DPLL outputs */
+
+static const char *abe_dpll_sys_clk_mux_parents[] = {
+ "sys_clkin1", "sys_clkin2",
+};
+
+DEFINE_CLK_MUX(abe_dpll_sys_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_PLL_SYS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *abe_dpll_bypass_clk_mux_parents[] = {
+ "abe_dpll_sys_clk_mux", "sys_32k_ck",
+};
+
+DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL,
+ 0x0, DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(abe_dpll_clk_mux, abe_dpll_bypass_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_PLL_REF, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+/* DPLL_ABE */
+static struct dpll_data dpll_abe_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_ABE,
+ .clk_bypass = &abe_dpll_bypass_clk_mux,
+ .clk_ref = &abe_dpll_clk_mux,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_ABE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_ABE,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_ABE,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .m4xen_mask = DRA7XX_DPLL_REGM4XEN_MASK,
+ .lpmode_mask = DRA7XX_DPLL_LPMODE_EN_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_abe_ck_parents[] = {
+ "abe_dpll_clk_mux", "abe_dpll_bypass_clk_mux"
+};
+
+static struct clk dpll_abe_ck;
+
+static const struct clk_ops dpll_abe_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap4_dpll_regm4xen_recalc,
+ .round_rate = &omap4_dpll_regm4xen_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_abe_ck_hw = {
+ .hw = {
+ .clk = &dpll_abe_ck,
+ },
+ .dpll_data = &dpll_abe_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
+
+static const char *dpll_abe_x2_ck_parents[] = {
+ "dpll_abe_ck",
+};
+
+static struct clk dpll_abe_x2_ck;
+
+static const struct clk_ops dpll_abe_x2_ck_ops = {
+ .recalc_rate = &omap3_clkoutx2_recalc,
+};
+
+static struct clk_hw_omap dpll_abe_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_abe_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+static const struct clk_ops omap_hsdivider_ops = {
+ .set_rate = &omap2_clksel_set_rate,
+ .recalc_rate = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+};
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M2_DPLL_ABE, DRA7XX_DIVHS_MASK);
+
+static const struct clk_div_table abe_24m_fclk_rates[] = {
+ { .div = 8, .val = 0 },
+ { .div = 16, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_ABE_24M, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, abe_24m_fclk_rates,
+ NULL);
+
+DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_ABE, DRA7XX_CLKSEL_OPP_SHIFT,
+ DRA7XX_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
+ DRA7XX_CM_CLKSEL_AESS_FCLK_DIV, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(abe_giclk_div, "aess_fclk", &aess_fclk, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_GICLK_DIV, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const struct clk_div_table abe_lp_clk_div_rates[] = {
+ { .div = 16, .val = 0 },
+ { .div = 32, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(abe_lp_clk_div, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_ABE_LP_CLK,
+ DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0,
+ abe_lp_clk_div_rates, NULL);
+
+DEFINE_CLK_DIVIDER(abe_sys_clk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_ABE_SYS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *adc_gfclk_mux_parents[] = {
+ "sys_clkin1", "sys_clkin2", "sys_32k_ck",
+};
+
+DEFINE_CLK_MUX(adc_gfclk_mux, adc_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_ADC_GFCLK, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+/* DPLL_PCIE_REF */
+static struct dpll_data dpll_pcie_ref_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PCIE_REF,
+ .clk_bypass = &sys_clkin1,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_PCIE_REF,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PCIE_REF,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+};
+
+static const char *dpll_pcie_ref_ck_parents[] = {
+ "sys_clkin1",
+};
+
+static struct clk dpll_pcie_ref_ck;
+
+static const struct clk_ops dpll_pcie_ref_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_pcie_ref_ck_hw = {
+ .hw = {
+ .clk = &dpll_pcie_ref_ck,
+ },
+ .dpll_data = &dpll_pcie_ref_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_pcie_ref_ck, dpll_pcie_ref_ck_parents,
+ dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_pcie_ref_m2ldo_ck, "dpll_pcie_ref_ck",
+ &dpll_pcie_ref_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_PCIE_REF,
+ DRA7XX_DIVHS_MASK);
+
+/* APLL_PCIE */
+static struct dpll_data apll_pcie_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PCIE_REF,
+ .clk_bypass = &dpll_pcie_ref_ck,
+ .clk_ref = &dpll_pcie_ref_ck,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_PCIE_REF,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PCIE_REF,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = -1,
+ .max_divider = 0,
+ .min_divider = 1,
+};
+
+static const char *apll_pcie_ck_parents[] = {
+ "BUGGED",
+};
+
+static struct clk apll_pcie_ck;
+
+static struct clk_hw_omap apll_pcie_ck_hw = {
+ .hw = {
+ .clk = &apll_pcie_ck,
+ },
+ .dpll_data = &apll_pcie_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(apll_pcie_ck, apll_pcie_ck_parents, dpll_pcie_ref_ck_ops);
+
+static const char *apll_pcie_clkvcoldo_parents[] = {
+ "apll_pcie_ck",
+};
+
+static struct clk apll_pcie_clkvcoldo;
+
+static const struct clk_ops apll_pcie_clkvcoldo_ops = {
+};
+
+static struct clk_hw_omap apll_pcie_clkvcoldo_hw = {
+ .hw = {
+ .clk = &apll_pcie_clkvcoldo,
+ },
+ .clksel_reg = DRA7XX_CM_CLKVCOLDO_APLL_PCIE,
+};
+
+DEFINE_STRUCT_CLK(apll_pcie_clkvcoldo, apll_pcie_clkvcoldo_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk apll_pcie_clkvcoldo_div;
+
+static struct clk_hw_omap apll_pcie_clkvcoldo_div_hw = {
+ .hw = {
+ .clk = &apll_pcie_clkvcoldo_div,
+ },
+ .clksel_reg = DRA7XX_CM_CLKVCOLDO_APLL_PCIE,
+};
+
+DEFINE_STRUCT_CLK(apll_pcie_clkvcoldo_div, apll_pcie_clkvcoldo_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(apll_pcie_m2_ck, "apll_pcie_ck", &apll_pcie_ck, 0x0,
+ DRA7XX_CM_DIV_M2_APLL_PCIE, DRA7XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_DIVIDER(sys_clk1_dclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(sys_clk2_dclk_div, "sys_clkin2", &sys_clkin2, 0x0,
+ DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_ABE, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(per_abe_x1_dclk_div, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M3_DPLL_ABE, DRA7XX_DIVHS_MASK);
+
+/* DPLL_CORE */
+static struct dpll_data dpll_core_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_CORE,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_CORE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_CORE,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_CORE,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_core_ck_parents[] = {
+ "sys_clkin1", "dpll_abe_m3x2_ck"
+};
+
+static struct clk dpll_core_ck;
+
+static const struct clk_ops dpll_core_ck_ops = {
+ .recalc_rate = &omap3_dpll_recalc,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_core_ck_hw = {
+ .hw = {
+ .clk = &dpll_core_ck,
+ },
+ .dpll_data = &dpll_core_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
+
+static const char *dpll_core_x2_ck_parents[] = {
+ "dpll_core_ck",
+};
+
+static struct clk dpll_core_x2_ck;
+
+static struct clk_hw_omap dpll_core_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_core_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h12x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+static const char *mpu_dpll_hs_clk_div_parents[] = {
+ "dpll_core_h12x2_ck",
+};
+
+static struct clk mpu_dpll_hs_clk_div;
+
+static struct clk_hw_omap mpu_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &mpu_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(mpu_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_MPU */
+static struct dpll_data dpll_mpu_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_MPU,
+ .clk_bypass = &mpu_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_MPU,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_MPU,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_MPU,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_mpu_ck_parents[] = {
+ "sys_clkin1", "mpu_dpll_hs_clk_div"
+};
+
+static struct clk dpll_mpu_ck;
+
+static const struct clk_ops dpll_mpu_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap5_mpu_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+};
+
+static struct clk_hw_omap dpll_mpu_ck_hw = {
+ .hw = {
+ .clk = &dpll_mpu_ck,
+ },
+ .dpll_data = &dpll_mpu_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_mpu_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_MPU, DRA7XX_DIVHS_MASK);
+
+static const char *mpu_dclk_div_parents[] = {
+ "dpll_mpu_m2_ck",
+};
+
+static struct clk mpu_dclk_div;
+
+static struct clk_hw_omap mpu_dclk_div_hw = {
+ .hw = {
+ .clk = &mpu_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(mpu_dclk_div, mpu_dclk_div_parents, apll_pcie_clkvcoldo_ops);
+
+static struct clk dsp_dpll_hs_clk_div;
+
+static struct clk_hw_omap dsp_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &dsp_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(dsp_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_DSP */
+static struct dpll_data dpll_dsp_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_DSP,
+ .clk_bypass = &dsp_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_DSP,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_DSP,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_DSP,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_dsp_ck_parents[] = {
+ "sys_clkin1", "dsp_dpll_hs_clk_div"
+};
+
+static struct clk dpll_dsp_ck;
+
+static struct clk_hw_omap dpll_dsp_ck_hw = {
+ .hw = {
+ .clk = &dpll_dsp_ck,
+ },
+ .dpll_data = &dpll_dsp_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_dsp_ck, dpll_dsp_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_dsp_m2_ck, "dpll_dsp_ck", &dpll_dsp_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_DSP, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(dsp_gclk_div, "dpll_dsp_m2_ck", &dpll_dsp_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk iva_dpll_hs_clk_div;
+
+static struct clk_hw_omap iva_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &iva_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(iva_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_IVA */
+static struct dpll_data dpll_iva_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_IVA,
+ .clk_bypass = &iva_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_IVA,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_IVA,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_IVA,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_iva_ck_parents[] = {
+ "sys_clkin1", "iva_dpll_hs_clk_div"
+};
+
+static struct clk dpll_iva_ck;
+
+static struct clk_hw_omap dpll_iva_ck_hw = {
+ .hw = {
+ .clk = &dpll_iva_ck,
+ },
+ .dpll_data = &dpll_iva_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_iva_m2_ck, "dpll_iva_ck", &dpll_iva_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_IVA, DRA7XX_DIVHS_MASK);
+
+static const char *iva_dclk_parents[] = {
+ "dpll_iva_m2_ck",
+};
+
+static struct clk iva_dclk;
+
+static struct clk_hw_omap iva_dclk_hw = {
+ .hw = {
+ .clk = &iva_dclk,
+ },
+};
+
+DEFINE_STRUCT_CLK(iva_dclk, iva_dclk_parents, apll_pcie_clkvcoldo_ops);
+
+/* DPLL_GPU */
+static struct dpll_data dpll_gpu_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_GPU,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_GPU,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_GPU,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_GPU,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static struct clk dpll_gpu_ck;
+
+static struct clk_hw_omap dpll_gpu_ck_hw = {
+ .hw = {
+ .clk = &dpll_gpu_ck,
+ },
+ .dpll_data = &dpll_gpu_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_gpu_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gpu_m2_ck, "dpll_gpu_ck", &dpll_gpu_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_GPU, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(gpu_dclk, "dpll_gpu_m2_ck", &dpll_gpu_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_CORE, DRA7XX_DIVHS_MASK);
+
+static const char *core_dpll_out_dclk_div_parents[] = {
+ "dpll_core_m2_ck",
+};
+
+static struct clk core_dpll_out_dclk_div;
+
+static struct clk_hw_omap core_dpll_out_dclk_div_hw = {
+ .hw = {
+ .clk = &core_dpll_out_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(core_dpll_out_dclk_div, core_dpll_out_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_DDR */
+static struct dpll_data dpll_ddr_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_DDR,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_DDR,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_DDR,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_DDR,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static struct clk dpll_ddr_ck;
+
+static struct clk_hw_omap dpll_ddr_ck_hw = {
+ .hw = {
+ .clk = &dpll_ddr_ck,
+ },
+ .dpll_data = &dpll_ddr_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_DDR, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(emif_phy_dclk_div, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+/* DPLL_GMAC */
+static struct dpll_data dpll_gmac_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_GMAC,
+ .clk_bypass = &dpll_abe_m3x2_ck,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_GMAC,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_GMAC,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_GMAC,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static struct clk dpll_gmac_ck;
+
+static struct clk_hw_omap dpll_gmac_ck_hw = {
+ .hw = {
+ .clk = &dpll_gmac_ck,
+ },
+ .dpll_data = &dpll_gmac_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_gmac_ck, dpll_core_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_m2_ck, "dpll_gmac_ck", &dpll_gmac_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_GMAC, DRA7XX_DIVHS_MASK);
+
+DEFINE_CLK_DIVIDER(gmac_250m_dclk_div, "dpll_gmac_m2_ck", &dpll_gmac_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static const char *video2_dclk_div_parents[] = {
+ "video2_m2_clkin",
+};
+
+static struct clk video2_dclk_div;
+
+static struct clk_hw_omap video2_dclk_div_hw = {
+ .hw = {
+ .clk = &video2_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video2_dclk_div, video2_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const char *video1_dclk_div_parents[] = {
+ "video1_m2_clkin",
+};
+
+static struct clk video1_dclk_div;
+
+static struct clk_hw_omap video1_dclk_div_hw = {
+ .hw = {
+ .clk = &video1_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video1_dclk_div, video1_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const char *hdmi_dclk_div_parents[] = {
+ "hdmi_clkin",
+};
+
+static struct clk hdmi_dclk_div;
+
+static struct clk_hw_omap hdmi_dclk_div_hw = {
+ .hw = {
+ .clk = &hdmi_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(hdmi_dclk_div, hdmi_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_FIXED_FACTOR(per_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
+ &dpll_abe_m3x2_ck, 0x0, 1, 2);
+
+/* DPLL_PER */
+static struct dpll_data dpll_per_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_PER,
+ .clk_bypass = &per_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_PER,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_PER,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_PER,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_per_ck_parents[] = {
+ "sys_clkin1", "per_dpll_hs_clk_div"
+};
+
+static struct clk dpll_per_ck;
+
+static struct clk_hw_omap dpll_per_ck_hw = {
+ .hw = {
+ .clk = &dpll_per_ck,
+ },
+ .dpll_data = &dpll_per_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_PER, DRA7XX_DIVHS_MASK);
+
+static const char *func_96m_aon_dclk_div_parents[] = {
+ "dpll_per_m2_ck",
+};
+
+static struct clk func_96m_aon_dclk_div;
+
+static struct clk_hw_omap func_96m_aon_dclk_div_hw = {
+ .hw = {
+ .clk = &func_96m_aon_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(func_96m_aon_dclk_div, func_96m_aon_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_FIXED_FACTOR(usb_dpll_hs_clk_div, "dpll_abe_m3x2_ck",
+ &dpll_abe_m3x2_ck, 0x0, 1, 3);
+
+/* DPLL_USB */
+static struct dpll_data dpll_usb_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_USB,
+ .clk_bypass = &usb_dpll_hs_clk_div,
+ .flags = DPLL_J_TYPE,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_USB,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_USB,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_USB,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .sddiv_mask = DRA7XX_DPLL_SD_DIV_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
+ .min_divider = 1,
+};
+
+static const char *dpll_usb_ck_parents[] = {
+ "sys_clkin1", "usb_dpll_hs_clk_div"
+};
+
+static struct clk dpll_usb_ck;
+
+static const struct clk_ops dpll_usb_ck_ops = {
+ .enable = &omap3_noncore_dpll_enable,
+ .disable = &omap3_noncore_dpll_disable,
+ .recalc_rate = &omap3_dpll_recalc,
+ .round_rate = &omap2_dpll_round_rate,
+ .set_rate = &omap3_noncore_dpll_set_rate,
+ .get_parent = &omap2_init_dpll_parent,
+ .init = &omap2_init_clk_clkdm,
+};
+
+static struct clk_hw_omap dpll_usb_ck_hw = {
+ .hw = {
+ .clk = &dpll_usb_ck,
+ },
+ .dpll_data = &dpll_usb_dd,
+ .clkdm_name = "coreaon_clkdm",
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_USB, DRA7XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_DIVIDER(l3init_480m_dclk_div, "dpll_usb_m2_ck", &dpll_usb_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(usb_otg_dclk_div, "usb_otg_clkin_ck", &usb_otg_clkin_ck, 0x0,
+ DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(sata_dclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_pcie_ref_m2_ck, "dpll_pcie_ref_ck",
+ &dpll_pcie_ref_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_PCIE_REF,
+ DRA7XX_DIVHS_0_6_MASK);
+
+DEFINE_CLK_DIVIDER(pcie2_dclk_div, "dpll_pcie_ref_m2_ck", &dpll_pcie_ref_m2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(pcie_dclk_div, "apll_pcie_m2_ck", &apll_pcie_m2_ck, 0x0,
+ DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(emu_dclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(secure_32k_dclk_div, "secure_32k_clk_src_ck",
+ &secure_32k_clk_src_ck, 0x0,
+ DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static struct clk eve_dpll_hs_clk_div;
+
+static struct clk_hw_omap eve_dpll_hs_clk_div_hw = {
+ .hw = {
+ .clk = &eve_dpll_hs_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(eve_dpll_hs_clk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+/* DPLL_EVE */
+static struct dpll_data dpll_eve_dd = {
+ .mult_div1_reg = DRA7XX_CM_CLKSEL_DPLL_EVE,
+ .clk_bypass = &eve_dpll_hs_clk_div,
+ .clk_ref = &sys_clkin1,
+ .control_reg = DRA7XX_CM_CLKMODE_DPLL_EVE,
+ .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
+ .autoidle_reg = DRA7XX_CM_AUTOIDLE_DPLL_EVE,
+ .idlest_reg = DRA7XX_CM_IDLEST_DPLL_EVE,
+ .mult_mask = DRA7XX_DPLL_MULT_MASK,
+ .div1_mask = DRA7XX_DPLL_DIV_MASK,
+ .enable_mask = DRA7XX_DPLL_EN_MASK,
+ .autoidle_mask = DRA7XX_AUTO_DPLL_MODE_MASK,
+ .idlest_mask = DRA7XX_ST_DPLL_CLK_MASK,
+ .max_multiplier = 2047,
+ .max_divider = 128,
+ .min_divider = 1,
+};
+
+static const char *dpll_eve_ck_parents[] = {
+ "sys_clkin1", "eve_dpll_hs_clk_div"
+};
+
+static struct clk dpll_eve_ck;
+
+static struct clk_hw_omap dpll_eve_ck_hw = {
+ .hw = {
+ .clk = &dpll_eve_ck,
+ },
+ .dpll_data = &dpll_eve_dd,
+ .ops = &clkhwops_omap3_dpll,
+};
+
+DEFINE_STRUCT_CLK(dpll_eve_ck, dpll_eve_ck_parents, dpll_pcie_ref_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_eve_m2_ck, "dpll_eve_ck", &dpll_eve_ck, 0x0,
+ DRA7XX_CM_DIV_M2_DPLL_EVE, DRA7XX_DIVHS_MASK);
+
+static const char *eve_dclk_div_parents[] = {
+ "dpll_eve_m2_ck",
+};
+
+static struct clk eve_dclk_div;
+
+static struct clk_hw_omap eve_dclk_div_hw = {
+ .hw = {
+ .clk = &eve_dclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(eve_dclk_div, eve_dclk_div_parents, apll_pcie_clkvcoldo_ops);
+
+static const char *clkoutmux0_clk_mux_parents[] = {
+ "sys_clk1_dclk_div", "sys_clk2_dclk_div", "per_abe_x1_dclk_div",
+ "mpu_dclk_div", "dsp_gclk_div", "iva_dclk",
+ "gpu_dclk", "core_dpll_out_dclk_div", "emif_phy_dclk_div",
+ "gmac_250m_dclk_div", "video2_dclk_div", "video1_dclk_div",
+ "hdmi_dclk_div", "func_96m_aon_dclk_div", "l3init_480m_dclk_div",
+ "usb_otg_dclk_div", "sata_dclk_div", "pcie2_dclk_div",
+ "pcie_dclk_div", "emu_dclk_div", "secure_32k_dclk_div",
+ "eve_dclk_div",
+};
+
+DEFINE_CLK_MUX(clkoutmux0_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_CLKOUTMUX0, DRA7XX_CLKSEL_0_4_SHIFT,
+ DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(clkoutmux1_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_CLKOUTMUX1, DRA7XX_CLKSEL_0_4_SHIFT,
+ DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(clkoutmux2_clk_mux, clkoutmux0_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_CLKOUTMUX2, DRA7XX_CLKSEL_0_4_SHIFT,
+ DRA7XX_CLKSEL_0_4_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_FIXED_FACTOR(custefuse_sys_gfclk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ 1, 2);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h13x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h14x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H14_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h22x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H22_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h23x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H23_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_core_h24x2_ck, "dpll_core_x2_ck",
+ &dpll_core_x2_ck, 0x0, DRA7XX_CM_DIV_H24_DPLL_CORE,
+ DRA7XX_DIVHS_0_5_MASK);
+
+static const char *dpll_ddr_x2_ck_parents[] = {
+ "dpll_ddr_ck",
+};
+
+static struct clk dpll_ddr_x2_ck;
+
+static struct clk_hw_omap dpll_ddr_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_ddr_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_ddr_x2_ck, dpll_ddr_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_ddr_h11x2_ck, "dpll_ddr_x2_ck",
+ &dpll_ddr_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_DDR,
+ DRA7XX_DIVHS_0_5_MASK);
+
+static const char *dpll_dsp_x2_ck_parents[] = {
+ "dpll_dsp_ck",
+};
+
+static struct clk dpll_dsp_x2_ck;
+
+static struct clk_hw_omap dpll_dsp_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_dsp_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_dsp_x2_ck, dpll_dsp_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_dsp_m3x2_ck, "dpll_dsp_x2_ck", &dpll_dsp_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M3_DPLL_DSP, DRA7XX_DIVHS_MASK);
+
+static const char *dpll_gmac_x2_ck_parents[] = {
+ "dpll_gmac_ck",
+};
+
+static struct clk dpll_gmac_x2_ck;
+
+static struct clk_hw_omap dpll_gmac_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_gmac_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_gmac_x2_ck, dpll_gmac_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h11x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_GMAC,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h12x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_GMAC,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_h13x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_GMAC,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_gmac_m3x2_ck, "dpll_gmac_x2_ck",
+ &dpll_gmac_x2_ck, 0x0, DRA7XX_CM_DIV_M3_DPLL_GMAC,
+ DRA7XX_DIVHS_MASK);
+
+static const char *dpll_per_x2_ck_parents[] = {
+ "dpll_per_ck",
+};
+
+static struct clk dpll_per_x2_ck;
+
+static struct clk_hw_omap dpll_per_x2_ck_hw = {
+ .hw = {
+ .clk = &dpll_per_x2_ck,
+ },
+};
+
+DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h11x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H11_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h12x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H12_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h13x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H13_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_h14x2_ck, "dpll_per_x2_ck",
+ &dpll_per_x2_ck, 0x0, DRA7XX_CM_DIV_H14_DPLL_PER,
+ DRA7XX_DIVHS_0_5_MASK);
+
+DEFINE_CLK_OMAP_HSDIVIDER63(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
+ 0x0, DRA7XX_CM_DIV_M2_DPLL_PER, DRA7XX_DIVHS_MASK);
+
+static const char *dpll_usb_clkdcoldo_parents[] = {
+ "dpll_usb_ck",
+};
+
+static struct clk dpll_usb_clkdcoldo;
+
+static struct clk_hw_omap dpll_usb_clkdcoldo_hw = {
+ .hw = {
+ .clk = &dpll_usb_clkdcoldo,
+ },
+ .clksel_reg = DRA7XX_CM_CLKDCOLDO_DPLL_USB,
+};
+
+DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo, dpll_usb_clkdcoldo_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const char *eve_clk_parents[] = {
+ "dpll_eve_m2_ck", "dpll_dsp_m3x2_ck",
+};
+
+DEFINE_CLK_MUX(eve_clk, eve_clk_parents, NULL, 0x0, DRA7XX_CM_CLKSEL_EVE_CLK,
+ DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_FIXED_FACTOR(func_128m_clk, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck,
+ 0x0, 1, 2);
+
+DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 16);
+
+DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
+ 4);
+
+DEFINE_CLK_FIXED_FACTOR(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 4);
+
+DEFINE_CLK_FIXED_FACTOR(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
+ 0x0, 1, 2);
+
+DEFINE_CLK_FIXED_FACTOR(gmii_m_clk_div, "dpll_gmac_h11x2_ck",
+ &dpll_gmac_h11x2_ck, 0x0, 1, 2);
+
+static struct clk hdmi_clk2_div;
+
+static struct clk_hw_omap hdmi_clk2_div_hw = {
+ .hw = {
+ .clk = &hdmi_clk2_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(hdmi_clk2_div, hdmi_dclk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk hdmi_div_clk;
+
+static struct clk_hw_omap hdmi_div_clk_hw = {
+ .hw = {
+ .clk = &hdmi_div_clk,
+ },
+};
+
+DEFINE_STRUCT_CLK(hdmi_div_clk, hdmi_dclk_div_parents, apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_MUX(hdmi_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static struct clk l3_iclk_div;
+
+static struct clk_hw_omap l3_iclk_div_hw = {
+ .hw = {
+ .clk = &l3_iclk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(l3_iclk_div, mpu_dpll_hs_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static const struct clk_div_table l3init_60m_fclk_rates[] = {
+ { .div = 1, .val = 0 },
+ { .div = 8, .val = 1 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(l3init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_USB_60MHZ,
+ DRA7XX_CLKSEL_0_0_SHIFT, DRA7XX_CLKSEL_0_0_WIDTH, 0x0,
+ l3init_60m_fclk_rates, NULL);
+
+static const char *l4_root_clk_div_parents[] = {
+ "l3_iclk_div",
+};
+
+static struct clk l4_root_clk_div;
+
+static struct clk_hw_omap l4_root_clk_div_hw = {
+ .hw = {
+ .clk = &l4_root_clk_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(l4_root_clk_div, l4_root_clk_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_DIVIDER(mlb_clk, "mlb_clkin_ck", &mlb_clkin_ck, 0x0,
+ DRA7XX_CM_CLKSEL_MLB_MCASP, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(mlbp_clk, "mlbp_clkin_ck", &mlbp_clkin_ck, 0x0,
+ DRA7XX_CM_CLKSEL_MLBP_MCASP, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(per_abe_x1_gfclk2_div, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
+ 0x0, DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,
+ DRA7XX_CLKSEL_SHIFT, DRA7XX_CLKSEL_WIDTH,
+ CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_DIVIDER(timer_sys_clk_div, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_CLKSEL_TIMER_SYS, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+static const char *video1_clk2_div_parents[] = {
+ "video1_clkin",
+};
+
+static struct clk video1_clk2_div;
+
+static struct clk_hw_omap video1_clk2_div_hw = {
+ .hw = {
+ .clk = &video1_clk2_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video1_clk2_div, video1_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk video1_div_clk;
+
+static struct clk_hw_omap video1_div_clk_hw = {
+ .hw = {
+ .clk = &video1_div_clk,
+ },
+};
+
+DEFINE_STRUCT_CLK(video1_div_clk, video1_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_MUX(video1_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static const char *video2_clk2_div_parents[] = {
+ "video2_clkin",
+};
+
+static struct clk video2_clk2_div;
+
+static struct clk_hw_omap video2_clk2_div_hw = {
+ .hw = {
+ .clk = &video2_clk2_div,
+ },
+};
+
+DEFINE_STRUCT_CLK(video2_clk2_div, video2_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+static struct clk video2_div_clk;
+
+static struct clk_hw_omap video2_div_clk_hw = {
+ .hw = {
+ .clk = &video2_div_clk,
+ },
+};
+
+DEFINE_STRUCT_CLK(video2_div_clk, video2_clk2_div_parents,
+ apll_pcie_clkvcoldo_ops);
+
+DEFINE_CLK_MUX(video2_dpll_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX, DRA7XX_CLKSEL_SHIFT,
+ DRA7XX_CLKSEL_WIDTH, 0x0, NULL);
+
+static const char *wkupaon_iclk_mux_parents[] = {
+ "sys_clkin1", "abe_lp_clk_div",
+};
+
+DEFINE_CLK_MUX(wkupaon_iclk_mux, wkupaon_iclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CLKSEL_WKUPAON, DRA7XX_CLKSEL_0_0_SHIFT,
+ DRA7XX_CLKSEL_0_0_WIDTH, 0x0, NULL);
+
+/* Leaf clocks controlled by modules */
+
+DEFINE_CLK_GATE(dss_32khz_clk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_32KHZ_CLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(dss_48mhz_clk, "func_48m_fclk", &func_48m_fclk, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_48MHZ_CLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_DSSCLK_SHIFT, 0x0,
+ NULL);
+
+DEFINE_CLK_GATE(dss_hdmi_clk, "hdmi_dpll_clk_mux", &hdmi_dpll_clk_mux, 0x0,
+ DRA7XX_CM_DSS_DSS_CLKCTRL, DRA7XX_OPTFCLKEN_HDMI_CLK_SHIFT, 0x0,
+ NULL);
+
+DEFINE_CLK_GATE(dss_video1_clk, "video1_dpll_clk_mux", &video1_dpll_clk_mux,
+ 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL,
+ DRA7XX_OPTFCLKEN_VIDEO1_CLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(dss_video2_clk, "video2_dpll_clk_mux", &video2_dpll_clk_mux,
+ 0x0, DRA7XX_CM_DSS_DSS_CLKCTRL,
+ DRA7XX_OPTFCLKEN_VIDEO2_CLK_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO2_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO3_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO4_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO5_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO6_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio7_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO7_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(gpio8_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_GPIO8_CLKCTRL, DRA7XX_OPTFCLKEN_DBCLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc1_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc2_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc3_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(mmc4_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_OPTFCLKEN_CLK32K_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(sata_ref_clk, "sys_clkin1", &sys_clkin1, 0x0,
+ DRA7XX_CM_L3INIT_SATA_CLKCTRL, DRA7XX_OPTFCLKEN_REF_CLK_SHIFT,
+ 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_otg_ss1_refclk960m, "dpll_usb_clkdcoldo",
+ &dpll_usb_clkdcoldo, 0x0, DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL,
+ DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_otg_ss2_refclk960m, "dpll_usb_clkdcoldo",
+ &dpll_usb_clkdcoldo, 0x0, DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL,
+ DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_phy1_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL,
+ DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_phy2_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL,
+ DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+
+DEFINE_CLK_GATE(usb_phy3_always_on_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
+ DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL,
+ DRA7XX_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
+
+/* Remaining optional clocks */
+static const char *atl_dpll_clk_mux_parents[] = {
+ "sys_32k_ck", "video1_clkin", "video2_clkin",
+ "hdmi_clkin",
+};
+
+DEFINE_CLK_MUX(atl_dpll_clk_mux, atl_dpll_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_ATL_ATL_CLKCTRL, DRA7XX_CLKSEL_SOURCE1_SHIFT,
+ DRA7XX_CLKSEL_SOURCE1_WIDTH, 0x0, NULL);
+
+static const char *atl_gfclk_mux_parents[] = {
+ "l3_iclk_div", "dpll_abe_m2_ck", "atl_dpll_clk_mux",
+};
+
+DEFINE_CLK_MUX(atl_gfclk_mux, atl_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_ATL_ATL_CLKCTRL, DRA7XX_CLKSEL_SOURCE2_SHIFT,
+ DRA7XX_CLKSEL_SOURCE2_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(dcan1_sys_clk_mux, abe_dpll_sys_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+static const struct clk_div_table gmac_gmii_ref_clk_div_rates[] = {
+ { .div = 2, .val = 0 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(gmac_gmii_ref_clk_div, "dpll_gmac_m2_ck",
+ &dpll_gmac_m2_ck, 0x0, DRA7XX_CM_GMAC_GMAC_CLKCTRL,
+ DRA7XX_CLKSEL_REF_SHIFT, DRA7XX_CLKSEL_REF_WIDTH, 0x0,
+ gmac_gmii_ref_clk_div_rates, NULL);
+
+static const char *gmac_rft_clk_mux_parents[] = {
+ "video1_clkin", "video2_clkin", "dpll_abe_m2_ck",
+ "hdmi_clkin", "l3_iclk_div",
+};
+
+DEFINE_CLK_MUX(gmac_rft_clk_mux, gmac_rft_clk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_GMAC_GMAC_CLKCTRL, DRA7XX_CLKSEL_RFT_SHIFT,
+ DRA7XX_CLKSEL_RFT_WIDTH, 0x0, NULL);
+
+static const char *gpu_core_gclk_mux_parents[] = {
+ "dpll_core_h14x2_ck", "dpll_per_h14x2_ck", "dpll_gpu_m2_ck",
+};
+
+DEFINE_CLK_MUX(gpu_core_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_CORE_CLK_SHIFT,
+ DRA7XX_CLKSEL_CORE_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(gpu_hyd_gclk_mux, gpu_core_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_GPU_GPU_CLKCTRL, DRA7XX_CLKSEL_HYD_CLK_SHIFT,
+ DRA7XX_CLKSEL_HYD_CLK_WIDTH, 0x0, NULL);
+
+static const char *ipu1_gfclk_mux_parents[] = {
+ "dpll_abe_m2x2_ck", "dpll_core_h22x2_ck",
+};
+
+DEFINE_CLK_MUX(ipu1_gfclk_mux, ipu1_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU1_IPU1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+static const struct clk_div_table l3instr_ts_gclk_div_rates[] = {
+ { .div = 8, .val = 0 },
+ { .div = 16, .val = 1 },
+ { .div = 32, .val = 2 },
+ { .div = 0 },
+};
+DEFINE_CLK_DIVIDER_TABLE(l3instr_ts_gclk_div, "wkupaon_iclk_mux",
+ &wkupaon_iclk_mux, 0x0,
+ DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ DRA7XX_CLKSEL_24_25_SHIFT, DRA7XX_CLKSEL_24_25_WIDTH,
+ 0x0, l3instr_ts_gclk_div_rates, NULL);
+
+static const char *mcasp1_ahclkr_mux_parents[] = {
+ "abe_24m_fclk", "abe_sys_clk_div", "func_24m_clk",
+ "atlclkin3", "atl_clkin2", "atl_clkin1",
+ "atl_clkin0", "sys_clkin2", "ref_clkin0",
+ "ref_clkin1", "ref_clkin2", "ref_clkin3",
+ "mlb_clk", "mlbp_clk",
+};
+
+DEFINE_CLK_MUX(mcasp1_ahclkr_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT,
+ DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp1_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+static const char *mcasp1_aux_gfclk_mux_parents[] = {
+ "per_abe_x1_gfclk2_div", "video1_clk2_div", "video2_clk2_div",
+ "hdmi_clk2_div",
+};
+
+DEFINE_CLK_MUX(mcasp1_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_MCASP1_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp2_ahclkr_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT,
+ DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp2_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AHCLKR_SHIFT,
+ DRA7XX_CLKSEL_AHCLKR_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp2_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP2_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp3_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP3_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp3_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP3_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp4_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP4_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp4_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP4_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp5_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP5_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp5_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP5_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp6_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP6_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp6_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP6_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp7_ahclkx_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP7_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp7_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP7_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp8_ahclk_mux, mcasp1_ahclkr_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP8_CLKCTRL, DRA7XX_CLKSEL_AUX_CLK_SHIFT,
+ DRA7XX_CLKSEL_AUX_CLK_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(mcasp8_aux_gfclk_mux, mcasp1_aux_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_MCASP8_CLKCTRL, DRA7XX_CLKSEL_AHCLKX_SHIFT,
+ DRA7XX_CLKSEL_AHCLKX_WIDTH, 0x0, NULL);
+
+static const char *mmc1_fclk_mux_parents[] = {
+ "func_128m_clk", "dpll_per_m2x2_ck",
+};
+
+DEFINE_CLK_MUX(mmc1_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_CLKSEL_SOURCE_SHIFT,
+ DRA7XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc1_fclk_div, "mmc1_fclk_mux", &mmc1_fclk_mux, 0x0,
+ DRA7XX_CM_L3INIT_MMC1_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_MUX(mmc2_fclk_mux, mmc1_fclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_CLKSEL_SOURCE_SHIFT,
+ DRA7XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc2_fclk_div, "mmc2_fclk_mux", &mmc2_fclk_mux, 0x0,
+ DRA7XX_CM_L3INIT_MMC2_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static const char *mmc3_gfclk_mux_parents[] = {
+ "func_48m_fclk", "dpll_per_m2x2_ck",
+};
+
+DEFINE_CLK_MUX(mmc3_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_CLKSEL_MUX_SHIFT,
+ DRA7XX_CLKSEL_MUX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc3_gfclk_div, "mmc3_gfclk_mux", &mmc3_gfclk_mux, 0x0,
+ DRA7XX_CM_L4PER_MMC3_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+DEFINE_CLK_MUX(mmc4_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_CLKSEL_MUX_SHIFT,
+ DRA7XX_CLKSEL_MUX_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(mmc4_gfclk_div, "mmc4_gfclk_mux", &mmc4_gfclk_mux, 0x0,
+ DRA7XX_CM_L4PER_MMC4_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static const char *qspi_gfclk_mux_parents[] = {
+ "func_128m_clk", "dpll_per_h13x2_ck",
+};
+
+DEFINE_CLK_MUX(qspi_gfclk_mux, qspi_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_QSPI_CLKCTRL, DRA7XX_CLKSEL_SOURCE_SHIFT,
+ DRA7XX_CLKSEL_SOURCE_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_DIVIDER(qspi_gfclk_div, "qspi_gfclk_mux", &qspi_gfclk_mux, 0x0,
+ DRA7XX_CM_L4PER2_QSPI_CLKCTRL, DRA7XX_CLKSEL_DIV_SHIFT,
+ DRA7XX_CLKSEL_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
+
+static const char *timer10_gfclk_mux_parents[] = {
+ "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2",
+ "ref_clkin0", "ref_clkin1", "ref_clkin2",
+ "ref_clkin3", "abe_giclk_div", "video1_div_clk",
+ "video2_div_clk", "hdmi_div_clk",
+};
+
+DEFINE_CLK_MUX(timer10_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER10_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer11_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER11_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer13_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER3_TIMER13_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer14_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER3_TIMER14_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer15_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER3_TIMER15_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer16_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER3_TIMER16_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer1_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer2_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER2_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer3_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER3_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer4_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER4_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+static const char *timer5_gfclk_mux_parents[] = {
+ "timer_sys_clk_div", "sys_32k_ck", "sys_clkin2",
+ "ref_clkin0", "ref_clkin1", "ref_clkin2",
+ "ref_clkin3", "abe_giclk_div", "video1_div_clk",
+ "video2_div_clk", "hdmi_div_clk", "clkoutmux0_clk_mux",
+};
+
+DEFINE_CLK_MUX(timer5_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_TIMER5_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer6_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_TIMER6_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer7_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_TIMER7_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer8_gfclk_mux, timer5_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_TIMER8_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(timer9_gfclk_mux, timer10_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_TIMER9_CLKCTRL, DRA7XX_CLKSEL_24_27_SHIFT,
+ DRA7XX_CLKSEL_24_27_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart10_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_WKUPAON_UART10_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart1_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart2_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART2_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart3_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART3_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart4_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART4_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart5_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER_UART5_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart6_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_IPU_UART6_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart7_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_UART7_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart8_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_UART8_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(uart9_gfclk_mux, mmc3_gfclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_L4PER2_UART9_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+static const char *vip1_gclk_mux_parents[] = {
+ "l3_iclk_div", "dpll_core_h23x2_ck",
+};
+
+DEFINE_CLK_MUX(vip1_gclk_mux, vip1_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CAM_VIP1_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(vip2_gclk_mux, vip1_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CAM_VIP2_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+DEFINE_CLK_MUX(vip3_gclk_mux, vip1_gclk_mux_parents, NULL, 0x0,
+ DRA7XX_CM_CAM_VIP3_CLKCTRL, DRA7XX_CLKSEL_24_24_SHIFT,
+ DRA7XX_CLKSEL_24_24_WIDTH, 0x0, NULL);
+
+/*
+ * clkdev
+ */
+
+static struct omap_clk dra7xx_clks[] = {
+ CLK(NULL, "atl_clkin0_ck", &atl_clkin0_ck, CK_7XX),
+ CLK(NULL, "atl_clkin1_ck", &atl_clkin1_ck, CK_7XX),
+ CLK(NULL, "atl_clkin2_ck", &atl_clkin2_ck, CK_7XX),
+ CLK(NULL, "atlclkin3_ck", &atlclkin3_ck, CK_7XX),
+ CLK(NULL, "hdmi_clkin_ck", &hdmi_clkin_ck, CK_7XX),
+ CLK(NULL, "mlb_clkin_ck", &mlb_clkin_ck, CK_7XX),
+ CLK(NULL, "mlbp_clkin_ck", &mlbp_clkin_ck, CK_7XX),
+ CLK(NULL, "pciesref_acs_clk_ck", &pciesref_acs_clk_ck, CK_7XX),
+ CLK(NULL, "ref_clkin0_ck", &ref_clkin0_ck, CK_7XX),
+ CLK(NULL, "ref_clkin1_ck", &ref_clkin1_ck, CK_7XX),
+ CLK(NULL, "ref_clkin2_ck", &ref_clkin2_ck, CK_7XX),
+ CLK(NULL, "ref_clkin3_ck", &ref_clkin3_ck, CK_7XX),
+ CLK(NULL, "rmii_clk_ck", &rmii_clk_ck, CK_7XX),
+ CLK(NULL, "sdvenc_clkin_ck", &sdvenc_clkin_ck, CK_7XX),
+ CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_7XX),
+ CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_7XX),
+ CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_7XX),
+ CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_7XX),
+ CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_7XX),
+ CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_7XX),
+ CLK(NULL, "virt_20000000_ck", &virt_20000000_ck, CK_7XX),
+ CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_7XX),
+ CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_7XX),
+ CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_7XX),
+ CLK(NULL, "sys_clkin1", &sys_clkin1, CK_7XX),
+ CLK(NULL, "sys_clkin2", &sys_clkin2, CK_7XX),
+ CLK(NULL, "usb_otg_clkin_ck", &usb_otg_clkin_ck, CK_7XX),
+ CLK(NULL, "video1_clkin_ck", &video1_clkin_ck, CK_7XX),
+ CLK(NULL, "video1_m2_clkin_ck", &video1_m2_clkin_ck, CK_7XX),
+ CLK(NULL, "video2_clkin_ck", &video2_clkin_ck, CK_7XX),
+ CLK(NULL, "video2_m2_clkin_ck", &video2_m2_clkin_ck, CK_7XX),
+ CLK(NULL, "abe_dpll_sys_clk_mux", &abe_dpll_sys_clk_mux, CK_7XX),
+ CLK(NULL, "abe_dpll_bypass_clk_mux", &abe_dpll_bypass_clk_mux, CK_7XX),
+ CLK(NULL, "abe_dpll_clk_mux", &abe_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_7XX),
+ CLK(NULL, "dpll_abe_x2_ck", &dpll_abe_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_7XX),
+ CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_7XX),
+ CLK(NULL, "abe_clk", &abe_clk, CK_7XX),
+ CLK(NULL, "aess_fclk", &aess_fclk, CK_7XX),
+ CLK(NULL, "abe_giclk_div", &abe_giclk_div, CK_7XX),
+ CLK(NULL, "abe_lp_clk_div", &abe_lp_clk_div, CK_7XX),
+ CLK(NULL, "abe_sys_clk_div", &abe_sys_clk_div, CK_7XX),
+ CLK(NULL, "adc_gfclk_mux", &adc_gfclk_mux, CK_7XX),
+ CLK(NULL, "dpll_pcie_ref_ck", &dpll_pcie_ref_ck, CK_7XX),
+ CLK(NULL, "dpll_pcie_ref_m2ldo_ck", &dpll_pcie_ref_m2ldo_ck, CK_7XX),
+ CLK(NULL, "apll_pcie_ck", &apll_pcie_ck, CK_7XX),
+ CLK(NULL, "apll_pcie_clkvcoldo", &apll_pcie_clkvcoldo, CK_7XX),
+ CLK(NULL, "apll_pcie_clkvcoldo_div", &apll_pcie_clkvcoldo_div, CK_7XX),
+ CLK(NULL, "apll_pcie_m2_ck", &apll_pcie_m2_ck, CK_7XX),
+ CLK(NULL, "sys_clk1_dclk_div", &sys_clk1_dclk_div, CK_7XX),
+ CLK(NULL, "sys_clk2_dclk_div", &sys_clk2_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_7XX),
+ CLK(NULL, "per_abe_x1_dclk_div", &per_abe_x1_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_abe_m3x2_ck", &dpll_abe_m3x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_7XX),
+ CLK(NULL, "dpll_core_x2_ck", &dpll_core_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h12x2_ck", &dpll_core_h12x2_ck, CK_7XX),
+ CLK(NULL, "mpu_dpll_hs_clk_div", &mpu_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_7XX),
+ CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_7XX),
+ CLK(NULL, "mpu_dclk_div", &mpu_dclk_div, CK_7XX),
+ CLK(NULL, "dsp_dpll_hs_clk_div", &dsp_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_dsp_ck", &dpll_dsp_ck, CK_7XX),
+ CLK(NULL, "dpll_dsp_m2_ck", &dpll_dsp_m2_ck, CK_7XX),
+ CLK(NULL, "dsp_gclk_div", &dsp_gclk_div, CK_7XX),
+ CLK(NULL, "iva_dpll_hs_clk_div", &iva_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_7XX),
+ CLK(NULL, "dpll_iva_m2_ck", &dpll_iva_m2_ck, CK_7XX),
+ CLK(NULL, "iva_dclk", &iva_dclk, CK_7XX),
+ CLK(NULL, "dpll_gpu_ck", &dpll_gpu_ck, CK_7XX),
+ CLK(NULL, "dpll_gpu_m2_ck", &dpll_gpu_m2_ck, CK_7XX),
+ CLK(NULL, "gpu_dclk", &gpu_dclk, CK_7XX),
+ CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_7XX),
+ CLK(NULL, "core_dpll_out_dclk_div", &core_dpll_out_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_ddr_ck", &dpll_ddr_ck, CK_7XX),
+ CLK(NULL, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck, CK_7XX),
+ CLK(NULL, "emif_phy_dclk_div", &emif_phy_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_gmac_ck", &dpll_gmac_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_m2_ck", &dpll_gmac_m2_ck, CK_7XX),
+ CLK(NULL, "gmac_250m_dclk_div", &gmac_250m_dclk_div, CK_7XX),
+ CLK(NULL, "video2_dclk_div", &video2_dclk_div, CK_7XX),
+ CLK(NULL, "video1_dclk_div", &video1_dclk_div, CK_7XX),
+ CLK(NULL, "hdmi_dclk_div", &hdmi_dclk_div, CK_7XX),
+ CLK(NULL, "per_dpll_hs_clk_div", &per_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_7XX),
+ CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_7XX),
+ CLK(NULL, "func_96m_aon_dclk_div", &func_96m_aon_dclk_div, CK_7XX),
+ CLK(NULL, "usb_dpll_hs_clk_div", &usb_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_7XX),
+ CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_7XX),
+ CLK(NULL, "l3init_480m_dclk_div", &l3init_480m_dclk_div, CK_7XX),
+ CLK(NULL, "usb_otg_dclk_div", &usb_otg_dclk_div, CK_7XX),
+ CLK(NULL, "sata_dclk_div", &sata_dclk_div, CK_7XX),
+ CLK(NULL, "dpll_pcie_ref_m2_ck", &dpll_pcie_ref_m2_ck, CK_7XX),
+ CLK(NULL, "pcie2_dclk_div", &pcie2_dclk_div, CK_7XX),
+ CLK(NULL, "pcie_dclk_div", &pcie_dclk_div, CK_7XX),
+ CLK(NULL, "emu_dclk_div", &emu_dclk_div, CK_7XX),
+ CLK(NULL, "secure_32k_dclk_div", &secure_32k_dclk_div, CK_7XX),
+ CLK(NULL, "eve_dpll_hs_clk_div", &eve_dpll_hs_clk_div, CK_7XX),
+ CLK(NULL, "dpll_eve_ck", &dpll_eve_ck, CK_7XX),
+ CLK(NULL, "dpll_eve_m2_ck", &dpll_eve_m2_ck, CK_7XX),
+ CLK(NULL, "eve_dclk_div", &eve_dclk_div, CK_7XX),
+ CLK(NULL, "clkoutmux0_clk_mux", &clkoutmux0_clk_mux, CK_7XX),
+ CLK(NULL, "clkoutmux1_clk_mux", &clkoutmux1_clk_mux, CK_7XX),
+ CLK(NULL, "clkoutmux2_clk_mux", &clkoutmux2_clk_mux, CK_7XX),
+ CLK(NULL, "custefuse_sys_gfclk_div", &custefuse_sys_gfclk_div, CK_7XX),
+ CLK(NULL, "dpll_core_h13x2_ck", &dpll_core_h13x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h14x2_ck", &dpll_core_h14x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h22x2_ck", &dpll_core_h22x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h23x2_ck", &dpll_core_h23x2_ck, CK_7XX),
+ CLK(NULL, "dpll_core_h24x2_ck", &dpll_core_h24x2_ck, CK_7XX),
+ CLK(NULL, "dpll_ddr_x2_ck", &dpll_ddr_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_ddr_h11x2_ck", &dpll_ddr_h11x2_ck, CK_7XX),
+ CLK(NULL, "dpll_dsp_x2_ck", &dpll_dsp_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_dsp_m3x2_ck", &dpll_dsp_m3x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_x2_ck", &dpll_gmac_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_h11x2_ck", &dpll_gmac_h11x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_h12x2_ck", &dpll_gmac_h12x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_h13x2_ck", &dpll_gmac_h13x2_ck, CK_7XX),
+ CLK(NULL, "dpll_gmac_m3x2_ck", &dpll_gmac_m3x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_x2_ck", &dpll_per_x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_h11x2_ck", &dpll_per_h11x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_h12x2_ck", &dpll_per_h12x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_h13x2_ck", &dpll_per_h13x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_h14x2_ck", &dpll_per_h14x2_ck, CK_7XX),
+ CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_7XX),
+ CLK(NULL, "dpll_usb_clkdcoldo", &dpll_usb_clkdcoldo, CK_7XX),
+ CLK(NULL, "eve_clk", &eve_clk, CK_7XX),
+ CLK(NULL, "func_128m_clk", &func_128m_clk, CK_7XX),
+ CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_7XX),
+ CLK(NULL, "func_24m_clk", &func_24m_clk, CK_7XX),
+ CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_7XX),
+ CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_7XX),
+ CLK(NULL, "gmii_m_clk_div", &gmii_m_clk_div, CK_7XX),
+ CLK(NULL, "hdmi_clk2_div", &hdmi_clk2_div, CK_7XX),
+ CLK(NULL, "hdmi_div_clk", &hdmi_div_clk, CK_7XX),
+ CLK(NULL, "hdmi_dpll_clk_mux", &hdmi_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "l3_iclk_div", &l3_iclk_div, CK_7XX),
+ CLK(NULL, "l3init_60m_fclk", &l3init_60m_fclk, CK_7XX),
+ CLK(NULL, "l4_root_clk_div", &l4_root_clk_div, CK_7XX),
+ CLK(NULL, "mlb_clk", &mlb_clk, CK_7XX),
+ CLK(NULL, "mlbp_clk", &mlbp_clk, CK_7XX),
+ CLK(NULL, "per_abe_x1_gfclk2_div", &per_abe_x1_gfclk2_div, CK_7XX),
+ CLK(NULL, "timer_sys_clk_div", &timer_sys_clk_div, CK_7XX),
+ CLK(NULL, "video1_clk2_div", &video1_clk2_div, CK_7XX),
+ CLK(NULL, "video1_div_clk", &video1_div_clk, CK_7XX),
+ CLK(NULL, "video1_dpll_clk_mux", &video1_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "video2_clk2_div", &video2_clk2_div, CK_7XX),
+ CLK(NULL, "video2_div_clk", &video2_div_clk, CK_7XX),
+ CLK(NULL, "video2_dpll_clk_mux", &video2_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "wkupaon_iclk_mux", &wkupaon_iclk_mux, CK_7XX),
+ CLK(NULL, "dss_32khz_clk", &dss_32khz_clk, CK_7XX),
+ CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_7XX),
+ CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_7XX),
+ CLK(NULL, "dss_hdmi_clk", &dss_hdmi_clk, CK_7XX),
+ CLK(NULL, "dss_video1_clk", &dss_video1_clk, CK_7XX),
+ CLK(NULL, "dss_video2_clk", &dss_video2_clk, CK_7XX),
+ CLK(NULL, "gpio1_dbclk", &gpio1_dbclk, CK_7XX),
+ CLK(NULL, "gpio2_dbclk", &gpio2_dbclk, CK_7XX),
+ CLK(NULL, "gpio3_dbclk", &gpio3_dbclk, CK_7XX),
+ CLK(NULL, "gpio4_dbclk", &gpio4_dbclk, CK_7XX),
+ CLK(NULL, "gpio5_dbclk", &gpio5_dbclk, CK_7XX),
+ CLK(NULL, "gpio6_dbclk", &gpio6_dbclk, CK_7XX),
+ CLK(NULL, "gpio7_dbclk", &gpio7_dbclk, CK_7XX),
+ CLK(NULL, "gpio8_dbclk", &gpio8_dbclk, CK_7XX),
+ CLK(NULL, "mmc1_clk32k", &mmc1_clk32k, CK_7XX),
+ CLK(NULL, "mmc2_clk32k", &mmc2_clk32k, CK_7XX),
+ CLK(NULL, "mmc3_clk32k", &mmc3_clk32k, CK_7XX),
+ CLK(NULL, "mmc4_clk32k", &mmc4_clk32k, CK_7XX),
+ CLK(NULL, "sata_ref_clk", &sata_ref_clk, CK_7XX),
+ CLK(NULL, "usb_otg_ss1_refclk960m", &usb_otg_ss1_refclk960m, CK_7XX),
+ CLK(NULL, "usb_otg_ss2_refclk960m", &usb_otg_ss2_refclk960m, CK_7XX),
+ CLK(NULL, "usb_phy1_always_on_clk32k", &usb_phy1_always_on_clk32k, CK_7XX),
+ CLK(NULL, "usb_phy2_always_on_clk32k", &usb_phy2_always_on_clk32k, CK_7XX),
+ CLK(NULL, "usb_phy3_always_on_clk32k", &usb_phy3_always_on_clk32k, CK_7XX),
+ CLK(NULL, "atl_dpll_clk_mux", &atl_dpll_clk_mux, CK_7XX),
+ CLK(NULL, "atl_gfclk_mux", &atl_gfclk_mux, CK_7XX),
+ CLK(NULL, "dcan1_sys_clk_mux", &dcan1_sys_clk_mux, CK_7XX),
+ CLK(NULL, "gmac_gmii_ref_clk_div", &gmac_gmii_ref_clk_div, CK_7XX),
+ CLK(NULL, "gmac_rft_clk_mux", &gmac_rft_clk_mux, CK_7XX),
+ CLK(NULL, "gpu_core_gclk_mux", &gpu_core_gclk_mux, CK_7XX),
+ CLK(NULL, "gpu_hyd_gclk_mux", &gpu_hyd_gclk_mux, CK_7XX),
+ CLK(NULL, "ipu1_gfclk_mux", &ipu1_gfclk_mux, CK_7XX),
+ CLK(NULL, "l3instr_ts_gclk_div", &l3instr_ts_gclk_div, CK_7XX),
+ CLK(NULL, "mcasp1_ahclkr_mux", &mcasp1_ahclkr_mux, CK_7XX),
+ CLK(NULL, "mcasp1_ahclkx_mux", &mcasp1_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp1_aux_gfclk_mux", &mcasp1_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp2_ahclkr_mux", &mcasp2_ahclkr_mux, CK_7XX),
+ CLK(NULL, "mcasp2_ahclkx_mux", &mcasp2_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp2_aux_gfclk_mux", &mcasp2_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp3_ahclkx_mux", &mcasp3_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp3_aux_gfclk_mux", &mcasp3_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp4_ahclkx_mux", &mcasp4_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp4_aux_gfclk_mux", &mcasp4_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp5_ahclkx_mux", &mcasp5_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp5_aux_gfclk_mux", &mcasp5_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp6_ahclkx_mux", &mcasp6_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp6_aux_gfclk_mux", &mcasp6_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp7_ahclkx_mux", &mcasp7_ahclkx_mux, CK_7XX),
+ CLK(NULL, "mcasp7_aux_gfclk_mux", &mcasp7_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mcasp8_ahclk_mux", &mcasp8_ahclk_mux, CK_7XX),
+ CLK(NULL, "mcasp8_aux_gfclk_mux", &mcasp8_aux_gfclk_mux, CK_7XX),
+ CLK(NULL, "mmc1_fclk_mux", &mmc1_fclk_mux, CK_7XX),
+ CLK(NULL, "mmc1_fclk_div", &mmc1_fclk_div, CK_7XX),
+ CLK(NULL, "mmc2_fclk_mux", &mmc2_fclk_mux, CK_7XX),
+ CLK(NULL, "mmc2_fclk_div", &mmc2_fclk_div, CK_7XX),
+ CLK(NULL, "mmc3_gfclk_mux", &mmc3_gfclk_mux, CK_7XX),
+ CLK(NULL, "mmc3_gfclk_div", &mmc3_gfclk_div, CK_7XX),
+ CLK(NULL, "mmc4_gfclk_mux", &mmc4_gfclk_mux, CK_7XX),
+ CLK(NULL, "mmc4_gfclk_div", &mmc4_gfclk_div, CK_7XX),
+ CLK(NULL, "qspi_gfclk_mux", &qspi_gfclk_mux, CK_7XX),
+ CLK(NULL, "qspi_gfclk_div", &qspi_gfclk_div, CK_7XX),
+ CLK(NULL, "timer10_gfclk_mux", &timer10_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer11_gfclk_mux", &timer11_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer13_gfclk_mux", &timer13_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer14_gfclk_mux", &timer14_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer15_gfclk_mux", &timer15_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer16_gfclk_mux", &timer16_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer1_gfclk_mux", &timer1_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer2_gfclk_mux", &timer2_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer3_gfclk_mux", &timer3_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer4_gfclk_mux", &timer4_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer5_gfclk_mux", &timer5_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer6_gfclk_mux", &timer6_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer7_gfclk_mux", &timer7_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer8_gfclk_mux", &timer8_gfclk_mux, CK_7XX),
+ CLK(NULL, "timer9_gfclk_mux", &timer9_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart10_gfclk_mux", &uart10_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart1_gfclk_mux", &uart1_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart2_gfclk_mux", &uart2_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart3_gfclk_mux", &uart3_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart4_gfclk_mux", &uart4_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart5_gfclk_mux", &uart5_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart6_gfclk_mux", &uart6_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart7_gfclk_mux", &uart7_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart8_gfclk_mux", &uart8_gfclk_mux, CK_7XX),
+ CLK(NULL, "uart9_gfclk_mux", &uart9_gfclk_mux, CK_7XX),
+ CLK(NULL, "vip1_gclk_mux", &vip1_gclk_mux, CK_7XX),
+ CLK(NULL, "vip2_gclk_mux", &vip2_gclk_mux, CK_7XX),
+ CLK(NULL, "vip3_gclk_mux", &vip3_gclk_mux, CK_7XX),
+ CLK(NULL, "gpmc_ck", &dummy_ck, CK_7XX),
+ CLK("omap_i2c.1", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_i2c.2", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_i2c.3", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_i2c.4", "ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "mailboxes_ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_7XX),
+ CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_7XX),
+ CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_7XX),
+ CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_7XX),
+ CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_7XX),
+ CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_7XX),
+ CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_7XX),
+ CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_7XX),
+ CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_7XX),
+ CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "uart1_ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "uart2_ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "uart3_ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "uart4_ick", &dummy_ck, CK_7XX),
+ CLK("usbhs_omap", "usbhost_ick", &dummy_ck, CK_7XX),
+ CLK("usbhs_omap", "usbtll_fck", &dummy_ck, CK_7XX),
+ CLK("omap_wdt", "ick", &dummy_ck, CK_7XX),
+ CLK(NULL, "timer_32k_ck", &sys_32k_ck, CK_7XX),
+ CLK("4ae18000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48032000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48034000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48036000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("4803e000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48086000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48088000.timer", "timer_sys_ck", &sys_clkin2, CK_7XX),
+ CLK("48820000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX),
+ CLK("48822000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX),
+ CLK("48824000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX),
+ CLK("48826000.timer", "timer_sys_ck", &timer_sys_clk_div, CK_7XX),
+ CLK(NULL, "sys_clkin", &sys_clkin1, CK_7XX),
+};
+
+/*
+ * Prepare and enable a list of clocks.
+ * XXX Deprecated: Only needed until these clocks are properly claimed
+ * and enabled by the drivers or core code thats uses them.
+ */
+
+static const char *enable_init_clks[] = {
+};
+
+static struct reparent_init_clks reparent_clks[] = {
+ { .name = "abe_dpll_sys_clk_mux", .parent = "sys_clkin2" },
+};
+
+static struct rate_init_clks rate_clks[] = {
+ { .name = "dpll_abe_ck", .rate = DRA7_DPLL_ABE_DEFFREQ },
+ { .name = "dpll_gmac_ck", .rate = DRA7_DPLL_GMAC_DEFFREQ },
+};
+
+int __init dra7xx_clk_init(void)
+{
+ u32 cpu_clkflg;
+ struct omap_clk *c;
+
+ if (soc_is_dra7xx()) {
+ cpu_mask = RATE_IN_7XX;
+ cpu_clkflg = CK_7XX;
+ }
+
+ /*
+ * Must stay commented until all OMAP SoC drivers are
+ * converted to runtime PM, or drivers may start crashing
+ *
+ * omap2_clk_disable_clkdm_control();
+ */
+
+ for (c = dra7xx_clks; c < dra7xx_clks + ARRAY_SIZE(dra7xx_clks);
+ c++) {
+ if (c->cpu & cpu_clkflg) {
+ clkdev_add(&c->lk);
+ if (!__clk_init(NULL, c->lk.clk))
+ omap2_init_clk_hw_omap_clocks(c->lk.clk);
+ }
+ }
+
+ omap2_clk_disable_autoidle_all();
+
+ omap2_clk_reparent_init_clocks(reparent_clks,
+ ARRAY_SIZE(reparent_clks));
+ omap2_clk_rate_init_clocks(rate_clks, ARRAY_SIZE(rate_clks));
+ omap2_clk_enable_init_clocks(enable_init_clks,
+ ARRAY_SIZE(enable_init_clks));
+
+ return 0;
+}
index 9874ebea4f2240440d128064fcd4af28a9fbae87..35a3050390b9ed396c0be01c4ccb5792ffb16817 100644 (file)
#define CK_446X (1 << 8)
#define CK_AM33XX (1 << 9) /* AM33xx specific clocks */
#define CK_54XX (1 << 10) /* OMAP54xx specific clocks */
+#define CK_7XX (1 << 11)
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
#define RATE_IN_AM33XX (1 << 8)
#define RATE_IN_TI814X (1 << 9)
#define RATE_IN_54XX (1 << 10)
+#define RATE_IN_7XX (1 << 11)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
diff --git a/arch/arm/mach-omap2/clock7xx.h b/arch/arm/mach-omap2/clock7xx.h
--- /dev/null
@@ -0,0 +1,24 @@
+/*
+ * DRA7xx clock function prototypes and macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_DRA_CLOCK7xx_H
+#define __ARCH_ARM_MACH_DRA_CLOCK7xx_H
+
+int dra7xx_clk_init(void);
+
+#endif
index c918efb465af5a8a70ac4065c269735c56feaa25..6109807b9da9fefd5be1244b537325c8964d9dbd 100644 (file)
/* clksel_rate blocks shared between OMAP44xx and AM33xx */
const struct clksel_rate div_1_0_rates[] = {
- { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 0, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
};
const struct clksel_rate div_1_1_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div_1_2_rates[] = {
- { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div_1_3_rates[] = {
- { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div_1_4_rates[] = {
- { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div31_1to31_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
- { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX },
+ { .div = 1, .val = 1, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 7, .val = 7, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 10, .val = 10, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 11, .val = 11, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 13, .val = 13, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 14, .val = 14, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 15, .val = 15, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 17, .val = 17, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 18, .val = 18, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 19, .val = 19, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 20, .val = 20, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 21, .val = 21, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 22, .val = 22, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 23, .val = 23, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 24, .val = 24, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 25, .val = 25, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 26, .val = 26, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 27, .val = 27, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 28, .val = 28, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 29, .val = 29, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 30, .val = 30, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 31, .val = 31, .flags = RATE_IN_4430 | RATE_IN_AM33XX | RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
const struct clksel_rate div63_1to63_rates[] = {
- { .div = 1, .val = 1, .flags = RATE_IN_54XX },
- { .div = 2, .val = 2, .flags = RATE_IN_54XX },
- { .div = 3, .val = 3, .flags = RATE_IN_54XX },
- { .div = 4, .val = 4, .flags = RATE_IN_54XX },
- { .div = 5, .val = 5, .flags = RATE_IN_54XX },
- { .div = 6, .val = 6, .flags = RATE_IN_54XX },
- { .div = 7, .val = 7, .flags = RATE_IN_54XX },
- { .div = 8, .val = 8, .flags = RATE_IN_54XX },
- { .div = 9, .val = 9, .flags = RATE_IN_54XX },
- { .div = 10, .val = 10, .flags = RATE_IN_54XX },
- { .div = 11, .val = 11, .flags = RATE_IN_54XX },
- { .div = 12, .val = 12, .flags = RATE_IN_54XX },
- { .div = 13, .val = 13, .flags = RATE_IN_54XX },
- { .div = 14, .val = 14, .flags = RATE_IN_54XX },
- { .div = 15, .val = 15, .flags = RATE_IN_54XX },
- { .div = 16, .val = 16, .flags = RATE_IN_54XX },
- { .div = 17, .val = 17, .flags = RATE_IN_54XX },
- { .div = 18, .val = 18, .flags = RATE_IN_54XX },
- { .div = 19, .val = 19, .flags = RATE_IN_54XX },
- { .div = 20, .val = 20, .flags = RATE_IN_54XX },
- { .div = 21, .val = 21, .flags = RATE_IN_54XX },
- { .div = 22, .val = 22, .flags = RATE_IN_54XX },
- { .div = 23, .val = 23, .flags = RATE_IN_54XX },
- { .div = 24, .val = 24, .flags = RATE_IN_54XX },
- { .div = 25, .val = 25, .flags = RATE_IN_54XX },
- { .div = 26, .val = 26, .flags = RATE_IN_54XX },
- { .div = 27, .val = 27, .flags = RATE_IN_54XX },
- { .div = 28, .val = 28, .flags = RATE_IN_54XX },
- { .div = 29, .val = 29, .flags = RATE_IN_54XX },
- { .div = 30, .val = 30, .flags = RATE_IN_54XX },
- { .div = 31, .val = 31, .flags = RATE_IN_54XX },
- { .div = 32, .val = 32, .flags = RATE_IN_54XX },
- { .div = 33, .val = 33, .flags = RATE_IN_54XX },
- { .div = 34, .val = 34, .flags = RATE_IN_54XX },
- { .div = 35, .val = 35, .flags = RATE_IN_54XX },
- { .div = 36, .val = 36, .flags = RATE_IN_54XX },
- { .div = 37, .val = 37, .flags = RATE_IN_54XX },
- { .div = 38, .val = 38, .flags = RATE_IN_54XX },
- { .div = 39, .val = 39, .flags = RATE_IN_54XX },
- { .div = 40, .val = 40, .flags = RATE_IN_54XX },
- { .div = 41, .val = 41, .flags = RATE_IN_54XX },
- { .div = 42, .val = 42, .flags = RATE_IN_54XX },
- { .div = 43, .val = 43, .flags = RATE_IN_54XX },
- { .div = 44, .val = 44, .flags = RATE_IN_54XX },
- { .div = 45, .val = 45, .flags = RATE_IN_54XX },
- { .div = 46, .val = 46, .flags = RATE_IN_54XX },
- { .div = 47, .val = 47, .flags = RATE_IN_54XX },
- { .div = 48, .val = 48, .flags = RATE_IN_54XX },
- { .div = 49, .val = 49, .flags = RATE_IN_54XX },
- { .div = 50, .val = 50, .flags = RATE_IN_54XX },
- { .div = 51, .val = 51, .flags = RATE_IN_54XX },
- { .div = 52, .val = 52, .flags = RATE_IN_54XX },
- { .div = 53, .val = 53, .flags = RATE_IN_54XX },
- { .div = 54, .val = 54, .flags = RATE_IN_54XX },
- { .div = 55, .val = 55, .flags = RATE_IN_54XX },
- { .div = 56, .val = 56, .flags = RATE_IN_54XX },
- { .div = 57, .val = 57, .flags = RATE_IN_54XX },
- { .div = 58, .val = 58, .flags = RATE_IN_54XX },
- { .div = 59, .val = 59, .flags = RATE_IN_54XX },
- { .div = 60, .val = 60, .flags = RATE_IN_54XX },
- { .div = 61, .val = 61, .flags = RATE_IN_54XX },
- { .div = 62, .val = 62, .flags = RATE_IN_54XX },
- { .div = 63, .val = 63, .flags = RATE_IN_54XX },
+ { .div = 1, .val = 1, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 2, .val = 2, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 3, .val = 3, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 4, .val = 4, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 5, .val = 5, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 6, .val = 6, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 7, .val = 7, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 8, .val = 8, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 9, .val = 9, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 10, .val = 10, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 11, .val = 11, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 12, .val = 12, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 13, .val = 13, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 14, .val = 14, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 15, .val = 15, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 16, .val = 16, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 17, .val = 17, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 18, .val = 18, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 19, .val = 19, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 20, .val = 20, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 21, .val = 21, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 22, .val = 22, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 23, .val = 23, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 24, .val = 24, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 25, .val = 25, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 26, .val = 26, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 27, .val = 27, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 28, .val = 28, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 29, .val = 29, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 30, .val = 30, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 31, .val = 31, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 32, .val = 32, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 33, .val = 33, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 34, .val = 34, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 35, .val = 35, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 36, .val = 36, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 37, .val = 37, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 38, .val = 38, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 39, .val = 39, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 40, .val = 40, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 41, .val = 41, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 42, .val = 42, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 43, .val = 43, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 44, .val = 44, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 45, .val = 45, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 46, .val = 46, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 47, .val = 47, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 48, .val = 48, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 49, .val = 49, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 50, .val = 50, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 51, .val = 51, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 52, .val = 52, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 53, .val = 53, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 54, .val = 54, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 55, .val = 55, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 56, .val = 56, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 57, .val = 57, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 58, .val = 58, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 59, .val = 59, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 60, .val = 60, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 61, .val = 61, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 62, .val = 62, .flags = RATE_IN_54XX | RATE_IN_7XX },
+ { .div = 63, .val = 63, .flags = RATE_IN_54XX | RATE_IN_7XX },
{ .div = 0 },
};
index aa800679c80a2f3fa224665ca87b016c924a6fc6..d767b0199874afe9f2fbf258ef82896b1818281b 100644 (file)
extern void __init am33xx_clockdomains_init(void);
extern void __init omap44xx_clockdomains_init(void);
extern void __init omap54xx_clockdomains_init(void);
+extern void __init dra7xx_clockdomains_init(void);
extern void clkdm_add_autodeps(struct clockdomain *clkdm);
extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
--- /dev/null
@@ -0,0 +1,739 @@
+/*
+ * DRA7xx Clock domains framework
+ *
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm1_7xx.h"
+#include "cm2_7xx.h"
+
+#include "cm-regbits-7xx.h"
+#include "prm7xx.h"
+#include "prcm44xx.h"
+#include "prcm_mpu7xx.h"
+
+/* Static Dependencies for DRA7xx Clock Domains */
+
+static struct clkdm_dep cam_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dma_wkup_sleep_deps[] = {
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "cam_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "cam_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep dss_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep eve1_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep eve2_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep eve3_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep eve4_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep gmac_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep gpu_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep iva_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep l3init_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
+ { .clkdm_name = "cam_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "ipu2_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l3main1_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "pcie_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { .clkdm_name = "wkupaon_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep pcie_wkup_sleep_deps[] = {
+ { .clkdm_name = "atl_clkdm" },
+ { .clkdm_name = "cam_clkdm" },
+ { .clkdm_name = "dsp1_clkdm" },
+ { .clkdm_name = "dsp2_clkdm" },
+ { .clkdm_name = "dss_clkdm" },
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "eve1_clkdm" },
+ { .clkdm_name = "eve2_clkdm" },
+ { .clkdm_name = "eve3_clkdm" },
+ { .clkdm_name = "eve4_clkdm" },
+ { .clkdm_name = "gmac_clkdm" },
+ { .clkdm_name = "gpu_clkdm" },
+ { .clkdm_name = "ipu_clkdm" },
+ { .clkdm_name = "ipu1_clkdm" },
+ { .clkdm_name = "iva_clkdm" },
+ { .clkdm_name = "l3init_clkdm" },
+ { .clkdm_name = "l4cfg_clkdm" },
+ { .clkdm_name = "l4per_clkdm" },
+ { .clkdm_name = "l4per2_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { .clkdm_name = "l4sec_clkdm" },
+ { .clkdm_name = "vpe_clkdm" },
+ { NULL },
+};
+
+static struct clkdm_dep vpe_wkup_sleep_deps[] = {
+ { .clkdm_name = "emif_clkdm" },
+ { .clkdm_name = "l4per3_clkdm" },
+ { NULL },
+};
+
+static struct clockdomain l4per3_7xx_clkdm = {
+ .name = "l4per3_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
+ .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4per2_7xx_clkdm = {
+ .name = "l4per2_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
+ .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
+ .wkdep_srcs = l4per2_wkup_sleep_deps,
+ .sleepdep_srcs = l4per2_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mpu0_7xx_clkdm = {
+ .name = "mpu0_clkdm",
+ .pwrdm = { .name = "cpu0_pwrdm" },
+ .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
+ .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST,
+ .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain iva_7xx_clkdm = {
+ .name = "iva_clkdm",
+ .pwrdm = { .name = "iva_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_IVA_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
+ .dep_bit = DRA7XX_IVA_STATDEP_SHIFT,
+ .wkdep_srcs = iva_wkup_sleep_deps,
+ .sleepdep_srcs = iva_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain coreaon_7xx_clkdm = {
+ .name = "coreaon_clkdm",
+ .pwrdm = { .name = "coreaon_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_COREAON_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu1_7xx_clkdm = {
+ .name = "ipu1_clkdm",
+ .pwrdm = { .name = "ipu_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
+ .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT,
+ .wkdep_srcs = ipu1_wkup_sleep_deps,
+ .sleepdep_srcs = ipu1_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain ipu2_7xx_clkdm = {
+ .name = "ipu2_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
+ .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT,
+ .wkdep_srcs = ipu2_wkup_sleep_deps,
+ .sleepdep_srcs = ipu2_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l3init_7xx_clkdm = {
+ .name = "l3init_clkdm",
+ .pwrdm = { .name = "l3init_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
+ .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT,
+ .wkdep_srcs = l3init_wkup_sleep_deps,
+ .sleepdep_srcs = l3init_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4sec_7xx_clkdm = {
+ .name = "l4sec_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
+ .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
+ .wkdep_srcs = l4sec_wkup_sleep_deps,
+ .sleepdep_srcs = l4sec_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l3main1_7xx_clkdm = {
+ .name = "l3main1_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
+ .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain vpe_7xx_clkdm = {
+ .name = "vpe_clkdm",
+ .pwrdm = { .name = "vpe_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
+ .dep_bit = DRA7XX_VPE_STATDEP_SHIFT,
+ .wkdep_srcs = vpe_wkup_sleep_deps,
+ .sleepdep_srcs = vpe_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mpu_7xx_clkdm = {
+ .name = "mpu_clkdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
+ .wkdep_srcs = mpu_wkup_sleep_deps,
+ .sleepdep_srcs = mpu_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain custefuse_7xx_clkdm = {
+ .name = "custefuse_clkdm",
+ .pwrdm = { .name = "custefuse_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain ipu_7xx_clkdm = {
+ .name = "ipu_clkdm",
+ .pwrdm = { .name = "ipu_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
+ .dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain mpu1_7xx_clkdm = {
+ .name = "mpu1_clkdm",
+ .pwrdm = { .name = "cpu1_pwrdm" },
+ .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
+ .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST,
+ .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain gmac_7xx_clkdm = {
+ .name = "gmac_clkdm",
+ .pwrdm = { .name = "l3init_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
+ .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT,
+ .wkdep_srcs = gmac_wkup_sleep_deps,
+ .sleepdep_srcs = gmac_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4cfg_7xx_clkdm = {
+ .name = "l4cfg_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
+ .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain dma_7xx_clkdm = {
+ .name = "dma_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
+ .wkdep_srcs = dma_wkup_sleep_deps,
+ .sleepdep_srcs = dma_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain rtc_7xx_clkdm = {
+ .name = "rtc_clkdm",
+ .pwrdm = { .name = "rtc_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain pcie_7xx_clkdm = {
+ .name = "pcie_clkdm",
+ .pwrdm = { .name = "l3init_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
+ .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
+ .wkdep_srcs = pcie_wkup_sleep_deps,
+ .sleepdep_srcs = pcie_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain atl_7xx_clkdm = {
+ .name = "atl_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
+ .dep_bit = DRA7XX_ATL_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain l3instr_7xx_clkdm = {
+ .name = "l3instr_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
+};
+
+static struct clockdomain dss_7xx_clkdm = {
+ .name = "dss_clkdm",
+ .pwrdm = { .name = "dss_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_DSS_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
+ .dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
+ .wkdep_srcs = dss_wkup_sleep_deps,
+ .sleepdep_srcs = dss_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain emif_7xx_clkdm = {
+ .name = "emif_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CORE_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
+ .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain emu_7xx_clkdm = {
+ .name = "emu_clkdm",
+ .pwrdm = { .name = "emu_pwrdm" },
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .cm_inst = DRA7XX_PRM_EMU_CM_INST,
+ .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain dsp2_7xx_clkdm = {
+ .name = "dsp2_clkdm",
+ .pwrdm = { .name = "dsp2_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
+ .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT,
+ .wkdep_srcs = dsp2_wkup_sleep_deps,
+ .sleepdep_srcs = dsp2_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain dsp1_7xx_clkdm = {
+ .name = "dsp1_clkdm",
+ .pwrdm = { .name = "dsp1_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
+ .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT,
+ .wkdep_srcs = dsp1_wkup_sleep_deps,
+ .sleepdep_srcs = dsp1_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain cam_7xx_clkdm = {
+ .name = "cam_clkdm",
+ .pwrdm = { .name = "cam_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_CAM_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
+ .dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
+ .wkdep_srcs = cam_wkup_sleep_deps,
+ .sleepdep_srcs = cam_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain l4per_7xx_clkdm = {
+ .name = "l4per_clkdm",
+ .pwrdm = { .name = "l4per_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
+ .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain gpu_7xx_clkdm = {
+ .name = "gpu_clkdm",
+ .pwrdm = { .name = "gpu_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_GPU_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
+ .dep_bit = DRA7XX_GPU_STATDEP_SHIFT,
+ .wkdep_srcs = gpu_wkup_sleep_deps,
+ .sleepdep_srcs = gpu_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain eve4_7xx_clkdm = {
+ .name = "eve4_clkdm",
+ .pwrdm = { .name = "eve4_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
+ .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT,
+ .wkdep_srcs = eve4_wkup_sleep_deps,
+ .sleepdep_srcs = eve4_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain eve2_7xx_clkdm = {
+ .name = "eve2_clkdm",
+ .pwrdm = { .name = "eve2_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
+ .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT,
+ .wkdep_srcs = eve2_wkup_sleep_deps,
+ .sleepdep_srcs = eve2_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain eve3_7xx_clkdm = {
+ .name = "eve3_clkdm",
+ .pwrdm = { .name = "eve3_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
+ .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT,
+ .wkdep_srcs = eve3_wkup_sleep_deps,
+ .sleepdep_srcs = eve3_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+static struct clockdomain wkupaon_7xx_clkdm = {
+ .name = "wkupaon_clkdm",
+ .pwrdm = { .name = "wkupaon_pwrdm" },
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST,
+ .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
+ .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+};
+
+static struct clockdomain eve1_7xx_clkdm = {
+ .name = "eve1_clkdm",
+ .pwrdm = { .name = "eve1_pwrdm" },
+ .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
+ .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST,
+ .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
+ .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT,
+ .wkdep_srcs = eve1_wkup_sleep_deps,
+ .sleepdep_srcs = eve1_wkup_sleep_deps,
+ .flags = CLKDM_CAN_HWSUP_SWSUP,
+};
+
+/* As clockdomains are added or removed above, this list must also be changed */
+static struct clockdomain *clockdomains_dra7xx[] __initdata = {
+ &l4per3_7xx_clkdm,
+ &l4per2_7xx_clkdm,
+ &mpu0_7xx_clkdm,
+ &iva_7xx_clkdm,
+ &coreaon_7xx_clkdm,
+ &ipu1_7xx_clkdm,
+ &ipu2_7xx_clkdm,
+ &l3init_7xx_clkdm,
+ &l4sec_7xx_clkdm,
+ &l3main1_7xx_clkdm,
+ &vpe_7xx_clkdm,
+ &mpu_7xx_clkdm,
+ &custefuse_7xx_clkdm,
+ &ipu_7xx_clkdm,
+ &mpu1_7xx_clkdm,
+ &gmac_7xx_clkdm,
+ &l4cfg_7xx_clkdm,
+ &dma_7xx_clkdm,
+ &rtc_7xx_clkdm,
+ &pcie_7xx_clkdm,
+ &atl_7xx_clkdm,
+ &l3instr_7xx_clkdm,
+ &dss_7xx_clkdm,
+ &emif_7xx_clkdm,
+ &emu_7xx_clkdm,
+ &dsp2_7xx_clkdm,
+ &dsp1_7xx_clkdm,
+ &cam_7xx_clkdm,
+ &l4per_7xx_clkdm,
+ &gpu_7xx_clkdm,
+ &eve4_7xx_clkdm,
+ &eve2_7xx_clkdm,
+ &eve3_7xx_clkdm,
+ &wkupaon_7xx_clkdm,
+ &eve1_7xx_clkdm,
+ NULL
+};
+
+void __init dra7xx_clockdomains_init(void)
+{
+ clkdm_register_platform_funcs(&omap4_clkdm_operations);
+ clkdm_register_clkdms(clockdomains_dra7xx);
+ clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h
--- /dev/null
@@ -0,0 +1,2207 @@
+/*
+ * DRA7xx Clock Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
+
+/* Used by CM_L4PER2_DYNAMICDEP */
+#define DRA7XX_ATL_DYNDEP_SHIFT 6
+#define DRA7XX_ATL_DYNDEP_WIDTH 0x1
+#define DRA7XX_ATL_DYNDEP_MASK (1 << 6)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_DSP2_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_ATL_STATDEP_SHIFT 30
+#define DRA7XX_ATL_STATDEP_WIDTH 0x1
+#define DRA7XX_ATL_STATDEP_MASK (1 << 30)
+
+/*
+ * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR,
+ * CM_AUTOIDLE_DPLL_DSP, CM_AUTOIDLE_DPLL_EVE, CM_AUTOIDLE_DPLL_GMAC,
+ * CM_AUTOIDLE_DPLL_GPU, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
+ * CM_AUTOIDLE_DPLL_PCIE_REF, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_USB
+ */
+#define DRA7XX_AUTO_DPLL_MODE_SHIFT 0
+#define DRA7XX_AUTO_DPLL_MODE_WIDTH 0x3
+#define DRA7XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
+
+/* Used by CM_IPU2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP */
+#define DRA7XX_CAM_DYNDEP_SHIFT 9
+#define DRA7XX_CAM_DYNDEP_WIDTH 0x1
+#define DRA7XX_CAM_DYNDEP_MASK (1 << 9)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_CAM_STATDEP_SHIFT 9
+#define DRA7XX_CAM_STATDEP_WIDTH 0x1
+#define DRA7XX_CAM_STATDEP_MASK (1 << 9)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ABE_GICLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 16)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ADC_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_ADC_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ADC_GFCLK_MASK (1 << 10)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ADC_L3_GICLK_SHIFT 19
+#define DRA7XX_CLKACTIVITY_ADC_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ADC_L3_GICLK_MASK (1 << 19)
+
+/* Used by CM_ATL_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ATL_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_ATL_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ATL_GFCLK_MASK (1 << 9)
+
+/* Used by CM_ATL_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ATL_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_ATL_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ATL_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8)
+
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8)
+
+/* Used by CM_CUSTEFUSE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DCAN1_SYS_CLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_DCAN1_SYS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DCAN1_SYS_CLK_MASK (1 << 16)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DCAN2_SYS_CLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_DCAN2_SYS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DCAN2_SYS_CLK_MASK (1 << 15)
+
+/* Used by CM_DMA_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_DSP1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSP1_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_DSP1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSP1_GFCLK_MASK (1 << 8)
+
+/* Used by CM_DSP2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSP2_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_DSP2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSP2_GFCLK_MASK (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSS_L4_GICLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_DSS_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSS_L4_GICLK_MASK (1 << 15)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 16)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EMIF_DLL_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_EMIF_DLL_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EMIF_DLL_GCLK_MASK (1 << 9)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_EMIF_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10)
+
+/* Used by CM_EMU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8)
+
+/* Used by CM_EVE1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EVE1_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EVE1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EVE1_GFCLK_MASK (1 << 8)
+
+/* Used by CM_EVE2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EVE2_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EVE2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EVE2_GFCLK_MASK (1 << 8)
+
+/* Used by CM_EVE3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EVE3_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EVE3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EVE3_GFCLK_MASK (1 << 8)
+
+/* Used by CM_EVE4_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_EVE4_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_EVE4_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_EVE4_GFCLK_MASK (1 << 8)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GMAC_MAIN_CLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_GMAC_MAIN_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GMAC_MAIN_CLK_MASK (1 << 12)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GMAC_RFT_CLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_GMAC_RFT_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GMAC_RFT_CLK_MASK (1 << 11)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GMII_250MHZ_CLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_GMII_250MHZ_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GMII_250MHZ_CLK_MASK (1 << 8)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GPIO_GFCLK_SHIFT 24
+#define DRA7XX_CLKACTIVITY_GPIO_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GPIO_GFCLK_MASK (1 << 24)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10)
+
+/* Used by CM_GPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_GPU_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_GPU_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_GPU_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 17
+#define DRA7XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 17)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_HDMI_DPLL_CLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_HDMI_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_HDMI_DPLL_CLK_MASK (1 << 11)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 18
+#define DRA7XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 18)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_HSI_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 14)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ICSS_CLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_ICSS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ICSS_CLK_MASK (1 << 8)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_ICSS_IEP_CLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_ICSS_IEP_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_ICSS_IEP_CLK_MASK (1 << 14)
+
+/* Used by CM_IPU1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IPU1_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_IPU1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IPU1_GFCLK_MASK (1 << 8)
+
+/* Used by CM_IPU2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IPU2_GFCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_IPU2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IPU2_GFCLK_MASK (1 << 8)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IPU_96M_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_IPU_96M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IPU_96M_GFCLK_MASK (1 << 13)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IPU_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_IPU_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IPU_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_IVA_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_IVA_GCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_32K_GFCLK_SHIFT 23
+#define DRA7XX_CLKACTIVITY_L3INIT_32K_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_32K_GFCLK_MASK (1 << 23)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_480M_GFCLK_SHIFT 21
+#define DRA7XX_CLKACTIVITY_L3INIT_480M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_480M_GFCLK_MASK (1 << 21)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_960M_GFCLK_SHIFT 22
+#define DRA7XX_CLKACTIVITY_L3INIT_960M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_960M_GFCLK_MASK (1 << 22)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INIT_USB_LFPS_TX_GFCLK_MASK (1 << 10)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L3INSTR_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10)
+
+/* Used by CM_L3MAIN1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L3MAIN1_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L4_GICLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L3MAIN1_L4_GICLK_MASK (1 << 9)
+
+/* Used by CM_L4CFG_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4CFG_L3_GICLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_L4CFG_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4CFG_L3_GICLK_MASK (1 << 9)
+
+/* Used by CM_L4CFG_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4PER2_L3_GICLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_L4PER2_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4PER2_L3_GICLK_MASK (1 << 16)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4PER3_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L4PER3_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4PER3_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4PER_32K_GFCLK_SHIFT 27
+#define DRA7XX_CLKACTIVITY_L4PER_32K_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4PER_32K_GFCLK_MASK (1 << 27)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4PER_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L4PER_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4PER_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_L4SEC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_LVDSRX_96M_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_LVDSRX_96M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_LVDSRX_96M_GFCLK_MASK (1 << 12)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_LVDSRX_L4_GICLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_LVDSRX_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_LVDSRX_L4_GICLK_MASK (1 << 11)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKR_SHIFT 18
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKR_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKR_MASK (1 << 18)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKX_SHIFT 17
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP1_AHCLKX_MASK (1 << 17)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP1_AUX_GFCLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_MCASP1_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP1_AUX_GFCLK_MASK (1 << 16)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKR_SHIFT 18
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKR_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKR_MASK (1 << 18)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKX_SHIFT 17
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP2_AHCLKX_MASK (1 << 17)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP2_AUX_GFCLK_SHIFT 19
+#define DRA7XX_CLKACTIVITY_MCASP2_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP2_AUX_GFCLK_MASK (1 << 19)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP3_AHCLKX_SHIFT 20
+#define DRA7XX_CLKACTIVITY_MCASP3_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP3_AHCLKX_MASK (1 << 20)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP3_AUX_GFCLK_SHIFT 21
+#define DRA7XX_CLKACTIVITY_MCASP3_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP3_AUX_GFCLK_MASK (1 << 21)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP4_AHCLKX_SHIFT 22
+#define DRA7XX_CLKACTIVITY_MCASP4_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP4_AHCLKX_MASK (1 << 22)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP4_AUX_GFCLK_SHIFT 23
+#define DRA7XX_CLKACTIVITY_MCASP4_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP4_AUX_GFCLK_MASK (1 << 23)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP5_AHCLKX_SHIFT 25
+#define DRA7XX_CLKACTIVITY_MCASP5_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP5_AHCLKX_MASK (1 << 25)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP5_AUX_GFCLK_SHIFT 24
+#define DRA7XX_CLKACTIVITY_MCASP5_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP5_AUX_GFCLK_MASK (1 << 24)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP6_AHCLKX_SHIFT 26
+#define DRA7XX_CLKACTIVITY_MCASP6_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP6_AHCLKX_MASK (1 << 26)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP6_AUX_GFCLK_SHIFT 27
+#define DRA7XX_CLKACTIVITY_MCASP6_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP6_AUX_GFCLK_MASK (1 << 27)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP7_AHCLKX_SHIFT 28
+#define DRA7XX_CLKACTIVITY_MCASP7_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP7_AHCLKX_MASK (1 << 28)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP7_AUX_GFCLK_SHIFT 29
+#define DRA7XX_CLKACTIVITY_MCASP7_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP7_AUX_GFCLK_MASK (1 << 29)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP8_AHCLKX_SHIFT 30
+#define DRA7XX_CLKACTIVITY_MCASP8_AHCLKX_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP8_AHCLKX_MASK (1 << 30)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MCASP8_AUX_GFCLK_SHIFT 31
+#define DRA7XX_CLKACTIVITY_MCASP8_AUX_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MCASP8_AUX_GFCLK_MASK (1 << 31)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MLB_SHB_L3_GICLK_SHIFT 17
+#define DRA7XX_CLKACTIVITY_MLB_SHB_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MLB_SHB_L3_GICLK_MASK (1 << 17)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MLB_SPB_L4_GICLK_SHIFT 18
+#define DRA7XX_CLKACTIVITY_MLB_SPB_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MLB_SPB_L4_GICLK_MASK (1 << 18)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MLB_SYS_L3_GFCLK_SHIFT 19
+#define DRA7XX_CLKACTIVITY_MLB_SYS_L3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MLB_SYS_L3_GFCLK_MASK (1 << 19)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 15)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 16)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MMC3_GFCLK_SHIFT 22
+#define DRA7XX_CLKACTIVITY_MMC3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MMC3_GFCLK_MASK (1 << 22)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MMC4_GFCLK_SHIFT 23
+#define DRA7XX_CLKACTIVITY_MMC4_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MMC4_GFCLK_MASK (1 << 23)
+
+/* Used by CM_MPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_MPU_GCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_32K_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_PCIE_32K_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_32K_GFCLK_MASK (1 << 13)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_L3_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_PCIE_L3_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_L3_GICLK_MASK (1 << 8)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_DIV_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_DIV_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_DIV_GCLK_MASK (1 << 10)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_PHY_GCLK_MASK (1 << 9)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_REF_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_PCIE_REF_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_REF_GFCLK_MASK (1 << 11)
+
+/* Used by CM_PCIE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PCIE_SYS_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_PCIE_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PCIE_SYS_GFCLK_MASK (1 << 12)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 19
+#define DRA7XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 19)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_MASK (1 << 13)
+
+/* Renamed from CLKACTIVITY_PER_192M_GFCLK Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_25_25_SHIFT 25
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_25_25_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_192M_GFCLK_25_25_MASK (1 << 25)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 20
+#define DRA7XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 20)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 21
+#define DRA7XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 21)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_QSPI_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_QSPI_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_QSPI_GFCLK_MASK (1 << 12)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_RGMII_5MHZ_CLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_RGMII_5MHZ_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_RGMII_5MHZ_CLK_MASK (1 << 9)
+
+/* Used by CM_GMAC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_RMII_50MHZ_CLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_RMII_50MHZ_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_RMII_50MHZ_CLK_MASK (1 << 10)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_RTC_AUX_CLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_RTC_AUX_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_RTC_AUX_CLK_MASK (1 << 10)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_RTC_L4_GICLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_RTC_L4_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_RTC_L4_GICLK_MASK (1 << 8)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 24
+#define DRA7XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 24)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SDVENC_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_SDVENC_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SDVENC_GFCLK_MASK (1 << 14)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_DSPEVE_SYS_GFCLK_MASK (1 << 13)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_GPU_SYS_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_SR_GPU_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_GPU_SYS_GFCLK_MASK (1 << 10)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_IVAHD_SYS_GFCLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_SR_IVAHD_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_IVAHD_SYS_GFCLK_MASK (1 << 15)
+
+/* Used by CM_COREAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SYS_CLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15
+#define DRA7XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14
+#define DRA7XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER13_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_TIMER13_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER13_GFCLK_MASK (1 << 9)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER14_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_TIMER14_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER14_GFCLK_MASK (1 << 10)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER15_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_TIMER15_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER15_GFCLK_MASK (1 << 11)
+
+/* Used by CM_L4PER3_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER16_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_TIMER16_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER16_GFCLK_MASK (1 << 12)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER1_GFCLK_SHIFT 17
+#define DRA7XX_CLKACTIVITY_TIMER1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER1_GFCLK_MASK (1 << 17)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER5_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_TIMER5_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER5_GFCLK_MASK (1 << 9)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER6_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_TIMER6_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER6_GFCLK_MASK (1 << 10)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER7_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_TIMER7_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER7_GFCLK_MASK (1 << 11)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER8_GFCLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_TIMER8_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER8_GFCLK_MASK (1 << 12)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART10_GFCLK_SHIFT 18
+#define DRA7XX_CLKACTIVITY_UART10_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART10_GFCLK_MASK (1 << 18)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART1_GFCLK_SHIFT 15
+#define DRA7XX_CLKACTIVITY_UART1_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART1_GFCLK_MASK (1 << 15)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART2_GFCLK_SHIFT 16
+#define DRA7XX_CLKACTIVITY_UART2_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART2_GFCLK_MASK (1 << 16)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART3_GFCLK_SHIFT 17
+#define DRA7XX_CLKACTIVITY_UART3_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART3_GFCLK_MASK (1 << 17)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART4_GFCLK_SHIFT 18
+#define DRA7XX_CLKACTIVITY_UART4_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART4_GFCLK_MASK (1 << 18)
+
+/* Used by CM_L4PER_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART5_GFCLK_SHIFT 26
+#define DRA7XX_CLKACTIVITY_UART5_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART5_GFCLK_MASK (1 << 26)
+
+/* Used by CM_IPU_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART6_GFCLK_SHIFT 14
+#define DRA7XX_CLKACTIVITY_UART6_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART6_GFCLK_MASK (1 << 14)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART7_GFCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_UART7_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART7_GFCLK_MASK (1 << 9)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART8_GFCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_UART8_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART8_GFCLK_MASK (1 << 10)
+
+/* Used by CM_L4PER2_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_UART9_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_UART9_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_UART9_GFCLK_MASK (1 << 11)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 12)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 13)
+
+/* Used by CM_L3INIT_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 20
+#define DRA7XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 20)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIDEO1_DPLL_CLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_VIDEO1_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIDEO1_DPLL_CLK_MASK (1 << 10)
+
+/* Used by CM_DSS_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIDEO2_DPLL_CLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_VIDEO2_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIDEO2_DPLL_CLK_MASK (1 << 12)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIP1_GCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_VIP1_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIP1_GCLK_MASK (1 << 8)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIP2_GCLK_SHIFT 9
+#define DRA7XX_CLKACTIVITY_VIP2_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIP2_GCLK_MASK (1 << 9)
+
+/* Used by CM_CAM_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VIP3_GCLK_SHIFT 10
+#define DRA7XX_CLKACTIVITY_VIP3_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VIP3_GCLK_MASK (1 << 10)
+
+/* Used by CM_VPE_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_VPE_GCLK_SHIFT 8
+#define DRA7XX_CLKACTIVITY_VPE_GCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_VPE_GCLK_MASK (1 << 8)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12
+#define DRA7XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13
+#define DRA7XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13)
+
+/* Used by CM_WKUPAON_CLKSTCTRL */
+#define DRA7XX_CLKACTIVITY_WKUPAON_SYS_GFCLK_SHIFT 11
+#define DRA7XX_CLKACTIVITY_WKUPAON_SYS_GFCLK_WIDTH 0x1
+#define DRA7XX_CLKACTIVITY_WKUPAON_SYS_GFCLK_MASK (1 << 11)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_CLKDIV_BYPASS_SHIFT 8
+#define DRA7XX_CLKDIV_BYPASS_WIDTH 0x1
+#define DRA7XX_CLKDIV_BYPASS_MASK (1 << 8)
+
+/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
+#define DRA7XX_CLKEN_SRCOMP_FCLK_SHIFT 8
+#define DRA7XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1
+#define DRA7XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8)
+
+/* Used by CM_DIV_M2_DPLL_PCIE_REF */
+#define DRA7XX_CLKLDOST_SHIFT 10
+#define DRA7XX_CLKLDOST_WIDTH 0x1
+#define DRA7XX_CLKLDOST_MASK (1 << 10)
+
+/*
+ * Used by CM_CLKSEL_ABE_CLK_DIV, CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX,
+ * CM_CLKSEL_DSP_GFCLK_CLKOUTMUX, CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX,
+ * CM_CLKSEL_EMU_CLK_CLKOUTMUX, CM_CLKSEL_EVE_GFCLK_CLKOUTMUX,
+ * CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX, CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX,
+ * CM_CLKSEL_GPU_GCLK_CLKOUTMUX, CM_CLKSEL_HDMI_CLK_CLKOUTMUX,
+ * CM_CLKSEL_HDMI_MCASP_AUX, CM_CLKSEL_HDMI_TIMER,
+ * CM_CLKSEL_IVA_GCLK_CLKOUTMUX, CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX,
+ * CM_CLKSEL_MLBP_MCASP, CM_CLKSEL_MLB_MCASP, CM_CLKSEL_MPU_GCLK_CLKOUTMUX,
+ * CM_CLKSEL_PCIE1_CLK_CLKOUTMUX, CM_CLKSEL_PCIE2_CLK_CLKOUTMUX,
+ * CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX, CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX,
+ * CM_CLKSEL_SATA_CLK_CLKOUTMUX, CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX,
+ * CM_CLKSEL_SYS_CLK1_CLKOUTMUX, CM_CLKSEL_SYS_CLK2_CLKOUTMUX,
+ * CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX, CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX,
+ * CM_CLKSEL_VIDEO1_MCASP_AUX, CM_CLKSEL_VIDEO1_TIMER,
+ * CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX, CM_CLKSEL_VIDEO2_MCASP_AUX,
+ * CM_CLKSEL_VIDEO2_TIMER
+ */
+#define DRA7XX_CLKSEL_SHIFT 0
+#define DRA7XX_CLKSEL_WIDTH 0x3
+#define DRA7XX_CLKSEL_MASK (0x7 << 0)
+
+/*
+ * Renamed from CLKSEL Used by CM_CLKSEL_ABE_24M, CM_CLKSEL_ABE_GICLK_DIV,
+ * CM_CLKSEL_ABE_LP_CLK, CM_CLKSEL_ABE_PLL_BYPAS, CM_CLKSEL_ABE_PLL_REF,
+ * CM_CLKSEL_ABE_PLL_SYS, CM_CLKSEL_ABE_SYS, CM_CLKSEL_AESS_FCLK_DIV,
+ * CM_CLKSEL_EVE_CLK, CM_CLKSEL_HDMI_PLL_SYS, CM_CLKSEL_MCASP_SYS,
+ * CM_CLKSEL_SYSCLK1, CM_CLKSEL_SYS_CLK1_32K, CM_CLKSEL_TIMER_SYS,
+ * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_VIDEO1_PLL_SYS, CM_CLKSEL_VIDEO2_PLL_SYS,
+ * CM_CLKSEL_WKUPAON
+ */
+#define DRA7XX_CLKSEL_0_0_SHIFT 0
+#define DRA7XX_CLKSEL_0_0_WIDTH 0x1
+#define DRA7XX_CLKSEL_0_0_MASK (1 << 0)
+
+/*
+ * Renamed from CLKSEL Used by CM_CAM_VIP1_CLKCTRL, CM_CAM_VIP2_CLKCTRL,
+ * CM_CAM_VIP3_CLKCTRL, CM_IPU1_IPU1_CLKCTRL, CM_IPU_UART6_CLKCTRL,
+ * CM_L4PER2_UART7_CLKCTRL, CM_L4PER2_UART8_CLKCTRL, CM_L4PER2_UART9_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4PER_UART5_CLKCTRL, CM_WKUPAON_DCAN1_CLKCTRL,
+ * CM_WKUPAON_UART10_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_24_24_SHIFT 24
+#define DRA7XX_CLKSEL_24_24_WIDTH 0x1
+#define DRA7XX_CLKSEL_24_24_MASK (1 << 24)
+
+/*
+ * Renamed from CLKSEL Used by CM_IPU_TIMER5_CLKCTRL, CM_IPU_TIMER6_CLKCTRL,
+ * CM_IPU_TIMER7_CLKCTRL, CM_IPU_TIMER8_CLKCTRL, CM_L4PER3_TIMER13_CLKCTRL,
+ * CM_L4PER3_TIMER14_CLKCTRL, CM_L4PER3_TIMER15_CLKCTRL,
+ * CM_L4PER3_TIMER16_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
+ * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
+ * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_24_27_SHIFT 24
+#define DRA7XX_CLKSEL_24_27_WIDTH 0x4
+#define DRA7XX_CLKSEL_24_27_MASK (0xf << 24)
+
+/*
+ * Renamed from CLKSEL Used by CM_BYPCLK_DPLL_DSP, CM_BYPCLK_DPLL_EVE,
+ * CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU, CM_CLKSEL_ADC_GFCLK
+ */
+#define DRA7XX_CLKSEL_0_1_SHIFT 0
+#define DRA7XX_CLKSEL_0_1_WIDTH 0x2
+#define DRA7XX_CLKSEL_0_1_MASK (0x3 << 0)
+
+/*
+ * Renamed from CLKSEL Used by CM_CLKSEL_CLKOUTMUX0, CM_CLKSEL_CLKOUTMUX1,
+ * CM_CLKSEL_CLKOUTMUX2
+ */
+#define DRA7XX_CLKSEL_0_4_SHIFT 0
+#define DRA7XX_CLKSEL_0_4_WIDTH 0x5
+#define DRA7XX_CLKSEL_0_4_MASK (0x1f << 0)
+
+/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
+#define DRA7XX_CLKSEL_24_25_SHIFT 24
+#define DRA7XX_CLKSEL_24_25_WIDTH 0x2
+#define DRA7XX_CLKSEL_24_25_MASK (0x3 << 24)
+
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define DRA7XX_CLKSEL_ABE_DIV_MODE_SHIFT 26
+#define DRA7XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
+#define DRA7XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
+
+/* Used by CM_IPU_MCASP1_CLKCTRL, CM_L4PER2_MCASP2_CLKCTRL */
+#define DRA7XX_CLKSEL_AHCLKR_SHIFT 28
+#define DRA7XX_CLKSEL_AHCLKR_WIDTH 0x4
+#define DRA7XX_CLKSEL_AHCLKR_MASK (0xf << 28)
+
+/*
+ * Used by CM_IPU_MCASP1_CLKCTRL, CM_L4PER2_MCASP2_CLKCTRL,
+ * CM_L4PER2_MCASP3_CLKCTRL, CM_L4PER2_MCASP4_CLKCTRL,
+ * CM_L4PER2_MCASP5_CLKCTRL, CM_L4PER2_MCASP6_CLKCTRL,
+ * CM_L4PER2_MCASP7_CLKCTRL, CM_L4PER2_MCASP8_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_AHCLKX_SHIFT 24
+#define DRA7XX_CLKSEL_AHCLKX_WIDTH 0x4
+#define DRA7XX_CLKSEL_AHCLKX_MASK (0xf << 24)
+
+/*
+ * Used by CM_IPU_MCASP1_CLKCTRL, CM_L4PER2_MCASP2_CLKCTRL,
+ * CM_L4PER2_MCASP3_CLKCTRL, CM_L4PER2_MCASP4_CLKCTRL,
+ * CM_L4PER2_MCASP5_CLKCTRL, CM_L4PER2_MCASP6_CLKCTRL,
+ * CM_L4PER2_MCASP7_CLKCTRL, CM_L4PER2_MCASP8_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_AUX_CLK_SHIFT 22
+#define DRA7XX_CLKSEL_AUX_CLK_WIDTH 0x2
+#define DRA7XX_CLKSEL_AUX_CLK_MASK (0x3 << 22)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define DRA7XX_CLKSEL_CORE_CLK_SHIFT 24
+#define DRA7XX_CLKSEL_CORE_CLK_WIDTH 0x2
+#define DRA7XX_CLKSEL_CORE_CLK_MASK (0x3 << 24)
+
+/*
+ * Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L4PER2_QSPI_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_DIV_SHIFT 25
+#define DRA7XX_CLKSEL_DIV_WIDTH 0x2
+#define DRA7XX_CLKSEL_DIV_MASK (0x3 << 25)
+
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define DRA7XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define DRA7XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2
+#define DRA7XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24)
+
+/* Used by CM_GPU_GPU_CLKCTRL */
+#define DRA7XX_CLKSEL_HYD_CLK_SHIFT 26
+#define DRA7XX_CLKSEL_HYD_CLK_WIDTH 0x2
+#define DRA7XX_CLKSEL_HYD_CLK_MASK (0x3 << 26)
+
+/* Used by CM_CLKSEL_CORE */
+#define DRA7XX_CLKSEL_L3_SHIFT 4
+#define DRA7XX_CLKSEL_L3_WIDTH 0x1
+#define DRA7XX_CLKSEL_L3_MASK (1 << 4)
+
+/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
+#define DRA7XX_CLKSEL_L3_1_1_SHIFT 1
+#define DRA7XX_CLKSEL_L3_1_1_WIDTH 0x1
+#define DRA7XX_CLKSEL_L3_1_1_MASK (1 << 1)
+
+/* Used by CM_CLKSEL_CORE */
+#define DRA7XX_CLKSEL_L4_SHIFT 8
+#define DRA7XX_CLKSEL_L4_WIDTH 0x1
+#define DRA7XX_CLKSEL_L4_MASK (1 << 8)
+
+/* Used by CM_EMIF_EMIF1_CLKCTRL */
+#define DRA7XX_CLKSEL_LL_SHIFT 24
+#define DRA7XX_CLKSEL_LL_WIDTH 0x1
+#define DRA7XX_CLKSEL_LL_MASK (1 << 24)
+
+/* Used by CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL */
+#define DRA7XX_CLKSEL_MUX_SHIFT 24
+#define DRA7XX_CLKSEL_MUX_WIDTH 0x1
+#define DRA7XX_CLKSEL_MUX_MASK (1 << 24)
+
+/* Used by CM_CLKSEL_ABE */
+#define DRA7XX_CLKSEL_OPP_SHIFT 0
+#define DRA7XX_CLKSEL_OPP_WIDTH 0x2
+#define DRA7XX_CLKSEL_OPP_MASK (0x3 << 0)
+
+/* Used by CM_GMAC_GMAC_CLKCTRL */
+#define DRA7XX_CLKSEL_REF_SHIFT 24
+#define DRA7XX_CLKSEL_REF_WIDTH 0x1
+#define DRA7XX_CLKSEL_REF_MASK (1 << 24)
+
+/* Used by CM_GMAC_GMAC_CLKCTRL */
+#define DRA7XX_CLKSEL_RFT_SHIFT 25
+#define DRA7XX_CLKSEL_RFT_WIDTH 0x3
+#define DRA7XX_CLKSEL_RFT_MASK (0x7 << 25)
+
+/*
+ * Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L4PER2_QSPI_CLKCTRL
+ */
+#define DRA7XX_CLKSEL_SOURCE_SHIFT 24
+#define DRA7XX_CLKSEL_SOURCE_WIDTH 0x1
+#define DRA7XX_CLKSEL_SOURCE_MASK (1 << 24)
+
+/* Used by CM_ATL_ATL_CLKCTRL */
+#define DRA7XX_CLKSEL_SOURCE1_SHIFT 24
+#define DRA7XX_CLKSEL_SOURCE1_WIDTH 0x2
+#define DRA7XX_CLKSEL_SOURCE1_MASK (0x3 << 24)
+
+/* Used by CM_ATL_ATL_CLKCTRL */
+#define DRA7XX_CLKSEL_SOURCE2_SHIFT 26
+#define DRA7XX_CLKSEL_SOURCE2_WIDTH 0x2
+#define DRA7XX_CLKSEL_SOURCE2_MASK (0x3 << 26)
+
+/*
+ * Used by CM_CLKVCOLDO_APLL_PCIE, CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_DDR,
+ * CM_DIV_H11_DPLL_GMAC, CM_DIV_H11_DPLL_PER, CM_DIV_H12_DPLL_CORE,
+ * CM_DIV_H12_DPLL_GMAC, CM_DIV_H12_DPLL_PER, CM_DIV_H13_DPLL_CORE,
+ * CM_DIV_H13_DPLL_GMAC, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_GMAC, CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE,
+ * CM_DIV_H22_DPLL_CORE, CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE,
+ * CM_DIV_M2_APLL_PCIE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
+ * CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DSP, CM_DIV_M2_DPLL_EVE,
+ * CM_DIV_M2_DPLL_GMAC, CM_DIV_M2_DPLL_GPU, CM_DIV_M2_DPLL_IVA,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PCIE_REF, CM_DIV_M2_DPLL_PER,
+ * CM_DIV_M2_DPLL_USB, CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_DDR, CM_DIV_M3_DPLL_DSP, CM_DIV_M3_DPLL_EVE,
+ * CM_DIV_M3_DPLL_GMAC, CM_DIV_M3_DPLL_GPU, CM_DIV_M3_DPLL_IVA,
+ * CM_DIV_M3_DPLL_PER
+ */
+#define DRA7XX_CLKST_SHIFT 9
+#define DRA7XX_CLKST_WIDTH 0x1
+#define DRA7XX_CLKST_MASK (1 << 9)
+
+/*
+ * Used by CM_ATL_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_COREAON_CLKSTCTRL,
+ * CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL, CM_DSP1_CLKSTCTRL,
+ * CM_DSP2_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
+ * CM_EVE1_CLKSTCTRL, CM_EVE2_CLKSTCTRL, CM_EVE3_CLKSTCTRL, CM_EVE4_CLKSTCTRL,
+ * CM_GMAC_CLKSTCTRL, CM_GPU_CLKSTCTRL, CM_IPU1_CLKSTCTRL, CM_IPU2_CLKSTCTRL,
+ * CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
+ * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L4CFG_CLKSTCTRL,
+ * CM_L4PER2_CLKSTCTRL, CM_L4PER3_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
+ * CM_L4SEC_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_PCIE_CLKSTCTRL, CM_RTC_CLKSTCTRL,
+ * CM_VPE_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
+ */
+#define DRA7XX_CLKTRCTRL_SHIFT 0
+#define DRA7XX_CLKTRCTRL_WIDTH 0x2
+#define DRA7XX_CLKTRCTRL_MASK (0x3 << 0)
+
+/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
+#define DRA7XX_CLKX2ST_SHIFT 11
+#define DRA7XX_CLKX2ST_WIDTH 0x1
+#define DRA7XX_CLKX2ST_MASK (1 << 11)
+
+/* Used by CM_CLKVCOLDO_APLL_PCIE */
+#define DRA7XX_CLK_DIVST_SHIFT 10
+#define DRA7XX_CLK_DIVST_WIDTH 0x1
+#define DRA7XX_CLK_DIVST_MASK (1 << 10)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define DRA7XX_COREAON_DYNDEP_SHIFT 16
+#define DRA7XX_COREAON_DYNDEP_WIDTH 0x1
+#define DRA7XX_COREAON_DYNDEP_MASK (1 << 16)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_DSP2_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_COREAON_STATDEP_SHIFT 16
+#define DRA7XX_COREAON_STATDEP_WIDTH 0x1
+#define DRA7XX_COREAON_STATDEP_MASK (1 << 16)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define DRA7XX_CUSTEFUSE_DYNDEP_SHIFT 17
+#define DRA7XX_CUSTEFUSE_DYNDEP_WIDTH 0x1
+#define DRA7XX_CUSTEFUSE_DYNDEP_MASK (1 << 17)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_DSP2_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_CUSTEFUSE_STATDEP_SHIFT 17
+#define DRA7XX_CUSTEFUSE_STATDEP_WIDTH 0x1
+#define DRA7XX_CUSTEFUSE_STATDEP_MASK (1 << 17)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_CUSTOM_SHIFT 6
+#define DRA7XX_CUSTOM_WIDTH 0x2
+#define DRA7XX_CUSTOM_MASK (0x3 << 6)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR,
+ * CM_CLKSEL_DPLL_DSP, CM_CLKSEL_DPLL_EVE, CM_CLKSEL_DPLL_GMAC,
+ * CM_CLKSEL_DPLL_GPU, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU,
+ * CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_USB
+ */
+#define DRA7XX_DCC_EN_SHIFT 22
+#define DRA7XX_DCC_EN_WIDTH 0x1
+#define DRA7XX_DCC_EN_MASK (1 << 22)
+
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
+ * CM_SSC_DELTAMSTEP_DPLL_DDR, CM_SSC_DELTAMSTEP_DPLL_DSP,
+ * CM_SSC_DELTAMSTEP_DPLL_EVE, CM_SSC_DELTAMSTEP_DPLL_GMAC,
+ * CM_SSC_DELTAMSTEP_DPLL_GPU, CM_SSC_DELTAMSTEP_DPLL_IVA,
+ * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER
+ */
+#define DRA7XX_DELTAMSTEP_SHIFT 0
+#define DRA7XX_DELTAMSTEP_WIDTH 0x14
+#define DRA7XX_DELTAMSTEP_MASK (0xfffff << 0)
+
+/*
+ * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_PCIE_REF,
+ * CM_SSC_DELTAMSTEP_DPLL_USB
+ */
+#define DRA7XX_DELTAMSTEP_0_20_SHIFT 0
+#define DRA7XX_DELTAMSTEP_0_20_WIDTH 0x15
+#define DRA7XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
+
+/*
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDR,
+ * CM_DIV_M2_DPLL_DSP, CM_DIV_M2_DPLL_EVE, CM_DIV_M2_DPLL_GMAC,
+ * CM_DIV_M2_DPLL_GPU, CM_DIV_M2_DPLL_IVA, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
+ * CM_DIV_M3_DPLL_DDR, CM_DIV_M3_DPLL_DSP, CM_DIV_M3_DPLL_EVE,
+ * CM_DIV_M3_DPLL_GMAC, CM_DIV_M3_DPLL_GPU, CM_DIV_M3_DPLL_IVA,
+ * CM_DIV_M3_DPLL_PER
+ */
+#define DRA7XX_DIVHS_SHIFT 0
+#define DRA7XX_DIVHS_WIDTH 0x5
+#define DRA7XX_DIVHS_MASK (0x1f << 0)
+
+/*
+ * Renamed from DIVHS Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_DDR,
+ * CM_DIV_H11_DPLL_GMAC, CM_DIV_H11_DPLL_PER, CM_DIV_H12_DPLL_CORE,
+ * CM_DIV_H12_DPLL_GMAC, CM_DIV_H12_DPLL_PER, CM_DIV_H13_DPLL_CORE,
+ * CM_DIV_H13_DPLL_GMAC, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
+ * CM_DIV_H14_DPLL_GMAC, CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE,
+ * CM_DIV_H22_DPLL_CORE, CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
+ */
+#define DRA7XX_DIVHS_0_5_SHIFT 0
+#define DRA7XX_DIVHS_0_5_WIDTH 0x6
+#define DRA7XX_DIVHS_0_5_MASK (0x3f << 0)
+
+/*
+ * Renamed from DIVHS Used by CM_DIV_M2_APLL_PCIE, CM_DIV_M2_DPLL_PCIE_REF,
+ * CM_DIV_M2_DPLL_USB
+ */
+#define DRA7XX_DIVHS_0_6_SHIFT 0
+#define DRA7XX_DIVHS_0_6_WIDTH 0x7
+#define DRA7XX_DIVHS_0_6_MASK (0x7f << 0)
+
+/* Used by CM_DLL_CTRL */
+#define DRA7XX_DLL_OVERRIDE_SHIFT 0
+#define DRA7XX_DLL_OVERRIDE_WIDTH 0x1
+#define DRA7XX_DLL_OVERRIDE_MASK (1 << 0)
+
+/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_DLL_OVERRIDE_2_2_SHIFT 2
+#define DRA7XX_DLL_OVERRIDE_2_2_WIDTH 0x1
+#define DRA7XX_DLL_OVERRIDE_2_2_MASK (1 << 2)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_DLL_RESET_SHIFT 3
+#define DRA7XX_DLL_RESET_WIDTH 0x1
+#define DRA7XX_DLL_RESET_MASK (1 << 3)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR,
+ * CM_CLKSEL_DPLL_DSP, CM_CLKSEL_DPLL_EVE, CM_CLKSEL_DPLL_GMAC,
+ * CM_CLKSEL_DPLL_GPU, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU,
+ * CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_USB
+ */
+#define DRA7XX_DPLL_BYP_CLKSEL_SHIFT 23
+#define DRA7XX_DPLL_BYP_CLKSEL_WIDTH 0x1
+#define DRA7XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
+
+/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_GMAC, CM_CLKSEL_DPLL_GPU */
+#define DRA7XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
+#define DRA7XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
+#define DRA7XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define DRA7XX_DPLL_CORE_H12_DIV_SHIFT 2
+#define DRA7XX_DPLL_CORE_H12_DIV_WIDTH 0x6
+#define DRA7XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_DPLL_DDR_DPLL_EN_SHIFT 16
+#define DRA7XX_DPLL_DDR_DPLL_EN_WIDTH 0x3
+#define DRA7XX_DPLL_DDR_DPLL_EN_MASK (0x7 << 16)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_DPLL_DDR_M2_DIV_SHIFT 11
+#define DRA7XX_DPLL_DDR_M2_DIV_WIDTH 0x5
+#define DRA7XX_DPLL_DDR_M2_DIV_MASK (0x1f << 11)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR,
+ * CM_CLKSEL_DPLL_DSP, CM_CLKSEL_DPLL_EVE, CM_CLKSEL_DPLL_GMAC,
+ * CM_CLKSEL_DPLL_GPU, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU,
+ * CM_CLKSEL_DPLL_PER
+ */
+#define DRA7XX_DPLL_DIV_SHIFT 0
+#define DRA7XX_DPLL_DIV_WIDTH 0x7
+#define DRA7XX_DPLL_DIV_MASK (0x7f << 0)
+
+/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_USB */
+#define DRA7XX_DPLL_DIV_PCIE_REF_SHIFT 0
+#define DRA7XX_DPLL_DIV_PCIE_REF_WIDTH 0x8
+#define DRA7XX_DPLL_DIV_PCIE_REF_MASK (0xff << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PER
+ */
+#define DRA7XX_DPLL_DRIFTGUARD_EN_SHIFT 8
+#define DRA7XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1
+#define DRA7XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PCIE_REF, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB
+ */
+#define DRA7XX_DPLL_EN_SHIFT 0
+#define DRA7XX_DPLL_EN_WIDTH 0x3
+#define DRA7XX_DPLL_EN_MASK (0x7 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PER
+ */
+#define DRA7XX_DPLL_LPMODE_EN_SHIFT 10
+#define DRA7XX_DPLL_LPMODE_EN_WIDTH 0x1
+#define DRA7XX_DPLL_LPMODE_EN_MASK (1 << 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR,
+ * CM_CLKSEL_DPLL_DSP, CM_CLKSEL_DPLL_EVE, CM_CLKSEL_DPLL_GMAC,
+ * CM_CLKSEL_DPLL_GPU, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU,
+ * CM_CLKSEL_DPLL_PER
+ */
+#define DRA7XX_DPLL_MULT_SHIFT 8
+#define DRA7XX_DPLL_MULT_WIDTH 0xb
+#define DRA7XX_DPLL_MULT_MASK (0x7ff << 8)
+
+/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_USB */
+#define DRA7XX_DPLL_MULT_8_19_SHIFT 8
+#define DRA7XX_DPLL_MULT_8_19_WIDTH 0xc
+#define DRA7XX_DPLL_MULT_8_19_MASK (0xfff << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PER
+ */
+#define DRA7XX_DPLL_REGM4XEN_SHIFT 11
+#define DRA7XX_DPLL_REGM4XEN_WIDTH 0x1
+#define DRA7XX_DPLL_REGM4XEN_MASK (1 << 11)
+
+/* Used by CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_USB */
+#define DRA7XX_DPLL_SD_DIV_SHIFT 24
+#define DRA7XX_DPLL_SD_DIV_WIDTH 0x8
+#define DRA7XX_DPLL_SD_DIV_MASK (0xff << 24)
+
+/* Used by CM_CLKSEL_DPLL_PCIE_REF, CM_CLKSEL_DPLL_USB */
+#define DRA7XX_DPLL_SELFREQDCO_SHIFT 21
+#define DRA7XX_DPLL_SELFREQDCO_WIDTH 0x1
+#define DRA7XX_DPLL_SELFREQDCO_MASK (1 << 21)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PCIE_REF, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB
+ */
+#define DRA7XX_DPLL_SSC_ACK_SHIFT 13
+#define DRA7XX_DPLL_SSC_ACK_WIDTH 0x1
+#define DRA7XX_DPLL_SSC_ACK_MASK (1 << 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PCIE_REF, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB
+ */
+#define DRA7XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
+#define DRA7XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
+#define DRA7XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR,
+ * CM_CLKMODE_DPLL_DSP, CM_CLKMODE_DPLL_EVE, CM_CLKMODE_DPLL_GMAC,
+ * CM_CLKMODE_DPLL_GPU, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU,
+ * CM_CLKMODE_DPLL_PCIE_REF, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB
+ */
+#define DRA7XX_DPLL_SSC_EN_SHIFT 12
+#define DRA7XX_DPLL_SSC_EN_WIDTH 0x1
+#define DRA7XX_DPLL_SSC_EN_MASK (1 << 12)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_DSP1_DYNDEP_SHIFT 1
+#define DRA7XX_DSP1_DYNDEP_WIDTH 0x1
+#define DRA7XX_DSP1_DYNDEP_MASK (1 << 1)
+
+/*
+ * Used by CM_DSP2_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP,
+ * CM_L4PER2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_DSP1_STATDEP_SHIFT 1
+#define DRA7XX_DSP1_STATDEP_WIDTH 0x1
+#define DRA7XX_DSP1_STATDEP_MASK (1 << 1)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_DSP2_DYNDEP_SHIFT 20
+#define DRA7XX_DSP2_DYNDEP_WIDTH 0x1
+#define DRA7XX_DSP2_DYNDEP_MASK (1 << 20)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP,
+ * CM_L4PER2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_DSP2_STATDEP_SHIFT 18
+#define DRA7XX_DSP2_STATDEP_WIDTH 0x1
+#define DRA7XX_DSP2_STATDEP_MASK (1 << 18)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define DRA7XX_DSS_DYNDEP_SHIFT 8
+#define DRA7XX_DSS_DYNDEP_WIDTH 0x1
+#define DRA7XX_DSS_DYNDEP_MASK (1 << 8)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_DSS_STATDEP_SHIFT 8
+#define DRA7XX_DSS_STATDEP_WIDTH 0x1
+#define DRA7XX_DSS_STATDEP_MASK (1 << 8)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP */
+#define DRA7XX_EMIF_DYNDEP_SHIFT 4
+#define DRA7XX_EMIF_DYNDEP_WIDTH 0x1
+#define DRA7XX_EMIF_DYNDEP_MASK (1 << 4)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_DSS_STATICDEP, CM_EVE1_STATICDEP, CM_EVE2_STATICDEP,
+ * CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_GMAC_STATICDEP, CM_GPU_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_IVA_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP, CM_VPE_STATICDEP
+ */
+#define DRA7XX_EMIF_STATDEP_SHIFT 4
+#define DRA7XX_EMIF_STATDEP_WIDTH 0x1
+#define DRA7XX_EMIF_STATDEP_MASK (1 << 4)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_EVE1_DYNDEP_SHIFT 28
+#define DRA7XX_EVE1_DYNDEP_WIDTH 0x1
+#define DRA7XX_EVE1_DYNDEP_MASK (1 << 28)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_EVE2_STATICDEP, CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_EVE1_STATDEP_SHIFT 19
+#define DRA7XX_EVE1_STATDEP_WIDTH 0x1
+#define DRA7XX_EVE1_STATDEP_MASK (1 << 19)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_EVE2_DYNDEP_SHIFT 29
+#define DRA7XX_EVE2_DYNDEP_WIDTH 0x1
+#define DRA7XX_EVE2_DYNDEP_MASK (1 << 29)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_EVE1_STATICDEP, CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_EVE2_STATDEP_SHIFT 20
+#define DRA7XX_EVE2_STATDEP_WIDTH 0x1
+#define DRA7XX_EVE2_STATDEP_MASK (1 << 20)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_EVE3_DYNDEP_SHIFT 30
+#define DRA7XX_EVE3_DYNDEP_WIDTH 0x1
+#define DRA7XX_EVE3_DYNDEP_MASK (1 << 30)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_EVE1_STATICDEP, CM_EVE2_STATICDEP, CM_EVE4_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_EVE3_STATDEP_SHIFT 21
+#define DRA7XX_EVE3_STATDEP_WIDTH 0x1
+#define DRA7XX_EVE3_STATDEP_MASK (1 << 21)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_EVE4_DYNDEP_SHIFT 31
+#define DRA7XX_EVE4_DYNDEP_WIDTH 0x1
+#define DRA7XX_EVE4_DYNDEP_MASK (1 << 31)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_EVE1_STATICDEP, CM_EVE2_STATICDEP, CM_EVE3_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_EVE4_STATDEP_SHIFT 22
+#define DRA7XX_EVE4_STATDEP_WIDTH 0x1
+#define DRA7XX_EVE4_STATDEP_MASK (1 << 22)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
+#define DRA7XX_FREQ_UPDATE_SHIFT 0
+#define DRA7XX_FREQ_UPDATE_WIDTH 0x1
+#define DRA7XX_FREQ_UPDATE_MASK (1 << 0)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_FUNC_SHIFT 16
+#define DRA7XX_FUNC_WIDTH 0xc
+#define DRA7XX_FUNC_MASK (0xfff << 16)
+
+/* Used by CM_L4PER2_DYNAMICDEP */
+#define DRA7XX_GMAC_DYNDEP_SHIFT 22
+#define DRA7XX_GMAC_DYNDEP_WIDTH 0x1
+#define DRA7XX_GMAC_DYNDEP_MASK (1 << 22)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_GMAC_STATDEP_SHIFT 25
+#define DRA7XX_GMAC_STATDEP_WIDTH 0x1
+#define DRA7XX_GMAC_STATDEP_MASK (1 << 25)
+
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
+#define DRA7XX_GPMC_FREQ_UPDATE_SHIFT 0
+#define DRA7XX_GPMC_FREQ_UPDATE_WIDTH 0x1
+#define DRA7XX_GPMC_FREQ_UPDATE_MASK (1 << 0)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_GPU_DYNDEP_SHIFT 10
+#define DRA7XX_GPU_DYNDEP_WIDTH 0x1
+#define DRA7XX_GPU_DYNDEP_MASK (1 << 10)
+
+/*
+ * Used by CM_DSP1_STATICDEP, CM_DSP2_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_GPU_STATDEP_SHIFT 10
+#define DRA7XX_GPU_STATDEP_WIDTH 0x1
+#define DRA7XX_GPU_STATDEP_MASK (1 << 10)
+
+/*
+ * Used by CM_ATL_ATL_CLKCTRL, CM_CAM_CSI1_CLKCTRL, CM_CAM_CSI2_CLKCTRL,
+ * CM_CAM_LVDSRX_CLKCTRL, CM_CAM_VIP1_CLKCTRL, CM_CAM_VIP2_CLKCTRL,
+ * CM_CAM_VIP3_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL, CM_COREAON_SMARTREFLEX_GPU_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP1_DSP1_CLKCTRL, CM_DSP2_DSP2_CLKCTRL, CM_DSS_BB2D_CLKCTRL,
+ * CM_DSS_DSS_CLKCTRL, CM_DSS_SDVENC_CLKCTRL, CM_EMIF_DMM_CLKCTRL,
+ * CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, CM_EMIF_EMIF_OCP_FW_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_EVE1_EVE1_CLKCTRL,
+ * CM_EVE2_EVE2_CLKCTRL, CM_EVE3_EVE3_CLKCTRL, CM_EVE4_EVE4_CLKCTRL,
+ * CM_GMAC_GMAC_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU1_IPU1_CLKCTRL,
+ * CM_IPU2_IPU2_CLKCTRL, CM_IPU_I2C5_CLKCTRL, CM_IPU_MCASP1_CLKCTRL,
+ * CM_IPU_TIMER5_CLKCTRL, CM_IPU_TIMER6_CLKCTRL, CM_IPU_TIMER7_CLKCTRL,
+ * CM_IPU_TIMER8_CLKCTRL, CM_IPU_UART6_CLKCTRL, CM_IVA_IVA_CLKCTRL,
+ * CM_IVA_SL2_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
+ * CM_L3INIT_MLB_SS_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_USB_OTG_SS1_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS2_CLKCTRL, CM_L3INIT_USB_OTG_SS3_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS4_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_2_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_GPMC_CLKCTRL, CM_L3MAIN1_L3_MAIN_1_CLKCTRL,
+ * CM_L3MAIN1_MMU_EDMA_CLKCTRL, CM_L3MAIN1_OCMC_RAM1_CLKCTRL,
+ * CM_L3MAIN1_OCMC_RAM2_CLKCTRL, CM_L3MAIN1_OCMC_RAM3_CLKCTRL,
+ * CM_L3MAIN1_OCMC_ROM_CLKCTRL, CM_L3MAIN1_SPARE_CME_CLKCTRL,
+ * CM_L3MAIN1_SPARE_HDMI_CLKCTRL, CM_L3MAIN1_SPARE_ICM_CLKCTRL,
+ * CM_L3MAIN1_SPARE_IVA2_CLKCTRL, CM_L3MAIN1_SPARE_SATA2_CLKCTRL,
+ * CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL, CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL,
+ * CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL, CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL,
+ * CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL, CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL,
+ * CM_L3MAIN1_TPCC_CLKCTRL, CM_L3MAIN1_TPTC1_CLKCTRL, CM_L3MAIN1_TPTC2_CLKCTRL,
+ * CM_L3MAIN1_VCP1_CLKCTRL, CM_L3MAIN1_VCP2_CLKCTRL,
+ * CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX10_CLKCTRL, CM_L4CFG_MAILBOX11_CLKCTRL,
+ * CM_L4CFG_MAILBOX12_CLKCTRL, CM_L4CFG_MAILBOX13_CLKCTRL,
+ * CM_L4CFG_MAILBOX1_CLKCTRL, CM_L4CFG_MAILBOX2_CLKCTRL,
+ * CM_L4CFG_MAILBOX3_CLKCTRL, CM_L4CFG_MAILBOX4_CLKCTRL,
+ * CM_L4CFG_MAILBOX5_CLKCTRL, CM_L4CFG_MAILBOX6_CLKCTRL,
+ * CM_L4CFG_MAILBOX7_CLKCTRL, CM_L4CFG_MAILBOX8_CLKCTRL,
+ * CM_L4CFG_MAILBOX9_CLKCTRL, CM_L4CFG_OCP2SCP2_CLKCTRL,
+ * CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL,
+ * CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL,
+ * CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL, CM_L4CFG_SPINLOCK_CLKCTRL,
+ * CM_L4PER2_DCAN2_CLKCTRL, CM_L4PER2_L4_PER2_CLKCTRL,
+ * CM_L4PER2_MCASP2_CLKCTRL, CM_L4PER2_MCASP3_CLKCTRL,
+ * CM_L4PER2_MCASP4_CLKCTRL, CM_L4PER2_MCASP5_CLKCTRL,
+ * CM_L4PER2_MCASP6_CLKCTRL, CM_L4PER2_MCASP7_CLKCTRL,
+ * CM_L4PER2_MCASP8_CLKCTRL, CM_L4PER2_PRUSS1_CLKCTRL,
+ * CM_L4PER2_PRUSS2_CLKCTRL, CM_L4PER2_PWMSS1_CLKCTRL,
+ * CM_L4PER2_PWMSS2_CLKCTRL, CM_L4PER2_PWMSS3_CLKCTRL, CM_L4PER2_QSPI_CLKCTRL,
+ * CM_L4PER2_UART7_CLKCTRL, CM_L4PER2_UART8_CLKCTRL, CM_L4PER2_UART9_CLKCTRL,
+ * CM_L4PER3_L4_PER3_CLKCTRL, CM_L4PER3_TIMER13_CLKCTRL,
+ * CM_L4PER3_TIMER14_CLKCTRL, CM_L4PER3_TIMER15_CLKCTRL,
+ * CM_L4PER3_TIMER16_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_L4_PER1_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL,
+ * CM_L4PER_TIMER10_CLKCTRL, CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL,
+ * CM_L4PER_TIMER3_CLKCTRL, CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4PER_UART5_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L4SEC_SHA2MD52_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_RTC_RTCSS_CLKCTRL, CM_VPE_VPE_CLKCTRL,
+ * CM_WKUPAON_ADC_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_DCAN1_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_SPARE_SAFETY1_CLKCTRL, CM_WKUPAON_SPARE_SAFETY2_CLKCTRL,
+ * CM_WKUPAON_SPARE_SAFETY3_CLKCTRL, CM_WKUPAON_SPARE_SAFETY4_CLKCTRL,
+ * CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL, CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_UART10_CLKCTRL, CM_WKUPAON_WD_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define DRA7XX_IDLEST_SHIFT 16
+#define DRA7XX_IDLEST_WIDTH 0x2
+#define DRA7XX_IDLEST_MASK (0x3 << 16)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_INPSEL_SHIFT 3
+#define DRA7XX_INPSEL_WIDTH 0x3
+#define DRA7XX_INPSEL_MASK (0x7 << 3)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_IPU1_DYNDEP_SHIFT 18
+#define DRA7XX_IPU1_DYNDEP_WIDTH 0x1
+#define DRA7XX_IPU1_DYNDEP_MASK (1 << 18)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_L4PER2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_IPU1_STATDEP_SHIFT 23
+#define DRA7XX_IPU1_STATDEP_WIDTH 0x1
+#define DRA7XX_IPU1_STATDEP_MASK (1 << 23)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_IPU2_DYNDEP_SHIFT 0
+#define DRA7XX_IPU2_DYNDEP_WIDTH 0x1
+#define DRA7XX_IPU2_DYNDEP_MASK (1 << 0)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_L4PER2_STATICDEP, CM_MPU_STATICDEP
+ */
+#define DRA7XX_IPU2_STATDEP_SHIFT 0
+#define DRA7XX_IPU2_STATDEP_WIDTH 0x1
+#define DRA7XX_IPU2_STATDEP_MASK (1 << 0)
+
+/*
+ * Used by CM_L3MAIN1_DYNAMICDEP, CM_L4PER2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP
+ */
+#define DRA7XX_IPU_DYNDEP_SHIFT 3
+#define DRA7XX_IPU_DYNDEP_WIDTH 0x1
+#define DRA7XX_IPU_DYNDEP_MASK (1 << 3)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_IPU_STATDEP_SHIFT 24
+#define DRA7XX_IPU_STATDEP_WIDTH 0x1
+#define DRA7XX_IPU_STATDEP_MASK (1 << 24)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_IVA_DYNDEP_SHIFT 2
+#define DRA7XX_IVA_DYNDEP_WIDTH 0x1
+#define DRA7XX_IVA_DYNDEP_MASK (1 << 2)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_DSS_STATICDEP, CM_EVE1_STATICDEP, CM_EVE2_STATICDEP,
+ * CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_GPU_STATICDEP, CM_IPU1_STATICDEP,
+ * CM_IPU2_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_IVA_STATDEP_SHIFT 2
+#define DRA7XX_IVA_STATDEP_WIDTH 0x1
+#define DRA7XX_IVA_STATDEP_MASK (1 << 2)
+
+/*
+ * Used by CM_L4CFG_DYNAMICDEP, CM_L4PER2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP
+ */
+#define DRA7XX_L3INIT_DYNDEP_SHIFT 7
+#define DRA7XX_L3INIT_DYNDEP_WIDTH 0x1
+#define DRA7XX_L3INIT_DYNDEP_MASK (1 << 7)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L3INIT_STATDEP_SHIFT 7
+#define DRA7XX_L3INIT_STATDEP_WIDTH 0x1
+#define DRA7XX_L3INIT_STATDEP_MASK (1 << 7)
+
+/*
+ * Used by CM_DMA_DYNAMICDEP, CM_DSP1_DYNAMICDEP, CM_DSP2_DYNAMICDEP,
+ * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GMAC_DYNAMICDEP,
+ * CM_IPU1_DYNAMICDEP, CM_IPU2_DYNAMICDEP, CM_IVA_DYNAMICDEP,
+ * CM_L3INIT_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER3_DYNAMICDEP,
+ * CM_L4SEC_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define DRA7XX_L3MAIN1_DYNDEP_SHIFT 5
+#define DRA7XX_L3MAIN1_DYNDEP_WIDTH 0x1
+#define DRA7XX_L3MAIN1_DYNDEP_MASK (1 << 5)
+
+/* Renamed from L3MAIN1_DYNDEP Used by CM_GPU_DYNAMICDEP */
+#define DRA7XX_L3MAIN1_DYNDEP_6_6_SHIFT 6
+#define DRA7XX_L3MAIN1_DYNDEP_6_6_WIDTH 0x1
+#define DRA7XX_L3MAIN1_DYNDEP_6_6_MASK (1 << 6)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_DSS_STATICDEP, CM_EVE1_STATICDEP, CM_EVE2_STATICDEP,
+ * CM_EVE3_STATICDEP, CM_EVE4_STATICDEP, CM_GMAC_STATICDEP, CM_GPU_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_IVA_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_L4PER2_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_VPE_STATICDEP
+ */
+#define DRA7XX_L3MAIN1_STATDEP_SHIFT 5
+#define DRA7XX_L3MAIN1_STATDEP_WIDTH 0x1
+#define DRA7XX_L3MAIN1_STATDEP_MASK (1 << 5)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP, CM_L4PER2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP */
+#define DRA7XX_L4CFG_DYNDEP_SHIFT 12
+#define DRA7XX_L4CFG_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4CFG_DYNDEP_MASK (1 << 12)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L4CFG_STATDEP_SHIFT 12
+#define DRA7XX_L4CFG_STATDEP_WIDTH 0x1
+#define DRA7XX_L4CFG_STATDEP_MASK (1 << 12)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_L4PER2_DYNDEP_SHIFT 22
+#define DRA7XX_L4PER2_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4PER2_DYNDEP_MASK (1 << 22)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_GMAC_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP,
+ * CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L4PER2_STATDEP_SHIFT 26
+#define DRA7XX_L4PER2_STATDEP_WIDTH 0x1
+#define DRA7XX_L4PER2_STATDEP_MASK (1 << 26)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_L4PER3_DYNDEP_SHIFT 23
+#define DRA7XX_L4PER3_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4PER3_DYNDEP_MASK (1 << 23)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DMA_STATICDEP, CM_DSP1_STATICDEP,
+ * CM_DSP2_STATICDEP, CM_IPU1_STATICDEP, CM_IPU2_STATICDEP,
+ * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP, CM_VPE_STATICDEP
+ */
+#define DRA7XX_L4PER3_STATDEP_SHIFT 27
+#define DRA7XX_L4PER3_STATDEP_WIDTH 0x1
+#define DRA7XX_L4PER3_STATDEP_MASK (1 << 27)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_L4PER_DYNDEP_SHIFT 13
+#define DRA7XX_L4PER_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4PER_DYNDEP_MASK (1 << 13)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L4PER_STATDEP_SHIFT 13
+#define DRA7XX_L4PER_STATDEP_WIDTH 0x1
+#define DRA7XX_L4PER_STATDEP_MASK (1 << 13)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
+#define DRA7XX_L4SEC_DYNDEP_SHIFT 14
+#define DRA7XX_L4SEC_DYNDEP_WIDTH 0x1
+#define DRA7XX_L4SEC_DYNDEP_MASK (1 << 14)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
+ * CM_PCIE_STATICDEP
+ */
+#define DRA7XX_L4SEC_STATDEP_SHIFT 14
+#define DRA7XX_L4SEC_STATDEP_WIDTH 0x1
+#define DRA7XX_L4SEC_STATDEP_MASK (1 << 14)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_MODE_SHIFT 2
+#define DRA7XX_MODE_WIDTH 0x1
+#define DRA7XX_MODE_MASK (1 << 2)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_MODE_SELECT_SHIFT 0
+#define DRA7XX_MODE_SELECT_WIDTH 0x2
+#define DRA7XX_MODE_SELECT_MASK (0x3 << 0)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_DDR, CM_SSC_MODFREQDIV_DPLL_DSP,
+ * CM_SSC_MODFREQDIV_DPLL_EVE, CM_SSC_MODFREQDIV_DPLL_GMAC,
+ * CM_SSC_MODFREQDIV_DPLL_GPU, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PCIE_REF,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define DRA7XX_MODFREQDIV_EXPONENT_SHIFT 8
+#define DRA7XX_MODFREQDIV_EXPONENT_WIDTH 0x3
+#define DRA7XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
+ * CM_SSC_MODFREQDIV_DPLL_DDR, CM_SSC_MODFREQDIV_DPLL_DSP,
+ * CM_SSC_MODFREQDIV_DPLL_EVE, CM_SSC_MODFREQDIV_DPLL_GMAC,
+ * CM_SSC_MODFREQDIV_DPLL_GPU, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PCIE_REF,
+ * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_USB
+ */
+#define DRA7XX_MODFREQDIV_MANTISSA_SHIFT 0
+#define DRA7XX_MODFREQDIV_MANTISSA_WIDTH 0x7
+#define DRA7XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
+
+/*
+ * Used by CM_ATL_ATL_CLKCTRL, CM_CAM_CSI1_CLKCTRL, CM_CAM_CSI2_CLKCTRL,
+ * CM_CAM_LVDSRX_CLKCTRL, CM_CAM_VIP1_CLKCTRL, CM_CAM_VIP2_CLKCTRL,
+ * CM_CAM_VIP3_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
+ * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL, CM_COREAON_SMARTREFLEX_GPU_CLKCTRL,
+ * CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
+ * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP1_DSP1_CLKCTRL, CM_DSP2_DSP2_CLKCTRL, CM_DSS_BB2D_CLKCTRL,
+ * CM_DSS_DSS_CLKCTRL, CM_DSS_SDVENC_CLKCTRL, CM_EMIF_DMM_CLKCTRL,
+ * CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, CM_EMIF_EMIF_OCP_FW_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_EVE1_EVE1_CLKCTRL,
+ * CM_EVE2_EVE2_CLKCTRL, CM_EVE3_EVE3_CLKCTRL, CM_EVE4_EVE4_CLKCTRL,
+ * CM_GMAC_GMAC_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU1_IPU1_CLKCTRL,
+ * CM_IPU2_IPU2_CLKCTRL, CM_IPU_I2C5_CLKCTRL, CM_IPU_MCASP1_CLKCTRL,
+ * CM_IPU_TIMER5_CLKCTRL, CM_IPU_TIMER6_CLKCTRL, CM_IPU_TIMER7_CLKCTRL,
+ * CM_IPU_TIMER8_CLKCTRL, CM_IPU_UART6_CLKCTRL, CM_IVA_IVA_CLKCTRL,
+ * CM_IVA_SL2_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
+ * CM_L3INIT_MLB_SS_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_USB_OTG_SS1_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS2_CLKCTRL, CM_L3INIT_USB_OTG_SS3_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS4_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
+ * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_L3_MAIN_2_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
+ * CM_L3MAIN1_GPMC_CLKCTRL, CM_L3MAIN1_L3_MAIN_1_CLKCTRL,
+ * CM_L3MAIN1_MMU_EDMA_CLKCTRL, CM_L3MAIN1_OCMC_RAM1_CLKCTRL,
+ * CM_L3MAIN1_OCMC_RAM2_CLKCTRL, CM_L3MAIN1_OCMC_RAM3_CLKCTRL,
+ * CM_L3MAIN1_OCMC_ROM_CLKCTRL, CM_L3MAIN1_SPARE_CME_CLKCTRL,
+ * CM_L3MAIN1_SPARE_HDMI_CLKCTRL, CM_L3MAIN1_SPARE_ICM_CLKCTRL,
+ * CM_L3MAIN1_SPARE_IVA2_CLKCTRL, CM_L3MAIN1_SPARE_SATA2_CLKCTRL,
+ * CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL, CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL,
+ * CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL, CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL,
+ * CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL, CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL,
+ * CM_L3MAIN1_TPCC_CLKCTRL, CM_L3MAIN1_TPTC1_CLKCTRL, CM_L3MAIN1_TPTC2_CLKCTRL,
+ * CM_L3MAIN1_VCP1_CLKCTRL, CM_L3MAIN1_VCP2_CLKCTRL,
+ * CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
+ * CM_L4CFG_MAILBOX10_CLKCTRL, CM_L4CFG_MAILBOX11_CLKCTRL,
+ * CM_L4CFG_MAILBOX12_CLKCTRL, CM_L4CFG_MAILBOX13_CLKCTRL,
+ * CM_L4CFG_MAILBOX1_CLKCTRL, CM_L4CFG_MAILBOX2_CLKCTRL,
+ * CM_L4CFG_MAILBOX3_CLKCTRL, CM_L4CFG_MAILBOX4_CLKCTRL,
+ * CM_L4CFG_MAILBOX5_CLKCTRL, CM_L4CFG_MAILBOX6_CLKCTRL,
+ * CM_L4CFG_MAILBOX7_CLKCTRL, CM_L4CFG_MAILBOX8_CLKCTRL,
+ * CM_L4CFG_MAILBOX9_CLKCTRL, CM_L4CFG_OCP2SCP2_CLKCTRL,
+ * CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL,
+ * CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL,
+ * CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL, CM_L4CFG_SPINLOCK_CLKCTRL,
+ * CM_L4PER2_DCAN2_CLKCTRL, CM_L4PER2_L4_PER2_CLKCTRL,
+ * CM_L4PER2_MCASP2_CLKCTRL, CM_L4PER2_MCASP3_CLKCTRL,
+ * CM_L4PER2_MCASP4_CLKCTRL, CM_L4PER2_MCASP5_CLKCTRL,
+ * CM_L4PER2_MCASP6_CLKCTRL, CM_L4PER2_MCASP7_CLKCTRL,
+ * CM_L4PER2_MCASP8_CLKCTRL, CM_L4PER2_PRUSS1_CLKCTRL,
+ * CM_L4PER2_PRUSS2_CLKCTRL, CM_L4PER2_PWMSS1_CLKCTRL,
+ * CM_L4PER2_PWMSS2_CLKCTRL, CM_L4PER2_PWMSS3_CLKCTRL, CM_L4PER2_QSPI_CLKCTRL,
+ * CM_L4PER2_UART7_CLKCTRL, CM_L4PER2_UART8_CLKCTRL, CM_L4PER2_UART9_CLKCTRL,
+ * CM_L4PER3_L4_PER3_CLKCTRL, CM_L4PER3_TIMER13_CLKCTRL,
+ * CM_L4PER3_TIMER14_CLKCTRL, CM_L4PER3_TIMER15_CLKCTRL,
+ * CM_L4PER3_TIMER16_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
+ * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
+ * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
+ * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
+ * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_L4_PER1_CLKCTRL,
+ * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
+ * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL,
+ * CM_L4PER_TIMER10_CLKCTRL, CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL,
+ * CM_L4PER_TIMER3_CLKCTRL, CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4PER_UART5_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
+ * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
+ * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L4SEC_SHA2MD52_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_RTC_RTCSS_CLKCTRL, CM_VPE_VPE_CLKCTRL,
+ * CM_WKUPAON_ADC_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
+ * CM_WKUPAON_DCAN1_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
+ * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
+ * CM_WKUPAON_SPARE_SAFETY1_CLKCTRL, CM_WKUPAON_SPARE_SAFETY2_CLKCTRL,
+ * CM_WKUPAON_SPARE_SAFETY3_CLKCTRL, CM_WKUPAON_SPARE_SAFETY4_CLKCTRL,
+ * CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL, CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL,
+ * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
+ * CM_WKUPAON_UART10_CLKCTRL, CM_WKUPAON_WD_TIMER1_CLKCTRL,
+ * CM_WKUPAON_WD_TIMER2_CLKCTRL
+ */
+#define DRA7XX_MODULEMODE_SHIFT 0
+#define DRA7XX_MODULEMODE_WIDTH 0x2
+#define DRA7XX_MODULEMODE_MASK (0x3 << 0)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define DRA7XX_MPU_DYNDEP_SHIFT 19
+#define DRA7XX_MPU_DYNDEP_WIDTH 0x1
+#define DRA7XX_MPU_DYNDEP_MASK (1 << 19)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11
+#define DRA7XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9
+#define DRA7XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
+
+/* Used by CM_COREAON_DUMMY_MODULE4_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_ABE_GICLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_ABE_GICLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_ABE_GICLK_MASK (1 << 8)
+
+/*
+ * Used by CM_COREAON_USB_PHY1_CORE_CLKCTRL, CM_COREAON_USB_PHY2_CORE_CLKCTRL,
+ * CM_COREAON_USB_PHY3_CORE_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, CM_L4PER_MMC4_CLKCTRL
+ */
+#define DRA7XX_OPTFCLKEN_CLK32K_SHIFT 8
+#define DRA7XX_OPTFCLKEN_CLK32K_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_CLK32K_MASK (1 << 8)
+
+/* Used by CM_COREAON_DUMMY_MODULE1_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX1_CLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX1_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX1_CLK_MASK (1 << 8)
+
+/* Used by CM_COREAON_DUMMY_MODULE2_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX2_CLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX2_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_CLKOUTMUX2_CLK_MASK (1 << 8)
+
+/*
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
+ * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
+ */
+#define DRA7XX_OPTFCLKEN_DBCLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_DBCLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_DBCLK_MASK (1 << 8)
+
+/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_DLL_CLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_DSSCLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_DSSCLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_DSSCLK_MASK (1 << 8)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_HDMI_CLK_SHIFT 10
+#define DRA7XX_OPTFCLKEN_HDMI_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_HDMI_CLK_MASK (1 << 10)
+
+/* Used by CM_COREAON_DUMMY_MODULE3_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_L3INIT_60M_GFCLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_L3INIT_60M_GFCLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_L3INIT_60M_GFCLK_MASK (1 << 8)
+
+/* Used by CM_L3INIT_USB_OTG_SS1_CLKCTRL, CM_L3INIT_USB_OTG_SS2_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_REFCLK960M_SHIFT 8
+#define DRA7XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8)
+
+/* Used by CM_L3INIT_SATA_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_REF_CLK_SHIFT 8
+#define DRA7XX_OPTFCLKEN_REF_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_REF_CLK_MASK (1 << 8)
+
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_SCRM_CORE_SHIFT 8
+#define DRA7XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
+
+/* Used by CM_WKUPAON_SCRM_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_SCRM_PER_SHIFT 9
+#define DRA7XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_VIDEO1_CLK_SHIFT 12
+#define DRA7XX_OPTFCLKEN_VIDEO1_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_VIDEO1_CLK_MASK (1 << 12)
+
+/* Used by CM_DSS_DSS_CLKCTRL */
+#define DRA7XX_OPTFCLKEN_VIDEO2_CLK_SHIFT 13
+#define DRA7XX_OPTFCLKEN_VIDEO2_CLK_WIDTH 0x1
+#define DRA7XX_OPTFCLKEN_VIDEO2_CLK_MASK (1 << 13)
+
+/* Used by CM_CORE_AON_DEBUG_OUT */
+#define DRA7XX_OUTPUT_SHIFT 0
+#define DRA7XX_OUTPUT_WIDTH 0x20
+#define DRA7XX_OUTPUT_MASK (0xffffffff << 0)
+
+/* Used by CM_CLKSEL_ABE */
+#define DRA7XX_PAD_CLKS_GATE_SHIFT 8
+#define DRA7XX_PAD_CLKS_GATE_WIDTH 0x1
+#define DRA7XX_PAD_CLKS_GATE_MASK (1 << 8)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_PCIE_DYNDEP_SHIFT 21
+#define DRA7XX_PCIE_DYNDEP_WIDTH 0x1
+#define DRA7XX_PCIE_DYNDEP_MASK (1 << 21)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP
+ */
+#define DRA7XX_PCIE_STATDEP_SHIFT 29
+#define DRA7XX_PCIE_STATDEP_WIDTH 0x1
+#define DRA7XX_PCIE_STATDEP_MASK (1 << 29)
+
+/* Used by CM_RESTORE_ST */
+#define DRA7XX_PHASE1_COMPLETED_SHIFT 0
+#define DRA7XX_PHASE1_COMPLETED_WIDTH 0x1
+#define DRA7XX_PHASE1_COMPLETED_MASK (1 << 0)
+
+/* Used by CM_RESTORE_ST */
+#define DRA7XX_PHASE2A_COMPLETED_SHIFT 1
+#define DRA7XX_PHASE2A_COMPLETED_WIDTH 0x1
+#define DRA7XX_PHASE2A_COMPLETED_MASK (1 << 1)
+
+/* Used by CM_RESTORE_ST */
+#define DRA7XX_PHASE2B_COMPLETED_SHIFT 2
+#define DRA7XX_PHASE2B_COMPLETED_WIDTH 0x1
+#define DRA7XX_PHASE2B_COMPLETED_MASK (1 << 2)
+
+/* Used by CM_DYN_DEP_PRESCAL */
+#define DRA7XX_PRESCAL_SHIFT 0
+#define DRA7XX_PRESCAL_WIDTH 0x6
+#define DRA7XX_PRESCAL_MASK (0x3f << 0)
+
+/* Used by CM_CLKMODE_APLL_PCIE */
+#define DRA7XX_REFSEL_SHIFT 7
+#define DRA7XX_REFSEL_WIDTH 0x1
+#define DRA7XX_REFSEL_MASK (1 << 7)
+
+/* Used by CM_L4PER3_DYNAMICDEP */
+#define DRA7XX_RTC_DYNDEP_SHIFT 23
+#define DRA7XX_RTC_DYNDEP_WIDTH 0x1
+#define DRA7XX_RTC_DYNDEP_MASK (1 << 23)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_R_RTL_SHIFT 11
+#define DRA7XX_R_RTL_WIDTH 0x5
+#define DRA7XX_R_RTL_MASK (0x1f << 11)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_SCHEME_SHIFT 30
+#define DRA7XX_SCHEME_WIDTH 0x2
+#define DRA7XX_SCHEME_MASK (0x3 << 30)
+
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define DRA7XX_SDMA_DYNDEP_SHIFT 11
+#define DRA7XX_SDMA_DYNDEP_WIDTH 0x1
+#define DRA7XX_SDMA_DYNDEP_MASK (1 << 11)
+
+/*
+ * Used by CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP,
+ * CM_PCIE_STATICDEP
+ */
+#define DRA7XX_SDMA_STATDEP_SHIFT 11
+#define DRA7XX_SDMA_STATDEP_WIDTH 0x1
+#define DRA7XX_SDMA_STATDEP_MASK (1 << 11)
+
+/* Used by CM_CORE_AON_DEBUG_CFG0 */
+#define DRA7XX_SEL0_SHIFT 0
+#define DRA7XX_SEL0_WIDTH 0xa
+#define DRA7XX_SEL0_MASK (0x3ff << 0)
+
+/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
+#define DRA7XX_SEL0_CORE_DEBUG_CFG_SHIFT 0
+#define DRA7XX_SEL0_CORE_DEBUG_CFG_WIDTH 0x8
+#define DRA7XX_SEL0_CORE_DEBUG_CFG_MASK (0xff << 0)
+
+/* Used by CM_CORE_AON_DEBUG_CFG1 */
+#define DRA7XX_SEL1_SHIFT 0
+#define DRA7XX_SEL1_WIDTH 0xa
+#define DRA7XX_SEL1_MASK (0x3ff << 0)
+
+/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
+#define DRA7XX_SEL1_CORE_DEBUG_CFG_SHIFT 8
+#define DRA7XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8
+#define DRA7XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8)
+
+/* Used by CM_CORE_AON_DEBUG_CFG2 */
+#define DRA7XX_SEL2_SHIFT 0
+#define DRA7XX_SEL2_WIDTH 0xa
+#define DRA7XX_SEL2_MASK (0x3ff << 0)
+
+/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
+#define DRA7XX_SEL2_CORE_DEBUG_CFG_SHIFT 16
+#define DRA7XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8
+#define DRA7XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16)
+
+/* Used by CM_CORE_AON_DEBUG_CFG3 */
+#define DRA7XX_SEL3_SHIFT 0
+#define DRA7XX_SEL3_WIDTH 0xa
+#define DRA7XX_SEL3_MASK (0x3ff << 0)
+
+/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
+#define DRA7XX_SEL3_24_31_SHIFT 24
+#define DRA7XX_SEL3_24_31_WIDTH 0x8
+#define DRA7XX_SEL3_24_31_MASK (0xff << 24)
+
+/* Used by CM_CLKSEL_ABE */
+#define DRA7XX_SLIMBUS1_CLK_GATE_SHIFT 10
+#define DRA7XX_SLIMBUS1_CLK_GATE_WIDTH 0x1
+#define DRA7XX_SLIMBUS1_CLK_GATE_MASK (1 << 10)
+
+/*
+ * Used by CM_CAM_CSI1_CLKCTRL, CM_CAM_CSI2_CLKCTRL, CM_CAM_VIP1_CLKCTRL,
+ * CM_CAM_VIP2_CLKCTRL, CM_CAM_VIP3_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
+ * CM_DSP1_DSP1_CLKCTRL, CM_DSP2_DSP2_CLKCTRL, CM_DSS_BB2D_CLKCTRL,
+ * CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_EVE1_EVE1_CLKCTRL,
+ * CM_EVE2_EVE2_CLKCTRL, CM_EVE3_EVE3_CLKCTRL, CM_EVE4_EVE4_CLKCTRL,
+ * CM_GMAC_GMAC_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU1_IPU1_CLKCTRL,
+ * CM_IPU2_IPU2_CLKCTRL, CM_IVA_IVA_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
+ * CM_L3INIT_MLB_SS_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
+ * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_USB_OTG_SS1_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS2_CLKCTRL, CM_L3INIT_USB_OTG_SS3_CLKCTRL,
+ * CM_L3INIT_USB_OTG_SS4_CLKCTRL, CM_L3MAIN1_TPTC1_CLKCTRL,
+ * CM_L3MAIN1_TPTC2_CLKCTRL, CM_L4PER2_PRUSS1_CLKCTRL,
+ * CM_L4PER2_PRUSS2_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_VPE_VPE_CLKCTRL
+ */
+#define DRA7XX_STBYST_SHIFT 18
+#define DRA7XX_STBYST_WIDTH 0x1
+#define DRA7XX_STBYST_MASK (1 << 18)
+
+/* Used by CM_IDLEST_APLL_PCIE */
+#define DRA7XX_ST_APLL_CLK_SHIFT 0
+#define DRA7XX_ST_APLL_CLK_WIDTH 0x1
+#define DRA7XX_ST_APLL_CLK_MASK (1 << 0)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR,
+ * CM_IDLEST_DPLL_DSP, CM_IDLEST_DPLL_EVE, CM_IDLEST_DPLL_GMAC,
+ * CM_IDLEST_DPLL_GPU, CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU,
+ * CM_IDLEST_DPLL_PCIE_REF, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_USB
+ */
+#define DRA7XX_ST_DPLL_CLK_SHIFT 0
+#define DRA7XX_ST_DPLL_CLK_WIDTH 0x1
+#define DRA7XX_ST_DPLL_CLK_MASK (1 << 0)
+
+/* Used by CM_CLKDCOLDO_DPLL_USB */
+#define DRA7XX_ST_DPLL_CLKDCOLDO_SHIFT 9
+#define DRA7XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1
+#define DRA7XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR,
+ * CM_IDLEST_DPLL_DSP, CM_IDLEST_DPLL_EVE, CM_IDLEST_DPLL_GMAC,
+ * CM_IDLEST_DPLL_GPU, CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU,
+ * CM_IDLEST_DPLL_PCIE_REF, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_USB
+ */
+#define DRA7XX_ST_DPLL_INIT_SHIFT 4
+#define DRA7XX_ST_DPLL_INIT_WIDTH 0x1
+#define DRA7XX_ST_DPLL_INIT_MASK (1 << 4)
+
+/*
+ * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR,
+ * CM_IDLEST_DPLL_DSP, CM_IDLEST_DPLL_EVE, CM_IDLEST_DPLL_GMAC,
+ * CM_IDLEST_DPLL_GPU, CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU,
+ * CM_IDLEST_DPLL_PCIE_REF, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_USB
+ */
+#define DRA7XX_ST_DPLL_MODE_SHIFT 1
+#define DRA7XX_ST_DPLL_MODE_WIDTH 0x3
+#define DRA7XX_ST_DPLL_MODE_MASK (0x7 << 1)
+
+/* Used by CM_CLKSEL_SYS */
+#define DRA7XX_SYS_CLKSEL_SHIFT 0
+#define DRA7XX_SYS_CLKSEL_WIDTH 0x3
+#define DRA7XX_SYS_CLKSEL_MASK (0x7 << 0)
+
+/* Used by CM_L4PER3_DYNAMICDEP */
+#define DRA7XX_VPE_DYNDEP_SHIFT 31
+#define DRA7XX_VPE_DYNDEP_WIDTH 0x1
+#define DRA7XX_VPE_DYNDEP_MASK (1 << 31)
+
+/*
+ * Used by CM_CAM_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_MPU_STATICDEP, CM_PCIE_STATICDEP
+ */
+#define DRA7XX_VPE_STATDEP_SHIFT 28
+#define DRA7XX_VPE_STATDEP_WIDTH 0x1
+#define DRA7XX_VPE_STATDEP_MASK (1 << 28)
+
+/*
+ * Used by CM_DSP1_DYNAMICDEP, CM_DSP2_DYNAMICDEP, CM_EMU_DYNAMICDEP,
+ * CM_IPU1_DYNAMICDEP, CM_IPU2_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
+ * CM_L4CFG_DYNAMICDEP, CM_L4PER2_DYNAMICDEP, CM_L4PER3_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP
+ */
+#define DRA7XX_WINDOWSIZE_SHIFT 24
+#define DRA7XX_WINDOWSIZE_WIDTH 0x4
+#define DRA7XX_WINDOWSIZE_MASK (0xf << 24)
+
+/* Used by CM_L3MAIN1_DYNAMICDEP */
+#define DRA7XX_WKUPAON_DYNDEP_SHIFT 15
+#define DRA7XX_WKUPAON_DYNDEP_WIDTH 0x1
+#define DRA7XX_WKUPAON_DYNDEP_MASK (1 << 15)
+
+/*
+ * Used by CM_DMA_STATICDEP, CM_DSP1_STATICDEP, CM_DSP2_STATICDEP,
+ * CM_IPU1_STATICDEP, CM_IPU2_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
+ */
+#define DRA7XX_WKUPAON_STATDEP_SHIFT 15
+#define DRA7XX_WKUPAON_STATDEP_WIDTH 0x1
+#define DRA7XX_WKUPAON_STATDEP_MASK (1 << 15)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_X_MAJOR_SHIFT 8
+#define DRA7XX_X_MAJOR_WIDTH 0x3
+#define DRA7XX_X_MAJOR_MASK (0x7 << 8)
+
+/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
+#define DRA7XX_Y_MINOR_SHIFT 0
+#define DRA7XX_Y_MINOR_WIDTH 0x6
+#define DRA7XX_Y_MINOR_MASK (0x3f << 0)
+#endif
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
--- /dev/null
@@ -0,0 +1,326 @@
+/*
+ * DRA7xx CM1 instance offset macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
+
+/* CM1 base address */
+#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
+
+#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
+ OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
+
+/* CM_CORE_AON instances */
+#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
+#define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
+#define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
+#define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
+#define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
+#define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
+#define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
+#define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
+#define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
+#define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700
+#define DRA7XX_CM_CORE_AON_RTC_INST 0x0740
+#define DRA7XX_CM_CORE_AON_VPE_INST 0x0760
+#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00
+#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00
+
+/* CM_CORE_AON clockdomain register offsets (from instance start) */
+#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040
+#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000
+
+/* CM_CORE_AON */
+
+/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
+#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000
+#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
+#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8
+#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc
+
+/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
+#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000
+#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
+#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008
+#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
+#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010
+#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
+#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
+#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
+#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
+#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
+#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
+#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
+#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
+#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
+#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
+#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
+#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
+#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
+#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
+#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
+#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
+#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
+#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
+#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
+#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
+#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
+#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
+#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
+#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
+#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
+#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
+#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
+#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
+#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
+#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
+#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
+#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
+#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
+#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
+#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
+#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
+#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
+#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
+#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
+#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
+#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
+#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
+#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
+#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
+#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
+#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
+#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
+#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
+#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0
+#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
+#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4
+#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
+#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
+#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
+#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
+#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
+#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
+#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
+#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
+#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
+#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
+#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
+#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
+#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
+#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
+#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
+#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110
+#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
+#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114
+#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
+#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118
+#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
+#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c
+#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
+#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120
+#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
+#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124
+#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
+#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128
+#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130
+#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134
+#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
+#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138
+#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
+#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c
+#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
+#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140
+#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
+#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144
+#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
+#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148
+#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150
+#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154
+#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
+#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
+#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
+#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
+#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180
+#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184
+#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
+#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188
+#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
+#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c
+#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
+#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190
+#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
+#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194
+#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
+#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198
+#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0
+#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4
+#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
+#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8
+#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
+#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac
+#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
+#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0
+#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
+#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4
+#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
+#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8
+#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
+#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc
+#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
+#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0
+#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
+#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4
+#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
+#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8
+#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
+#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc
+#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4
+#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8
+#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
+#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc
+#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
+#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0
+#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
+#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4
+#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
+#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8
+#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
+#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec
+#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4
+
+/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
+#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
+#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
+
+/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
+#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
+
+/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
+#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
+#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040
+#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
+#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
+#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060
+#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
+#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068
+#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
+#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070
+#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
+#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
+#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080
+#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
+
+/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
+#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
+
+/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
+
+/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
+
+/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
+
+/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
+#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
+
+/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
+#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004
+#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
+
+/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
+#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004
+#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
+#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008
+
+/* Function prototypes */
+extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm1_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
--- /dev/null
@@ -0,0 +1,515 @@
+/*
+ * DRA7xx CM2 instance offset macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
+
+/* CM2 base address */
+#define DRA7XX_CM_CORE_BASE 0x4a008000
+
+#define DRA7XX_CM_CORE_REGADDR(inst, reg) \
+ OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
+
+/* CM_CORE instances */
+#define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
+#define DRA7XX_CM_CORE_CKGEN_INST 0x0104
+#define DRA7XX_CM_CORE_COREAON_INST 0x0600
+#define DRA7XX_CM_CORE_CORE_INST 0x0700
+#define DRA7XX_CM_CORE_IVA_INST 0x0f00
+#define DRA7XX_CM_CORE_CAM_INST 0x1000
+#define DRA7XX_CM_CORE_DSS_INST 0x1100
+#define DRA7XX_CM_CORE_GPU_INST 0x1200
+#define DRA7XX_CM_CORE_L3INIT_INST 0x1300
+#define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600
+#define DRA7XX_CM_CORE_L4PER_INST 0x1700
+#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18
+
+/* CM_CORE clockdomain register offsets (from instance start) */
+#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200
+#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
+#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
+#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520
+#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
+#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
+#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0
+#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0
+#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000
+#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180
+#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc
+#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210
+
+/* CM_CORE */
+
+/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
+#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000
+#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
+#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0
+
+/* CM_CORE.CKGEN_CM_CORE register offsets */
+#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000
+#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
+#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c
+#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
+#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040
+#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
+#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044
+#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
+#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048
+#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
+#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c
+#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
+#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050
+#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
+#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054
+#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
+#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058
+#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
+#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c
+#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
+#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060
+#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068
+#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c
+#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
+#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080
+#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
+#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084
+#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
+#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088
+#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
+#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c
+#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8
+#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0
+#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
+#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc
+#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
+#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100
+#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
+#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104
+#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
+#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108
+#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
+#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c
+#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
+#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110
+#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114
+#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118
+#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
+#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c
+#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
+#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120
+#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
+#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124
+#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
+
+/* CM_CORE.COREAON_CM_CORE register offsets */
+#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
+#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
+#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
+#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068
+#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
+#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
+#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
+#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098
+#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
+#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
+
+/* CM_CORE.CORE_CM_CORE register offsets */
+#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
+#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
+#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060
+#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
+#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068
+#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
+#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070
+#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
+#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
+#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080
+#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
+#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
+#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090
+#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
+#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098
+#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
+#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
+#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8
+#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
+#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0
+#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
+#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8
+#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8
+#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
+#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200
+#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204
+#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208
+#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220
+#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
+#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
+#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304
+#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
+#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
+#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
+#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
+#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
+#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
+#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
+#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
+#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
+#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
+#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
+#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
+#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
+#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
+#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500
+#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
+#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520
+#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
+#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
+#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
+#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
+#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
+#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
+#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630
+#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
+#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
+#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
+#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
+#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
+#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648
+#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
+#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650
+#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
+#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658
+#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
+#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660
+#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
+#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668
+#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
+#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670
+#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
+#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678
+#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
+#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680
+#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
+#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688
+#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
+#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690
+#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
+#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698
+#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
+#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0
+#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8
+#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
+#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0
+#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
+#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
+#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720
+#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
+#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
+#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
+#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
+#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
+#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
+#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
+#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
+#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
+
+/* CM_CORE.IVA_CM_CORE register offsets */
+#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
+#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
+
+/* CM_CORE.CAM_CM_CORE register offsets */
+#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
+#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
+#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
+#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038
+#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
+#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
+#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048
+#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
+
+/* CM_CORE.DSS_CM_CORE register offsets */
+#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
+#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
+#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c
+#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
+
+/* CM_CORE.GPU_CM_CORE register offsets */
+#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
+
+/* CM_CORE.L3INIT_CM_CORE register offsets */
+#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
+#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
+#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048
+#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
+#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
+#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
+#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
+#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
+#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
+#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
+#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
+#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
+#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
+#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
+#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
+#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0
+#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
+
+/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
+#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
+
+/* CM_CORE.L4PER_CM_CORE register offsets */
+#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c
+#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
+#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014
+#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
+#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018
+#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
+#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
+#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
+#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
+#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038
+#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
+#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
+#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048
+#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
+#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
+#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
+#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
+#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
+#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
+#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
+#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
+#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
+#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
+#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
+#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
+#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
+#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
+#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090
+#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
+#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098
+#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
+#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
+#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
+#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
+#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
+#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
+#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
+#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
+#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
+#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4
+#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
+#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8
+#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
+#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
+#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8
+#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
+#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
+#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
+#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
+#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
+#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
+#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
+#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
+#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
+#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110
+#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
+#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118
+#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
+#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120
+#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
+#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128
+#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
+#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130
+#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
+#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138
+#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
+#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
+#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
+#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
+#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
+#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
+#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
+#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
+#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
+#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160
+#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
+#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168
+#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
+#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170
+#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
+#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178
+#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
+#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
+#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184
+#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
+#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190
+#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
+#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198
+#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
+#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
+#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
+#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
+#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
+#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
+#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
+#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8
+#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
+#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
+#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
+#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
+#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
+#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0
+#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
+#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8
+#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
+#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0
+#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
+#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8
+#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
+#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0
+#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
+#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8
+#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
+#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc
+#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200
+#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204
+#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
+#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208
+#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
+#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c
+#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210
+#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214
+
+/* Function prototypes */
+extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_cm2_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+#endif
index a6d95614d7a415a4b37d56ca894ff8155d0ceb19..f263327116357ac807c034407795220b1f28511e 100644 (file)
void ti81xx_init_late(void);
void omap5_init_late(void);
int omap2_common_pm_late_init(void);
+void dra7xx_init_early(void);
+void dra7xx_init_late(void);
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
void omap2xxx_restart(char mode, const char *cmd);
}
#endif
-#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
+#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
+ defined(CONFIG_SOC_DRA7XX)
void omap44xx_restart(char mode, const char *cmd);
#else
static inline void omap44xx_restart(char mode, const char *cmd)
index a9d28c28d334e109b3762459f097cba9e7cb3966..379b14bab5e3cc2567a73cb77c0d18f129c2c8f1 100644 (file)
#define OMAP5XXX_CONTROL_STATUS 0x134
#define OMAP5_DEVICETYPE_MASK (0x7 << 6)
+/* DRA7XX BOOTSTRAP register */
+#define DRA7XX_BOOTSTRAP_CONTROL 0x6C4
/*
* REVISIT: This list of registers is not comprehensive - there are more
* that should be added.
index 2890968ca349173ddc4f387ba496313e057fe3db..2216df75af0fe2945f5d186096ebe7b75c62944f 100644 (file)
_omap3_noncore_dpll_bypass(clk);
/*
- * Set jitter correction. No jitter correction for OMAP4 and 3630
- * since freqsel field is no longer present
+ * Set jitter correction. Jitter correction is applicable only for
+ * OMAP343x devices since its the only one which supports freqsel
*/
- if (!soc_is_am33xx() && !cpu_is_omap44xx() && !cpu_is_omap3630()
- && !soc_is_omap54xx()) {
+ if (cpu_is_omap343x()) {
v = __raw_readl(dd->control_reg);
v &= ~dd->freqsel_mask;
v |= freqsel << __ffs(dd->freqsel_mask);
if (dd->last_rounded_rate == 0)
return -EINVAL;
- /* No freqsel on AM335x, OMAP4 and OMAP3630 */
- if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
- !cpu_is_omap3630() && !soc_is_omap54xx()) {
+ /* Freqsel is available only on OMAP343X devices */
+ if (cpu_is_omap343x()) {
freqsel = _omap3_dpll_compute_freqsel(clk,
dd->last_rounded_n);
WARN_ON(!freqsel);
index 93c347e5e1865d670792f8fff2bdc549f7f11426..a688bfa30e4de6f47ad39f3b6dc4ba80a2da4eb4 100644 (file)
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
} else if (cpu_is_omap44xx()) {
val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
- } else if (soc_is_omap54xx()) {
+ } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
val &= OMAP5_DEVICETYPE_MASK;
val >>= 6;
mask |= OMAP2_SYSBOOT_6_MASK | OMAP2_SYSBOOT_7_MASK;
} else if (soc_is_omap54xx()) {
val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
+ } else if (soc_is_dra7xx()) {
+ val = omap_ctrl_readl(DRA7XX_BOOTSTRAP_CONTROL);
} else {
pr_err("Cannot detect omap type!\n");
}
void omap_get_die_id(struct omap_die_id *odi)
{
- if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+ if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
omap_rev() >> 16, ((omap_rev() >> 12) & 0xf));
}
+void __init dra7xx_check_revision(void)
+{
+ u32 idcode;
+ u16 hawkeye;
+ u8 rev;
+
+ idcode = read_tap_reg(OMAP_TAP_IDCODE);
+ hawkeye = (idcode >> 12) & 0xffff;
+ rev = (idcode >> 28) & 0xff;
+ switch (hawkeye) {
+ case 0xb990:
+ switch (rev) {
+ case 0:
+ default:
+ omap_revision = DRA752_REV_ES1_0;
+ }
+ break;
+ default:
+ /* Unknown. Default to latest silicon revision */
+ omap_revision = DRA752_REV_ES1_0;
+ }
+
+ pr_info("DRA%03x ES%d.%d\n", omap_rev() >> 16,
+ ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
+}
+
/*
* Set up things for map_io and processor detection later on. Gets called
* pretty much first thing from board init. For multi-omap, this gets
index ec34d8ef4323caac0a5f060174050aecef3ac166..216f1969400388c800a1a92add92fbb4249922d5 100644 (file)
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
#include "clock3xxx.h"
#include "clock44xx.h"
#include "clock54xx.h"
+#include "clock7xx.h"
#include "omap-pm.h"
#include "sdrc.h"
#include "control.h"
};
#endif
-#ifdef CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
static struct map_desc omap54xx_io_desc[] __initdata = {
{
.virtual = L3_54XX_VIRT,
}
#endif
-#ifdef CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
void __init omap5_map_io(void)
{
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
}
#endif
+#ifdef CONFIG_SOC_DRA7XX
+void __init dra7xx_init_early(void)
+{
+ omap2_set_globals_tap(DRA7XX_CLASS,
+ OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
+ omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
+ OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
+ omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
+ omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
+ OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
+ omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
+ omap_prm_base_init();
+ omap_cm_base_init();
+ dra7xx_check_revision();
+ omap44xx_prm_init();
+ dra7xx_powerdomains_init();
+ dra7xx_clockdomains_init();
+ dra7xx_hwmod_init();
+ omap_hwmod_init_postsetup();
+ dra7xx_clk_init();
+}
+
+void __init dra7xx_init_late(void)
+{
+ omap2_common_pm_late_init();
+ omap4_pm_init();
+ omap2_clk_enable_autoidle_all();
+}
+#endif
+
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
struct omap_sdrc_params *sdrc_cs1)
{
index 539082a5a991fe017a19a6948211ddf5449f16bf..8a15f77d4f94f9acae8ff6e82094f973d05c6899 100644 (file)
#include "omap-wakeupgen.h"
#include "common.h"
#include "powerdomain.h"
+#include "soc.h"
/*
* platform-specific code to shutdown a CPU
/*
* Enter into low power state
*/
- omap4_mpuss_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_OFF);
+ if (soc_is_dra7xx())
+ omap4_mpuss_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_CSWR);
+ else
+ omap4_mpuss_hotplug_cpu(cpu, PWRDM_FUNC_PWRST_OFF);
if (omap_secure_apis_support())
boot_cpu = omap_read_auxcoreboot0();
index 8380b3240a61ae7a531e0228cc63585af01e205f..d46a2693efbd29ab4bc297b8a9fe48a81bbfc899 100644 (file)
* XXX should not be writing directly into another IP block's
* address space!
*/
- __raw_writel(addr, pm_info->wkup_sar_addr);
+ if (pm_info->wkup_sar_addr)
+ __raw_writel(addr, pm_info->wkup_sar_addr);
}
/*
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
u32 scu_pwr_st;
+ if (!pm_info->scu_sar_addr)
+ return;
+
switch (fpwrst) {
case PWRDM_FUNC_PWRST_CSWR:
case PWRDM_FUNC_PWRST_OSWR: /* XXX is this accurate? */
* XXX should not be writing directly into another IP block's
* address space!
*/
- __raw_writel(save_state, pm_info->l2x0_sar_addr);
+ if (pm_info->l2x0_sar_addr)
+ __raw_writel(save_state, pm_info->l2x0_sar_addr);
}
/*
else if (soc_is_omap54xx())
cpu_wakeup_addr = OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
pm_info = &per_cpu(omap4_pm_info, 0x0);
- pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
- pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
- pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+ if (sar_base) {
+ pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
+ pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
+ pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
+ }
pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
if (!pm_info->pwrdm) {
pr_err("Lookup failed for CPU0 pwrdm\n");
else if (soc_is_omap54xx())
cpu_wakeup_addr = OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
pm_info = &per_cpu(omap4_pm_info, 0x1);
- pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
- pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
- pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+ if (sar_base) {
+ pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
+ pm_info->wkup_sar_addr = sar_base + cpu_wakeup_addr;
+ pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
+ }
pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
if (!pm_info->pwrdm) {
mpuss_clear_prev_logic_pwrst();
/* Save device type on scratchpad for low level code to use */
- if (omap_type() != OMAP2_DEVICE_TYPE_GP)
- __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
- else
- __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
+ if (sar_base) {
+ if (omap_type() != OMAP2_DEVICE_TYPE_GP)
+ __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
+ else
+ __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
- save_l2x0_context();
+ save_l2x0_context();
+ }
if (cpu_is_omap44xx()) {
omap_pm_ops.finish_suspend = omap4_finish_suspend;
omap_pm_ops.resume = omap4_cpu_resume;
omap_pm_ops.scu_prepare = scu_pwrst_prepare;
cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
- } else if (soc_is_omap54xx()) {
+ } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
omap_pm_ops.finish_suspend = omap5_finish_suspend;
omap_pm_ops.hotplug_restart = omap5_secondary_startup;
omap_pm_ops.resume = omap5_cpu_resume;
index f57b0b8ccdd01ea91112187f3a0689fc08e5bb71..996636a443e9d6226fec81919f0bb99310091681 100644 (file)
static void __init irq_pm_init(void)
{
- cpu_pm_register_notifier(&irq_notifier_block);
+ /* No OFF mode support on dra7xx */
+ if (!soc_is_dra7xx())
+ cpu_pm_register_notifier(&irq_notifier_block);
}
#else
static void __init irq_pm_init(void)
index 18865459abb9333948b879cba6fa2abfca9b7c0f..f585e6f9506f776a74232f6f157e3a3cd3cdc452 100644 (file)
void __iomem *omap4_get_sar_ram_base(void)
{
- return sar_ram_base;
+ if (sar_ram_base)
+ return sar_ram_base;
+ else
+ return NULL;
}
/*
index a086ba15868b2c4a32ea24de917e5cbd6d734675..92395cc59bb19d04430d85367beb166dd9530c7c 100644 (file)
#define OMAP54XX_CTRL_BASE 0x4a002800
#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
+#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
+#define DRA7XX_CTRL_BASE 0x4a003400
+#define DRA7XX_TAP_BASE 0x4ae0c000
#endif /* __ASM_SOC_OMAP555554XX_H */
index ac1cb40cd1deda543d6b277e80d7049c8cff91c5..d4be257b512fbe68cfae3876fdb98ce2350326a2 100644 (file)
soc_ops.assert_hardreset = _omap2_assert_hardreset;
soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
- } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
+ } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
soc_ops.enable_module = _omap4_enable_module;
soc_ops.disable_module = _omap4_disable_module;
soc_ops.wait_target_ready = _omap4_wait_target_ready;
index 82ec62daa8b6e4323d759d4c4e2af2df66e7f4be..9f536eccab51644b3f807d01127dcdf363439010 100644 (file)
extern int omap44xx_hwmod_init(void);
extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
+extern int dra7xx_hwmod_init(void);
extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
--- /dev/null
@@ -0,0 +1,6244 @@
+/*
+ * Hardware modules present on the DRA7xx chips
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley
+ * Benoit Cousson
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/platform_data/gpio-omap.h>
+#include <linux/power/smartreflex.h>
+#include <linux/platform_data/omap_ocp2scp.h>
+#include <linux/i2c-omap.h>
+
+#include <linux/omap-dma.h>
+#include <linux/platform_data/spi-omap2-mcspi.h>
+#include <linux/platform_data/asoc-ti-mcbsp.h>
+#include <plat/dmtimer.h>
+
+#include "omap_hwmod.h"
+#include "omap_hwmod_common_data.h"
+#include "cm1_7xx.h"
+#include "cm2_7xx.h"
+#include "prm7xx.h"
+#include "prm-regbits-7xx.h"
+#include "i2c.h"
+#include "mmc.h"
+#include "wd_timer.h"
+
+/* Base offset for all DRA7XX interrupts external to MPUSS */
+#define DRA7XX_IRQ_GIC_START 32
+
+/* Base offset for all DRA7XX dma requests */
+#define DRA7XX_DMA_REQ_START 1
+
+
+/*
+ * IP blocks
+ */
+
+/*
+ * 'dmm' class
+ * instance(s): dmm
+ */
+static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
+ .name = "dmm",
+};
+
+/* dmm */
+static struct omap_hwmod_irq_info dra7xx_dmm_irqs[] = {
+ { .irq = 113 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_dmm_hwmod = {
+ .name = "dmm",
+ .class = &dra7xx_dmm_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .mpu_irqs = dra7xx_dmm_irqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'emif_ocp_fw' class
+ * instance(s): emif_ocp_fw
+ */
+static struct omap_hwmod_class dra7xx_emif_ocp_fw_hwmod_class = {
+ .name = "emif_ocp_fw",
+};
+
+/* emif_ocp_fw */
+static struct omap_hwmod dra7xx_emif_ocp_fw_hwmod = {
+ .name = "emif_ocp_fw",
+ .class = &dra7xx_emif_ocp_fw_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'l3' class
+ * instance(s): l3_instr, l3_main_1, l3_main_2
+ */
+static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
+ .name = "l3",
+};
+
+/* l3_instr */
+static struct omap_hwmod dra7xx_l3_instr_hwmod = {
+ .name = "l3_instr",
+ .class = &dra7xx_l3_hwmod_class,
+ .clkdm_name = "l3instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* l3_main_1 */
+static struct omap_hwmod_irq_info dra7xx_l3_main_1_irqs[] = {
+ { .name = "dbg_err", .irq = 9 + DRA7XX_IRQ_GIC_START },
+ { .name = "app_err", .irq = 10 + DRA7XX_IRQ_GIC_START },
+ { .name = "stat_alarm", .irq = 16 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
+ .name = "l3_main_1",
+ .class = &dra7xx_l3_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .mpu_irqs = dra7xx_l3_main_1_irqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* l3_main_2 */
+static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
+ .name = "l3_main_2",
+ .class = &dra7xx_l3_hwmod_class,
+ .clkdm_name = "l3instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'l4' class
+ * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
+ */
+static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
+ .name = "l4",
+};
+
+/* l4_cfg */
+static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
+ .name = "l4_cfg",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* l4_per1 */
+static struct omap_hwmod dra7xx_l4_per1_hwmod = {
+ .name = "l4_per1",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/* l4_per2 */
+static struct omap_hwmod dra7xx_l4_per2_hwmod = {
+ .name = "l4_per2",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/* l4_per3 */
+static struct omap_hwmod dra7xx_l4_per3_hwmod = {
+ .name = "l4_per3",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/* l4_wkup */
+static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
+ .name = "l4_wkup",
+ .class = &dra7xx_l4_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'mpu_bus' class
+ * instance(s): mpu_private
+ */
+static struct omap_hwmod_class dra7xx_mpu_bus_hwmod_class = {
+ .name = "mpu_bus",
+};
+
+/* mpu_private */
+static struct omap_hwmod dra7xx_mpu_private_hwmod = {
+ .name = "mpu_private",
+ .class = &dra7xx_mpu_bus_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/*
+ * 'ocp_wp_noc' class
+ * instance(s): ocp_wp_noc
+ */
+static struct omap_hwmod_class dra7xx_ocp_wp_noc_hwmod_class = {
+ .name = "ocp_wp_noc",
+};
+
+/* ocp_wp_noc */
+static struct omap_hwmod dra7xx_ocp_wp_noc_hwmod = {
+ .name = "ocp_wp_noc",
+ .class = &dra7xx_ocp_wp_noc_hwmod_class,
+ .clkdm_name = "l3instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'atl' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
+ .name = "atl",
+};
+
+/* atl */
+static struct omap_hwmod dra7xx_atl_hwmod = {
+ .name = "atl",
+ .class = &dra7xx_atl_hwmod_class,
+ .clkdm_name = "atl_clkdm",
+ .main_clk = "atl_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'bb2d' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
+ .name = "bb2d",
+};
+
+/* bb2d */
+static struct omap_hwmod_irq_info dra7xx_bb2d_irqs[] = {
+ { .irq = 125 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_bb2d_hwmod = {
+ .name = "bb2d",
+ .class = &dra7xx_bb2d_hwmod_class,
+ .clkdm_name = "dss_clkdm",
+ .mpu_irqs = dra7xx_bb2d_irqs,
+ .main_clk = "dpll_core_h24x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'counter' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
+ .name = "counter",
+ .sysc = &dra7xx_counter_sysc,
+};
+
+/* counter_32k */
+static struct omap_hwmod dra7xx_counter_32k_hwmod = {
+ .name = "counter_32k",
+ .class = &dra7xx_counter_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE,
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'ctrl_module' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
+ .name = "ctrl_module",
+};
+
+/* ctrl_module_wkup */
+static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
+ .name = "ctrl_module_wkup",
+ .class = &dra7xx_ctrl_module_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .prcm = {
+ .omap4 = {
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+};
+
+/*
+ * 'dcan' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
+ .name = "dcan",
+};
+
+/* dcan1 */
+static struct omap_hwmod dra7xx_dcan1_hwmod = {
+ .name = "dcan1",
+ .class = &dra7xx_dcan_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "dcan1_sys_clk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* dcan2 */
+static struct omap_hwmod dra7xx_dcan2_hwmod = {
+ .name = "dcan2",
+ .class = &dra7xx_dcan_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "sys_clkin1",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'dma' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x002c,
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
+ .name = "dma",
+ .sysc = &dra7xx_dma_sysc,
+};
+
+/* dma dev_attr */
+static struct omap_dma_dev_attr dma_dev_attr = {
+ .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
+ IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
+ .lch_count = 32,
+};
+
+/* dma_system */
+static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
+ { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
+ { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
+ { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
+ { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_dma_system_hwmod = {
+ .name = "dma_system",
+ .class = &dra7xx_dma_hwmod_class,
+ .clkdm_name = "dma_clkdm",
+ .mpu_irqs = dra7xx_dma_system_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
+ },
+ },
+ .dev_attr = &dma_dev_attr,
+};
+
+/*
+ * 'dss' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
+ .rev_offs = 0x0000,
+ .syss_offs = 0x0014,
+ .sysc_flags = SYSS_HAS_RESET_STATUS,
+};
+
+static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
+ .name = "dss",
+ .sysc = &dra7xx_dss_sysc,
+ .reset = omap_dss_reset,
+};
+
+/* dss */
+static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
+ { .dma_req = 75 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+ { .role = "dss_clk", .clk = "dss_dss_clk" },
+ { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
+ { .role = "32khz_clk", .clk = "dss_32khz_clk" },
+ { .role = "video2_clk", .clk = "dss_video2_clk" },
+ { .role = "video1_clk", .clk = "dss_video1_clk" },
+ { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
+};
+
+static struct omap_hwmod dra7xx_dss_hwmod = {
+ .name = "dss_core",
+ .class = &dra7xx_dss_hwmod_class,
+ .clkdm_name = "dss_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .sdma_reqs = dra7xx_dss_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = dss_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
+ .name = "dispc",
+ .sysc = &dra7xx_dispc_sysc,
+};
+
+/* dss_dispc */
+static struct omap_hwmod_irq_info dra7xx_dss_dispc_irqs[] = {
+ { .irq = 25 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_dss_dispc_sdma_reqs[] = {
+ { .dma_req = 5 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* dss_dispc dev_attr */
+static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
+ .has_framedonetv_irq = 1,
+ .manager_count = 4,
+};
+
+static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
+ .name = "dss_dispc",
+ .class = &dra7xx_dispc_hwmod_class,
+ .clkdm_name = "dss_clkdm",
+ .mpu_irqs = dra7xx_dss_dispc_irqs,
+ .sdma_reqs = dra7xx_dss_dispc_sdma_reqs,
+ .main_clk = "dss_dss_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+ .dev_attr = &dss_dispc_dev_attr,
+};
+
+/*
+ * 'hdmi' class
+ * hdmi controller
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
+ .name = "hdmi",
+ .sysc = &dra7xx_hdmi_sysc,
+};
+
+/* dss_hdmi */
+static struct omap_hwmod_irq_info dra7xx_dss_hdmi_irqs[] = {
+ { .irq = 101 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_dss_hdmi_sdma_reqs[] = {
+ { .dma_req = 75 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
+ { .role = "sys_clk", .clk = "dss_hdmi_clk" },
+};
+
+static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
+ .name = "dss_hdmi",
+ .class = &dra7xx_hdmi_hwmod_class,
+ .clkdm_name = "dss_clkdm",
+ .mpu_irqs = dra7xx_dss_hdmi_irqs,
+ .sdma_reqs = dra7xx_dss_hdmi_sdma_reqs,
+ .main_clk = "dss_48mhz_clk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+ },
+ },
+ .opt_clks = dss_hdmi_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
+};
+
+/*
+ * 'elm' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
+ .name = "elm",
+ .sysc = &dra7xx_elm_sysc,
+};
+
+/* elm */
+static struct omap_hwmod_irq_info dra7xx_elm_irqs[] = {
+ { .irq = 4 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_elm_hwmod = {
+ .name = "elm",
+ .class = &dra7xx_elm_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_elm_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'emif' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_emif_sysc = {
+ .rev_offs = 0x0000,
+};
+
+static struct omap_hwmod_class dra7xx_emif_hwmod_class = {
+ .name = "emif",
+ .sysc = &dra7xx_emif_sysc,
+};
+
+/* emif1 */
+static struct omap_hwmod_irq_info dra7xx_emif1_irqs[] = {
+ { .irq = 110 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_emif1_hwmod = {
+ .name = "emif1",
+ .class = &dra7xx_emif_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_emif1_irqs,
+ .main_clk = "dpll_ddr_h11x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* emif2 */
+static struct omap_hwmod_irq_info dra7xx_emif2_irqs[] = {
+ { .irq = 111 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_emif2_hwmod = {
+ .name = "emif2",
+ .class = &dra7xx_emif_hwmod_class,
+ .clkdm_name = "emif_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_emif2_irqs,
+ .main_clk = "dpll_ddr_h11x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'gpio' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0114,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &dra7xx_gpio_sysc,
+ .rev = 2,
+};
+
+/* gpio dev_attr */
+static struct omap_gpio_dev_attr gpio_dev_attr = {
+ .bank_width = 32,
+ .dbck_flag = true,
+};
+
+/* gpio1 */
+static struct omap_hwmod_irq_info dra7xx_gpio1_irqs[] = {
+ { .irq = 29 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio1_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio1_hwmod = {
+ .name = "gpio1",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .mpu_irqs = dra7xx_gpio1_irqs,
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio2 */
+static struct omap_hwmod_irq_info dra7xx_gpio2_irqs[] = {
+ { .irq = 30 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio2_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio2_hwmod = {
+ .name = "gpio2",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio2_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio3 */
+static struct omap_hwmod_irq_info dra7xx_gpio3_irqs[] = {
+ { .irq = 31 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio3_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio3_hwmod = {
+ .name = "gpio3",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio3_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio4 */
+static struct omap_hwmod_irq_info dra7xx_gpio4_irqs[] = {
+ { .irq = 32 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio4_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio4_hwmod = {
+ .name = "gpio4",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio4_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio5 */
+static struct omap_hwmod_irq_info dra7xx_gpio5_irqs[] = {
+ { .irq = 33 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio5_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio5_hwmod = {
+ .name = "gpio5",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio5_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio5_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio6 */
+static struct omap_hwmod_irq_info dra7xx_gpio6_irqs[] = {
+ { .irq = 34 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio6_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio6_hwmod = {
+ .name = "gpio6",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio6_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio6_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio7 */
+static struct omap_hwmod_irq_info dra7xx_gpio7_irqs[] = {
+ { .irq = 35 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio7_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio7_hwmod = {
+ .name = "gpio7",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio7_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio7_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/* gpio8 */
+static struct omap_hwmod_irq_info dra7xx_gpio8_irqs[] = {
+ { .irq = 121 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
+ { .role = "dbclk", .clk = "gpio8_dbclk" },
+};
+
+static struct omap_hwmod dra7xx_gpio8_hwmod = {
+ .name = "gpio8",
+ .class = &dra7xx_gpio_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+ .mpu_irqs = dra7xx_gpio8_irqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = gpio8_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
+ .dev_attr = &gpio_dev_attr,
+};
+
+/*
+ * 'gpmc' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
+ .name = "gpmc",
+ .sysc = &dra7xx_gpmc_sysc,
+};
+
+/* gpmc */
+static struct omap_hwmod_irq_info dra7xx_gpmc_irqs[] = {
+ { .irq = 20 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_gpmc_sdma_reqs[] = {
+ { .dma_req = 3 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_gpmc_hwmod = {
+ .name = "gpmc",
+ .class = &dra7xx_gpmc_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_gpmc_irqs,
+ .sdma_reqs = dra7xx_gpmc_sdma_reqs,
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'hdq1w' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0014,
+ .syss_offs = 0x0018,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
+ .name = "hdq1w",
+ .sysc = &dra7xx_hdq1w_sysc,
+};
+
+/* hdq1w */
+static struct omap_hwmod_irq_info dra7xx_hdq1w_irqs[] = {
+ { .irq = 58 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_hdq1w_hwmod = {
+ .name = "hdq1w",
+ .class = &dra7xx_hdq1w_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_hdq1w_irqs,
+ .main_clk = "func_12m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'i2c' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0090,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .clockact = CLOCKACT_TEST_ICLK,
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
+ .name = "i2c",
+ .sysc = &dra7xx_i2c_sysc,
+ .reset = &omap_i2c_reset,
+ .rev = OMAP_I2C_IP_VERSION_2,
+};
+
+/* i2c dev_attr */
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
+};
+
+/* i2c1 */
+static struct omap_hwmod_irq_info dra7xx_i2c1_irqs[] = {
+ { .irq = 56 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_i2c1_sdma_reqs[] = {
+ { .name = "27", .dma_req = 26 + DRA7XX_DMA_REQ_START },
+ { .name = "28", .dma_req = 27 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c1_hwmod = {
+ .name = "i2c1",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c1_irqs,
+ .sdma_reqs = dra7xx_i2c1_sdma_reqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c2 */
+static struct omap_hwmod_irq_info dra7xx_i2c2_irqs[] = {
+ { .irq = 57 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_i2c2_sdma_reqs[] = {
+ { .name = "29", .dma_req = 28 + DRA7XX_DMA_REQ_START },
+ { .name = "30", .dma_req = 29 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c2_hwmod = {
+ .name = "i2c2",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c2_irqs,
+ .sdma_reqs = dra7xx_i2c2_sdma_reqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c3 */
+static struct omap_hwmod_irq_info dra7xx_i2c3_irqs[] = {
+ { .irq = 61 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_i2c3_sdma_reqs[] = {
+ { .name = "25", .dma_req = 24 + DRA7XX_DMA_REQ_START },
+ { .name = "26", .dma_req = 25 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c3_hwmod = {
+ .name = "i2c3",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c3_irqs,
+ .sdma_reqs = dra7xx_i2c3_sdma_reqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c4 */
+static struct omap_hwmod_irq_info dra7xx_i2c4_irqs[] = {
+ { .irq = 62 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_i2c4_sdma_reqs[] = {
+ { .name = "124", .dma_req = 123 + DRA7XX_DMA_REQ_START },
+ { .name = "125", .dma_req = 124 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c4_hwmod = {
+ .name = "i2c4",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c4_irqs,
+ .sdma_reqs = dra7xx_i2c4_sdma_reqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/* i2c5 */
+static struct omap_hwmod_irq_info dra7xx_i2c5_irqs[] = {
+ { .irq = 60 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_i2c5_hwmod = {
+ .name = "i2c5",
+ .class = &dra7xx_i2c_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
+ .mpu_irqs = dra7xx_i2c5_irqs,
+ .main_clk = "func_96m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &i2c_dev_attr,
+};
+
+/*
+ * 'mailbox' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &dra7xx_mailbox_sysc,
+};
+
+/* mailbox1 */
+static struct omap_hwmod dra7xx_mailbox1_hwmod = {
+ .name = "mailbox1",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox2 */
+static struct omap_hwmod dra7xx_mailbox2_hwmod = {
+ .name = "mailbox2",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox3 */
+static struct omap_hwmod dra7xx_mailbox3_hwmod = {
+ .name = "mailbox3",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox4 */
+static struct omap_hwmod dra7xx_mailbox4_hwmod = {
+ .name = "mailbox4",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox5 */
+static struct omap_hwmod dra7xx_mailbox5_hwmod = {
+ .name = "mailbox5",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox6 */
+static struct omap_hwmod dra7xx_mailbox6_hwmod = {
+ .name = "mailbox6",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox7 */
+static struct omap_hwmod dra7xx_mailbox7_hwmod = {
+ .name = "mailbox7",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox8 */
+static struct omap_hwmod dra7xx_mailbox8_hwmod = {
+ .name = "mailbox8",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox9 */
+static struct omap_hwmod dra7xx_mailbox9_hwmod = {
+ .name = "mailbox9",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox10 */
+static struct omap_hwmod dra7xx_mailbox10_hwmod = {
+ .name = "mailbox10",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox11 */
+static struct omap_hwmod dra7xx_mailbox11_hwmod = {
+ .name = "mailbox11",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox12 */
+static struct omap_hwmod dra7xx_mailbox12_hwmod = {
+ .name = "mailbox12",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* mailbox13 */
+static struct omap_hwmod dra7xx_mailbox13_hwmod = {
+ .name = "mailbox13",
+ .class = &dra7xx_mailbox_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'mcasp' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
+ .sysc_offs = 0x0004,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
+ .name = "mcasp",
+ .sysc = &dra7xx_mcasp_sysc,
+};
+
+/* mcasp1 */
+static struct omap_hwmod dra7xx_mcasp1_hwmod = {
+ .name = "mcasp1",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .main_clk = "mcasp1_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp2 */
+static struct omap_hwmod dra7xx_mcasp2_hwmod = {
+ .name = "mcasp2",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp2_ahclkr_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp3 */
+static struct omap_hwmod dra7xx_mcasp3_hwmod = {
+ .name = "mcasp3",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp3_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp4 */
+static struct omap_hwmod dra7xx_mcasp4_hwmod = {
+ .name = "mcasp4",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp4_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp5 */
+static struct omap_hwmod dra7xx_mcasp5_hwmod = {
+ .name = "mcasp5",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp5_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp6 */
+static struct omap_hwmod dra7xx_mcasp6_hwmod = {
+ .name = "mcasp6",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp6_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp7 */
+static struct omap_hwmod dra7xx_mcasp7_hwmod = {
+ .name = "mcasp7",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp7_ahclkx_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* mcasp8 */
+static struct omap_hwmod dra7xx_mcasp8_hwmod = {
+ .name = "mcasp8",
+ .class = &dra7xx_mcasp_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "mcasp8_ahclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'mcspi' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
+ .name = "mcspi",
+ .sysc = &dra7xx_mcspi_sysc,
+ .rev = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod_irq_info dra7xx_mcspi1_irqs[] = {
+ { .irq = 65 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mcspi1_sdma_reqs[] = {
+ { .name = "35", .dma_req = 34 + DRA7XX_DMA_REQ_START },
+ { .name = "36", .dma_req = 35 + DRA7XX_DMA_REQ_START },
+ { .name = "37", .dma_req = 36 + DRA7XX_DMA_REQ_START },
+ { .name = "38", .dma_req = 37 + DRA7XX_DMA_REQ_START },
+ { .name = "39", .dma_req = 38 + DRA7XX_DMA_REQ_START },
+ { .name = "40", .dma_req = 39 + DRA7XX_DMA_REQ_START },
+ { .name = "41", .dma_req = 40 + DRA7XX_DMA_REQ_START },
+ { .name = "42", .dma_req = 41 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* mcspi1 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
+ .num_chipselect = 4,
+};
+
+static struct omap_hwmod dra7xx_mcspi1_hwmod = {
+ .name = "mcspi1",
+ .class = &dra7xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mcspi1_irqs,
+ .sdma_reqs = dra7xx_mcspi1_sdma_reqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi1_dev_attr,
+};
+
+/* mcspi2 */
+static struct omap_hwmod_irq_info dra7xx_mcspi2_irqs[] = {
+ { .irq = 66 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mcspi2_sdma_reqs[] = {
+ { .name = "43", .dma_req = 42 + DRA7XX_DMA_REQ_START },
+ { .name = "44", .dma_req = 43 + DRA7XX_DMA_REQ_START },
+ { .name = "45", .dma_req = 44 + DRA7XX_DMA_REQ_START },
+ { .name = "46", .dma_req = 45 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* mcspi2 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
+ .num_chipselect = 2,
+};
+
+static struct omap_hwmod dra7xx_mcspi2_hwmod = {
+ .name = "mcspi2",
+ .class = &dra7xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mcspi2_irqs,
+ .sdma_reqs = dra7xx_mcspi2_sdma_reqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi2_dev_attr,
+};
+
+/* mcspi3 */
+static struct omap_hwmod_irq_info dra7xx_mcspi3_irqs[] = {
+ { .irq = 91 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mcspi3_sdma_reqs[] = {
+ { .name = "15", .dma_req = 14 + DRA7XX_DMA_REQ_START },
+ { .name = "16", .dma_req = 15 + DRA7XX_DMA_REQ_START },
+ { .name = "23", .dma_req = 22 + DRA7XX_DMA_REQ_START },
+ { .name = "24", .dma_req = 23 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* mcspi3 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
+ .num_chipselect = 2,
+};
+
+static struct omap_hwmod dra7xx_mcspi3_hwmod = {
+ .name = "mcspi3",
+ .class = &dra7xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mcspi3_irqs,
+ .sdma_reqs = dra7xx_mcspi3_sdma_reqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi3_dev_attr,
+};
+
+/* mcspi4 */
+static struct omap_hwmod_irq_info dra7xx_mcspi4_irqs[] = {
+ { .irq = 48 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mcspi4_sdma_reqs[] = {
+ { .name = "70", .dma_req = 69 + DRA7XX_DMA_REQ_START },
+ { .name = "71", .dma_req = 70 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+/* mcspi4 dev_attr */
+static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
+ .num_chipselect = 1,
+};
+
+static struct omap_hwmod dra7xx_mcspi4_hwmod = {
+ .name = "mcspi4",
+ .class = &dra7xx_mcspi_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mcspi4_irqs,
+ .sdma_reqs = dra7xx_mcspi4_sdma_reqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &mcspi4_dev_attr,
+};
+
+/*
+ * 'mmc' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
+ .name = "mmc",
+ .sysc = &dra7xx_mmc_sysc,
+};
+
+/* mmc1 */
+static struct omap_hwmod_irq_info dra7xx_mmc1_irqs[] = {
+ { .irq = 83 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mmc1_sdma_reqs[] = {
+ { .name = "61", .dma_req = 60 + DRA7XX_DMA_REQ_START },
+ { .name = "62", .dma_req = 61 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
+ { .role = "clk32k", .clk = "mmc1_clk32k" },
+};
+
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+ .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod dra7xx_mmc1_hwmod = {
+ .name = "mmc1",
+ .class = &dra7xx_mmc_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .mpu_irqs = dra7xx_mmc1_irqs,
+ .sdma_reqs = dra7xx_mmc1_sdma_reqs,
+ .main_clk = "mmc1_fclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mmc1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
+ .dev_attr = &mmc1_dev_attr,
+};
+
+/* mmc2 */
+static struct omap_hwmod_irq_info dra7xx_mmc2_irqs[] = {
+ { .irq = 86 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mmc2_sdma_reqs[] = {
+ { .name = "47", .dma_req = 46 + DRA7XX_DMA_REQ_START },
+ { .name = "48", .dma_req = 47 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
+ { .role = "clk32k", .clk = "mmc2_clk32k" },
+};
+
+static struct omap_hwmod dra7xx_mmc2_hwmod = {
+ .name = "mmc2",
+ .class = &dra7xx_mmc_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .mpu_irqs = dra7xx_mmc2_irqs,
+ .sdma_reqs = dra7xx_mmc2_sdma_reqs,
+ .main_clk = "mmc2_fclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mmc2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
+};
+
+/* mmc3 */
+static struct omap_hwmod_irq_info dra7xx_mmc3_irqs[] = {
+ { .irq = 94 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mmc3_sdma_reqs[] = {
+ { .name = "77", .dma_req = 76 + DRA7XX_DMA_REQ_START },
+ { .name = "78", .dma_req = 77 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
+ { .role = "clk32k", .clk = "mmc3_clk32k" },
+};
+
+static struct omap_hwmod dra7xx_mmc3_hwmod = {
+ .name = "mmc3",
+ .class = &dra7xx_mmc_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mmc3_irqs,
+ .sdma_reqs = dra7xx_mmc3_sdma_reqs,
+ .main_clk = "mmc3_gfclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mmc3_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
+};
+
+/* mmc4 */
+static struct omap_hwmod_irq_info dra7xx_mmc4_irqs[] = {
+ { .irq = 96 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_mmc4_sdma_reqs[] = {
+ { .name = "57", .dma_req = 56 + DRA7XX_DMA_REQ_START },
+ { .name = "58", .dma_req = 57 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
+ { .role = "clk32k", .clk = "mmc4_clk32k" },
+};
+
+static struct omap_hwmod dra7xx_mmc4_hwmod = {
+ .name = "mmc4",
+ .class = &dra7xx_mmc_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_mmc4_irqs,
+ .sdma_reqs = dra7xx_mmc4_sdma_reqs,
+ .main_clk = "mmc4_gfclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = mmc4_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
+};
+
+/*
+ * 'mpu' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
+ .name = "mpu",
+};
+
+/* mpu */
+static struct omap_hwmod_irq_info dra7xx_mpu_irqs[] = {
+ { .irq = 132 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_mpu_hwmod = {
+ .name = "mpu",
+ .class = &dra7xx_mpu_hwmod_class,
+ .clkdm_name = "mpu_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
+ .mpu_irqs = dra7xx_mpu_irqs,
+ .main_clk = "dpll_mpu_m2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'ocmc_ram' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_ocmc_ram_hwmod_class = {
+ .name = "ocmc_ram",
+};
+
+/* ocmc_ram1 */
+static struct omap_hwmod dra7xx_ocmc_ram1_hwmod = {
+ .name = "ocmc_ram1",
+ .class = &dra7xx_ocmc_ram_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* ocmc_ram2 */
+static struct omap_hwmod dra7xx_ocmc_ram2_hwmod = {
+ .name = "ocmc_ram2",
+ .class = &dra7xx_ocmc_ram_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* ocmc_ram3 */
+static struct omap_hwmod dra7xx_ocmc_ram3_hwmod = {
+ .name = "ocmc_ram3",
+ .class = &dra7xx_ocmc_ram_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'ocmc_rom' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_ocmc_rom_hwmod_class = {
+ .name = "ocmc_rom",
+};
+
+/* ocmc_rom */
+static struct omap_hwmod dra7xx_ocmc_rom_hwmod = {
+ .name = "ocmc_rom",
+ .class = &dra7xx_ocmc_rom_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'ocp2scp' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
+ .name = "ocp2scp",
+ .sysc = &dra7xx_ocp2scp_sysc,
+};
+
+/* ocp2scp1 */
+static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
+ .name = "ocp2scp1",
+ .class = &dra7xx_ocp2scp_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'pruss' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pruss_hwmod_class = {
+ .name = "pruss",
+};
+
+/* pruss1 */
+static struct omap_hwmod dra7xx_pruss1_hwmod = {
+ .name = "pruss1",
+ .class = &dra7xx_pruss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "dpll_per_m2x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pruss2 */
+static struct omap_hwmod dra7xx_pruss2_hwmod = {
+ .name = "pruss2",
+ .class = &dra7xx_pruss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "dpll_per_m2x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'pwmss' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pwmss_hwmod_class = {
+ .name = "pwmss",
+};
+
+/* pwmss1 */
+static struct omap_hwmod dra7xx_pwmss1_hwmod = {
+ .name = "pwmss1",
+ .class = &dra7xx_pwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pwmss2 */
+static struct omap_hwmod dra7xx_pwmss2_hwmod = {
+ .name = "pwmss2",
+ .class = &dra7xx_pwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pwmss3 */
+static struct omap_hwmod dra7xx_pwmss3_hwmod = {
+ .name = "pwmss3",
+ .class = &dra7xx_pwmss_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'qspi' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
+ .sysc_offs = 0x0010,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
+ .name = "qspi",
+ .sysc = &dra7xx_qspi_sysc,
+};
+
+/* qspi */
+static struct omap_hwmod dra7xx_qspi_hwmod = {
+ .name = "qspi",
+ .class = &dra7xx_qspi_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "qspi_gfclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'rtcss' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
+ .sysc_offs = 0x0078,
+ .sysc_flags = SYSC_HAS_SIDLEMODE,
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type3,
+};
+
+static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
+ .name = "rtcss",
+ .sysc = &dra7xx_rtcss_sysc,
+};
+
+/* rtcss */
+static struct omap_hwmod dra7xx_rtcss_hwmod = {
+ .name = "rtcss",
+ .class = &dra7xx_rtcss_hwmod_class,
+ .clkdm_name = "rtc_clkdm",
+ .main_clk = "sys_32k_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'sata' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
+ .sysc_offs = 0x0000,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
+ .name = "sata",
+ .sysc = &dra7xx_sata_sysc,
+};
+
+/* sata */
+static struct omap_hwmod_irq_info dra7xx_sata_irqs[] = {
+ { .irq = 54 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_opt_clk sata_opt_clks[] = {
+ { .role = "ref_clk", .clk = "sata_ref_clk" },
+};
+
+static struct omap_hwmod dra7xx_sata_hwmod = {
+ .name = "sata",
+ .class = &dra7xx_sata_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
+ .mpu_irqs = dra7xx_sata_irqs,
+ .main_clk = "func_48m_fclk",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .opt_clks = sata_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
+};
+
+/*
+ * 'smartreflex' class
+ *
+ */
+
+/* The IP is not compliant to type1 / type2 scheme */
+static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
+ .sidle_shift = 24,
+ .enwkup_shift = 26,
+};
+
+static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
+ .sysc_offs = 0x0038,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
+};
+
+static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
+ .name = "smartreflex",
+ .sysc = &dra7xx_smartreflex_sysc,
+ .rev = 2,
+};
+
+/* smartreflex_core */
+static struct omap_hwmod_irq_info dra7xx_smartreflex_core_irqs[] = {
+ { .irq = 19 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+/* smartreflex_core dev_attr */
+static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
+ .sensor_voltdm_name = "core",
+};
+
+static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
+ .name = "smartreflex_core",
+ .class = &dra7xx_smartreflex_hwmod_class,
+ .clkdm_name = "coreaon_clkdm",
+ .mpu_irqs = dra7xx_smartreflex_core_irqs,
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &smartreflex_core_dev_attr,
+};
+
+/* smartreflex_dspeve */
+static struct omap_hwmod dra7xx_smartreflex_dspeve_hwmod = {
+ .name = "smartreflex_dspeve",
+ .class = &dra7xx_smartreflex_hwmod_class,
+ .clkdm_name = "coreaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* smartreflex_gpu */
+static struct omap_hwmod dra7xx_smartreflex_gpu_hwmod = {
+ .name = "smartreflex_gpu",
+ .class = &dra7xx_smartreflex_hwmod_class,
+ .clkdm_name = "coreaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* smartreflex_mpu */
+static struct omap_hwmod_irq_info dra7xx_smartreflex_mpu_irqs[] = {
+ { .irq = 18 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+/* smartreflex_mpu dev_attr */
+static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
+ .sensor_voltdm_name = "mpu",
+};
+
+static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
+ .name = "smartreflex_mpu",
+ .class = &dra7xx_smartreflex_hwmod_class,
+ .clkdm_name = "coreaon_clkdm",
+ .mpu_irqs = dra7xx_smartreflex_mpu_irqs,
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+ .dev_attr = &smartreflex_mpu_dev_attr,
+};
+
+/*
+ * 'spare' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_spare_hwmod_class = {
+ .name = "spare",
+};
+
+/* spare_cme */
+static struct omap_hwmod dra7xx_spare_cme_hwmod = {
+ .name = "spare_cme",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_icm */
+static struct omap_hwmod dra7xx_spare_icm_hwmod = {
+ .name = "spare_icm",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_iva2 */
+static struct omap_hwmod dra7xx_spare_iva2_hwmod = {
+ .name = "spare_iva2",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_safety1 */
+static struct omap_hwmod dra7xx_spare_safety1_hwmod = {
+ .name = "spare_safety1",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_safety2 */
+static struct omap_hwmod dra7xx_spare_safety2_hwmod = {
+ .name = "spare_safety2",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_safety3 */
+static struct omap_hwmod dra7xx_spare_safety3_hwmod = {
+ .name = "spare_safety3",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_safety4 */
+static struct omap_hwmod dra7xx_spare_safety4_hwmod = {
+ .name = "spare_safety4",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown2 */
+static struct omap_hwmod dra7xx_spare_unknown2_hwmod = {
+ .name = "spare_unknown2",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown3 */
+static struct omap_hwmod dra7xx_spare_unknown3_hwmod = {
+ .name = "spare_unknown3",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "wkupaon_iclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown4 */
+static struct omap_hwmod dra7xx_spare_unknown4_hwmod = {
+ .name = "spare_unknown4",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown5 */
+static struct omap_hwmod dra7xx_spare_unknown5_hwmod = {
+ .name = "spare_unknown5",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_unknown6 */
+static struct omap_hwmod dra7xx_spare_unknown6_hwmod = {
+ .name = "spare_unknown6",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_videopll1 */
+static struct omap_hwmod dra7xx_spare_videopll1_hwmod = {
+ .name = "spare_videopll1",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_videopll2 */
+static struct omap_hwmod dra7xx_spare_videopll2_hwmod = {
+ .name = "spare_videopll2",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_videopll3 */
+static struct omap_hwmod dra7xx_spare_videopll3_hwmod = {
+ .name = "spare_videopll3",
+ .class = &dra7xx_spare_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'spare_sata2' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_spare_sata2_hwmod_class = {
+ .name = "spare_sata2",
+};
+
+/* spare_sata2 */
+static struct omap_hwmod dra7xx_spare_sata2_hwmod = {
+ .name = "spare_sata2",
+ .class = &dra7xx_spare_sata2_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'spare_smartreflex' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_spare_smartreflex_hwmod_class = {
+ .name = "spare_smartreflex",
+};
+
+/* spare_smartreflex_rtc */
+static struct omap_hwmod dra7xx_spare_smartreflex_rtc_hwmod = {
+ .name = "spare_smartreflex_rtc",
+ .class = &dra7xx_spare_smartreflex_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_smartreflex_sdram */
+static struct omap_hwmod dra7xx_spare_smartreflex_sdram_hwmod = {
+ .name = "spare_smartreflex_sdram",
+ .class = &dra7xx_spare_smartreflex_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* spare_smartreflex_wkup */
+static struct omap_hwmod dra7xx_spare_smartreflex_wkup_hwmod = {
+ .name = "spare_smartreflex_wkup",
+ .class = &dra7xx_spare_smartreflex_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'spinlock' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
+ .name = "spinlock",
+ .sysc = &dra7xx_spinlock_sysc,
+};
+
+/* spinlock */
+static struct omap_hwmod dra7xx_spinlock_hwmod = {
+ .name = "spinlock",
+ .class = &dra7xx_spinlock_hwmod_class,
+ .clkdm_name = "l4cfg_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'timer' class
+ *
+ * This class contains several variants: ['timer_1ms', 'timer_secure',
+ * 'timer']
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
+ .name = "timer",
+ .sysc = &dra7xx_timer_1ms_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
+ .name = "timer",
+ .sysc = &dra7xx_timer_secure_sysc,
+};
+
+static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &dra7xx_timer_sysc,
+};
+
+/* timer1 */
+static struct omap_hwmod_irq_info dra7xx_timer1_irqs[] = {
+ { .irq = 37 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer1_hwmod = {
+ .name = "timer1",
+ .class = &dra7xx_timer_1ms_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .mpu_irqs = dra7xx_timer1_irqs,
+ .main_clk = "timer1_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer2 */
+static struct omap_hwmod_irq_info dra7xx_timer2_irqs[] = {
+ { .irq = 38 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer2_hwmod = {
+ .name = "timer2",
+ .class = &dra7xx_timer_1ms_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer2_irqs,
+ .main_clk = "timer2_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer3 */
+static struct omap_hwmod_irq_info dra7xx_timer3_irqs[] = {
+ { .irq = 39 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer3_hwmod = {
+ .name = "timer3",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer3_irqs,
+ .main_clk = "timer3_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer4 */
+static struct omap_hwmod_irq_info dra7xx_timer4_irqs[] = {
+ { .irq = 40 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer4_hwmod = {
+ .name = "timer4",
+ .class = &dra7xx_timer_secure_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer4_irqs,
+ .main_clk = "timer4_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer5 */
+static struct omap_hwmod_irq_info dra7xx_timer5_irqs[] = {
+ { .irq = 41 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer5_hwmod = {
+ .name = "timer5",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_timer5_irqs,
+ .main_clk = "timer5_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer6 */
+static struct omap_hwmod_irq_info dra7xx_timer6_irqs[] = {
+ { .irq = 42 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer6_hwmod = {
+ .name = "timer6",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_timer6_irqs,
+ .main_clk = "timer6_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer7 */
+static struct omap_hwmod_irq_info dra7xx_timer7_irqs[] = {
+ { .irq = 43 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer7_hwmod = {
+ .name = "timer7",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_timer7_irqs,
+ .main_clk = "timer7_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer8 */
+static struct omap_hwmod_irq_info dra7xx_timer8_irqs[] = {
+ { .irq = 44 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer8_hwmod = {
+ .name = "timer8",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_timer8_irqs,
+ .main_clk = "timer8_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer9 */
+static struct omap_hwmod_irq_info dra7xx_timer9_irqs[] = {
+ { .irq = 45 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer9_hwmod = {
+ .name = "timer9",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer9_irqs,
+ .main_clk = "timer9_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer10 */
+static struct omap_hwmod_irq_info dra7xx_timer10_irqs[] = {
+ { .irq = 46 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer10_hwmod = {
+ .name = "timer10",
+ .class = &dra7xx_timer_1ms_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer10_irqs,
+ .main_clk = "timer10_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer11 */
+static struct omap_hwmod_irq_info dra7xx_timer11_irqs[] = {
+ { .irq = 47 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_timer11_hwmod = {
+ .name = "timer11",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_timer11_irqs,
+ .main_clk = "timer11_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer13 */
+static struct omap_hwmod dra7xx_timer13_hwmod = {
+ .name = "timer13",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .main_clk = "timer13_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer14 */
+static struct omap_hwmod dra7xx_timer14_hwmod = {
+ .name = "timer14",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .main_clk = "timer14_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer15 */
+static struct omap_hwmod dra7xx_timer15_hwmod = {
+ .name = "timer15",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .main_clk = "timer15_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* timer16 */
+static struct omap_hwmod dra7xx_timer16_hwmod = {
+ .name = "timer16",
+ .class = &dra7xx_timer_hwmod_class,
+ .clkdm_name = "l4per3_clkdm",
+ .main_clk = "timer16_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'uart' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
+ .rev_offs = 0x0050,
+ .sysc_offs = 0x0054,
+ .syss_offs = 0x0058,
+ .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
+ SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
+ .name = "uart",
+ .sysc = &dra7xx_uart_sysc,
+};
+
+/* uart1 */
+static struct omap_hwmod_irq_info dra7xx_uart1_irqs[] = {
+ { .irq = 72 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart1_sdma_reqs[] = {
+ { .name = "49", .dma_req = 48 + DRA7XX_DMA_REQ_START },
+ { .name = "50", .dma_req = 49 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart1_hwmod = {
+ .name = "uart1",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_uart1_irqs,
+ .sdma_reqs = dra7xx_uart1_sdma_reqs,
+ .main_clk = "uart1_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart2 */
+static struct omap_hwmod_irq_info dra7xx_uart2_irqs[] = {
+ { .irq = 73 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart2_sdma_reqs[] = {
+ { .name = "51", .dma_req = 50 + DRA7XX_DMA_REQ_START },
+ { .name = "52", .dma_req = 51 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart2_hwmod = {
+ .name = "uart2",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_uart2_irqs,
+ .sdma_reqs = dra7xx_uart2_sdma_reqs,
+ .main_clk = "uart2_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart3 */
+static struct omap_hwmod_irq_info dra7xx_uart3_irqs[] = {
+ { .irq = 74 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart3_sdma_reqs[] = {
+ { .name = "53", .dma_req = 52 + DRA7XX_DMA_REQ_START },
+ { .name = "54", .dma_req = 53 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart3_hwmod = {
+ .name = "uart3",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+ HWMOD_SWSUP_SIDLE_ACT,
+ .mpu_irqs = dra7xx_uart3_irqs,
+ .sdma_reqs = dra7xx_uart3_sdma_reqs,
+ .main_clk = "uart3_gfclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart4 */
+static struct omap_hwmod_irq_info dra7xx_uart4_irqs[] = {
+ { .irq = 70 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart4_sdma_reqs[] = {
+ { .name = "55", .dma_req = 54 + DRA7XX_DMA_REQ_START },
+ { .name = "56", .dma_req = 55 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart4_hwmod = {
+ .name = "uart4",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_uart4_irqs,
+ .sdma_reqs = dra7xx_uart4_sdma_reqs,
+ .main_clk = "uart4_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart5 */
+static struct omap_hwmod_irq_info dra7xx_uart5_irqs[] = {
+ { .irq = 105 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart5_sdma_reqs[] = {
+ { .name = "63", .dma_req = 62 + DRA7XX_DMA_REQ_START },
+ { .name = "64", .dma_req = 63 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart5_hwmod = {
+ .name = "uart5",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per_clkdm",
+ .mpu_irqs = dra7xx_uart5_irqs,
+ .sdma_reqs = dra7xx_uart5_sdma_reqs,
+ .main_clk = "uart5_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart6 */
+static struct omap_hwmod_irq_info dra7xx_uart6_irqs[] = {
+ { .irq = 106 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod_dma_info dra7xx_uart6_sdma_reqs[] = {
+ { .name = "79", .dma_req = 78 + DRA7XX_DMA_REQ_START },
+ { .name = "80", .dma_req = 79 + DRA7XX_DMA_REQ_START },
+ { .dma_req = -1 }
+};
+
+static struct omap_hwmod dra7xx_uart6_hwmod = {
+ .name = "uart6",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "ipu_clkdm",
+ .mpu_irqs = dra7xx_uart6_irqs,
+ .sdma_reqs = dra7xx_uart6_sdma_reqs,
+ .main_clk = "uart6_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart7 */
+static struct omap_hwmod dra7xx_uart7_hwmod = {
+ .name = "uart7",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "uart7_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart8 */
+static struct omap_hwmod dra7xx_uart8_hwmod = {
+ .name = "uart8",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "uart8_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart9 */
+static struct omap_hwmod dra7xx_uart9_hwmod = {
+ .name = "uart9",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "l4per2_clkdm",
+ .main_clk = "uart9_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* uart10 */
+static struct omap_hwmod dra7xx_uart10_hwmod = {
+ .name = "uart10",
+ .class = &dra7xx_uart_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .main_clk = "uart10_gfclk_mux",
+ .flags = HWMOD_SWSUP_SIDLE_ACT,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
+ * 'usb_otg_ss' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
+ .name = "usb_otg_ss",
+};
+
+/* usb_otg_ss1 */
+static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
+ { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
+};
+
+static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
+ .name = "usb_otg_ss1",
+ .class = &dra7xx_usb_otg_ss_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "dpll_core_h13x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = usb_otg_ss1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
+};
+
+/* usb_otg_ss2 */
+static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
+ { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
+};
+
+static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
+ .name = "usb_otg_ss2",
+ .class = &dra7xx_usb_otg_ss_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "dpll_core_h13x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+ .opt_clks = usb_otg_ss2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
+};
+
+/* usb_otg_ss3 */
+static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
+ .name = "usb_otg_ss3",
+ .class = &dra7xx_usb_otg_ss_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "dpll_core_h13x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* usb_otg_ss4 */
+static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
+ .name = "usb_otg_ss4",
+ .class = &dra7xx_usb_otg_ss_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "dpll_core_h13x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'vcp' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
+ .name = "vcp",
+};
+
+/* vcp1 */
+static struct omap_hwmod dra7xx_vcp1_hwmod = {
+ .name = "vcp1",
+ .class = &dra7xx_vcp_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/* vcp2 */
+static struct omap_hwmod dra7xx_vcp2_hwmod = {
+ .name = "vcp2",
+ .class = &dra7xx_vcp_hwmod_class,
+ .clkdm_name = "l3main1_clkdm",
+ .main_clk = "l3_iclk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
+ },
+ },
+};
+
+/*
+ * 'vip' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_vip_sysc = {
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_vip_hwmod_class = {
+ .name = "vip",
+ .sysc = &dra7xx_vip_sysc,
+};
+
+/* vip1 */
+static struct omap_hwmod dra7xx_vip1_hwmod = {
+ .name = "vip1",
+ .class = &dra7xx_vip_hwmod_class,
+ .clkdm_name = "cam_clkdm",
+ .main_clk = "vip1_gclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* vip2 */
+static struct omap_hwmod dra7xx_vip2_hwmod = {
+ .name = "vip2",
+ .class = &dra7xx_vip_hwmod_class,
+ .clkdm_name = "cam_clkdm",
+ .main_clk = "vip2_gclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/* vip3 */
+static struct omap_hwmod dra7xx_vip3_hwmod = {
+ .name = "vip3",
+ .class = &dra7xx_vip_hwmod_class,
+ .clkdm_name = "cam_clkdm",
+ .main_clk = "vip3_gclk_mux",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'vpe' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_vpe_sysc = {
+ .sysc_offs = 0x0010,
+ .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class dra7xx_vpe_hwmod_class = {
+ .name = "vpe",
+ .sysc = &dra7xx_vpe_sysc,
+};
+
+/* vpe */
+static struct omap_hwmod dra7xx_vpe_hwmod = {
+ .name = "vpe",
+ .class = &dra7xx_vpe_hwmod_class,
+ .clkdm_name = "vpe_clkdm",
+ .main_clk = "dpll_core_h23x2_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
+};
+
+/*
+ * 'wd_timer' class
+ *
+ */
+
+static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ SIDLE_SMART_WKUP),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+ .sysc = &dra7xx_wd_timer_sysc,
+ .pre_shutdown = &omap2_wd_timer_disable,
+ .reset = &omap2_wd_timer_reset,
+};
+
+/* wd_timer2 */
+static struct omap_hwmod_irq_info dra7xx_wd_timer2_irqs[] = {
+ { .irq = 80 + DRA7XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
+static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
+ .name = "wd_timer2",
+ .class = &dra7xx_wd_timer_hwmod_class,
+ .clkdm_name = "wkupaon_clkdm",
+ .mpu_irqs = dra7xx_wd_timer2_irqs,
+ .main_clk = "sys_32k_ck",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+
+/*
+ * Interfaces
+ */
+
+static struct omap_hwmod_addr_space dra7xx_dmm_addrs[] = {
+ {
+ .pa_start = 0x4e000000,
+ .pa_end = 0x4e0007ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> dmm */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_dmm_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dmm_addrs,
+ .user = OCP_USER_SDMA,
+};
+
+/* dmm -> emif_ocp_fw */
+static struct omap_hwmod_ocp_if dra7xx_dmm__emif_ocp_fw = {
+ .master = &dra7xx_dmm_hwmod,
+ .slave = &dra7xx_emif_ocp_fw_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> emif_ocp_fw */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__emif_ocp_fw = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_emif_ocp_fw_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> l3_instr */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
+ .master = &dra7xx_l3_main_2_hwmod,
+ .slave = &dra7xx_l3_instr_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* ocp_wp_noc -> l3_instr */
+static struct omap_hwmod_ocp_if dra7xx_ocp_wp_noc__l3_instr = {
+ .master = &dra7xx_ocp_wp_noc_hwmod,
+ .slave = &dra7xx_l3_instr_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> l3_main_1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_l3_main_1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_l3_main_1_addrs[] = {
+ {
+ .pa_start = 0x44000000,
+ .pa_end = 0x44805fff,
+ },
+ { }
+};
+
+/* mpu -> l3_main_1 */
+static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
+ .master = &dra7xx_mpu_hwmod,
+ .slave = &dra7xx_l3_main_1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_l3_main_1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space dra7xx_l3_main_2_addrs[] = {
+ {
+ .pa_start = 0x45000000,
+ .pa_end = 0x4500afff,
+ },
+ { }
+};
+
+/* l3_main_1 -> l3_main_2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l3_main_2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_l3_main_2_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4_cfg -> l3_main_2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_l3_main_2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_cfg */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_cfg_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_per1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_per1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_per2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_per2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_per3 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_per3_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> l4_wkup */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_l4_wkup_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mpu -> mpu_private */
+static struct omap_hwmod_ocp_if dra7xx_mpu__mpu_private = {
+ .master = &dra7xx_mpu_hwmod,
+ .slave = &dra7xx_mpu_private_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_2 -> ocp_wp_noc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_2__ocp_wp_noc = {
+ .master = &dra7xx_l3_main_2_hwmod,
+ .slave = &dra7xx_ocp_wp_noc_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_ocp_wp_noc_addrs[] = {
+ {
+ .pa_start = 0x4a102000,
+ .pa_end = 0x4a10207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> ocp_wp_noc */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp_wp_noc = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_ocp_wp_noc_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_ocp_wp_noc_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* l4_per2 -> atl */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_atl_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_bb2d_addrs[] = {
+ {
+ .pa_start = 0x59000000,
+ .pa_end = 0x590007ff,
+ },
+ { }
+};
+
+/* l3_main_1 -> bb2d */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_bb2d_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_bb2d_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_counter_32k_addrs[] = {
+ {
+ .pa_start = 0x4ae04000,
+ .pa_end = 0x4ae0403f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> counter_32k */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_counter_32k_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_counter_32k_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_ctrl_module_wkup_addrs[] = {
+ {
+ .name = "avatar_control_wkup_ocpintf",
+ .pa_start = 0x4ae0c100,
+ .pa_end = 0x4ae0c8ff,
+ },
+ {
+ .name = "avatar_control_wkup_pad_ocpintf",
+ .pa_start = 0x4ae0c5a0,
+ .pa_end = 0x4ae0c61f,
+ },
+ { }
+};
+
+/* l4_wkup -> ctrl_module_wkup */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_ctrl_module_wkup_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_ctrl_module_wkup_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> dcan1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_dcan1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> dcan2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_dcan2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
+ {
+ .pa_start = 0x4a056000,
+ .pa_end = 0x4a056fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> dma_system */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_dma_system_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dma_system_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
+ {
+ .name = "family",
+ .pa_start = 0x58000000,
+ .pa_end = 0x5800007f,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "pllctrl1",
+ .pa_start = 0x58004000,
+ .pa_end = 0x5800433f,
+ },
+ {
+ .name = "pllctrl2",
+ .pa_start = 0x58005000,
+ .pa_end = 0x5800533f,
+ },
+};
+
+/* l3_main_1 -> dss */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_dss_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
+ {
+ .name = "dispc",
+ .pa_start = 0x58001000,
+ .pa_end = 0x58001fff,
+ .flags = ADDR_TYPE_RT
+ },
+};
+
+/* l3_main_1 -> dispc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_dss_dispc_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dss_dispc_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
+ {
+ .name = "hdmi_wp",
+ .pa_start = 0x58040000,
+ .pa_end = 0x580400ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "pllctrl",
+ .pa_start = 0x58040200,
+ .pa_end = 0x5804023f,
+ },
+ {
+ .name = "hdmitxphy",
+ .pa_start = 0x58040300,
+ .pa_end = 0x5804033f,
+ },
+ {
+ .name = "hdmi_core",
+ .pa_start = 0x58060000,
+ .pa_end = 0x58078fff,
+ },
+ {
+ .name = "deshdcp",
+ .pa_start = 0x58007000,
+ .pa_end = 0x5800707f,
+ },
+ { }
+};
+
+/* l3_main_1 -> dispc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_dss_hdmi_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_dss_hdmi_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
+ {
+ .pa_start = 0x48078000,
+ .pa_end = 0x48078fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> elm */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_elm_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_elm_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* emif_ocp_fw -> emif1 */
+static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif1 = {
+ .master = &dra7xx_emif_ocp_fw_hwmod,
+ .slave = &dra7xx_emif1_hwmod,
+ .clk = "dpll_ddr_h11x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_emif1_addrs[] = {
+ {
+ .pa_start = 0x4c000000,
+ .pa_end = 0x4c0003ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* mpu -> emif1 */
+static struct omap_hwmod_ocp_if dra7xx_mpu__emif1 = {
+ .master = &dra7xx_mpu_hwmod,
+ .slave = &dra7xx_emif1_hwmod,
+ .clk = "dpll_ddr_h11x2_ck",
+ .addr = dra7xx_emif1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+/* emif_ocp_fw -> emif2 */
+static struct omap_hwmod_ocp_if dra7xx_emif_ocp_fw__emif2 = {
+ .master = &dra7xx_emif_ocp_fw_hwmod,
+ .slave = &dra7xx_emif2_hwmod,
+ .clk = "dpll_ddr_h11x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_emif2_addrs[] = {
+ {
+ .pa_start = 0x4d000000,
+ .pa_end = 0x4d0003ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* mpu -> emif2 */
+static struct omap_hwmod_ocp_if dra7xx_mpu__emif2 = {
+ .master = &dra7xx_mpu_hwmod,
+ .slave = &dra7xx_emif2_hwmod,
+ .clk = "dpll_ddr_h11x2_ck",
+ .addr = dra7xx_emif2_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio1_addrs[] = {
+ {
+ .pa_start = 0x4ae10000,
+ .pa_end = 0x4ae101ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> gpio1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_gpio1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_gpio1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio2_addrs[] = {
+ {
+ .pa_start = 0x48055000,
+ .pa_end = 0x480551ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio3_addrs[] = {
+ {
+ .pa_start = 0x48057000,
+ .pa_end = 0x480571ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio4_addrs[] = {
+ {
+ .pa_start = 0x48059000,
+ .pa_end = 0x480591ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio5_addrs[] = {
+ {
+ .pa_start = 0x4805b000,
+ .pa_end = 0x4805b1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio6_addrs[] = {
+ {
+ .pa_start = 0x4805d000,
+ .pa_end = 0x4805d1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio7_addrs[] = {
+ {
+ .pa_start = 0x48051000,
+ .pa_end = 0x480511ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpio8_addrs[] = {
+ {
+ .pa_start = 0x48053000,
+ .pa_end = 0x480531ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> gpio8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_gpio8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpio8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
+ {
+ .pa_start = 0x50000000,
+ .pa_end = 0x500003ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> gpmc */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_gpmc_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_gpmc_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
+ {
+ .pa_start = 0x480b2000,
+ .pa_end = 0x480b201f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> hdq1w */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_hdq1w_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_hdq1w_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c1_addrs[] = {
+ {
+ .pa_start = 0x48070000,
+ .pa_end = 0x480700ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c2_addrs[] = {
+ {
+ .pa_start = 0x48072000,
+ .pa_end = 0x480720ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c3_addrs[] = {
+ {
+ .pa_start = 0x48060000,
+ .pa_end = 0x480600ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c4_addrs[] = {
+ {
+ .pa_start = 0x4807a000,
+ .pa_end = 0x4807a0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_i2c5_addrs[] = {
+ {
+ .pa_start = 0x4807c000,
+ .pa_end = 0x4807c0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> i2c5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_i2c5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_i2c5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox1_addrs[] = {
+ {
+ .pa_start = 0x4a0f4000,
+ .pa_end = 0x4a0f41ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> mailbox1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_mailbox1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox2_addrs[] = {
+ {
+ .pa_start = 0x4883a000,
+ .pa_end = 0x4883a1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox3_addrs[] = {
+ {
+ .pa_start = 0x4883c000,
+ .pa_end = 0x4883c1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox4_addrs[] = {
+ {
+ .pa_start = 0x4883e000,
+ .pa_end = 0x4883e1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox5_addrs[] = {
+ {
+ .pa_start = 0x48840000,
+ .pa_end = 0x488401ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox6_addrs[] = {
+ {
+ .pa_start = 0x48842000,
+ .pa_end = 0x488421ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox7_addrs[] = {
+ {
+ .pa_start = 0x48844000,
+ .pa_end = 0x488441ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox8_addrs[] = {
+ {
+ .pa_start = 0x48846000,
+ .pa_end = 0x488461ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox9_addrs[] = {
+ {
+ .pa_start = 0x4885e000,
+ .pa_end = 0x4885e1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox9 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox9_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox10_addrs[] = {
+ {
+ .pa_start = 0x48860000,
+ .pa_end = 0x488601ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox10 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox10_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox11_addrs[] = {
+ {
+ .pa_start = 0x48862000,
+ .pa_end = 0x488621ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox11 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox11_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox12_addrs[] = {
+ {
+ .pa_start = 0x48864000,
+ .pa_end = 0x488641ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox12 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox12_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox12_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mailbox13_addrs[] = {
+ {
+ .pa_start = 0x48802000,
+ .pa_end = 0x488021ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> mailbox13 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_mailbox13_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mailbox13_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_mcasp1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp1_addrs[] = {
+ {
+ .pa_start = 0x48460000,
+ .pa_end = 0x484603ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp1_addrs,
+ .user = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp2_addrs[] = {
+ {
+ .pa_start = 0x48464000,
+ .pa_end = 0x484643ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> mcasp2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_mcasp2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp3_addrs[] = {
+ {
+ .pa_start = 0x48468000,
+ .pa_end = 0x484683ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> mcasp3 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_mcasp3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp4_addrs[] = {
+ {
+ .pa_start = 0x4846c000,
+ .pa_end = 0x4846c3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp5_addrs[] = {
+ {
+ .pa_start = 0x48470000,
+ .pa_end = 0x484703ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp6_addrs[] = {
+ {
+ .pa_start = 0x48474000,
+ .pa_end = 0x484743ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp7_addrs[] = {
+ {
+ .pa_start = 0x48478000,
+ .pa_end = 0x484783ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcasp8_addrs[] = {
+ {
+ .pa_start = 0x4847c000,
+ .pa_end = 0x4847c3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> mcasp8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_mcasp8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcasp8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcspi1_addrs[] = {
+ {
+ .pa_start = 0x48098000,
+ .pa_end = 0x480981ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mcspi1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mcspi1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcspi1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcspi2_addrs[] = {
+ {
+ .pa_start = 0x4809a000,
+ .pa_end = 0x4809a1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mcspi2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mcspi2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcspi2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcspi3_addrs[] = {
+ {
+ .pa_start = 0x480b8000,
+ .pa_end = 0x480b81ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mcspi3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mcspi3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcspi3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mcspi4_addrs[] = {
+ {
+ .pa_start = 0x480ba000,
+ .pa_end = 0x480ba1ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mcspi4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mcspi4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mcspi4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mmc1_addrs[] = {
+ {
+ .pa_start = 0x4809c000,
+ .pa_end = 0x4809c3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mmc1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mmc1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mmc1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mmc2_addrs[] = {
+ {
+ .pa_start = 0x480b4000,
+ .pa_end = 0x480b43ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mmc2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mmc2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mmc2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mmc3_addrs[] = {
+ {
+ .pa_start = 0x480ad000,
+ .pa_end = 0x480ad3ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mmc3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mmc3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mmc3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mmc4_addrs[] = {
+ {
+ .pa_start = 0x480d1000,
+ .pa_end = 0x480d13ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> mmc4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_mmc4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mmc4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_mpu_addrs[] = {
+ {
+ .pa_start = 0x47000000,
+ .pa_end = 0x482af27f,
+ },
+ { }
+};
+
+/* l4_cfg -> mpu */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_mpu_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_mpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> ocmc_ram1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram1 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_ocmc_ram1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> ocmc_ram2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_ocmc_ram2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> ocmc_ram3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__ocmc_ram3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_ocmc_ram3_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> ocmc_rom */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__ocmc_rom = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_ocmc_rom_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
+ {
+ .pa_start = 0x4a080000,
+ .pa_end = 0x4a08001f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> ocp2scp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_ocp2scp1_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_ocp2scp1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_pruss1_addrs[] = {
+ {
+ .name = "u_intc",
+ .pa_start = 0x4b220000,
+ .pa_end = 0x4b221fff,
+ },
+ {
+ .name = "u_pru0_ctrl",
+ .pa_start = 0x4b222000,
+ .pa_end = 0x4b22203f,
+ },
+ {
+ .name = "u_pru0_debug",
+ .pa_start = 0x4b222400,
+ .pa_end = 0x4b2224ff,
+ },
+ {
+ .name = "u_pru1_ctrl",
+ .pa_start = 0x4b224000,
+ .pa_end = 0x4b22403f,
+ },
+ {
+ .name = "u_pru1_debug",
+ .pa_start = 0x4b224400,
+ .pa_end = 0x4b2244ff,
+ },
+ {
+ .name = "u_cfg",
+ .pa_start = 0x4b226000,
+ .pa_end = 0x4b22607f,
+ },
+ {
+ .name = "u_uart",
+ .pa_start = 0x4b228000,
+ .pa_end = 0x4b22803f,
+ },
+ {
+ .name = "u_iep",
+ .pa_start = 0x4b22e000,
+ .pa_end = 0x4b22e3ff,
+ },
+ {
+ .name = "u_ecap",
+ .pa_start = 0x4b230000,
+ .pa_end = 0x4b23007f,
+ },
+ {
+ .name = "u_mii_rt_cfg",
+ .pa_start = 0x4b232000,
+ .pa_end = 0x4b23207f,
+ },
+ {
+ .name = "u_mii_mdio",
+ .pa_start = 0x4b232400,
+ .pa_end = 0x4b2324ff,
+ },
+ { }
+};
+
+/* l3_main_1 -> pruss1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pruss1_hwmod,
+ .clk = "dpll_gmac_h13x2_ck",
+ .addr = dra7xx_pruss1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_pruss2_addrs[] = {
+ {
+ .name = "u_intc",
+ .pa_start = 0x4b2a0000,
+ .pa_end = 0x4b2a1fff,
+ },
+ {
+ .name = "u_pru0_ctrl",
+ .pa_start = 0x4b2a2000,
+ .pa_end = 0x4b2a203f,
+ },
+ {
+ .name = "u_pru0_debug",
+ .pa_start = 0x4b2a2400,
+ .pa_end = 0x4b2a24ff,
+ },
+ {
+ .name = "u_pru1_ctrl",
+ .pa_start = 0x4b2a4000,
+ .pa_end = 0x4b2a403f,
+ },
+ {
+ .name = "u_pru1_debug",
+ .pa_start = 0x4b2a4400,
+ .pa_end = 0x4b2a44ff,
+ },
+ {
+ .name = "u_cfg",
+ .pa_start = 0x4b2a6000,
+ .pa_end = 0x4b2a607f,
+ },
+ {
+ .name = "u_uart",
+ .pa_start = 0x4b2a8000,
+ .pa_end = 0x4b2a803f,
+ },
+ {
+ .name = "u_iep",
+ .pa_start = 0x4b2ae000,
+ .pa_end = 0x4b2ae3ff,
+ },
+ {
+ .name = "u_ecap",
+ .pa_start = 0x4b2b0000,
+ .pa_end = 0x4b2b007f,
+ },
+ {
+ .name = "u_mii_rt_cfg",
+ .pa_start = 0x4b2b2000,
+ .pa_end = 0x4b2b207f,
+ },
+ {
+ .name = "u_mii_mdio",
+ .pa_start = 0x4b2b2400,
+ .pa_end = 0x4b2b24ff,
+ },
+ { }
+};
+
+/* l3_main_1 -> pruss2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pruss2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pruss2_hwmod,
+ .clk = "dpll_gmac_h13x2_ck",
+ .addr = dra7xx_pruss2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> pwmss1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss1 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_pwmss1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> pwmss2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss2 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_pwmss2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> pwmss3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__pwmss3 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_pwmss3_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
+ {
+ .pa_start = 0x4b300000,
+ .pa_end = 0x4b30007f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l3_main_1 -> qspi */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_qspi_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_qspi_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_rtcss_addrs[] = {
+ {
+ .pa_start = 0x48838000,
+ .pa_end = 0x488380ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> rtcss */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_rtcss_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_rtcss_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
+ {
+ .name = "ahci",
+ .pa_start = 0x4a140000,
+ .pa_end = 0x4a1401ff,
+ },
+ {
+ .name = "sysc",
+ .pa_start = 0x4a141100,
+ .pa_end = 0x4a141107,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> sata */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_sata_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_sata_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
+ {
+ .pa_start = 0x4a0dd000,
+ .pa_end = 0x4a0dd07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_core */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_smartreflex_core_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_smartreflex_core_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_dspeve_addrs[] = {
+ {
+ .pa_start = 0x4a183000,
+ .pa_end = 0x4a18307f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_dspeve */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_dspeve = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_smartreflex_dspeve_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_smartreflex_dspeve_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_gpu_addrs[] = {
+ {
+ .pa_start = 0x4a185000,
+ .pa_end = 0x4a18507f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_gpu */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_gpu = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_smartreflex_gpu_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_smartreflex_gpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
+ {
+ .pa_start = 0x4a0d9000,
+ .pa_end = 0x4a0d907f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> smartreflex_mpu */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_smartreflex_mpu_hwmod,
+ .clk = "l4_root_clk_div",
+ .addr = dra7xx_smartreflex_mpu_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_cme */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_cme = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_cme_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_icm */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_icm = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_icm_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> spare_iva2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__spare_iva2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_spare_iva2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_safety1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety1 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_safety1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_safety2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety2 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_safety2_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_safety3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety3 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_safety3_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_safety4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_safety4 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_safety4_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_unknown2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown2 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_unknown2_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_wkup -> spare_unknown3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__spare_unknown3 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_spare_unknown3_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> spare_unknown4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown4 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_spare_unknown4_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> spare_unknown5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown5 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_spare_unknown5_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> spare_unknown6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__spare_unknown6 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_spare_unknown6_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_videopll1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll1 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_videopll1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_videopll2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_videopll2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_videopll3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_videopll3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_videopll3_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> spare_sata2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__spare_sata2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_spare_sata2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> spare_smartreflex_rtc */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_rtc = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_spare_smartreflex_rtc_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> spare_smartreflex_sdram */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_sdram = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_spare_smartreflex_sdram_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> spare_smartreflex_wkup */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spare_smartreflex_wkup = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_spare_smartreflex_wkup_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
+ {
+ .pa_start = 0x4a0f6000,
+ .pa_end = 0x4a0f6fff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_cfg -> spinlock */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_spinlock_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_spinlock_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer1_addrs[] = {
+ {
+ .pa_start = 0x4ae18000,
+ .pa_end = 0x4ae1807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_timer1_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_timer1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer2_addrs[] = {
+ {
+ .pa_start = 0x48032000,
+ .pa_end = 0x4803207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer3_addrs[] = {
+ {
+ .pa_start = 0x48034000,
+ .pa_end = 0x4803407f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer4_addrs[] = {
+ {
+ .pa_start = 0x48036000,
+ .pa_end = 0x4803607f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer5_addrs[] = {
+ {
+ .pa_start = 0x48820000,
+ .pa_end = 0x4882007f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer6_addrs[] = {
+ {
+ .pa_start = 0x48822000,
+ .pa_end = 0x4882207f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer7_addrs[] = {
+ {
+ .pa_start = 0x48824000,
+ .pa_end = 0x4882407f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer8_addrs[] = {
+ {
+ .pa_start = 0x48826000,
+ .pa_end = 0x4882607f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer9_addrs[] = {
+ {
+ .pa_start = 0x4803e000,
+ .pa_end = 0x4803e07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer9 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer9_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer10_addrs[] = {
+ {
+ .pa_start = 0x48086000,
+ .pa_end = 0x4808607f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer10 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer10_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer11_addrs[] = {
+ {
+ .pa_start = 0x48088000,
+ .pa_end = 0x4808807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> timer11 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_timer11_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer11_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer13_addrs[] = {
+ {
+ .pa_start = 0x48828000,
+ .pa_end = 0x4882807f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer13 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer13_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer13_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer14_addrs[] = {
+ {
+ .pa_start = 0x4882a000,
+ .pa_end = 0x4882a07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer14 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer14_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer14_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer15_addrs[] = {
+ {
+ .pa_start = 0x4882c000,
+ .pa_end = 0x4882c07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer15 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer15_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer15_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_timer16_addrs[] = {
+ {
+ .pa_start = 0x4882e000,
+ .pa_end = 0x4882e07f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per3 -> timer16 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_timer16_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_timer16_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart1_addrs[] = {
+ {
+ .pa_start = 0x4806a000,
+ .pa_end = 0x4806a0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart2_addrs[] = {
+ {
+ .pa_start = 0x4806c000,
+ .pa_end = 0x4806c0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart3_addrs[] = {
+ {
+ .pa_start = 0x48020000,
+ .pa_end = 0x480200ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart4_addrs[] = {
+ {
+ .pa_start = 0x4806e000,
+ .pa_end = 0x4806e0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart4_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart4_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart5_addrs[] = {
+ {
+ .pa_start = 0x48066000,
+ .pa_end = 0x480660ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart5 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart5_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart5_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart6_addrs[] = {
+ {
+ .pa_start = 0x48068000,
+ .pa_end = 0x480680ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per1 -> uart6 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
+ .master = &dra7xx_l4_per1_hwmod,
+ .slave = &dra7xx_uart6_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart6_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart7_addrs[] = {
+ {
+ .pa_start = 0x48420000,
+ .pa_end = 0x484200ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> uart7 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_uart7_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart7_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart8_addrs[] = {
+ {
+ .pa_start = 0x48422000,
+ .pa_end = 0x484220ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> uart8 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_uart8_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart8_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart9_addrs[] = {
+ {
+ .pa_start = 0x48424000,
+ .pa_end = 0x484240ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_per2 -> uart9 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_uart9_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_uart9_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_uart10_addrs[] = {
+ {
+ .pa_start = 0x4ae2b000,
+ .pa_end = 0x4ae2b0ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> uart10 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_uart10_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_uart10_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_usb_otg_ss1_hwmod,
+ .clk = "dpll_core_h13x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_usb_otg_ss2_hwmod,
+ .clk = "dpll_core_h13x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_usb_otg_ss3_hwmod,
+ .clk = "dpll_core_h13x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per3 -> usb_otg_ss4 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_usb_otg_ss4_hwmod,
+ .clk = "dpll_core_h13x2_ck",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> vcp1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_vcp1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> vcp1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_vcp1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> vcp2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_vcp2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_per2 -> vcp2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
+ .master = &dra7xx_l4_per2_hwmod,
+ .slave = &dra7xx_vcp2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_vip1_addrs[] = {
+ {
+ .name = "vip_top_level",
+ .pa_start = 0x48970000,
+ .pa_end = 0x489701ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "vip_slice0_parser",
+ .pa_start = 0x48975500,
+ .pa_end = 0x489755ff,
+ },
+ {
+ .name = "vip_slice0_csc",
+ .pa_start = 0x48975700,
+ .pa_end = 0x4897571f,
+ },
+ {
+ .name = "vip_slice0_sc",
+ .pa_start = 0x48975800,
+ .pa_end = 0x4897587f,
+ },
+ {
+ .name = "vip_slice1_parser",
+ .pa_start = 0x48975a00,
+ .pa_end = 0x48975aff,
+ },
+ {
+ .name = "vip_slice1_csc",
+ .pa_start = 0x48975c00,
+ .pa_end = 0x48975c1f,
+ },
+ {
+ .name = "vip_slice1_sc",
+ .pa_start = 0x48975d00,
+ .pa_end = 0x48975d7f,
+ },
+ {
+ .name = "vip_vpdma",
+ .pa_start = 0x4897d000,
+ .pa_end = 0x4897d3ff,
+ },
+ { }
+};
+
+/* l4_per3 -> vip1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip1 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_vip1_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_vip1_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_vip2_addrs[] = {
+ {
+ .name = "vip_top_level",
+ .pa_start = 0x48990000,
+ .pa_end = 0x489901ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "vip_slice0_parser",
+ .pa_start = 0x48995500,
+ .pa_end = 0x489955ff,
+ },
+ {
+ .name = "vip_slice0_csc",
+ .pa_start = 0x48995700,
+ .pa_end = 0x4899571f,
+ },
+ {
+ .name = "vip_slice0_sc",
+ .pa_start = 0x48995800,
+ .pa_end = 0x4899587f,
+ },
+ {
+ .name = "vip_slice1_parser",
+ .pa_start = 0x48995a00,
+ .pa_end = 0x48995aff,
+ },
+ {
+ .name = "vip_slice1_csc",
+ .pa_start = 0x48995c00,
+ .pa_end = 0x48995c1f,
+ },
+ {
+ .name = "vip_slice1_sc",
+ .pa_start = 0x48995d00,
+ .pa_end = 0x48995d7f,
+ },
+ {
+ .name = "vip_vpdma",
+ .pa_start = 0x4899d000,
+ .pa_end = 0x4899d3ff,
+ },
+ { }
+};
+
+/* l4_per3 -> vip2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip2 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_vip2_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_vip2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_vip3_addrs[] = {
+ {
+ .name = "vip_top_level",
+ .pa_start = 0x489b0000,
+ .pa_end = 0x489b01ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "vip_slice0_parser",
+ .pa_start = 0x489b5500,
+ .pa_end = 0x489b55ff,
+ },
+ {
+ .name = "vip_slice0_csc",
+ .pa_start = 0x489b5700,
+ .pa_end = 0x489b571f,
+ },
+ {
+ .name = "vip_slice0_sc",
+ .pa_start = 0x489b5800,
+ .pa_end = 0x489b587f,
+ },
+ {
+ .name = "vip_slice1_parser",
+ .pa_start = 0x489b5a00,
+ .pa_end = 0x489b5aff,
+ },
+ {
+ .name = "vip_slice1_csc",
+ .pa_start = 0x489b5c00,
+ .pa_end = 0x489b5c1f,
+ },
+ {
+ .name = "vip_slice1_sc",
+ .pa_start = 0x489b5d00,
+ .pa_end = 0x489b5d7f,
+ },
+ {
+ .name = "vip_vpdma",
+ .pa_start = 0x489bd000,
+ .pa_end = 0x489bd3ff,
+ },
+ { }
+};
+
+/* l4_per3 -> vip3 */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__vip3 = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_vip3_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_vip3_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_vpe_addrs[] = {
+ {
+ .name = "vpe0_vayu_register_inst_0",
+ .pa_start = 0x489d0000,
+ .pa_end = 0x489d01ff,
+ .flags = ADDR_TYPE_RT
+ },
+ {
+ .name = "dss_chr_us_register_inst_0",
+ .pa_start = 0x489d0300,
+ .pa_end = 0x489d033f,
+ },
+ {
+ .name = "dss_chr_us_register_inst_1",
+ .pa_start = 0x489d0400,
+ .pa_end = 0x489d043f,
+ },
+ {
+ .name = "dss_chr_us_register_inst_2",
+ .pa_start = 0x489d0500,
+ .pa_end = 0x489d053f,
+ },
+ {
+ .name = "dss_dei_register_inst_0",
+ .pa_start = 0x489d0600,
+ .pa_end = 0x489d063f,
+ },
+ {
+ .name = "dss_sc_m_register_inst_0",
+ .pa_start = 0x489d0700,
+ .pa_end = 0x489d077f,
+ },
+ {
+ .name = "dss_csc_register_inst_0",
+ .pa_start = 0x489d5700,
+ .pa_end = 0x489d571f,
+ },
+ {
+ .name = "hd_dss_centaurus_vpdma_register_inst_0",
+ .pa_start = 0x489dd000,
+ .pa_end = 0x489dd3ff,
+ },
+ { }
+};
+
+/* l4_per3 -> vpe */
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__vpe = {
+ .master = &dra7xx_l4_per3_hwmod,
+ .slave = &dra7xx_vpe_hwmod,
+ .clk = "l3_iclk_div",
+ .addr = dra7xx_vpe_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_addr_space dra7xx_wd_timer2_addrs[] = {
+ {
+ .pa_start = 0x4ae14000,
+ .pa_end = 0x4ae1407f,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+/* l4_wkup -> wd_timer2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
+ .master = &dra7xx_l4_wkup_hwmod,
+ .slave = &dra7xx_wd_timer2_hwmod,
+ .clk = "wkupaon_iclk_mux",
+ .addr = dra7xx_wd_timer2_addrs,
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
+ &dra7xx_l3_main_1__dmm,
+ &dra7xx_dmm__emif_ocp_fw,
+ &dra7xx_l4_cfg__emif_ocp_fw,
+ &dra7xx_l3_main_2__l3_instr,
+ &dra7xx_ocp_wp_noc__l3_instr,
+ &dra7xx_l4_cfg__l3_main_1,
+ &dra7xx_mpu__l3_main_1,
+ &dra7xx_l3_main_1__l3_main_2,
+ &dra7xx_l4_cfg__l3_main_2,
+ &dra7xx_l3_main_1__l4_cfg,
+ &dra7xx_l3_main_1__l4_per1,
+ &dra7xx_l3_main_1__l4_per2,
+ &dra7xx_l3_main_1__l4_per3,
+ &dra7xx_l3_main_1__l4_wkup,
+ &dra7xx_mpu__mpu_private,
+ &dra7xx_l3_main_2__ocp_wp_noc,
+ &dra7xx_l4_cfg__ocp_wp_noc,
+ &dra7xx_l4_per2__atl,
+ &dra7xx_l3_main_1__bb2d,
+ &dra7xx_l4_wkup__counter_32k,
+ &dra7xx_l4_wkup__ctrl_module_wkup,
+ &dra7xx_l4_wkup__dcan1,
+ &dra7xx_l4_per2__dcan2,
+ &dra7xx_l4_cfg__dma_system,
+ &dra7xx_l3_main_1__dss,
+ &dra7xx_l3_main_1__dispc,
+ &dra7xx_l3_main_1__hdmi,
+ &dra7xx_l4_per1__elm,
+ &dra7xx_emif_ocp_fw__emif1,
+ &dra7xx_mpu__emif1,
+ &dra7xx_emif_ocp_fw__emif2,
+ &dra7xx_mpu__emif2,
+ &dra7xx_l4_wkup__gpio1,
+ &dra7xx_l4_per1__gpio2,
+ &dra7xx_l4_per1__gpio3,
+ &dra7xx_l4_per1__gpio4,
+ &dra7xx_l4_per1__gpio5,
+ &dra7xx_l4_per1__gpio6,
+ &dra7xx_l4_per1__gpio7,
+ &dra7xx_l4_per1__gpio8,
+ &dra7xx_l3_main_1__gpmc,
+ &dra7xx_l4_per1__hdq1w,
+ &dra7xx_l4_per1__i2c1,
+ &dra7xx_l4_per1__i2c2,
+ &dra7xx_l4_per1__i2c3,
+ &dra7xx_l4_per1__i2c4,
+ &dra7xx_l4_per1__i2c5,
+ &dra7xx_l4_cfg__mailbox1,
+ &dra7xx_l4_per3__mailbox2,
+ &dra7xx_l4_per3__mailbox3,
+ &dra7xx_l4_per3__mailbox4,
+ &dra7xx_l4_per3__mailbox5,
+ &dra7xx_l4_per3__mailbox6,
+ &dra7xx_l4_per3__mailbox7,
+ &dra7xx_l4_per3__mailbox8,
+ &dra7xx_l4_per3__mailbox9,
+ &dra7xx_l4_per3__mailbox10,
+ &dra7xx_l4_per3__mailbox11,
+ &dra7xx_l4_per3__mailbox12,
+ &dra7xx_l4_per3__mailbox13,
+ &dra7xx_l3_main_1__mcasp1,
+ &dra7xx_l4_per2__mcasp1,
+ &dra7xx_l3_main_1__mcasp2,
+ &dra7xx_l3_main_1__mcasp3,
+ &dra7xx_l4_per2__mcasp4,
+ &dra7xx_l4_per2__mcasp5,
+ &dra7xx_l4_per2__mcasp6,
+ &dra7xx_l4_per2__mcasp7,
+ &dra7xx_l4_per2__mcasp8,
+ &dra7xx_l4_per1__mcspi1,
+ &dra7xx_l4_per1__mcspi2,
+ &dra7xx_l4_per1__mcspi3,
+ &dra7xx_l4_per1__mcspi4,
+ &dra7xx_l4_per1__mmc1,
+ &dra7xx_l4_per1__mmc2,
+ &dra7xx_l4_per1__mmc3,
+ &dra7xx_l4_per1__mmc4,
+ &dra7xx_l4_cfg__mpu,
+ &dra7xx_l4_per3__ocmc_ram1,
+ &dra7xx_l4_per3__ocmc_ram2,
+ &dra7xx_l4_per3__ocmc_ram3,
+ &dra7xx_l3_main_1__ocmc_rom,
+ &dra7xx_l4_cfg__ocp2scp1,
+ &dra7xx_l3_main_1__pruss1,
+ &dra7xx_l3_main_1__pruss2,
+ &dra7xx_l4_per2__pwmss1,
+ &dra7xx_l4_per2__pwmss2,
+ &dra7xx_l4_per2__pwmss3,
+ &dra7xx_l3_main_1__qspi,
+ &dra7xx_l4_per3__rtcss,
+ &dra7xx_l4_cfg__sata,
+ &dra7xx_l4_cfg__smartreflex_core,
+ &dra7xx_l4_cfg__smartreflex_dspeve,
+ &dra7xx_l4_cfg__smartreflex_gpu,
+ &dra7xx_l4_cfg__smartreflex_mpu,
+ &dra7xx_l4_per3__spare_cme,
+ &dra7xx_l4_per3__spare_icm,
+ &dra7xx_l3_main_1__spare_iva2,
+ &dra7xx_l4_wkup__spare_safety1,
+ &dra7xx_l4_wkup__spare_safety2,
+ &dra7xx_l4_wkup__spare_safety3,
+ &dra7xx_l4_wkup__spare_safety4,
+ &dra7xx_l4_wkup__spare_unknown2,
+ &dra7xx_l4_wkup__spare_unknown3,
+ &dra7xx_l4_per2__spare_unknown4,
+ &dra7xx_l4_per2__spare_unknown5,
+ &dra7xx_l4_per2__spare_unknown6,
+ &dra7xx_l4_per3__spare_videopll1,
+ &dra7xx_l4_per3__spare_videopll2,
+ &dra7xx_l4_per3__spare_videopll3,
+ &dra7xx_l4_per3__spare_sata2,
+ &dra7xx_l4_cfg__spare_smartreflex_rtc,
+ &dra7xx_l4_cfg__spare_smartreflex_sdram,
+ &dra7xx_l4_cfg__spare_smartreflex_wkup,
+ &dra7xx_l4_cfg__spinlock,
+ &dra7xx_l4_wkup__timer1,
+ &dra7xx_l4_per1__timer2,
+ &dra7xx_l4_per1__timer3,
+ &dra7xx_l4_per1__timer4,
+ &dra7xx_l4_per3__timer5,
+ &dra7xx_l4_per3__timer6,
+ &dra7xx_l4_per3__timer7,
+ &dra7xx_l4_per3__timer8,
+ &dra7xx_l4_per1__timer9,
+ &dra7xx_l4_per1__timer10,
+ &dra7xx_l4_per1__timer11,
+ &dra7xx_l4_per3__timer13,
+ &dra7xx_l4_per3__timer14,
+ &dra7xx_l4_per3__timer15,
+ &dra7xx_l4_per3__timer16,
+ &dra7xx_l4_per1__uart1,
+ &dra7xx_l4_per1__uart2,
+ &dra7xx_l4_per1__uart3,
+ &dra7xx_l4_per1__uart4,
+ &dra7xx_l4_per1__uart5,
+ &dra7xx_l4_per1__uart6,
+ &dra7xx_l4_per2__uart7,
+ &dra7xx_l4_per2__uart8,
+ &dra7xx_l4_per2__uart9,
+ &dra7xx_l4_wkup__uart10,
+ &dra7xx_l4_per3__usb_otg_ss1,
+ &dra7xx_l4_per3__usb_otg_ss2,
+ &dra7xx_l4_per3__usb_otg_ss3,
+ &dra7xx_l4_per3__usb_otg_ss4,
+ &dra7xx_l3_main_1__vcp1,
+ &dra7xx_l4_per2__vcp1,
+ &dra7xx_l3_main_1__vcp2,
+ &dra7xx_l4_per2__vcp2,
+ &dra7xx_l4_per3__vip1,
+ &dra7xx_l4_per3__vip2,
+ &dra7xx_l4_per3__vip3,
+ &dra7xx_l4_per3__vpe,
+ &dra7xx_l4_wkup__wd_timer2,
+ NULL,
+};
+
+int __init dra7xx_hwmod_init(void)
+{
+ omap_hwmod_init();
+ return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
+}
index 0265ed2802c60ffa02e5f52ea3938790154ec4d6..2389682d3d8a8e576969c5efe7363ca098d37738 100644 (file)
};
static LIST_HEAD(pwrst_list);
+u32 cpu_suspend_state;
+u32 pwrdm_next_state;
#ifdef CONFIG_SUSPEND
static int omap4_pm_suspend(void)
* domain CSWR is not supported by hardware.
* More details can be found in OMAP4430 TRM section 4.3.4.2.
*/
- omap4_mpuss_enter_lowpower(cpu_id, PWRDM_FUNC_PWRST_OFF);
+ omap4_mpuss_enter_lowpower(cpu_id, cpu_suspend_state);
/* Restore next powerdomain state */
list_for_each_entry(pwrst, &pwrst_list, node) {
* XXX This should be replaced by explicit lists of
* powerdomains with specific powerstates to set
*/
- pwrst->next_fpwrst = PWRDM_FUNC_PWRST_CSWR;
+ pwrst->next_fpwrst = pwrdm_next_state;
if (!pwrdm_supports_fpwrst(pwrdm, pwrst->next_fpwrst))
pwrst->next_fpwrst = PWRDM_FUNC_PWRST_ON;
list_add(&pwrst->node, &pwrst_list);
if (cpu_is_omap44xx())
ret = omap4_init_static_deps();
- else if (soc_is_omap54xx())
+ else if (soc_is_omap54xx() || soc_is_dra7xx())
ret = omap5_init_static_deps();
if (ret) {
if (cpu_is_omap44xx() || soc_is_omap54xx())
omap4_idle_init();
+ if (soc_is_dra7xx()) {
+ cpu_suspend_state = PWRDM_FUNC_PWRST_ON;
+ pwrdm_next_state = PWRDM_FUNC_PWRST_ON;
+ } else {
+ cpu_suspend_state = PWRDM_FUNC_PWRST_OFF;
+ pwrdm_next_state = PWRDM_FUNC_PWRST_CSWR;
+ }
+
err2:
return ret;
}
index 72d6ce042edc2a02da2af948f90328439403fb23..6aa4d572d1461ad9507bebb7c89e81ec6d934f62 100644 (file)
if (_pwrdm_lookup(pwrdm->name))
return -EEXIST;
+ if (arch_pwrdm && arch_pwrdm->pwrdm_has_voltdm)
+ if (!arch_pwrdm->pwrdm_has_voltdm())
+ goto skip_voltdm;
+
voltdm = voltdm_lookup(pwrdm->voltdm.name);
if (!voltdm) {
pr_err("powerdomain: %s: voltagedomain %s does not exist\n",
pwrdm->voltdm.ptr = voltdm;
INIT_LIST_HEAD(&pwrdm->voltdm_node);
voltdm_add_pwrdm(voltdm, pwrdm);
- spin_lock_init(&pwrdm->_lock);
+skip_voltdm:
+ spin_lock_init(&pwrdm->_lock);
list_add(&pwrdm->node, &pwrdm_list);
/* Initialize the powerdomain's state counter */
index b8f3dbf564c13d0c00e3a1d689cb681702973875..55c1201c1943e045e9448b0d41c0943f434e272e 100644 (file)
* @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
* @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
* @pwrdm_wait_transition: Wait for a pd state transition to complete
+ * @pwrdm_has_voltdm; Check if a voltdm association is needed
*/
struct pwrdm_ops {
int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
+ int (*pwrdm_has_voltdm)(void);
};
int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
extern void am33xx_powerdomains_init(void);
extern void omap44xx_powerdomains_init(void);
extern void omap54xx_powerdomains_init(void);
+extern void dra7xx_powerdomains_init(void);
extern struct pwrdm_ops omap2_pwrdm_operations;
extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
--- /dev/null
@@ -0,0 +1,477 @@
+/*
+ * DRA7xx Power domains framework
+ *
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Nokia Corporation
+ *
+ * Abhijit Pagare (abhijitpagare@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+
+#include "prcm-common.h"
+#include "prcm44xx.h"
+#include "prm-regbits-7xx.h"
+#include "prm7xx.h"
+#include "prcm_mpu7xx.h"
+
+/* iva_7xx_pwrdm: IVA-HD power domain */
+static struct powerdomain iva_7xx_pwrdm = {
+ .name = "iva_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_IVA_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 4,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* hwa_mem */
+ [1] = PWRSTS_OFF_RET, /* sl2_mem */
+ [2] = PWRSTS_OFF_RET, /* tcm1_mem */
+ [3] = PWRSTS_OFF_RET, /* tcm2_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* hwa_mem */
+ [1] = PWRSTS_OFF_RET, /* sl2_mem */
+ [2] = PWRSTS_OFF_RET, /* tcm1_mem */
+ [3] = PWRSTS_OFF_RET, /* tcm2_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* rtc_7xx_pwrdm: */
+static struct powerdomain rtc_7xx_pwrdm = {
+ .name = "rtc_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_RTC_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+};
+
+/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
+static struct powerdomain custefuse_7xx_pwrdm = {
+ .name = "custefuse_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* ipu_7xx_pwrdm: Audio back end power domain */
+static struct powerdomain ipu_7xx_pwrdm = {
+ .name = "ipu_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_IPU_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* aessmem */
+ [1] = PWRSTS_OFF_RET, /* periphmem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* aessmem */
+ [1] = PWRSTS_OFF_RET, /* periphmem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dss_7xx_pwrdm: Display subsystem power domain */
+static struct powerdomain dss_7xx_pwrdm = {
+ .name = "dss_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_DSS_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* dss_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* dss_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* l4per_7xx_pwrdm: Target peripherals power domain */
+static struct powerdomain l4per_7xx_pwrdm = {
+ .name = "l4per_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_L4PER_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* nonretained_bank */
+ [1] = PWRSTS_OFF_RET, /* retained_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* nonretained_bank */
+ [1] = PWRSTS_OFF_RET, /* retained_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* gpu_7xx_pwrdm: 3D accelerator power domain */
+static struct powerdomain gpu_7xx_pwrdm = {
+ .name = "gpu_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_GPU_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* gpu_mem */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* gpu_mem */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* wkupaon_7xx_pwrdm: Wake-up power domain */
+static struct powerdomain wkupaon_7xx_pwrdm = {
+ .name = "wkupaon_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* wkup_bank */
+ },
+};
+
+/* core_7xx_pwrdm: CORE power domain */
+static struct powerdomain core_7xx_pwrdm = {
+ .name = "core_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_CORE_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 5,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [2] = PWRSTS_OFF_RET, /* core_other_bank */
+ [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
+ [4] = PWRSTS_OFF_RET, /* ipu_unicache */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* core_nret_bank */
+ [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [2] = PWRSTS_OFF_RET, /* core_other_bank */
+ [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
+ [4] = PWRSTS_OFF_RET, /* ipu_unicache */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
+static struct powerdomain coreaon_7xx_pwrdm = {
+ .name = "coreaon_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_COREAON_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_ON,
+};
+
+/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
+static struct powerdomain cpu0_7xx_pwrdm = {
+ .name = "cpu0_pwrdm",
+ .voltdm = { .name = "mpu" },
+ .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
+ .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* cpu0_l1 */
+ },
+};
+
+/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
+static struct powerdomain cpu1_7xx_pwrdm = {
+ .name = "cpu1_pwrdm",
+ .voltdm = { .name = "mpu" },
+ .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
+ .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_ON, /* cpu1_l1 */
+ },
+};
+
+/* vpe_7xx_pwrdm: */
+static struct powerdomain vpe_7xx_pwrdm = {
+ .name = "vpe_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_VPE_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* vpe_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* vpe_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
+static struct powerdomain mpu_7xx_pwrdm = {
+ .name = "mpu_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_MPU_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 2,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* mpu_l2 */
+ [1] = PWRSTS_RET, /* mpu_ram */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* mpu_l2 */
+ [1] = PWRSTS_OFF_RET, /* mpu_ram */
+ },
+};
+
+/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
+static struct powerdomain l3init_7xx_pwrdm = {
+ .name = "l3init_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_L3INIT_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_RET_ON,
+ .pwrsts_logic_ret = PWRSTS_OFF_RET,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* gmac_bank */
+ [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
+ [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* gmac_bank */
+ [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
+ [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve3_7xx_pwrdm: */
+static struct powerdomain eve3_7xx_pwrdm = {
+ .name = "eve3_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EVE3_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* eve3_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* eve3_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* emu_7xx_pwrdm: Emulation power domain */
+static struct powerdomain emu_7xx_pwrdm = {
+ .name = "emu_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EMU_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* emu_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* emu_bank */
+ },
+};
+
+/* dsp2_7xx_pwrdm: */
+static struct powerdomain dsp2_7xx_pwrdm = {
+ .name = "dsp2_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_DSP2_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* dsp2_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* dsp2_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* dsp1_7xx_pwrdm: Tesla processor power domain */
+static struct powerdomain dsp1_7xx_pwrdm = {
+ .name = "dsp1_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_DSP1_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 3,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* dsp1_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* dsp1_edma */
+ [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
+ [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* cam_7xx_pwrdm: Camera subsystem power domain */
+static struct powerdomain cam_7xx_pwrdm = {
+ .name = "cam_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_CAM_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* vip_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* vip_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve4_7xx_pwrdm: */
+static struct powerdomain eve4_7xx_pwrdm = {
+ .name = "eve4_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EVE4_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* eve4_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* eve4_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve2_7xx_pwrdm: */
+static struct powerdomain eve2_7xx_pwrdm = {
+ .name = "eve2_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EVE2_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* eve2_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* eve2_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/* eve1_7xx_pwrdm: */
+static struct powerdomain eve1_7xx_pwrdm = {
+ .name = "eve1_pwrdm",
+ .voltdm = { .name = "avatar" },
+ .prcm_offs = DRA7XX_PRM_EVE1_INST,
+ .prcm_partition = DRA7XX_PRM_PARTITION,
+ .pwrsts = PWRSTS_OFF_ON,
+ .banks = 1,
+ .pwrsts_mem_ret = {
+ [0] = PWRSTS_OFF_RET, /* eve1_bank */
+ },
+ .pwrsts_mem_on = {
+ [0] = PWRSTS_OFF_RET, /* eve1_bank */
+ },
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+};
+
+/*
+ * The following power domains are not under SW control
+ *
+ * mpuaon
+ * mmaon
+ */
+
+/* As powerdomains are added or removed above, this list must also be changed */
+static struct powerdomain *powerdomains_dra7xx[] __initdata = {
+ &iva_7xx_pwrdm,
+ &rtc_7xx_pwrdm,
+ &custefuse_7xx_pwrdm,
+ &ipu_7xx_pwrdm,
+ &dss_7xx_pwrdm,
+ &l4per_7xx_pwrdm,
+ &gpu_7xx_pwrdm,
+ &wkupaon_7xx_pwrdm,
+ &core_7xx_pwrdm,
+ &coreaon_7xx_pwrdm,
+ &cpu0_7xx_pwrdm,
+ &cpu1_7xx_pwrdm,
+ &vpe_7xx_pwrdm,
+ &mpu_7xx_pwrdm,
+ &l3init_7xx_pwrdm,
+ &eve3_7xx_pwrdm,
+ &emu_7xx_pwrdm,
+ &dsp2_7xx_pwrdm,
+ &dsp1_7xx_pwrdm,
+ &cam_7xx_pwrdm,
+ &eve4_7xx_pwrdm,
+ &eve2_7xx_pwrdm,
+ &eve1_7xx_pwrdm,
+ NULL
+};
+
+void __init dra7xx_powerdomains_init(void)
+{
+ pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
+ pwrdm_register_pwrdms(powerdomains_dra7xx);
+ pwrdm_complete_init();
+}
index f429cdd5a118aa5ca3ea647b1ee3307b18c3bf20..4fea2cfdf2c3a8c08794baa169509c24ca158ba2 100644 (file)
#define OMAP54XX_SCRM_PARTITION 4
#define OMAP54XX_PRCM_MPU_PARTITION 5
+#define DRA7XX_PRM_PARTITION 1
+#define DRA7XX_CM_CORE_AON_PARTITION 2
+#define DRA7XX_CM_CORE_PARTITION 3
+#define DRA7XX_MPU_PRCM_PARTITION 5
+
/*
* OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
* IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h
--- /dev/null
@@ -0,0 +1,83 @@
+/*
+ * DRA7xx PRCM MPU instance offset macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
+
+#define DRA7XX_PRCM_MPU_BASE 0x48243000
+
+#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
+ OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
+
+/* MPU_PRCM instances */
+#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
+#define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
+#define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
+#define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
+#define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
+#define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
+
+/* PRCM_MPU clockdomain register offsets (from instance start) */
+#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
+#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
+
+
+/* MPU_PRCM */
+
+/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
+#define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
+
+/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
+#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
+#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
+
+/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
+#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
+
+/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
+#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
+
+/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
+#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
+
+/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
+#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
+
+/* Function prototypes */
+# ifndef __ASSEMBLER__
+extern u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst,
+ s16 idx);
+# endif
+
+#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-7xx.h b/arch/arm/mach-omap2/prm-regbits-7xx.h
--- /dev/null
@@ -0,0 +1,6763 @@
+/*
+ * DRA7xx Power Management register bits
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_7XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_7XX_H
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ABBOFF_ACT_SHIFT 1
+#define DRA7XX_ABBOFF_ACT_WIDTH 0x1
+#define DRA7XX_ABBOFF_ACT_MASK (1 << 1)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ABBOFF_SLEEP_SHIFT 2
+#define DRA7XX_ABBOFF_SLEEP_WIDTH 0x1
+#define DRA7XX_ABBOFF_SLEEP_MASK (1 << 2)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_ABB_DSPEVE_DONE_EN_SHIFT 29
+#define DRA7XX_ABB_DSPEVE_DONE_EN_WIDTH 0x1
+#define DRA7XX_ABB_DSPEVE_DONE_EN_MASK (1 << 29)
+
+/* Renamed from ABB_DSPEVE_DONE_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_ABB_DSPEVE_DONE_EN_30_30_SHIFT 30
+#define DRA7XX_ABB_DSPEVE_DONE_EN_30_30_WIDTH 0x1
+#define DRA7XX_ABB_DSPEVE_DONE_EN_30_30_MASK (1 << 30)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_ABB_DSPEVE_DONE_ST_SHIFT 29
+#define DRA7XX_ABB_DSPEVE_DONE_ST_WIDTH 0x1
+#define DRA7XX_ABB_DSPEVE_DONE_ST_MASK (1 << 29)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_ABB_GPU_DONE_EN_SHIFT 28
+#define DRA7XX_ABB_GPU_DONE_EN_WIDTH 0x1
+#define DRA7XX_ABB_GPU_DONE_EN_MASK (1 << 28)
+
+/* Renamed from ABB_GPU_DONE_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_ABB_GPU_DONE_EN_PRM_IRQENABLE_MPU_SHIFT 29
+#define DRA7XX_ABB_GPU_DONE_EN_PRM_IRQENABLE_MPU_WIDTH 0x1
+#define DRA7XX_ABB_GPU_DONE_EN_PRM_IRQENABLE_MPU_MASK (1 << 29)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_ABB_GPU_DONE_ST_SHIFT 28
+#define DRA7XX_ABB_GPU_DONE_ST_WIDTH 0x1
+#define DRA7XX_ABB_GPU_DONE_ST_MASK (1 << 28)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_ABB_IVA_DONE_EN_SHIFT 30
+#define DRA7XX_ABB_IVA_DONE_EN_WIDTH 0x1
+#define DRA7XX_ABB_IVA_DONE_EN_MASK (1 << 30)
+
+/* Renamed from ABB_IVA_DONE_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_ABB_IVA_DONE_EN_PRM_IRQENABLE_MPU_SHIFT 31
+#define DRA7XX_ABB_IVA_DONE_EN_PRM_IRQENABLE_MPU_WIDTH 0x1
+#define DRA7XX_ABB_IVA_DONE_EN_PRM_IRQENABLE_MPU_MASK (1 << 31)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_ABB_IVA_DONE_ST_SHIFT 30
+#define DRA7XX_ABB_IVA_DONE_ST_WIDTH 0x1
+#define DRA7XX_ABB_IVA_DONE_ST_MASK (1 << 30)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_ABB_MPU_DONE_EN_SHIFT 31
+#define DRA7XX_ABB_MPU_DONE_EN_WIDTH 0x1
+#define DRA7XX_ABB_MPU_DONE_EN_MASK (1 << 31)
+
+/* Renamed from ABB_MPU_DONE_EN Used by PRM_IRQENABLE_MPU_2 */
+#define DRA7XX_ABB_MPU_DONE_EN_7_7_SHIFT 7
+#define DRA7XX_ABB_MPU_DONE_EN_7_7_WIDTH 0x1
+#define DRA7XX_ABB_MPU_DONE_EN_7_7_MASK (1 << 7)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2
+ */
+#define DRA7XX_ABB_MPU_DONE_ST_SHIFT 31
+#define DRA7XX_ABB_MPU_DONE_ST_WIDTH 0x1
+#define DRA7XX_ABB_MPU_DONE_ST_MASK (1 << 31)
+
+/* Renamed from ABB_MPU_DONE_ST Used by PRM_IRQSTATUS_MPU_2 */
+#define DRA7XX_ABB_MPU_DONE_ST_7_7_SHIFT 7
+#define DRA7XX_ABB_MPU_DONE_ST_7_7_WIDTH 0x1
+#define DRA7XX_ABB_MPU_DONE_ST_7_7_MASK (1 << 7)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
+ * PRM_ABBLDO_MPU_SETUP
+ */
+#define DRA7XX_ACTIVE_FBB_SEL_SHIFT 2
+#define DRA7XX_ACTIVE_FBB_SEL_WIDTH 0x1
+#define DRA7XX_ACTIVE_FBB_SEL_MASK (1 << 2)
+
+/* Used by PM_IPU_PWRSTCTRL */
+#define DRA7XX_AESSMEM_ONSTATE_SHIFT 16
+#define DRA7XX_AESSMEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_AESSMEM_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_IPU_PWRSTCTRL */
+#define DRA7XX_AESSMEM_RETSTATE_SHIFT 8
+#define DRA7XX_AESSMEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_AESSMEM_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_IPU_PWRSTST */
+#define DRA7XX_AESSMEM_STATEST_SHIFT 4
+#define DRA7XX_AESSMEM_STATEST_WIDTH 0x2
+#define DRA7XX_AESSMEM_STATEST_MASK (0x3 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_AIPOFF_SHIFT 8
+#define DRA7XX_AIPOFF_WIDTH 0x1
+#define DRA7XX_AIPOFF_MASK (1 << 8)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0
+#define DRA7XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2
+#define DRA7XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_AUTO_CTRL_VDD_MM_L_SHIFT 4
+#define DRA7XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2
+#define DRA7XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2
+#define DRA7XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2
+#define DRA7XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_C2C_RST_SHIFT 10
+#define DRA7XX_C2C_RST_WIDTH 0x1
+#define DRA7XX_C2C_RST_MASK (1 << 10)
+
+/* Used by PRM_CLKREQCTRL */
+#define DRA7XX_CLKREQ_COND_SHIFT 0
+#define DRA7XX_CLKREQ_COND_WIDTH 0x3
+#define DRA7XX_CLKREQ_COND_MASK (0x7 << 0)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_CORE_OCMRAM_ONSTATE_SHIFT 18
+#define DRA7XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2
+#define DRA7XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_CORE_OCMRAM_RETSTATE_SHIFT 9
+#define DRA7XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1
+#define DRA7XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_CORE_OCMRAM_STATEST_SHIFT 6
+#define DRA7XX_CORE_OCMRAM_STATEST_WIDTH 0x2
+#define DRA7XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8
+#define DRA7XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_CORE_OTHER_BANK_STATEST_SHIFT 4
+#define DRA7XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_CUSTOM_SHIFT 6
+#define DRA7XX_CUSTOM_WIDTH 0x2
+#define DRA7XX_CUSTOM_MASK (0x3 << 6)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define DRA7XX_DEVICE_OFF_ENABLE_SHIFT 0
+#define DRA7XX_DEVICE_OFF_ENABLE_WIDTH 0x1
+#define DRA7XX_DEVICE_OFF_ENABLE_MASK (1 << 0)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_ABE_RECAL_EN_SHIFT 4
+#define DRA7XX_DPLL_ABE_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_ABE_RECAL_EN_MASK (1 << 4)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_ABE_RECAL_ST_SHIFT 4
+#define DRA7XX_DPLL_ABE_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_ABE_RECAL_ST_MASK (1 << 4)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_CORE_RECAL_EN_SHIFT 0
+#define DRA7XX_DPLL_CORE_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_CORE_RECAL_EN_MASK (1 << 0)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_CORE_RECAL_ST_SHIFT 0
+#define DRA7XX_DPLL_CORE_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_CORE_RECAL_ST_MASK (1 << 0)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_DDR_RECAL_EN_SHIFT 7
+#define DRA7XX_DPLL_DDR_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_DDR_RECAL_EN_MASK (1 << 7)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_DDR_RECAL_ST_SHIFT 7
+#define DRA7XX_DPLL_DDR_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_DDR_RECAL_ST_MASK (1 << 7)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_DPLL_DSP_RECAL_EN_SHIFT 11
+#define DRA7XX_DPLL_DSP_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_DSP_RECAL_EN_MASK (1 << 11)
+
+/* Renamed from DPLL_DSP_RECAL_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_DPLL_DSP_RECAL_EN_PRM_IRQENABLE_MPU_SHIFT 10
+#define DRA7XX_DPLL_DSP_RECAL_EN_PRM_IRQENABLE_MPU_WIDTH 0x1
+#define DRA7XX_DPLL_DSP_RECAL_EN_PRM_IRQENABLE_MPU_MASK (1 << 10)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_DSP_RECAL_ST_SHIFT 11
+#define DRA7XX_DPLL_DSP_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_DSP_RECAL_ST_MASK (1 << 11)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_DPLL_EVE_RECAL_EN_SHIFT 12
+#define DRA7XX_DPLL_EVE_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_EVE_RECAL_EN_MASK (1 << 12)
+
+/* Renamed from DPLL_EVE_RECAL_EN Used by PRM_IRQENABLE_MPU */
+#define DRA7XX_DPLL_EVE_RECAL_EN_PRM_IRQENABLE_MPU_SHIFT 11
+#define DRA7XX_DPLL_EVE_RECAL_EN_PRM_IRQENABLE_MPU_WIDTH 0x1
+#define DRA7XX_DPLL_EVE_RECAL_EN_PRM_IRQENABLE_MPU_MASK (1 << 11)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_EVE_RECAL_ST_SHIFT 12
+#define DRA7XX_DPLL_EVE_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_EVE_RECAL_ST_MASK (1 << 12)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_GMAC_RECAL_EN_SHIFT 5
+#define DRA7XX_DPLL_GMAC_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_GMAC_RECAL_EN_MASK (1 << 5)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_GMAC_RECAL_ST_SHIFT 5
+#define DRA7XX_DPLL_GMAC_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_GMAC_RECAL_ST_MASK (1 << 5)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_GPU_RECAL_EN_SHIFT 6
+#define DRA7XX_DPLL_GPU_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_GPU_RECAL_EN_MASK (1 << 6)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_GPU_RECAL_ST_SHIFT 6
+#define DRA7XX_DPLL_GPU_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_GPU_RECAL_ST_MASK (1 << 6)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_IVA_RECAL_EN_SHIFT 2
+#define DRA7XX_DPLL_IVA_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_IVA_RECAL_EN_MASK (1 << 2)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_IVA_RECAL_ST_SHIFT 2
+#define DRA7XX_DPLL_IVA_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_IVA_RECAL_ST_MASK (1 << 2)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_MPU_RECAL_EN_SHIFT 1
+#define DRA7XX_DPLL_MPU_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_MPU_RECAL_EN_MASK (1 << 1)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_MPU_RECAL_ST_SHIFT 1
+#define DRA7XX_DPLL_MPU_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_MPU_RECAL_ST_MASK (1 << 1)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_DPLL_PER_RECAL_EN_SHIFT 3
+#define DRA7XX_DPLL_PER_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_PER_RECAL_EN_MASK (1 << 3)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_DPLL_PER_RECAL_ST_SHIFT 3
+#define DRA7XX_DPLL_PER_RECAL_ST_WIDTH 0x1
+#define DRA7XX_DPLL_PER_RECAL_ST_MASK (1 << 3)
+
+/* Used by PRM_IRQENABLE_DSP1 */
+#define DRA7XX_DPLL_USB_RECAL_EN_SHIFT 13
+#define DRA7XX_DPLL_USB_RECAL_EN_WIDTH 0x1
+#define DRA7XX_DPLL_USB_RECAL_EN_MASK (1 << 13)
+
+/* Used by PM_DSP1_PWRSTCTRL */
+#define DRA7XX_DSP1_EDMA_ONSTATE_SHIFT 20
+#define DRA7XX_DSP1_EDMA_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP1_EDMA_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_DSP1_PWRSTST */
+#define DRA7XX_DSP1_EDMA_STATEST_SHIFT 8
+#define DRA7XX_DSP1_EDMA_STATEST_WIDTH 0x2
+#define DRA7XX_DSP1_EDMA_STATEST_MASK (0x3 << 8)
+
+/* Used by PM_DSP1_PWRSTCTRL */
+#define DRA7XX_DSP1_L1_ONSTATE_SHIFT 16
+#define DRA7XX_DSP1_L1_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP1_L1_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_DSP1_PWRSTST */
+#define DRA7XX_DSP1_L1_STATEST_SHIFT 4
+#define DRA7XX_DSP1_L1_STATEST_WIDTH 0x2
+#define DRA7XX_DSP1_L1_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_DSP1_PWRSTCTRL */
+#define DRA7XX_DSP1_L2_ONSTATE_SHIFT 18
+#define DRA7XX_DSP1_L2_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP1_L2_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_DSP1_PWRSTST */
+#define DRA7XX_DSP1_L2_STATEST_SHIFT 6
+#define DRA7XX_DSP1_L2_STATEST_WIDTH 0x2
+#define DRA7XX_DSP1_L2_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_DSP2_PWRSTCTRL */
+#define DRA7XX_DSP2_EDMA_ONSTATE_SHIFT 20
+#define DRA7XX_DSP2_EDMA_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP2_EDMA_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_DSP2_PWRSTST */
+#define DRA7XX_DSP2_EDMA_STATEST_SHIFT 8
+#define DRA7XX_DSP2_EDMA_STATEST_WIDTH 0x2
+#define DRA7XX_DSP2_EDMA_STATEST_MASK (0x3 << 8)
+
+/* Used by PM_DSP2_PWRSTCTRL */
+#define DRA7XX_DSP2_L1_ONSTATE_SHIFT 16
+#define DRA7XX_DSP2_L1_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP2_L1_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_DSP2_PWRSTST */
+#define DRA7XX_DSP2_L1_STATEST_SHIFT 4
+#define DRA7XX_DSP2_L1_STATEST_WIDTH 0x2
+#define DRA7XX_DSP2_L1_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_DSP2_PWRSTCTRL */
+#define DRA7XX_DSP2_L2_ONSTATE_SHIFT 18
+#define DRA7XX_DSP2_L2_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSP2_L2_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_DSP2_PWRSTST */
+#define DRA7XX_DSP2_L2_STATEST_SHIFT 6
+#define DRA7XX_DSP2_L2_STATEST_WIDTH 0x2
+#define DRA7XX_DSP2_L2_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define DRA7XX_DSS_MEM_ONSTATE_SHIFT 16
+#define DRA7XX_DSS_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_DSS_MEM_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_DSS_PWRSTCTRL */
+#define DRA7XX_DSS_MEM_RETSTATE_SHIFT 8
+#define DRA7XX_DSS_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_DSS_MEM_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_DSS_PWRSTST */
+#define DRA7XX_DSS_MEM_STATEST_SHIFT 4
+#define DRA7XX_DSS_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_DSS_MEM_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define DRA7XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8
+#define DRA7XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1
+#define DRA7XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define DRA7XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9
+#define DRA7XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1
+#define DRA7XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
+
+/* Used by PM_EMU_PWRSTCTRL */
+#define DRA7XX_EMU_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EMU_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EMU_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EMU_PWRSTST */
+#define DRA7XX_EMU_BANK_STATEST_SHIFT 4
+#define DRA7XX_EMU_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EMU_BANK_STATEST_MASK (0x3 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP, PRM_SRAM_WKUP_SETUP
+ */
+#define DRA7XX_ENABLE_RTA_SHIFT 0
+#define DRA7XX_ENABLE_RTA_WIDTH 0x1
+#define DRA7XX_ENABLE_RTA_MASK (1 << 0)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC1_SHIFT 3
+#define DRA7XX_ENFUNC1_WIDTH 0x1
+#define DRA7XX_ENFUNC1_MASK (1 << 3)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC2_SHIFT 4
+#define DRA7XX_ENFUNC2_WIDTH 0x1
+#define DRA7XX_ENFUNC2_MASK (1 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC3_SHIFT 5
+#define DRA7XX_ENFUNC3_WIDTH 0x1
+#define DRA7XX_ENFUNC3_MASK (1 << 5)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC4_SHIFT 6
+#define DRA7XX_ENFUNC4_WIDTH 0x1
+#define DRA7XX_ENFUNC4_MASK (1 << 6)
+
+/*
+ * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_DSPEVE_SETUP, PRM_SLDO_GPU_SETUP,
+ * PRM_SLDO_IVA_SETUP, PRM_SLDO_MPU_SETUP
+ */
+#define DRA7XX_ENFUNC5_SHIFT 7
+#define DRA7XX_ENFUNC5_WIDTH 0x1
+#define DRA7XX_ENFUNC5_MASK (1 << 7)
+
+/* Used by PM_EVE1_PWRSTCTRL */
+#define DRA7XX_EVE1_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EVE1_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EVE1_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EVE1_PWRSTST */
+#define DRA7XX_EVE1_BANK_STATEST_SHIFT 4
+#define DRA7XX_EVE1_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EVE1_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_EVE2_PWRSTCTRL */
+#define DRA7XX_EVE2_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EVE2_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EVE2_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EVE2_PWRSTST */
+#define DRA7XX_EVE2_BANK_STATEST_SHIFT 4
+#define DRA7XX_EVE2_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EVE2_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_EVE3_PWRSTCTRL */
+#define DRA7XX_EVE3_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EVE3_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EVE3_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EVE3_PWRSTST */
+#define DRA7XX_EVE3_BANK_STATEST_SHIFT 4
+#define DRA7XX_EVE3_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EVE3_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_EVE4_PWRSTCTRL */
+#define DRA7XX_EVE4_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_EVE4_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_EVE4_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_EVE4_PWRSTST */
+#define DRA7XX_EVE4_BANK_STATEST_SHIFT 4
+#define DRA7XX_EVE4_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_EVE4_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_EXTERNAL_WARM_RST_SHIFT 5
+#define DRA7XX_EXTERNAL_WARM_RST_WIDTH 0x1
+#define DRA7XX_EXTERNAL_WARM_RST_MASK (1 << 5)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2
+ */
+#define DRA7XX_FORCEWKUP_EN_SHIFT 10
+#define DRA7XX_FORCEWKUP_EN_WIDTH 0x1
+#define DRA7XX_FORCEWKUP_EN_MASK (1 << 10)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2
+ */
+#define DRA7XX_FORCEWKUP_ST_SHIFT 10
+#define DRA7XX_FORCEWKUP_ST_WIDTH 0x1
+#define DRA7XX_FORCEWKUP_ST_MASK (1 << 10)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_FUNC_SHIFT 16
+#define DRA7XX_FUNC_WIDTH 0xc
+#define DRA7XX_FUNC_MASK (0xfff << 16)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_GLOBAL_COLD_RST_SHIFT 0
+#define DRA7XX_GLOBAL_COLD_RST_WIDTH 0x1
+#define DRA7XX_GLOBAL_COLD_RST_MASK (1 << 0)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_GLOBAL_WARM_SW_RST_SHIFT 1
+#define DRA7XX_GLOBAL_WARM_SW_RST_WIDTH 0x1
+#define DRA7XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_GLOBAL_WUEN_SHIFT 16
+#define DRA7XX_GLOBAL_WUEN_WIDTH 0x1
+#define DRA7XX_GLOBAL_WUEN_MASK (1 << 16)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_GMAC_BANK_ONSTATE_SHIFT 18
+#define DRA7XX_GMAC_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_GMAC_BANK_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_GMAC_BANK_RETSTATE_SHIFT 10
+#define DRA7XX_GMAC_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_GMAC_BANK_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_GPU_PWRSTCTRL */
+#define DRA7XX_GPU_MEM_ONSTATE_SHIFT 16
+#define DRA7XX_GPU_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_GPU_MEM_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_GPU_PWRSTST */
+#define DRA7XX_GPU_MEM_STATEST_SHIFT 4
+#define DRA7XX_GPU_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_GPU_MEM_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_PSCON_COUNT */
+#define DRA7XX_HG_PONOUT_2_PGOODIN_TIME_SHIFT 16
+#define DRA7XX_HG_PONOUT_2_PGOODIN_TIME_WIDTH 0x8
+#define DRA7XX_HG_PONOUT_2_PGOODIN_TIME_MASK (0xff << 16)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_HWA_MEM_ONSTATE_SHIFT 16
+#define DRA7XX_HWA_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_HWA_MEM_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_HWA_MEM_RETSTATE_SHIFT 8
+#define DRA7XX_HWA_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_HWA_MEM_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_IVA_PWRSTST */
+#define DRA7XX_HWA_MEM_STATEST_SHIFT 4
+#define DRA7XX_HWA_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_HWA_MEM_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_ICEPICK_RST_SHIFT 9
+#define DRA7XX_ICEPICK_RST_WIDTH 0x1
+#define DRA7XX_ICEPICK_RST_MASK (1 << 9)
+
+/*
+ * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
+ * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST, PRM_VOLTST_MM,
+ * PRM_VOLTST_MPU
+ */
+#define DRA7XX_INTRANSITION_SHIFT 20
+#define DRA7XX_INTRANSITION_WIDTH 0x1
+#define DRA7XX_INTRANSITION_MASK (1 << 20)
+
+/*
+ * Used by PRM_IRQENABLE_DSP1, PRM_IRQENABLE_DSP2, PRM_IRQENABLE_EVE1,
+ * PRM_IRQENABLE_EVE2, PRM_IRQENABLE_EVE3, PRM_IRQENABLE_EVE4,
+ * PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU
+ */
+#define DRA7XX_IO_EN_SHIFT 9
+#define DRA7XX_IO_EN_WIDTH 0x1
+#define DRA7XX_IO_EN_MASK (1 << 9)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_IO_ON_STATUS_SHIFT 5
+#define DRA7XX_IO_ON_STATUS_WIDTH 0x1
+#define DRA7XX_IO_ON_STATUS_MASK (1 << 5)
+
+/*
+ * Used by PRM_IRQSTATUS_DSP1, PRM_IRQSTATUS_DSP2, PRM_IRQSTATUS_EVE1,
+ * PRM_IRQSTATUS_EVE2, PRM_IRQSTATUS_EVE3, PRM_IRQSTATUS_EVE4,
+ * PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU
+ */
+#define DRA7XX_IO_ST_SHIFT 9
+#define DRA7XX_IO_ST_WIDTH 0x1
+#define DRA7XX_IO_ST_MASK (1 << 9)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_IPU_L2RAM_ONSTATE_SHIFT 20
+#define DRA7XX_IPU_L2RAM_ONSTATE_WIDTH 0x2
+#define DRA7XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_IPU_L2RAM_RETSTATE_SHIFT 10
+#define DRA7XX_IPU_L2RAM_RETSTATE_WIDTH 0x1
+#define DRA7XX_IPU_L2RAM_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_IPU_L2RAM_STATEST_SHIFT 8
+#define DRA7XX_IPU_L2RAM_STATEST_WIDTH 0x2
+#define DRA7XX_IPU_L2RAM_STATEST_MASK (0x3 << 8)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_IPU_UNICACHE_ONSTATE_SHIFT 22
+#define DRA7XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2
+#define DRA7XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_IPU_UNICACHE_RETSTATE_SHIFT 11
+#define DRA7XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1
+#define DRA7XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_IPU_UNICACHE_STATEST_SHIFT 10
+#define DRA7XX_IPU_UNICACHE_STATEST_WIDTH 0x2
+#define DRA7XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_ISOCLK_OVERRIDE_SHIFT 0
+#define DRA7XX_ISOCLK_OVERRIDE_WIDTH 0x1
+#define DRA7XX_ISOCLK_OVERRIDE_MASK (1 << 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_ISOCLK_STATUS_SHIFT 1
+#define DRA7XX_ISOCLK_STATUS_WIDTH 0x1
+#define DRA7XX_ISOCLK_STATUS_MASK (1 << 1)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_ISOOVR_EXTEND_SHIFT 4
+#define DRA7XX_ISOOVR_EXTEND_WIDTH 0x1
+#define DRA7XX_ISOOVR_EXTEND_MASK (1 << 4)
+
+/* Used by PRM_IO_COUNT */
+#define DRA7XX_ISO_2_ON_TIME_SHIFT 0
+#define DRA7XX_ISO_2_ON_TIME_WIDTH 0x8
+#define DRA7XX_ISO_2_ON_TIME_MASK (0xff << 0)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_L3INIT_BANK1_ONSTATE_SHIFT 14
+#define DRA7XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2
+#define DRA7XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 14)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_L3INIT_BANK1_RETSTATE_SHIFT 8
+#define DRA7XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1
+#define DRA7XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define DRA7XX_L3INIT_BANK1_STATEST_SHIFT 4
+#define DRA7XX_L3INIT_BANK1_STATEST_WIDTH 0x2
+#define DRA7XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_L3INIT_BANK2_ONSTATE_SHIFT 16
+#define DRA7XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2
+#define DRA7XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_L3INIT_PWRSTCTRL */
+#define DRA7XX_L3INIT_BANK2_RETSTATE_SHIFT 9
+#define DRA7XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1
+#define DRA7XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define DRA7XX_L3INIT_BANK2_STATEST_SHIFT 6
+#define DRA7XX_L3INIT_BANK2_STATEST_WIDTH 0x2
+#define DRA7XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_L3INIT_PWRSTST */
+#define DRA7XX_L3INIT_GMAC_STATEST_SHIFT 8
+#define DRA7XX_L3INIT_GMAC_STATEST_WIDTH 0x2
+#define DRA7XX_L3INIT_GMAC_STATEST_MASK (0x3 << 8)
+
+/*
+ * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
+ * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST
+ */
+#define DRA7XX_LASTPOWERSTATEENTERED_SHIFT 24
+#define DRA7XX_LASTPOWERSTATEENTERED_WIDTH 0x2
+#define DRA7XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_LLI_RST_SHIFT 14
+#define DRA7XX_LLI_RST_WIDTH 0x1
+#define DRA7XX_LLI_RST_MASK (1 << 14)
+
+/*
+ * Used by PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_IPU_PWRSTCTRL,
+ * PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL,
+ * PM_VPE_PWRSTCTRL
+ */
+#define DRA7XX_LOGICRETSTATE_SHIFT 2
+#define DRA7XX_LOGICRETSTATE_WIDTH 0x1
+#define DRA7XX_LOGICRETSTATE_MASK (1 << 2)
+
+/*
+ * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
+ * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST
+ */
+#define DRA7XX_LOGICSTATEST_SHIFT 2
+#define DRA7XX_LOGICSTATEST_WIDTH 0x1
+#define DRA7XX_LOGICSTATEST_MASK (1 << 2)
+
+/*
+ * Used by RM_ATL_ATL_CONTEXT, RM_CAM_CSI1_CONTEXT, RM_CAM_CSI2_CONTEXT,
+ * RM_CAM_LVDSRX_CONTEXT, RM_CAM_VIP1_CONTEXT, RM_CAM_VIP2_CONTEXT,
+ * RM_CAM_VIP3_CONTEXT, RM_COREAON_DUMMY_MODULE1_CONTEXT,
+ * RM_COREAON_DUMMY_MODULE2_CONTEXT, RM_COREAON_DUMMY_MODULE3_CONTEXT,
+ * RM_COREAON_DUMMY_MODULE4_CONTEXT, RM_COREAON_SMARTREFLEX_CORE_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT, RM_COREAON_SMARTREFLEX_GPU_CONTEXT,
+ * RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT, RM_COREAON_SMARTREFLEX_MPU_CONTEXT,
+ * RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, RM_DSP1_DSP1_CONTEXT,
+ * RM_DSP2_DSP2_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
+ * RM_DSS_SDVENC_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
+ * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_DLL_CONTEXT,
+ * RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_EVE1_EVE1_CONTEXT,
+ * RM_EVE2_EVE2_CONTEXT, RM_EVE3_EVE3_CONTEXT, RM_EVE4_EVE4_CONTEXT,
+ * RM_GMAC_GMAC_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU1_IPU1_CONTEXT,
+ * RM_IPU2_IPU2_CONTEXT, RM_IPU_I2C5_CONTEXT, RM_IPU_MCASP1_CONTEXT,
+ * RM_IPU_TIMER5_CONTEXT, RM_IPU_TIMER6_CONTEXT, RM_IPU_TIMER7_CONTEXT,
+ * RM_IPU_TIMER8_CONTEXT, RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT,
+ * RM_L3INIT_IEEE1500_2_OCP_CONTEXT, RM_L3INIT_MLB_SS_CONTEXT,
+ * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
+ * RM_L3INSTR_L3_MAIN_2_CONTEXT, RM_L3INSTR_OCP_WP_NOC_CONTEXT,
+ * RM_L3MAIN1_L3_MAIN_1_CONTEXT, RM_L3MAIN1_OCMC_RAM1_CONTEXT,
+ * RM_L3MAIN1_OCMC_RAM2_CONTEXT, RM_L3MAIN1_OCMC_RAM3_CONTEXT,
+ * RM_L3MAIN1_OCMC_ROM_CONTEXT, RM_L3MAIN1_SPARE_CME_CONTEXT,
+ * RM_L3MAIN1_SPARE_HDMI_CONTEXT, RM_L3MAIN1_SPARE_ICM_CONTEXT,
+ * RM_L3MAIN1_SPARE_IVA2_CONTEXT, RM_L3MAIN1_SPARE_SATA2_CONTEXT,
+ * RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT, RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT,
+ * RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT, RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT,
+ * RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT, RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT,
+ * RM_L3MAIN1_VCP1_CONTEXT, RM_L3MAIN1_VCP2_CONTEXT,
+ * RM_L4CFG_IO_DELAY_BLOCK_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
+ * RM_L4CFG_OCP2SCP2_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
+ * RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT,
+ * RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT,
+ * RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT, RM_L4PER2_DCAN2_CONTEXT,
+ * RM_L4PER2_L4PER2_CONTEXT, RM_L4PER2_MCASP2_CONTEXT,
+ * RM_L4PER2_MCASP3_CONTEXT, RM_L4PER2_MCASP4_CONTEXT,
+ * RM_L4PER2_MCASP5_CONTEXT, RM_L4PER2_MCASP6_CONTEXT,
+ * RM_L4PER2_MCASP7_CONTEXT, RM_L4PER2_MCASP8_CONTEXT,
+ * RM_L4PER2_PRUSS1_CONTEXT, RM_L4PER2_PRUSS2_CONTEXT,
+ * RM_L4PER2_PWMSS1_CONTEXT, RM_L4PER2_PWMSS2_CONTEXT,
+ * RM_L4PER2_PWMSS3_CONTEXT, RM_L4PER2_QSPI_CONTEXT, RM_L4PER3_L4PER3_CONTEXT,
+ * RM_L4PER3_TIMER13_CONTEXT, RM_L4PER3_TIMER14_CONTEXT,
+ * RM_L4PER3_TIMER15_CONTEXT, RM_L4PER3_TIMER16_CONTEXT, RM_L4PER_ELM_CONTEXT,
+ * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT,
+ * RM_L4PER_I2C4_CONTEXT, RM_L4PER_L4PER1_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
+ * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
+ * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_TIMER10_CONTEXT,
+ * RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, RM_L4PER_TIMER3_CONTEXT,
+ * RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, RM_L4SEC_FPKA_CONTEXT,
+ * RM_MPU_MPU_CONTEXT, RM_RTC_RTCSS_CONTEXT, RM_VPE_VPE_CONTEXT,
+ * RM_WKUPAON_ADC_CONTEXT, RM_WKUPAON_COUNTER_32K_CONTEXT,
+ * RM_WKUPAON_DCAN1_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, RM_WKUPAON_KBD_CONTEXT,
+ * RM_WKUPAON_L4_WKUP_CONTEXT, RM_WKUPAON_SAR_RAM_CONTEXT,
+ * RM_WKUPAON_SPARE_SAFETY1_CONTEXT, RM_WKUPAON_SPARE_SAFETY2_CONTEXT,
+ * RM_WKUPAON_SPARE_SAFETY3_CONTEXT, RM_WKUPAON_SPARE_SAFETY4_CONTEXT,
+ * RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT, RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT,
+ * RM_WKUPAON_TIMER12_CONTEXT, RM_WKUPAON_TIMER1_CONTEXT,
+ * RM_WKUPAON_UART10_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
+ * RM_WKUPAON_WD_TIMER2_CONTEXT
+ */
+#define DRA7XX_LOSTCONTEXT_DFF_SHIFT 0
+#define DRA7XX_LOSTCONTEXT_DFF_WIDTH 0x1
+#define DRA7XX_LOSTCONTEXT_DFF_MASK (1 << 0)
+
+/*
+ * Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT,
+ * RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
+ * RM_IPU1_IPU1_CONTEXT, RM_IPU2_IPU2_CONTEXT, RM_IPU_UART6_CONTEXT,
+ * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS1_CONTEXT, RM_L3INIT_USB_OTG_SS2_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS3_CONTEXT, RM_L3INIT_USB_OTG_SS4_CONTEXT,
+ * RM_L3INSTR_L3_MAIN_2_CONTEXT, RM_L3INSTR_OCP_WP_NOC_CONTEXT,
+ * RM_L3MAIN1_GPMC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
+ * RM_L3MAIN1_MMU_EDMA_CONTEXT, RM_L3MAIN1_TPCC_CONTEXT,
+ * RM_L3MAIN1_TPTC1_CONTEXT, RM_L3MAIN1_TPTC2_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
+ * RM_L4CFG_MAILBOX10_CONTEXT, RM_L4CFG_MAILBOX11_CONTEXT,
+ * RM_L4CFG_MAILBOX12_CONTEXT, RM_L4CFG_MAILBOX13_CONTEXT,
+ * RM_L4CFG_MAILBOX1_CONTEXT, RM_L4CFG_MAILBOX2_CONTEXT,
+ * RM_L4CFG_MAILBOX3_CONTEXT, RM_L4CFG_MAILBOX4_CONTEXT,
+ * RM_L4CFG_MAILBOX5_CONTEXT, RM_L4CFG_MAILBOX6_CONTEXT,
+ * RM_L4CFG_MAILBOX7_CONTEXT, RM_L4CFG_MAILBOX8_CONTEXT,
+ * RM_L4CFG_MAILBOX9_CONTEXT, RM_L4CFG_SPINLOCK_CONTEXT,
+ * RM_L4PER2_L4PER2_CONTEXT, RM_L4PER2_UART7_CONTEXT, RM_L4PER2_UART8_CONTEXT,
+ * RM_L4PER2_UART9_CONTEXT, RM_L4PER3_L4PER3_CONTEXT, RM_L4PER_GPIO2_CONTEXT,
+ * RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT,
+ * RM_L4PER_GPIO6_CONTEXT, RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT,
+ * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4PER1_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ * RM_L4PER_UART5_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
+ * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
+ * RM_L4SEC_SHA2MD51_CONTEXT, RM_L4SEC_SHA2MD52_CONTEXT, RM_MPU_MPU_CONTEXT
+ */
+#define DRA7XX_LOSTCONTEXT_RFF_SHIFT 1
+#define DRA7XX_LOSTCONTEXT_RFF_WIDTH 0x1
+#define DRA7XX_LOSTCONTEXT_RFF_MASK (1 << 1)
+
+/* Used by RM_ATL_ATL_CONTEXT */
+#define DRA7XX_LOSTMEM_ATL_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_ATL_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_ATL_BANK_MASK (1 << 8)
+
+/* Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
+#define DRA7XX_LOSTMEM_CORE_NRET_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8)
+
+/*
+ * Used by RM_L3MAIN1_OCMC_RAM1_CONTEXT, RM_L3MAIN1_OCMC_RAM2_CONTEXT,
+ * RM_L3MAIN1_OCMC_RAM3_CONTEXT
+ */
+#define DRA7XX_LOSTMEM_CORE_OCMRAM_SHIFT 8
+#define DRA7XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
+
+/* Used by RM_L3MAIN1_OCMC_ROM_CONTEXT */
+#define DRA7XX_LOSTMEM_CORE_OCMROM_SHIFT 8
+#define DRA7XX_LOSTMEM_CORE_OCMROM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_CORE_OCMROM_MASK (1 << 8)
+
+/* Used by RM_DMA_DMA_SYSTEM_CONTEXT */
+#define DRA7XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
+
+/* Used by RM_L4PER2_DCAN2_CONTEXT */
+#define DRA7XX_LOSTMEM_DCAN_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_DCAN_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DCAN_BANK_MASK (1 << 8)
+
+/* Used by RM_WKUPAON_DCAN1_CONTEXT */
+#define DRA7XX_LOSTMEM_DCAN_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_DCAN_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DCAN_MEM_MASK (1 << 8)
+
+/* Used by RM_DSP1_DSP1_CONTEXT, RM_DSP2_DSP2_CONTEXT */
+#define DRA7XX_LOSTMEM_DSP_EDMA_SHIFT 10
+#define DRA7XX_LOSTMEM_DSP_EDMA_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DSP_EDMA_MASK (1 << 10)
+
+/* Used by RM_DSP1_DSP1_CONTEXT, RM_DSP2_DSP2_CONTEXT */
+#define DRA7XX_LOSTMEM_DSP_L1_SHIFT 8
+#define DRA7XX_LOSTMEM_DSP_L1_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DSP_L1_MASK (1 << 8)
+
+/* Used by RM_DSP1_DSP1_CONTEXT, RM_DSP2_DSP2_CONTEXT */
+#define DRA7XX_LOSTMEM_DSP_L2_SHIFT 9
+#define DRA7XX_LOSTMEM_DSP_L2_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DSP_L2_MASK (1 << 9)
+
+/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
+#define DRA7XX_LOSTMEM_DSS_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_DSS_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_DSS_MEM_MASK (1 << 8)
+
+/* Used by RM_EMU_DEBUGSS_CONTEXT */
+#define DRA7XX_LOSTMEM_EMU_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_EMU_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_EMU_BANK_MASK (1 << 8)
+
+/*
+ * Used by RM_EVE1_EVE1_CONTEXT, RM_EVE2_EVE2_CONTEXT, RM_EVE3_EVE3_CONTEXT,
+ * RM_EVE4_EVE4_CONTEXT
+ */
+#define DRA7XX_LOSTMEM_EVE_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_EVE_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_EVE_BANK_MASK (1 << 8)
+
+/* Used by RM_GMAC_GMAC_CONTEXT */
+#define DRA7XX_LOSTMEM_GMAC_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_GMAC_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_GMAC_BANK_MASK (1 << 8)
+
+/* Used by RM_GPU_GPU_CONTEXT */
+#define DRA7XX_LOSTMEM_GPU_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_GPU_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_GPU_MEM_MASK (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define DRA7XX_LOSTMEM_HWA_MEM_SHIFT 10
+#define DRA7XX_LOSTMEM_HWA_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_HWA_MEM_MASK (1 << 10)
+
+/* Used by RM_IPU1_IPU1_CONTEXT, RM_IPU2_IPU2_CONTEXT */
+#define DRA7XX_LOSTMEM_IPU_L2RAM_SHIFT 9
+#define DRA7XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9)
+
+/* Used by RM_IPU1_IPU1_CONTEXT, RM_IPU2_IPU2_CONTEXT */
+#define DRA7XX_LOSTMEM_IPU_UNICACHE_SHIFT 8
+#define DRA7XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1
+#define DRA7XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8)
+
+/*
+ * Used by RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
+ * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_USB_OTG_SS1_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS2_CONTEXT, RM_L3INIT_USB_OTG_SS3_CONTEXT,
+ * RM_L3INIT_USB_OTG_SS4_CONTEXT
+ */
+#define DRA7XX_LOSTMEM_L3INIT_BANK1_SHIFT 8
+#define DRA7XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1
+#define DRA7XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
+
+/* Used by RM_L3INIT_MLB_SS_CONTEXT */
+#define DRA7XX_LOSTMEM_MLB_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_MLB_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_MLB_BANK_MASK (1 << 8)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define DRA7XX_LOSTMEM_MPU_L2_SHIFT 9
+#define DRA7XX_LOSTMEM_MPU_L2_WIDTH 0x1
+#define DRA7XX_LOSTMEM_MPU_L2_MASK (1 << 9)
+
+/* Used by RM_MPU_MPU_CONTEXT */
+#define DRA7XX_LOSTMEM_MPU_RAM_SHIFT 10
+#define DRA7XX_LOSTMEM_MPU_RAM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_MPU_RAM_MASK (1 << 10)
+
+/* Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4SEC_FPKA_CONTEXT */
+#define DRA7XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
+
+/* Used by RM_L4PER2_PRUSS1_CONTEXT */
+#define DRA7XX_LOSTMEM_PRUSS1_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_PRUSS1_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_PRUSS1_BANK_MASK (1 << 8)
+
+/* Used by RM_L4PER2_PRUSS2_CONTEXT */
+#define DRA7XX_LOSTMEM_PRUSS2_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_PRUSS2_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_PRUSS2_BANK_MASK (1 << 8)
+
+/*
+ * Used by RM_IPU_UART6_CONTEXT, RM_L4PER2_UART7_CONTEXT,
+ * RM_L4PER2_UART8_CONTEXT, RM_L4PER2_UART9_CONTEXT, RM_L4PER_UART1_CONTEXT,
+ * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
+ * RM_L4PER_UART5_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT,
+ * RM_WKUPAON_UART10_CONTEXT
+ */
+#define DRA7XX_LOSTMEM_RETAINED_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
+
+/* Used by RM_IVA_SL2_CONTEXT */
+#define DRA7XX_LOSTMEM_SL2_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_SL2_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_SL2_MEM_MASK (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define DRA7XX_LOSTMEM_TCM1_MEM_SHIFT 8
+#define DRA7XX_LOSTMEM_TCM1_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_TCM1_MEM_MASK (1 << 8)
+
+/* Used by RM_IVA_IVA_CONTEXT */
+#define DRA7XX_LOSTMEM_TCM2_MEM_SHIFT 9
+#define DRA7XX_LOSTMEM_TCM2_MEM_WIDTH 0x1
+#define DRA7XX_LOSTMEM_TCM2_MEM_MASK (1 << 9)
+
+/* Used by RM_L3MAIN1_TPCC_CONTEXT */
+#define DRA7XX_LOSTMEM_TPCC_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_TPCC_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_TPCC_BANK_MASK (1 << 8)
+
+/* Used by RM_L3MAIN1_TPTC1_CONTEXT, RM_L3MAIN1_TPTC2_CONTEXT */
+#define DRA7XX_LOSTMEM_TPTC_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_TPTC_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_TPTC_BANK_MASK (1 << 8)
+
+/* Used by RM_L3MAIN1_VCP1_CONTEXT, RM_L3MAIN1_VCP2_CONTEXT */
+#define DRA7XX_LOSTMEM_VCP_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_VCP_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_VCP_BANK_MASK (1 << 8)
+
+/* Used by RM_CAM_VIP1_CONTEXT, RM_CAM_VIP2_CONTEXT, RM_CAM_VIP3_CONTEXT */
+#define DRA7XX_LOSTMEM_VIP_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_VIP_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_VIP_BANK_MASK (1 << 8)
+
+/* Used by RM_VPE_VPE_CONTEXT */
+#define DRA7XX_LOSTMEM_VPE_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_VPE_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_VPE_BANK_MASK (1 << 8)
+
+/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
+#define DRA7XX_LOSTMEM_WKUP_BANK_SHIFT 8
+#define DRA7XX_LOSTMEM_WKUP_BANK_WIDTH 0x1
+#define DRA7XX_LOSTMEM_WKUP_BANK_MASK (1 << 8)
+
+/*
+ * Used by PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CUSTEFUSE_PWRSTCTRL,
+ * PM_DSP1_PWRSTCTRL, PM_DSP2_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EVE1_PWRSTCTRL,
+ * PM_EVE2_PWRSTCTRL, PM_EVE3_PWRSTCTRL, PM_EVE4_PWRSTCTRL, PM_GPU_PWRSTCTRL,
+ * PM_IPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_VPE_PWRSTCTRL
+ */
+#define DRA7XX_LOWPOWERSTATECHANGE_SHIFT 4
+#define DRA7XX_LOWPOWERSTATECHANGE_WIDTH 0x1
+#define DRA7XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define DRA7XX_MODEM_SHUTDOWN_IRQ_SHIFT 9
+#define DRA7XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1
+#define DRA7XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
+
+/* Used by PRM_MODEM_IF_CTRL */
+#define DRA7XX_MODEM_WAKE_IRQ_SHIFT 8
+#define DRA7XX_MODEM_WAKE_IRQ_WIDTH 0x1
+#define DRA7XX_MODEM_WAKE_IRQ_MASK (1 << 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define DRA7XX_MPU_L2_ONSTATE_SHIFT 18
+#define DRA7XX_MPU_L2_ONSTATE_WIDTH 0x2
+#define DRA7XX_MPU_L2_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define DRA7XX_MPU_L2_RETSTATE_SHIFT 9
+#define DRA7XX_MPU_L2_RETSTATE_WIDTH 0x1
+#define DRA7XX_MPU_L2_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_MPU_PWRSTST */
+#define DRA7XX_MPU_L2_STATEST_SHIFT 6
+#define DRA7XX_MPU_L2_STATEST_WIDTH 0x2
+#define DRA7XX_MPU_L2_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define DRA7XX_MPU_RAM_ONSTATE_SHIFT 20
+#define DRA7XX_MPU_RAM_ONSTATE_WIDTH 0x2
+#define DRA7XX_MPU_RAM_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define DRA7XX_MPU_RAM_RETSTATE_SHIFT 10
+#define DRA7XX_MPU_RAM_RETSTATE_WIDTH 0x1
+#define DRA7XX_MPU_RAM_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_MPU_PWRSTST */
+#define DRA7XX_MPU_RAM_STATEST_SHIFT 8
+#define DRA7XX_MPU_RAM_STATEST_WIDTH 0x2
+#define DRA7XX_MPU_RAM_STATEST_MASK (0x3 << 8)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_MPU_SECURITY_VIOL_RST_SHIFT 2
+#define DRA7XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1
+#define DRA7XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_MPU_WDT_RST_SHIFT 3
+#define DRA7XX_MPU_WDT_RST_WIDTH 0x1
+#define DRA7XX_MPU_WDT_RST_MASK (1 << 3)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
+ * PRM_ABBLDO_MPU_SETUP
+ */
+#define DRA7XX_NOCAP_SHIFT 4
+#define DRA7XX_NOCAP_WIDTH 0x1
+#define DRA7XX_NOCAP_MASK (1 << 4)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define DRA7XX_NONRETAINED_BANK_ONSTATE_SHIFT 18
+#define DRA7XX_NONRETAINED_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define DRA7XX_NONRETAINED_BANK_RETSTATE_SHIFT 9
+#define DRA7XX_NONRETAINED_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_NONRETAINED_BANK_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_L4PER_PWRSTST */
+#define DRA7XX_NONRETAINED_BANK_STATEST_SHIFT 6
+#define DRA7XX_NONRETAINED_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_NONRETAINED_BANK_STATEST_MASK (0x3 << 6)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_OCP_NRET_BANK_ONSTATE_SHIFT 24
+#define DRA7XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
+
+/* Used by PM_CORE_PWRSTCTRL */
+#define DRA7XX_OCP_NRET_BANK_RETSTATE_SHIFT 12
+#define DRA7XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
+
+/* Used by PM_CORE_PWRSTST */
+#define DRA7XX_OCP_NRET_BANK_STATEST_SHIFT 12
+#define DRA7XX_OCP_NRET_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
+ * PRM_ABBLDO_MPU_CTRL
+ */
+#define DRA7XX_OPP_CHANGE_SHIFT 2
+#define DRA7XX_OPP_CHANGE_WIDTH 0x1
+#define DRA7XX_OPP_CHANGE_MASK (1 << 2)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
+ * PRM_ABBLDO_MPU_CTRL
+ */
+#define DRA7XX_OPP_SEL_SHIFT 0
+#define DRA7XX_OPP_SEL_WIDTH 0x2
+#define DRA7XX_OPP_SEL_MASK (0x3 << 0)
+
+/* Used by PRM_DEBUG_OUT */
+#define DRA7XX_OUTPUT_SHIFT 0
+#define DRA7XX_OUTPUT_WIDTH 0x20
+#define DRA7XX_OUTPUT_MASK (0xffffffff << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define DRA7XX_PCHARGECNT_VALUE_SHIFT 0
+#define DRA7XX_PCHARGECNT_VALUE_WIDTH 0x6
+#define DRA7XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
+
+/* Used by PRM_PSCON_COUNT */
+#define DRA7XX_PCHARGE_TIME_SHIFT 0
+#define DRA7XX_PCHARGE_TIME_WIDTH 0x8
+#define DRA7XX_PCHARGE_TIME_MASK (0xff << 0)
+
+/* Used by PM_IPU_PWRSTCTRL */
+#define DRA7XX_PERIPHMEM_ONSTATE_SHIFT 20
+#define DRA7XX_PERIPHMEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_IPU_PWRSTCTRL */
+#define DRA7XX_PERIPHMEM_RETSTATE_SHIFT 10
+#define DRA7XX_PERIPHMEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_PERIPHMEM_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_IPU_PWRSTST */
+#define DRA7XX_PERIPHMEM_STATEST_SHIFT 8
+#define DRA7XX_PERIPHMEM_STATEST_WIDTH 0x2
+#define DRA7XX_PERIPHMEM_STATEST_MASK (0x3 << 8)
+
+/* Used by PRM_PHASE1_CNDP */
+#define DRA7XX_PHASE1_CNDP_SHIFT 0
+#define DRA7XX_PHASE1_CNDP_WIDTH 0x20
+#define DRA7XX_PHASE1_CNDP_MASK (0xffffffff << 0)
+
+/* Used by PRM_PHASE2A_CNDP */
+#define DRA7XX_PHASE2A_CNDP_SHIFT 0
+#define DRA7XX_PHASE2A_CNDP_WIDTH 0x20
+#define DRA7XX_PHASE2A_CNDP_MASK (0xffffffff << 0)
+
+/* Used by PRM_PHASE2B_CNDP */
+#define DRA7XX_PHASE2B_CNDP_SHIFT 0
+#define DRA7XX_PHASE2B_CNDP_WIDTH 0x20
+#define DRA7XX_PHASE2B_CNDP_MASK (0xffffffff << 0)
+
+/* Used by PRM_PSCON_COUNT */
+#define DRA7XX_PONOUT_2_PGOODIN_TIME_SHIFT 8
+#define DRA7XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8
+#define DRA7XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
+
+/*
+ * Used by PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CUSTEFUSE_PWRSTCTRL,
+ * PM_DSP1_PWRSTCTRL, PM_DSP2_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL,
+ * PM_EVE1_PWRSTCTRL, PM_EVE2_PWRSTCTRL, PM_EVE3_PWRSTCTRL, PM_EVE4_PWRSTCTRL,
+ * PM_GPU_PWRSTCTRL, PM_IPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
+ * PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_VPE_PWRSTCTRL
+ */
+#define DRA7XX_POWERSTATE_SHIFT 0
+#define DRA7XX_POWERSTATE_WIDTH 0x2
+#define DRA7XX_POWERSTATE_MASK (0x3 << 0)
+
+/*
+ * Used by PM_CAM_PWRSTST, PM_CORE_PWRSTST, PM_CUSTEFUSE_PWRSTST,
+ * PM_DSP1_PWRSTST, PM_DSP2_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
+ * PM_EVE1_PWRSTST, PM_EVE2_PWRSTST, PM_EVE3_PWRSTST, PM_EVE4_PWRSTST,
+ * PM_GPU_PWRSTST, PM_IPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST,
+ * PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_VPE_PWRSTST
+ */
+#define DRA7XX_POWERSTATEST_SHIFT 0
+#define DRA7XX_POWERSTATEST_WIDTH 0x2
+#define DRA7XX_POWERSTATEST_MASK (0x3 << 0)
+
+/* Used by PRM_PWRREQCTRL */
+#define DRA7XX_PWRREQ_COND_SHIFT 0
+#define DRA7XX_PWRREQ_COND_WIDTH 0x2
+#define DRA7XX_PWRREQ_COND_MASK (0x3 << 0)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define DRA7XX_RAMP_DOWN_COUNT_SHIFT 16
+#define DRA7XX_RAMP_DOWN_COUNT_WIDTH 0x6
+#define DRA7XX_RAMP_DOWN_COUNT_MASK (0x3f << 16)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define DRA7XX_RAMP_DOWN_PRESCAL_SHIFT 24
+#define DRA7XX_RAMP_DOWN_PRESCAL_WIDTH 0x2
+#define DRA7XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define DRA7XX_RAMP_UP_COUNT_SHIFT 0
+#define DRA7XX_RAMP_UP_COUNT_WIDTH 0x6
+#define DRA7XX_RAMP_UP_COUNT_MASK (0x3f << 0)
+
+/*
+ * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
+ * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
+ * PRM_VOLTSETUP_MPU_RET_SLEEP
+ */
+#define DRA7XX_RAMP_UP_PRESCAL_SHIFT 8
+#define DRA7XX_RAMP_UP_PRESCAL_WIDTH 0x2
+#define DRA7XX_RAMP_UP_PRESCAL_MASK (0x3 << 8)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define DRA7XX_RETAINED_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_RETAINED_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_RETAINED_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_L4PER_PWRSTCTRL */
+#define DRA7XX_RETAINED_BANK_RETSTATE_SHIFT 8
+#define DRA7XX_RETAINED_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_RETAINED_BANK_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_L4PER_PWRSTST */
+#define DRA7XX_RETAINED_BANK_STATEST_SHIFT 4
+#define DRA7XX_RETAINED_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_RETAINED_BANK_STATEST_MASK (0x3 << 4)
+
+/*
+ * Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_DSPEVE_CTRL, PRM_SLDO_GPU_CTRL,
+ * PRM_SLDO_IVA_CTRL, PRM_SLDO_MPU_CTRL
+ */
+#define DRA7XX_RETMODE_ENABLE_SHIFT 0
+#define DRA7XX_RETMODE_ENABLE_WIDTH 0x1
+#define DRA7XX_RETMODE_ENABLE_MASK (1 << 0)
+
+/* Used by PRM_RSTTIME */
+#define DRA7XX_RSTTIME1_SHIFT 0
+#define DRA7XX_RSTTIME1_WIDTH 0xa
+#define DRA7XX_RSTTIME1_MASK (0x3ff << 0)
+
+/* Used by PRM_RSTTIME */
+#define DRA7XX_RSTTIME2_SHIFT 10
+#define DRA7XX_RSTTIME2_WIDTH 0x5
+#define DRA7XX_RSTTIME2_MASK (0x1f << 10)
+
+/* Used by RM_IPU1_RSTCTRL, RM_IPU1_RSTST, RM_IPU2_RSTCTRL, RM_IPU2_RSTST */
+#define DRA7XX_RST_CPU0_SHIFT 0
+#define DRA7XX_RST_CPU0_WIDTH 0x1
+#define DRA7XX_RST_CPU0_MASK (1 << 0)
+
+/* Used by RM_IPU1_RSTCTRL, RM_IPU1_RSTST, RM_IPU2_RSTCTRL, RM_IPU2_RSTST */
+#define DRA7XX_RST_CPU1_SHIFT 1
+#define DRA7XX_RST_CPU1_WIDTH 0x1
+#define DRA7XX_RST_CPU1_MASK (1 << 1)
+
+/* Used by RM_DSP1_RSTCTRL, RM_DSP1_RSTST */
+#define DRA7XX_RST_DSP1_SHIFT 1
+#define DRA7XX_RST_DSP1_WIDTH 0x1
+#define DRA7XX_RST_DSP1_MASK (1 << 1)
+
+/* Used by RM_DSP1_RSTST */
+#define DRA7XX_RST_DSP1_EMU_SHIFT 2
+#define DRA7XX_RST_DSP1_EMU_WIDTH 0x1
+#define DRA7XX_RST_DSP1_EMU_MASK (1 << 2)
+
+/* Used by RM_DSP1_RSTST */
+#define DRA7XX_RST_DSP1_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_DSP1_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_DSP1_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_DSP1_RSTCTRL, RM_DSP1_RSTST */
+#define DRA7XX_RST_DSP1_LRST_SHIFT 0
+#define DRA7XX_RST_DSP1_LRST_WIDTH 0x1
+#define DRA7XX_RST_DSP1_LRST_MASK (1 << 0)
+
+/* Used by RM_DSP2_RSTCTRL, RM_DSP2_RSTST */
+#define DRA7XX_RST_DSP2_SHIFT 1
+#define DRA7XX_RST_DSP2_WIDTH 0x1
+#define DRA7XX_RST_DSP2_MASK (1 << 1)
+
+/* Used by RM_DSP2_RSTST */
+#define DRA7XX_RST_DSP2_EMU_SHIFT 2
+#define DRA7XX_RST_DSP2_EMU_WIDTH 0x1
+#define DRA7XX_RST_DSP2_EMU_MASK (1 << 2)
+
+/* Used by RM_DSP2_RSTST */
+#define DRA7XX_RST_DSP2_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_DSP2_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_DSP2_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_DSP2_RSTCTRL, RM_DSP2_RSTST */
+#define DRA7XX_RST_DSP2_LRST_SHIFT 0
+#define DRA7XX_RST_DSP2_LRST_WIDTH 0x1
+#define DRA7XX_RST_DSP2_LRST_MASK (1 << 0)
+
+/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
+#define DRA7XX_RST_EMULATION_CPU0_SHIFT 3
+#define DRA7XX_RST_EMULATION_CPU0_WIDTH 0x1
+#define DRA7XX_RST_EMULATION_CPU0_MASK (1 << 3)
+
+/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
+#define DRA7XX_RST_EMULATION_CPU1_SHIFT 4
+#define DRA7XX_RST_EMULATION_CPU1_WIDTH 0x1
+#define DRA7XX_RST_EMULATION_CPU1_MASK (1 << 4)
+
+/* Used by RM_IVA_RSTST */
+#define DRA7XX_RST_EMULATION_SEQ1_SHIFT 3
+#define DRA7XX_RST_EMULATION_SEQ1_WIDTH 0x1
+#define DRA7XX_RST_EMULATION_SEQ1_MASK (1 << 3)
+
+/* Used by RM_IVA_RSTST */
+#define DRA7XX_RST_EMULATION_SEQ2_SHIFT 4
+#define DRA7XX_RST_EMULATION_SEQ2_WIDTH 0x1
+#define DRA7XX_RST_EMULATION_SEQ2_MASK (1 << 4)
+
+/* Used by RM_EVE1_RSTCTRL, RM_EVE1_RSTST */
+#define DRA7XX_RST_EVE1_SHIFT 1
+#define DRA7XX_RST_EVE1_WIDTH 0x1
+#define DRA7XX_RST_EVE1_MASK (1 << 1)
+
+/* Used by RM_EVE1_RSTST */
+#define DRA7XX_RST_EVE1_EMU_SHIFT 2
+#define DRA7XX_RST_EVE1_EMU_WIDTH 0x1
+#define DRA7XX_RST_EVE1_EMU_MASK (1 << 2)
+
+/* Used by RM_EVE1_RSTST */
+#define DRA7XX_RST_EVE1_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_EVE1_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_EVE1_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_EVE1_RSTCTRL, RM_EVE1_RSTST */
+#define DRA7XX_RST_EVE1_LRST_SHIFT 0
+#define DRA7XX_RST_EVE1_LRST_WIDTH 0x1
+#define DRA7XX_RST_EVE1_LRST_MASK (1 << 0)
+
+/* Used by RM_EVE2_RSTCTRL, RM_EVE2_RSTST */
+#define DRA7XX_RST_EVE2_SHIFT 1
+#define DRA7XX_RST_EVE2_WIDTH 0x1
+#define DRA7XX_RST_EVE2_MASK (1 << 1)
+
+/* Used by RM_EVE2_RSTST */
+#define DRA7XX_RST_EVE2_EMU_SHIFT 2
+#define DRA7XX_RST_EVE2_EMU_WIDTH 0x1
+#define DRA7XX_RST_EVE2_EMU_MASK (1 << 2)
+
+/* Used by RM_EVE2_RSTST */
+#define DRA7XX_RST_EVE2_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_EVE2_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_EVE2_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_EVE2_RSTCTRL, RM_EVE2_RSTST */
+#define DRA7XX_RST_EVE2_LRST_SHIFT 0
+#define DRA7XX_RST_EVE2_LRST_WIDTH 0x1
+#define DRA7XX_RST_EVE2_LRST_MASK (1 << 0)
+
+/* Used by RM_EVE3_RSTCTRL, RM_EVE3_RSTST */
+#define DRA7XX_RST_EVE3_SHIFT 1
+#define DRA7XX_RST_EVE3_WIDTH 0x1
+#define DRA7XX_RST_EVE3_MASK (1 << 1)
+
+/* Used by RM_EVE3_RSTST */
+#define DRA7XX_RST_EVE3_EMU_SHIFT 2
+#define DRA7XX_RST_EVE3_EMU_WIDTH 0x1
+#define DRA7XX_RST_EVE3_EMU_MASK (1 << 2)
+
+/* Used by RM_EVE3_RSTST */
+#define DRA7XX_RST_EVE3_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_EVE3_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_EVE3_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_EVE3_RSTCTRL, RM_EVE3_RSTST */
+#define DRA7XX_RST_EVE3_LRST_SHIFT 0
+#define DRA7XX_RST_EVE3_LRST_WIDTH 0x1
+#define DRA7XX_RST_EVE3_LRST_MASK (1 << 0)
+
+/* Used by RM_EVE4_RSTCTRL, RM_EVE4_RSTST */
+#define DRA7XX_RST_EVE4_SHIFT 1
+#define DRA7XX_RST_EVE4_WIDTH 0x1
+#define DRA7XX_RST_EVE4_MASK (1 << 1)
+
+/* Used by RM_EVE4_RSTST */
+#define DRA7XX_RST_EVE4_EMU_SHIFT 2
+#define DRA7XX_RST_EVE4_EMU_WIDTH 0x1
+#define DRA7XX_RST_EVE4_EMU_MASK (1 << 2)
+
+/* Used by RM_EVE4_RSTST */
+#define DRA7XX_RST_EVE4_EMU_REQ_SHIFT 3
+#define DRA7XX_RST_EVE4_EMU_REQ_WIDTH 0x1
+#define DRA7XX_RST_EVE4_EMU_REQ_MASK (1 << 3)
+
+/* Used by RM_EVE4_RSTCTRL, RM_EVE4_RSTST */
+#define DRA7XX_RST_EVE4_LRST_SHIFT 0
+#define DRA7XX_RST_EVE4_LRST_WIDTH 0x1
+#define DRA7XX_RST_EVE4_LRST_MASK (1 << 0)
+
+/* Used by PRM_RSTCTRL */
+#define DRA7XX_RST_GLOBAL_COLD_SW_SHIFT 1
+#define DRA7XX_RST_GLOBAL_COLD_SW_WIDTH 0x1
+#define DRA7XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
+
+/* Used by PRM_RSTCTRL */
+#define DRA7XX_RST_GLOBAL_WARM_SW_SHIFT 0
+#define DRA7XX_RST_GLOBAL_WARM_SW_WIDTH 0x1
+#define DRA7XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
+
+/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
+#define DRA7XX_RST_ICECRUSHER_CPU0_SHIFT 5
+#define DRA7XX_RST_ICECRUSHER_CPU0_WIDTH 0x1
+#define DRA7XX_RST_ICECRUSHER_CPU0_MASK (1 << 5)
+
+/* Used by RM_IPU1_RSTST, RM_IPU2_RSTST */
+#define DRA7XX_RST_ICECRUSHER_CPU1_SHIFT 6
+#define DRA7XX_RST_ICECRUSHER_CPU1_WIDTH 0x1
+#define DRA7XX_RST_ICECRUSHER_CPU1_MASK (1 << 6)
+
+/* Used by RM_IVA_RSTST */
+#define DRA7XX_RST_ICECRUSHER_SEQ1_SHIFT 5
+#define DRA7XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1
+#define DRA7XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5)
+
+/* Used by RM_IVA_RSTST */
+#define DRA7XX_RST_ICECRUSHER_SEQ2_SHIFT 6
+#define DRA7XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1
+#define DRA7XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6)
+
+/* Used by RM_IPU1_RSTCTRL, RM_IPU1_RSTST, RM_IPU2_RSTCTRL, RM_IPU2_RSTST */
+#define DRA7XX_RST_IPU_SHIFT 2
+#define DRA7XX_RST_IPU_WIDTH 0x1
+#define DRA7XX_RST_IPU_MASK (1 << 2)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define DRA7XX_RST_LOGIC_SHIFT 2
+#define DRA7XX_RST_LOGIC_WIDTH 0x1
+#define DRA7XX_RST_LOGIC_MASK (1 << 2)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define DRA7XX_RST_SEQ1_SHIFT 0
+#define DRA7XX_RST_SEQ1_WIDTH 0x1
+#define DRA7XX_RST_SEQ1_MASK (1 << 0)
+
+/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
+#define DRA7XX_RST_SEQ2_SHIFT 1
+#define DRA7XX_RST_SEQ2_WIDTH 0x1
+#define DRA7XX_RST_SEQ2_MASK (1 << 1)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_R_RTL_SHIFT 11
+#define DRA7XX_R_RTL_WIDTH 0x5
+#define DRA7XX_R_RTL_MASK (0x1f << 11)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_SCHEME_SHIFT 30
+#define DRA7XX_SCHEME_WIDTH 0x2
+#define DRA7XX_SCHEME_MASK (0x3 << 30)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_SECURE_WDT_RST_SHIFT 4
+#define DRA7XX_SECURE_WDT_RST_WIDTH 0x1
+#define DRA7XX_SECURE_WDT_RST_MASK (1 << 4)
+
+/* Used by PRM_DEBUG_CFG1 */
+#define DRA7XX_PRM_SEL1_SHIFT 0
+#define DRA7XX_PRM_SEL1_WIDTH 0x9
+#define DRA7XX_PRM_SEL1_MASK (0x1ff << 0)
+
+/* Used by PRM_DEBUG_CFG2 */
+#define DRA7XX_PRM_SEL2_SHIFT 0
+#define DRA7XX_PRM_SEL2_WIDTH 0x9
+#define DRA7XX_PRM_SEL2_MASK (0x1ff << 0)
+
+/* Used by PRM_DEBUG_CFG3 */
+#define DRA7XX_PRM_SEL3_SHIFT 0
+#define DRA7XX_PRM_SEL3_WIDTH 0x9
+#define DRA7XX_PRM_SEL3_MASK (0x1ff << 0)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_SL2_MEM_ONSTATE_SHIFT 18
+#define DRA7XX_SL2_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_SL2_MEM_ONSTATE_MASK (0x3 << 18)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_SL2_MEM_RETSTATE_SHIFT 9
+#define DRA7XX_SL2_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_SL2_MEM_RETSTATE_MASK (1 << 9)
+
+/* Used by PM_IVA_PWRSTST */
+#define DRA7XX_SL2_MEM_STATEST_SHIFT 6
+#define DRA7XX_SL2_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_SL2_MEM_STATEST_MASK (0x3 << 6)
+
+/* Used by PRM_SRAM_COUNT */
+#define DRA7XX_SLPCNT_VALUE_SHIFT 16
+#define DRA7XX_SLPCNT_VALUE_WIDTH 0x8
+#define DRA7XX_SLPCNT_VALUE_MASK (0xff << 16)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
+ * PRM_ABBLDO_MPU_SETUP
+ */
+#define DRA7XX_SR2EN_SHIFT 0
+#define DRA7XX_SR2EN_WIDTH 0x1
+#define DRA7XX_SR2EN_MASK (1 << 0)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
+ * PRM_ABBLDO_MPU_CTRL
+ */
+#define DRA7XX_SR2_IN_TRANSITION_SHIFT 6
+#define DRA7XX_SR2_IN_TRANSITION_WIDTH 0x1
+#define DRA7XX_SR2_IN_TRANSITION_MASK (1 << 6)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_CTRL, PRM_ABBLDO_GPU_CTRL, PRM_ABBLDO_IVA_CTRL,
+ * PRM_ABBLDO_MPU_CTRL
+ */
+#define DRA7XX_SR2_STATUS_SHIFT 3
+#define DRA7XX_SR2_STATUS_WIDTH 0x2
+#define DRA7XX_SR2_STATUS_MASK (0x3 << 3)
+
+/*
+ * Used by PRM_ABBLDO_DSPEVE_SETUP, PRM_ABBLDO_GPU_SETUP, PRM_ABBLDO_IVA_SETUP,
+ * PRM_ABBLDO_MPU_SETUP
+ */
+#define DRA7XX_SR2_WTCNT_VALUE_SHIFT 8
+#define DRA7XX_SR2_WTCNT_VALUE_WIDTH 0x8
+#define DRA7XX_SR2_WTCNT_VALUE_MASK (0xff << 8)
+
+/*
+ * Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_DSPEVE_CTRL, PRM_SLDO_GPU_CTRL,
+ * PRM_SLDO_IVA_CTRL, PRM_SLDO_MPU_CTRL
+ */
+#define DRA7XX_SRAMLDO_STATUS_SHIFT 8
+#define DRA7XX_SRAMLDO_STATUS_WIDTH 0x1
+#define DRA7XX_SRAMLDO_STATUS_MASK (1 << 8)
+
+/*
+ * Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_DSPEVE_CTRL, PRM_SLDO_GPU_CTRL,
+ * PRM_SLDO_IVA_CTRL, PRM_SLDO_MPU_CTRL
+ */
+#define DRA7XX_SRAM_IN_TRANSITION_SHIFT 9
+#define DRA7XX_SRAM_IN_TRANSITION_WIDTH 0x1
+#define DRA7XX_SRAM_IN_TRANSITION_MASK (1 << 9)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define DRA7XX_STABLE_COUNT_SHIFT 0
+#define DRA7XX_STABLE_COUNT_WIDTH 0x6
+#define DRA7XX_STABLE_COUNT_MASK (0x3f << 0)
+
+/* Used by PRM_VOLTSETUP_WARMRESET */
+#define DRA7XX_STABLE_PRESCAL_SHIFT 8
+#define DRA7XX_STABLE_PRESCAL_WIDTH 0x2
+#define DRA7XX_STABLE_PRESCAL_MASK (0x3 << 8)
+
+/* Used by PRM_BANDGAP_SETUP */
+#define DRA7XX_STARTUP_COUNT_SHIFT 0
+#define DRA7XX_STARTUP_COUNT_WIDTH 0x8
+#define DRA7XX_STARTUP_COUNT_MASK (0xff << 0)
+
+/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
+#define DRA7XX_STARTUP_COUNT_24_31_SHIFT 24
+#define DRA7XX_STARTUP_COUNT_24_31_WIDTH 0x8
+#define DRA7XX_STARTUP_COUNT_24_31_MASK (0xff << 24)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_TCM1_MEM_ONSTATE_SHIFT 20
+#define DRA7XX_TCM1_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_TCM1_MEM_RETSTATE_SHIFT 10
+#define DRA7XX_TCM1_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_TCM1_MEM_RETSTATE_MASK (1 << 10)
+
+/* Used by PM_IVA_PWRSTST */
+#define DRA7XX_TCM1_MEM_STATEST_SHIFT 8
+#define DRA7XX_TCM1_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_TCM1_MEM_STATEST_MASK (0x3 << 8)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_TCM2_MEM_ONSTATE_SHIFT 22
+#define DRA7XX_TCM2_MEM_ONSTATE_WIDTH 0x2
+#define DRA7XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
+
+/* Used by PM_IVA_PWRSTCTRL */
+#define DRA7XX_TCM2_MEM_RETSTATE_SHIFT 11
+#define DRA7XX_TCM2_MEM_RETSTATE_WIDTH 0x1
+#define DRA7XX_TCM2_MEM_RETSTATE_MASK (1 << 11)
+
+/* Used by PM_IVA_PWRSTST */
+#define DRA7XX_TCM2_MEM_STATEST_SHIFT 10
+#define DRA7XX_TCM2_MEM_STATEST_WIDTH 0x2
+#define DRA7XX_TCM2_MEM_STATEST_MASK (0x3 << 10)
+
+/* Used by PRM_IRQENABLE_IPU1, PRM_IRQENABLE_IPU2, PRM_IRQENABLE_MPU */
+#define DRA7XX_TRANSITION_EN_SHIFT 8
+#define DRA7XX_TRANSITION_EN_WIDTH 0x1
+#define DRA7XX_TRANSITION_EN_MASK (1 << 8)
+
+/* Used by PRM_IRQSTATUS_IPU1, PRM_IRQSTATUS_IPU2, PRM_IRQSTATUS_MPU */
+#define DRA7XX_TRANSITION_ST_SHIFT 8
+#define DRA7XX_TRANSITION_ST_WIDTH 0x1
+#define DRA7XX_TRANSITION_ST_MASK (1 << 8)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_CORE_RST_SHIFT 13
+#define DRA7XX_TSHUT_CORE_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_CORE_RST_MASK (1 << 13)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_DSPEVE_RST_SHIFT 15
+#define DRA7XX_TSHUT_DSPEVE_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_DSPEVE_RST_MASK (1 << 15)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_IVA_RST_SHIFT 16
+#define DRA7XX_TSHUT_IVA_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_IVA_RST_MASK (1 << 16)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_MM_RST_SHIFT 12
+#define DRA7XX_TSHUT_MM_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_MM_RST_MASK (1 << 12)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_TSHUT_MPU_RST_SHIFT 11
+#define DRA7XX_TSHUT_MPU_RST_WIDTH 0x1
+#define DRA7XX_TSHUT_MPU_RST_MASK (1 << 11)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_CORE_I2C_DISABLE_SHIFT 12
+#define DRA7XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1
+#define DRA7XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8
+#define DRA7XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1
+#define DRA7XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_MM_I2C_DISABLE_SHIFT 14
+#define DRA7XX_VDD_MM_I2C_DISABLE_WIDTH 0x1
+#define DRA7XX_VDD_MM_I2C_DISABLE_MASK (1 << 14)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_MM_PRESENCE_SHIFT 9
+#define DRA7XX_VDD_MM_PRESENCE_WIDTH 0x1
+#define DRA7XX_VDD_MM_PRESENCE_MASK (1 << 9)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_VDD_MM_VOLT_MGR_RST_SHIFT 7
+#define DRA7XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1
+#define DRA7XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_MPU_I2C_DISABLE_SHIFT 13
+#define DRA7XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1
+#define DRA7XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
+
+/* Used by PRM_VOLTCTRL */
+#define DRA7XX_VDD_MPU_PRESENCE_SHIFT 8
+#define DRA7XX_VDD_MPU_PRESENCE_WIDTH 0x1
+#define DRA7XX_VDD_MPU_PRESENCE_MASK (1 << 8)
+
+/* Used by PRM_RSTST */
+#define DRA7XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6
+#define DRA7XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1
+#define DRA7XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
+
+/* Used by PM_CAM_PWRSTCTRL */
+#define DRA7XX_VIP_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_VIP_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_VIP_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_CAM_PWRSTST */
+#define DRA7XX_VIP_BANK_STATEST_SHIFT 4
+#define DRA7XX_VIP_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_VIP_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
+#define DRA7XX_VOLTSTATEST_SHIFT 0
+#define DRA7XX_VOLTSTATEST_WIDTH 0x2
+#define DRA7XX_VOLTSTATEST_MASK (0x3 << 0)
+
+/* Used by PM_VPE_PWRSTCTRL */
+#define DRA7XX_VPE_BANK_ONSTATE_SHIFT 16
+#define DRA7XX_VPE_BANK_ONSTATE_WIDTH 0x2
+#define DRA7XX_VPE_BANK_ONSTATE_MASK (0x3 << 16)
+
+/* Used by PM_VPE_PWRSTCTRL */
+#define DRA7XX_VPE_BANK_RETSTATE_SHIFT 8
+#define DRA7XX_VPE_BANK_RETSTATE_WIDTH 0x1
+#define DRA7XX_VPE_BANK_RETSTATE_MASK (1 << 8)
+
+/* Used by PM_VPE_PWRSTST */
+#define DRA7XX_VPE_BANK_STATEST_SHIFT 4
+#define DRA7XX_VPE_BANK_STATEST_WIDTH 0x2
+#define DRA7XX_VPE_BANK_STATEST_MASK (0x3 << 4)
+
+/* Used by PRM_SRAM_COUNT */
+#define DRA7XX_VSETUPCNT_VALUE_SHIFT 8
+#define DRA7XX_VSETUPCNT_VALUE_WIDTH 0x8
+#define DRA7XX_VSETUPCNT_VALUE_MASK (0xff << 8)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_ADC_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_ADC_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_ADC_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_ADC_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_ADC_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_ADC_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_ADC_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_ADC_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_ADC_WKDEP */
+#define DRA7XX_WKUPDEP_ADC_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_ADC_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_ADC_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_DCAN1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_DCAN1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_DCAN1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_DCAN1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_DCAN1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_DCAN1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_DCAN1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_DCAN1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_DCAN1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_DCAN1_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_DCAN1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN1_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_DCAN2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_DCAN2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_DCAN2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_DCAN2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_DCAN2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_DCAN2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_DCAN2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_DCAN2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_DCAN2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_DCAN2_WKDEP */
+#define DRA7XX_WKUPDEP_DCAN2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_DCAN2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DCAN2_SDMA_MASK (1 << 3)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_DISPC_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_DSP1_MASK (1 << 2)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_DISPC_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_DSP2_MASK (1 << 5)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_DISPC_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_EVE1_MASK (1 << 6)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_DISPC_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_EVE2_MASK (1 << 7)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_DISPC_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_EVE3_MASK (1 << 8)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_DISPC_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_EVE4_MASK (1 << 9)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_DISPC_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_IPU1_MASK (1 << 4)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_DISPC_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_IPU2_MASK (1 << 1)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_DISPC_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_MPU_MASK (1 << 0)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DISPC_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_DSI1_A_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_DSP1_MASK (1 << 12)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_DSI1_A_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_DSP2_MASK (1 << 15)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_DSI1_A_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_EVE1_MASK (1 << 16)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_DSI1_A_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_EVE2_MASK (1 << 17)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_DSI1_A_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_EVE3_MASK (1 << 18)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_DSI1_A_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_EVE4_MASK (1 << 19)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_DSI1_A_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_IPU1_MASK (1 << 14)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_DSI1_A_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_IPU2_MASK (1 << 11)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 10)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_A_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 13)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_DSP1_SHIFT 22
+#define DRA7XX_WKUPDEP_DSI1_B_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_DSP1_MASK (1 << 22)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_DSP2_SHIFT 25
+#define DRA7XX_WKUPDEP_DSI1_B_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_DSP2_MASK (1 << 25)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_EVE1_SHIFT 26
+#define DRA7XX_WKUPDEP_DSI1_B_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_EVE1_MASK (1 << 26)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_EVE2_SHIFT 27
+#define DRA7XX_WKUPDEP_DSI1_B_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_EVE2_MASK (1 << 27)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_EVE3_SHIFT 28
+#define DRA7XX_WKUPDEP_DSI1_B_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_EVE3_MASK (1 << 28)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_EVE4_SHIFT 29
+#define DRA7XX_WKUPDEP_DSI1_B_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_EVE4_MASK (1 << 29)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_IPU1_SHIFT 24
+#define DRA7XX_WKUPDEP_DSI1_B_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_IPU1_MASK (1 << 24)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_IPU2_SHIFT 21
+#define DRA7XX_WKUPDEP_DSI1_B_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_IPU2_MASK (1 << 21)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_MPU_SHIFT 20
+#define DRA7XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 20)
+
+/* Used by PM_DSS_DSS_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_B_SDMA_SHIFT 23
+#define DRA7XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 23)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_DSI1_C_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_DSP1_MASK (1 << 12)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_DSI1_C_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_DSP2_MASK (1 << 15)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_DSI1_C_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_EVE1_MASK (1 << 16)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_DSI1_C_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_EVE2_MASK (1 << 17)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_DSI1_C_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_EVE3_MASK (1 << 18)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_DSI1_C_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_EVE4_MASK (1 << 19)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_DSI1_C_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_IPU1_MASK (1 << 14)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_DSI1_C_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_IPU2_MASK (1 << 11)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 10)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_DSI1_C_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 13)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_EVE1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_DSP1_MASK (1 << 2)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_EVE1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_DSP2_MASK (1 << 5)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_EVE1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_EVE2_MASK (1 << 7)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_EVE1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_EVE3_MASK (1 << 8)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_EVE1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_EVE4_MASK (1 << 9)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_EVE1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_IPU1_MASK (1 << 4)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_EVE1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_IPU2_MASK (1 << 1)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_EVE1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_MPU_MASK (1 << 0)
+
+/* Used by PM_EVE1_EVE1_WKDEP */
+#define DRA7XX_WKUPDEP_EVE1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_EVE1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE1_SDMA_MASK (1 << 3)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_EVE2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_DSP1_MASK (1 << 2)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_EVE2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_DSP2_MASK (1 << 5)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_EVE2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_EVE1_MASK (1 << 6)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_EVE2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_EVE3_MASK (1 << 8)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_EVE2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_EVE4_MASK (1 << 9)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_EVE2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_IPU1_MASK (1 << 4)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_EVE2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_IPU2_MASK (1 << 1)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_EVE2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_MPU_MASK (1 << 0)
+
+/* Used by PM_EVE2_EVE2_WKDEP */
+#define DRA7XX_WKUPDEP_EVE2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_EVE2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE2_SDMA_MASK (1 << 3)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_EVE3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_DSP1_MASK (1 << 2)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_EVE3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_DSP2_MASK (1 << 5)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_EVE3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_EVE1_MASK (1 << 6)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_EVE3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_EVE2_MASK (1 << 7)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_EVE3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_EVE4_MASK (1 << 9)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_EVE3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_IPU1_MASK (1 << 4)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_EVE3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_IPU2_MASK (1 << 1)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_EVE3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_MPU_MASK (1 << 0)
+
+/* Used by PM_EVE3_EVE3_WKDEP */
+#define DRA7XX_WKUPDEP_EVE3_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_EVE3_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE3_SDMA_MASK (1 << 3)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_EVE4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_DSP1_MASK (1 << 2)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_EVE4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_DSP2_MASK (1 << 5)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_EVE4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_EVE1_MASK (1 << 6)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_EVE4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_EVE2_MASK (1 << 7)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_EVE4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_EVE3_MASK (1 << 8)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_EVE4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_IPU1_MASK (1 << 4)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_EVE4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_IPU2_MASK (1 << 1)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_EVE4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_MPU_MASK (1 << 0)
+
+/* Used by PM_EVE4_EVE4_WKDEP */
+#define DRA7XX_WKUPDEP_EVE4_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_EVE4_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_EVE4_SDMA_MASK (1 << 3)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_WKUPAON_GPIO1_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO1_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO2_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO2_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO3_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO3_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO4_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO4_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO5_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO5_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO6_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO6_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO7_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO7_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_L4PER_GPIO8_WKDEP */
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_GPIO8_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP1_SHIFT 22
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP1_MASK (1 << 22)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP2_SHIFT 25
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIDMA_DSP2_MASK (1 << 25)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 23
+#define DRA7XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 23)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_DSS_DSS2_WKDEP */
+#define DRA7XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_I2C1_WKDEP */
+#define DRA7XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_I2C2_WKDEP */
+#define DRA7XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_I2C3_WKDEP */
+#define DRA7XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_I2C4_WKDEP */
+#define DRA7XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_I2C5_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_I2C5_WKDEP */
+#define DRA7XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_KBD_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_KBD_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_KBD_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_KBD_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_KBD_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_KBD_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_KBD_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_KBD_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_KBD_WKDEP */
+#define DRA7XX_WKUPDEP_KBD_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_KBD_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_KBD_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP1_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_MCASP1_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP2_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP2_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP3_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP3_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP4_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP4_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP4_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP5_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP5_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP5_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP6_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP6_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP6_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP7_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP7_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP7_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP1_MASK (1 << 12)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_DMA_DSP2_MASK (1 << 15)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_DMA_SDMA_SHIFT 13
+#define DRA7XX_WKUPDEP_MCASP8_DMA_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_DMA_SDMA_MASK (1 << 13)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_MCASP8_WKDEP */
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCASP8_IRQ_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCSPI1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCSPI1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCSPI1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCSPI1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCSPI1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCSPI1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCSPI1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCSPI1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI1_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCSPI2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCSPI2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCSPI2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCSPI2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCSPI2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCSPI2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCSPI2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCSPI2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI2_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCSPI3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCSPI3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCSPI3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCSPI3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCSPI3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCSPI3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCSPI3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCSPI3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI3_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MCSPI4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MCSPI4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MCSPI4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MCSPI4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MCSPI4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MCSPI4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MCSPI4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MCSPI4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MCSPI4_WKDEP */
+#define DRA7XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MMC1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MMC1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MMC1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MMC1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MMC1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MMC1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MMC1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MMC1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MMC1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_MMC1_WKDEP */
+#define DRA7XX_WKUPDEP_MMC1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MMC2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MMC2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MMC2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MMC2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MMC2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MMC2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MMC2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MMC2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MMC2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_MMC2_WKDEP */
+#define DRA7XX_WKUPDEP_MMC2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MMC3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MMC3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MMC3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MMC3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MMC3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MMC3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MMC3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MMC3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MMC3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MMC3_WKDEP */
+#define DRA7XX_WKUPDEP_MMC3_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_MMC4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_MMC4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_MMC4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_MMC4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_MMC4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_MMC4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_MMC4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_MMC4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_MMC4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_MMC4_WKDEP */
+#define DRA7XX_WKUPDEP_MMC4_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_OCMC_RAM1_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_OCMC_RAM1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM1_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_OCMC_RAM2_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_OCMC_RAM2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM2_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_OCMC_RAM3_WKDEP */
+#define DRA7XX_WKUPDEP_OCMC_RAM3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_OCMC_RAM3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_OCMC_RAM3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_QSPI_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_QSPI_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_QSPI_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_QSPI_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_QSPI_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_QSPI_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_QSPI_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_QSPI_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_QSPI_WKDEP */
+#define DRA7XX_WKUPDEP_QSPI_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_QSPI_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_QSPI_MPU_MASK (1 << 0)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP1_MASK (1 << 2)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_DSP2_MASK (1 << 5)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE1_MASK (1 << 6)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE2_MASK (1 << 7)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE3_MASK (1 << 8)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_EVE4_MASK (1 << 9)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU1_MASK (1 << 4)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_IPU2_MASK (1 << 1)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_RTC_IRQ1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ1_MPU_MASK (1 << 0)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP1_SHIFT 12
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP1_MASK (1 << 12)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP2_SHIFT 15
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_DSP2_MASK (1 << 15)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE1_SHIFT 16
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE1_MASK (1 << 16)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE2_SHIFT 17
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE2_MASK (1 << 17)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE3_SHIFT 18
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE3_MASK (1 << 18)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE4_SHIFT 19
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_EVE4_MASK (1 << 19)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU1_SHIFT 14
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU1_MASK (1 << 14)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU2_SHIFT 11
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_IPU2_MASK (1 << 11)
+
+/* Used by PM_RTC_RTCSS_WKDEP */
+#define DRA7XX_WKUPDEP_RTC_IRQ2_MPU_SHIFT 10
+#define DRA7XX_WKUPDEP_RTC_IRQ2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_RTC_IRQ2_MPU_MASK (1 << 10)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SATA_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SATA_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SATA_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SATA_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SATA_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SATA_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SATA_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SATA_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_SATA_WKDEP */
+#define DRA7XX_WKUPDEP_SATA_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SATA_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SATA_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_DSPEVE_SDMA_MASK (1 << 3)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_GPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_GPU_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_IVAHD_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_IVAHD_MPU_MASK (1 << 0)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP1_MASK (1 << 2)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_DSP2_MASK (1 << 5)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE1_MASK (1 << 6)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE2_MASK (1 << 7)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE3_MASK (1 << 8)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_EVE4_MASK (1 << 9)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU1_MASK (1 << 4)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_IPU2_MASK (1 << 1)
+
+/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER10_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER10_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER10_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER10_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER10_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER10_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER10_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER10_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER10_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER10_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER11_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER11_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER11_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER11_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER11_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER11_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER11_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER11_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER11_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER11_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER12_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER12_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER12_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER12_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER12_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER12_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER12_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER12_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_TIMER12_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER12_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER13_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER13_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER13_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER13_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER13_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER13_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER13_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER13_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER13_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER13_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER13_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER13_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER14_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER14_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER14_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER14_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER14_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER14_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER14_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER14_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER14_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER14_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER14_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER14_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER15_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER15_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER15_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER15_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER15_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER15_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER15_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER15_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER15_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER15_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER15_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER15_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER16_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER16_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER16_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER16_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER16_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER16_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER16_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER16_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER16_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER16_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER16_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER16_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER3_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER4_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER5_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER5_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER5_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER5_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER5_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER5_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER5_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER5_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_TIMER5_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER5_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER6_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER6_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER6_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER6_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER6_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER6_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER6_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER6_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_TIMER6_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER6_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER7_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER7_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER7_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER7_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER7_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER7_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER7_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER7_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_TIMER7_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER7_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER8_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER8_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER8_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER8_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER8_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER8_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER8_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER8_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_TIMER8_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER8_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TIMER9_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TIMER9_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TIMER9_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TIMER9_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TIMER9_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TIMER9_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TIMER9_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TIMER9_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_TIMER9_WKDEP */
+#define DRA7XX_WKUPDEP_TIMER9_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TPCC_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TPCC_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TPCC_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TPCC_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TPCC_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TPCC_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TPCC_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TPCC_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_TPCC_WKDEP */
+#define DRA7XX_WKUPDEP_TPCC_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TPCC_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPCC_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TPTC1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TPTC1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TPTC1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TPTC1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TPTC1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TPTC1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TPTC1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TPTC1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_TPTC1_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TPTC1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC1_MPU_MASK (1 << 0)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_TPTC2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_TPTC2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_TPTC2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_TPTC2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_TPTC2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_TPTC2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_TPTC2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_TPTC2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3MAIN1_TPTC2_WKDEP */
+#define DRA7XX_WKUPDEP_TPTC2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_TPTC2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_TPTC2_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART10_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART10_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART10_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART10_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART10_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART10_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART10_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART10_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART10_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_UART10_WKDEP */
+#define DRA7XX_WKUPDEP_UART10_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART10_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART10_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART1_WKDEP */
+#define DRA7XX_WKUPDEP_UART1_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART1_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART1_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART2_WKDEP */
+#define DRA7XX_WKUPDEP_UART2_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART2_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART2_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART3_WKDEP */
+#define DRA7XX_WKUPDEP_UART3_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART3_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART3_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART4_WKDEP */
+#define DRA7XX_WKUPDEP_UART4_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART4_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART4_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART5_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART5_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART5_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART5_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART5_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART5_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART5_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART5_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART5_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER_UART5_WKDEP */
+#define DRA7XX_WKUPDEP_UART5_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART5_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART5_SDMA_MASK (1 << 3)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART6_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_DSP1_MASK (1 << 2)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART6_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_DSP2_MASK (1 << 5)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART6_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_EVE1_MASK (1 << 6)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART6_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_EVE2_MASK (1 << 7)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART6_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_EVE3_MASK (1 << 8)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART6_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_EVE4_MASK (1 << 9)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART6_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_IPU1_MASK (1 << 4)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART6_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_IPU2_MASK (1 << 1)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART6_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_MPU_MASK (1 << 0)
+
+/* Used by PM_IPU_UART6_WKDEP */
+#define DRA7XX_WKUPDEP_UART6_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART6_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART6_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART7_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART7_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART7_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART7_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART7_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART7_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART7_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART7_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART7_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_UART7_WKDEP */
+#define DRA7XX_WKUPDEP_UART7_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART7_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART7_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART8_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART8_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART8_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART8_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART8_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART8_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART8_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART8_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART8_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_UART8_WKDEP */
+#define DRA7XX_WKUPDEP_UART8_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART8_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART8_SDMA_MASK (1 << 3)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_UART9_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_DSP1_MASK (1 << 2)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_UART9_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_DSP2_MASK (1 << 5)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_UART9_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_EVE1_MASK (1 << 6)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_UART9_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_EVE2_MASK (1 << 7)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_UART9_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_EVE3_MASK (1 << 8)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_UART9_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_EVE4_MASK (1 << 9)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_UART9_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_IPU1_MASK (1 << 4)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_UART9_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_IPU2_MASK (1 << 1)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_UART9_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_MPU_MASK (1 << 0)
+
+/* Used by PM_L4PER2_UART9_WKDEP */
+#define DRA7XX_WKUPDEP_UART9_SDMA_SHIFT 3
+#define DRA7XX_WKUPDEP_UART9_SDMA_WIDTH 0x1
+#define DRA7XX_WKUPDEP_UART9_SDMA_MASK (1 << 3)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS1_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS1_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS2_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS2_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS3_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS3_MPU_MASK (1 << 0)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP1_MASK (1 << 2)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_DSP2_MASK (1 << 5)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE1_MASK (1 << 6)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE2_MASK (1 << 7)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE3_MASK (1 << 8)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_EVE4_MASK (1 << 9)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU1_MASK (1 << 4)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_IPU2_MASK (1 << 1)
+
+/* Used by PM_L3INIT_USB_OTG_SS4_WKDEP */
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_USB_OTG_SS4_MPU_MASK (1 << 0)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_VIP1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_DSP1_MASK (1 << 2)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_VIP1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_DSP2_MASK (1 << 5)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_VIP1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_EVE1_MASK (1 << 6)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_VIP1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_EVE2_MASK (1 << 7)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_VIP1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_EVE3_MASK (1 << 8)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_VIP1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_EVE4_MASK (1 << 9)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_VIP1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_IPU1_MASK (1 << 4)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_VIP1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_IPU2_MASK (1 << 1)
+
+/* Used by PM_CAM_VIP1_WKDEP */
+#define DRA7XX_WKUPDEP_VIP1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_VIP1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP1_MPU_MASK (1 << 0)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_VIP2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_DSP1_MASK (1 << 2)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_VIP2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_DSP2_MASK (1 << 5)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_VIP2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_EVE1_MASK (1 << 6)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_VIP2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_EVE2_MASK (1 << 7)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_VIP2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_EVE3_MASK (1 << 8)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_VIP2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_EVE4_MASK (1 << 9)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_VIP2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_IPU1_MASK (1 << 4)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_VIP2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_IPU2_MASK (1 << 1)
+
+/* Used by PM_CAM_VIP2_WKDEP */
+#define DRA7XX_WKUPDEP_VIP2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_VIP2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP2_MPU_MASK (1 << 0)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_VIP3_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_DSP1_MASK (1 << 2)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_VIP3_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_DSP2_MASK (1 << 5)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_VIP3_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_EVE1_MASK (1 << 6)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_VIP3_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_EVE2_MASK (1 << 7)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_VIP3_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_EVE3_MASK (1 << 8)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_VIP3_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_EVE4_MASK (1 << 9)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_VIP3_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_IPU1_MASK (1 << 4)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_VIP3_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_IPU2_MASK (1 << 1)
+
+/* Used by PM_CAM_VIP3_WKDEP */
+#define DRA7XX_WKUPDEP_VIP3_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_VIP3_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VIP3_MPU_MASK (1 << 0)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_VPE_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_DSP1_MASK (1 << 2)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_VPE_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_DSP2_MASK (1 << 5)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_VPE_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_EVE1_MASK (1 << 6)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_VPE_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_EVE2_MASK (1 << 7)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_VPE_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_EVE3_MASK (1 << 8)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_VPE_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_EVE4_MASK (1 << 9)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_VPE_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_IPU1_MASK (1 << 4)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_VPE_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_IPU2_MASK (1 << 1)
+
+/* Used by PM_VPE_VPE_WKDEP */
+#define DRA7XX_WKUPDEP_VPE_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_VPE_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_VPE_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_WD_TIMER1_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER1_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_WD_TIMER1_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER1_MPU_MASK (1 << 0)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP1_SHIFT 2
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP1_MASK (1 << 2)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP2_SHIFT 5
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_DSP2_MASK (1 << 5)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE1_SHIFT 6
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE1_MASK (1 << 6)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE2_SHIFT 7
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE2_MASK (1 << 7)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE3_SHIFT 8
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE3_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE3_MASK (1 << 8)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE4_SHIFT 9
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE4_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_EVE4_MASK (1 << 9)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU1_SHIFT 4
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU1_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU1_MASK (1 << 4)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU2_SHIFT 1
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU2_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_IPU2_MASK (1 << 1)
+
+/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
+#define DRA7XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0
+#define DRA7XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1
+#define DRA7XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_WUCLK_CTRL_SHIFT 8
+#define DRA7XX_WUCLK_CTRL_WIDTH 0x1
+#define DRA7XX_WUCLK_CTRL_MASK (1 << 8)
+
+/* Used by PRM_IO_PMCTRL */
+#define DRA7XX_WUCLK_STATUS_SHIFT 9
+#define DRA7XX_WUCLK_STATUS_WIDTH 0x1
+#define DRA7XX_WUCLK_STATUS_MASK (1 << 9)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_X_MAJOR_SHIFT 8
+#define DRA7XX_X_MAJOR_WIDTH 0x3
+#define DRA7XX_X_MAJOR_MASK (0x7 << 8)
+
+/* Used by REVISION_PRM */
+#define DRA7XX_Y_MINOR_SHIFT 0
+#define DRA7XX_Y_MINOR_WIDTH 0x6
+#define DRA7XX_Y_MINOR_MASK (0x3f << 0)
+#endif
index cb24b26f36e9d256090e82541a4e8ba3c67123a1..637b38a89e0dcb5510f4ceebcadb914e1ffa7cdc 100644 (file)
return 0;
}
+static int omap4_check_vcvp(void)
+{
+ if (soc_is_dra7xx())
+ return 0;
+
+ /* All others have VC/VP */
+ return 1;
+}
+
struct pwrdm_ops omap4_pwrdm_operations = {
.pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
.pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
.pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
.pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
.pwrdm_wait_transition = omap4_pwrdm_wait_transition,
+ .pwrdm_has_voltdm = omap4_check_vcvp,
};
/*
int __init omap44xx_prm_init(void)
{
- if (!cpu_is_omap44xx() && !soc_is_omap54xx())
+ if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
return 0;
return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
--- /dev/null
@@ -0,0 +1,690 @@
+/*
+ * DRA7xx PRM instance offset macros
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Paul Walmsley (paul@pwsan.com)
+ * Rajendra Nayak (rnayak@ti.com)
+ * Benoit Cousson (b-cousson@ti.com)
+ *
+ * This file is automatically generated from the OMAP hardware databases.
+ * We respectfully ask that any modifications to this file be coordinated
+ * with the public linux-omap@vger.kernel.org mailing list and the
+ * authors above to ensure that the autogeneration scripts are kept
+ * up-to-date with the file contents.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+#define DRA7XX_PRM_BASE 0x4ae06000
+
+#define DRA7XX_PRM_REGADDR(inst, reg) \
+ OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
+#define DRA7XX_PRM_CKGEN_INST 0x0100
+#define DRA7XX_PRM_MPU_INST 0x0300
+#define DRA7XX_PRM_DSP1_INST 0x0400
+#define DRA7XX_PRM_IPU_INST 0x0500
+#define DRA7XX_PRM_COREAON_INST 0x0628
+#define DRA7XX_PRM_CORE_INST 0x0700
+#define DRA7XX_PRM_IVA_INST 0x0f00
+#define DRA7XX_PRM_CAM_INST 0x1000
+#define DRA7XX_PRM_DSS_INST 0x1100
+#define DRA7XX_PRM_GPU_INST 0x1200
+#define DRA7XX_PRM_L3INIT_INST 0x1300
+#define DRA7XX_PRM_L4PER_INST 0x1400
+#define DRA7XX_PRM_CUSTEFUSE_INST 0x1600
+#define DRA7XX_PRM_WKUPAON_INST 0x1724
+#define DRA7XX_PRM_WKUPAON_CM_INST 0x1800
+#define DRA7XX_PRM_EMU_INST 0x1900
+#define DRA7XX_PRM_EMU_CM_INST 0x1a00
+#define DRA7XX_PRM_DSP2_INST 0x1b00
+#define DRA7XX_PRM_EVE1_INST 0x1b40
+#define DRA7XX_PRM_EVE2_INST 0x1b80
+#define DRA7XX_PRM_EVE3_INST 0x1bc0
+#define DRA7XX_PRM_EVE4_INST 0x1c00
+#define DRA7XX_PRM_RTC_INST 0x1c60
+#define DRA7XX_PRM_VPE_INST 0x1c80
+#define DRA7XX_PRM_DEVICE_INST 0x1d00
+#define DRA7XX_PRM_INSTR_INST 0x1f00
+
+/* PRM clockdomain register offsets (from instance start) */
+#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
+#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define DRA7XX_REVISION_PRM_OFFSET 0x0000
+#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
+#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
+#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
+#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
+#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020
+#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028
+#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030
+#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038
+#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040)
+#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044
+#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048
+#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c
+#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050
+#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054
+#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058
+#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c
+#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060
+#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064
+#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068
+#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c
+#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070
+#define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4
+#define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8
+#define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec
+#define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4
+
+/* PRM.CKGEN_PRM register offsets */
+#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000
+#define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
+#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
+#define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008)
+#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
+#define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c)
+#define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010
+#define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
+#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014
+#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014)
+#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018
+#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018)
+#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c
+#define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c)
+#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020
+#define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020)
+#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024
+#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024)
+#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028
+#define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028)
+#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c
+#define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c)
+#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030
+#define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030)
+#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034
+#define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034)
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038)
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040)
+#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044
+#define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044)
+#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048
+#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048)
+#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c
+#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c)
+#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050
+#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050)
+#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054
+#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054)
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058)
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c)
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060
+#define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060)
+#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064
+#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064)
+#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068
+#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068)
+#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c
+#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c)
+#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070
+#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070)
+#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074
+#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074)
+#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078
+#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078)
+#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080
+#define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080)
+#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084
+#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084)
+#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088
+#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088)
+#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c
+#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c)
+#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090
+#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090)
+#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094
+#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094)
+#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098
+#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098)
+#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c
+#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c)
+#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0
+#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0)
+#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4
+#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4)
+#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8
+#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8)
+#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac
+#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac)
+#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0
+#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0)
+#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4
+#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4)
+#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8
+#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8)
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc
+#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc)
+#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0
+#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0)
+#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4
+#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4)
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8
+#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8)
+#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc
+#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc)
+#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0
+#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0)
+#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4
+#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4)
+#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8
+#define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8)
+#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc
+#define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc)
+#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0
+#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)
+
+/* PRM.MPU_PRM register offsets */
+#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
+
+/* PRM.DSP1_PRM register offsets */
+#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024
+
+/* PRM.IPU_PRM register offsets */
+#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024
+#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054
+#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058
+#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c
+#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060
+#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064
+#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068
+#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c
+#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070
+#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074
+#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078
+#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c
+#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080
+#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084
+
+/* PRM.COREAON_PRM register offsets */
+#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000
+#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004
+#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010
+#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014
+#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030
+#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034
+#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040
+#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044
+#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054
+#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084
+#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094
+#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4
+#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4
+
+/* PRM.CORE_PRM register offsets */
+#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
+#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c
+#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c
+#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060
+#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064
+#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c
+#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070
+#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074
+#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078
+#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c
+#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080
+#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084
+#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c
+#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094
+#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c
+#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4
+#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac
+#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4
+#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc
+#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4
+#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc
+#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210
+#define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214
+#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224
+#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
+#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
+#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
+#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
+#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
+#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
+#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524
+#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
+#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
+#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634
+#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
+#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
+#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c
+#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654
+#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c
+#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664
+#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c
+#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674
+#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c
+#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684
+#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c
+#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694
+#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c
+#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4
+#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc
+#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4
+#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724
+#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
+#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
+
+/* PRM.IVA_PRM register offsets */
+#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
+#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
+
+/* PRM.CAM_PRM register offsets */
+#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004
+#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024
+#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028
+#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c
+#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030
+#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034
+#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c
+#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044
+#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c
+
+/* PRM.DSS_PRM register offsets */
+#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004
+#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
+#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028
+#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
+#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c
+
+/* PRM.GPU_PRM register offsets */
+#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
+
+/* PRM.L3INIT_PRM register offsets */
+#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
+#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
+#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
+#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
+#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
+#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040
+#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044
+#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048
+#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c
+#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054
+#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c
+#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
+#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
+#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
+#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
+#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
+#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
+#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0
+#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4
+
+/* PRM.L4PER_PRM register offsets */
+#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c
+#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014
+#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c
+#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024
+#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028
+#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c
+#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030
+#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034
+#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038
+#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c
+#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040
+#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044
+#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048
+#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c
+#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050
+#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054
+#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
+#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
+#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
+#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
+#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
+#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
+#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
+#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
+#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
+#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
+#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
+#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
+#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094
+#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c
+#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
+#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
+#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
+#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
+#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
+#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
+#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
+#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
+#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0
+#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4
+#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8
+#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc
+#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0
+#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4
+#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8
+#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc
+#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
+#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
+#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
+#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
+#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
+#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
+#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
+#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
+#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110
+#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114
+#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118
+#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c
+#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120
+#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124
+#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128
+#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c
+#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130
+#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134
+#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138
+#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c
+#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
+#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
+#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
+#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
+#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
+#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
+#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
+#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
+#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160
+#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164
+#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168
+#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c
+#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170
+#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174
+#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178
+#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c
+#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180
+#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184
+#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188
+#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c
+#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190
+#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194
+#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198
+#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c
+#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
+#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
+#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
+#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc
+#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
+#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
+#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0
+#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4
+#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc
+#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0
+#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4
+#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8
+#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec
+#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0
+#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4
+#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc
+
+/* PRM.CUSTEFUSE_PRM register offsets */
+#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
+
+/* PRM.WKUPAON_PRM register offsets */
+#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000
+#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004
+#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008
+#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c
+#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010
+#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014
+#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018
+#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c
+#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020
+#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024
+#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028
+#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030
+#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040
+#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054
+#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058
+#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c
+#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060
+#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064
+#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068
+#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c
+#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0
+#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8
+#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0
+#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8
+
+/* PRM.WKUPAON_CM register offsets */
+#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
+#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020)
+#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
+#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028)
+#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
+#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030)
+#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
+#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038)
+#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
+#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040)
+#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
+#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048)
+#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
+#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050)
+#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
+#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060)
+#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
+#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078)
+#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080
+#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080)
+#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088
+#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088)
+#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
+#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090)
+#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
+#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098)
+#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0
+#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0)
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8
+#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8)
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0)
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8
+#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8)
+
+/* PRM.EMU_PRM register offsets */
+#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
+
+/* PRM.EMU_CM register offsets */
+#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
+#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004
+#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004)
+#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
+#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c
+#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c)
+
+/* PRM.DSP2_PRM register offsets */
+#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014
+#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024
+
+/* PRM.EVE1_PRM register offsets */
+#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014
+#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024
+
+/* PRM.EVE2_PRM register offsets */
+#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014
+#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024
+
+/* PRM.EVE3_PRM register offsets */
+#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014
+#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024
+
+/* PRM.EVE4_PRM register offsets */
+#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004
+#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010
+#define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014
+#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024
+
+/* PRM.RTC_PRM register offsets */
+#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000
+#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004
+
+/* PRM.VPE_PRM register offsets */
+#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000
+#define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004
+#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020
+#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024
+
+/* PRM.DEVICE_PRM register offsets */
+#define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000
+#define DRA7XX_PRM_RSTST_OFFSET 0x0004
+#define DRA7XX_PRM_RSTTIME_OFFSET 0x0008
+#define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c
+#define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010
+#define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014
+#define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018
+#define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c
+#define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020
+#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
+#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
+#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
+#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
+#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
+#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
+#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
+#define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc
+#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
+#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
+#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
+#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
+#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
+#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4
+#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8
+#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
+#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
+#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4
+#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8
+#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
+#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
+#define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
+#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
+#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
+#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
+#define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110
+#define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114
+#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118
+#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c
+#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120
+#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124
+#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128
+#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c
+#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130
+#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134
+
+/* Function prototypes */
+#ifndef __ASSEMBLER__
+
+extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
+extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
+extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+
+/* PRM interrupt-related functions */
+extern void omap44xx_prm_read_pending_irqs(unsigned long *events);
+extern void omap44xx_prm_ocp_barrier(void);
+extern void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
+extern void omap44xx_prm_restore_irqen(u32 *saved_mask);
+
+#endif
+#endif
index 430fb1db14c255e1af193333c4bd0116399decc9..66a994bd006794bce7b35361acd204ef16719f0c 100644 (file)
#include "prcm-common.h"
#include "prm44xx.h"
#include "prm54xx.h"
+#include "prm7xx.h"
#include "prminst44xx.h"
#include "prm-regbits-44xx.h"
#include "prcm44xx.h"
{
u32 v;
s16 dev_inst = cpu_is_omap44xx() ? OMAP4430_PRM_DEVICE_INST :
- OMAP54XX_PRM_DEVICE_INST;
+ (soc_is_omap54xx() ?
+ OMAP54XX_PRM_DEVICE_INST :
+ DRA7XX_PRM_DEVICE_INST);
v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
dev_inst,
index 661af357b6b6f68ae3f585a2ba2e6421c4361998..872401c5cf08708e4caeb522b16d4145b5817a87 100644 (file)
* Written by Tony Lindgren <tony.lindgren@nokia.com>
*
* Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
+ * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
# endif
#endif
+#ifdef CONFIG_SOC_DRA7XX
+# ifdef OMAP_NAME
+# undef MULTI_OMAP2
+# define MULTI_OMAP2
+# else
+# define OMAP_NAME DRA7XX
+# endif
+#endif
/*
* Omap device type i.e. EMU/HS/TST/GP/BAD
*/
* cpu_is_omap446x(): True for OMAP4460
* cpu_is_omap447x(): True for OMAP4470
* soc_is_omap543x(): True for OMAP5430, OMAP5432
+ * soc_is_dra75x(): True for DRA752
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
return (GET_TI_CLASS == (id)) ? 1 : 0; \
}
+#define IS_DRA_CLASS(class, id) \
+static inline int is_dra ##class(void) \
+{ \
+ return (GET_OMAP_CLASS == (id)) ? 1 : 0; \
+}
+
#define GET_OMAP_SUBCLASS ((omap_rev() >> 20) & 0x0fff)
#define IS_OMAP_SUBCLASS(subclass, id) \
return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
}
+#define IS_DRA_SUBCLASS(subclass, id) \
+static inline int is_dra ##subclass(void) \
+{ \
+ return (GET_OMAP_SUBCLASS == (id)) ? 1 : 0; \
+}
+
IS_OMAP_CLASS(24xx, 0x24)
IS_OMAP_CLASS(34xx, 0x34)
IS_OMAP_CLASS(44xx, 0x44)
IS_AM_CLASS(35xx, 0x35)
IS_OMAP_CLASS(54xx, 0x54)
+
+IS_DRA_CLASS(7xx, 0x7)
+
IS_AM_CLASS(33xx, 0x33)
IS_TI_CLASS(81xx, 0x81)
IS_OMAP_SUBCLASS(447x, 0x447)
IS_OMAP_SUBCLASS(543x, 0x543)
+IS_DRA_SUBCLASS(75x, 0x75)
+IS_DRA_SUBCLASS(74x, 0x74)
+
IS_TI_SUBCLASS(816x, 0x816)
IS_TI_SUBCLASS(814x, 0x814)
IS_AM_SUBCLASS(335x, 0x335)
#define cpu_is_omap447x() 0
#define soc_is_omap54xx() 0
#define soc_is_omap543x() 0
+#define soc_is_dra7xx() 0
+#define soc_is_dra75x() 0
#if defined(MULTI_OMAP2)
# if defined(CONFIG_ARCH_OMAP2)
# define soc_is_omap543x() is_omap543x()
#endif
+# if defined(CONFIG_SOC_DRA7XX)
+# undef soc_is_dra7xx
+# undef soc_is_dra75x
+# define soc_is_dra7xx() is_dra7xx()
+# define soc_is_dra75x() is_dra75x()
+#endif
+
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024
#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
#define OMAP5432_REV_ES1_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x10 << 8))
#define OMAP5432_REV_ES2_0 (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
+#define DRA7XX_CLASS 0x07000007
+#define DRA752_REV_ES1_0 (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
+
void omap2xxx_check_revision(void);
void omap3xxx_check_revision(void);
void omap4xxx_check_revision(void);
void ti81xx_check_features(void);
void am33xx_check_features(void);
void omap4xxx_check_features(void);
+void dra7xx_check_revision(void);
/*
* Runtime detection of OMAP3 features
index 6c50e4c7fca3b521a03af718c884663283a6b20e..8d40e8eb3bdaa3fd7131116b5611b47f4c82bcda 100644 (file)
omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */
omap_sram_size -= OMAP5_SRAM_HS_RESERVE;
omap_sram_start += OMAP5_SRAM_HS_RESERVE;
+ } else if (soc_is_dra7xx()) {
+ omap_sram_start = OMAP4_SRAM_START_PA;
+ omap_sram_size = DRA7XX_SRAM_SIZE; /* 512KB */
+ /*
+ * Fix me:
+ * The reservation size might change based on
+ * the PPA requirements.
+ */
+ omap_sram_size -= OMAP5_SRAM_HS_RESERVE;
+ omap_sram_start += OMAP5_SRAM_HS_RESERVE;
} else {
omap_sram_start = OMAP2_SRAM_PUB_PA;
omap_sram_size = 0x800; /* 2K */
omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */
omap_sram_size -= OMAP5_SRAM_GP_RESERVE;
omap_sram_start += OMAP5_SRAM_GP_RESERVE;
+ } else if (soc_is_dra7xx()) {
+ omap_sram_start = OMAP4_SRAM_START_PA;
+ omap_sram_size = DRA7XX_SRAM_SIZE; /* 512KB */
+ omap_sram_size -= OMAP5_SRAM_GP_RESERVE;
+ omap_sram_start += OMAP5_SRAM_GP_RESERVE;
} else {
omap_sram_start = OMAP2_SRAM_PA;
if (cpu_is_omap242x())
index 6476c38b3da93e792994d03ff9aa661e6aa75343..e19ec2ee2f5d3ef8aac9933d0903443b30c9be2e 100644 (file)
#define OMAP4_SRAM_SIZE (SZ_64K - SZ_8K)
/* OMAP5 has 128K */
#define OMAP5_SRAM_SIZE SZ_128K
+
+/* DRA7XX has 512K */
+#define DRA7XX_SRAM_SIZE SZ_512K
+
/* 16K GP, 52K HS(default) for secure world */
#define OMAP4_SRAM_GP_RESERVE SZ_16K
#ifdef CONFIG_OMAP4_HS_SECURE_SRAM_SIZE
index 286e18661487a7fa460d869ffb8ad70b7299294c..c6e1adc4681203fb7b8baafdc3327287bccf4667 100644 (file)
OMAP_SYS_TIMER(4, local);
#endif /* CONFIG_ARCH_OMAP4 */
-#ifdef CONFIG_SOC_OMAP5
+#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
2, OMAP5_MPU_SOURCE);
static void __init omap5_realtime_timer_init(void)
index 23d429bbf73b708c083b12530ce52d2d64e8bc1c..5d6975084fb862672893bc36ade9eefb4d377333 100644 (file)
select TI_PRIV_EDMA
select USE_OF
help
- "Systems based on OMAP2, OMAP3, OMAP4 or OMAP5"
+ "Systems based on OMAP2, OMAP3, OMAP4, OMAP5 or DRA7XX"
endchoice
This timer saves power compared to the OMAP_MPU_TIMER, and has
support for no tick during idle. The 32KHz timer provides less
intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
- currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
+ currently only available for OMAP16XX, 24XX, 34XX, OMAP4/5 and DRA7XX.
On OMAP2PLUS this value is only used for CONFIG_HZ and
CLOCK_TICK_RATE compile time calculation.
index dae0667032531a1570012ab4cf994abc66778428..ef4fbc4b0075390572fa3ee3758f56ccc9350951 100644 (file)
cpu_dev = &pdev->dev;
cpu_dev->of_node = np;
+ cpu_reg = devm_regulator_get(cpu_dev, "cpu0");
+ if (IS_ERR(cpu_reg)) {
+ /*
+ * If cpu0 regulator supply node is present, but regulator is
+ * not yet registered, we should try defering probe.
+ */
+ if (PTR_ERR(cpu_reg) == -EPROBE_DEFER) {
+ dev_err(cpu_dev, "cpu0 regulator not ready, retry\n");
+ return -EPROBE_DEFER;
+ }
+ pr_err("failed to get cpu0 regulator: %ld\n", PTR_ERR(cpu_reg));
+ cpu_reg = NULL;
+ }
+
cpu_clk = devm_clk_get(cpu_dev, NULL);
if (IS_ERR(cpu_clk)) {
ret = PTR_ERR(cpu_clk);
goto out_put_node;
}
- cpu_reg = devm_regulator_get(cpu_dev, "cpu0");
- if (IS_ERR(cpu_reg)) {
- pr_warn("failed to get cpu0 regulator\n");
- cpu_reg = NULL;
- }
-
ret = of_init_opp_table(cpu_dev);
if (ret) {
pr_err("failed to init OPP table: %d\n", ret);
diff --git a/drivers/mfd/palmas.c b/drivers/mfd/palmas.c
index b077bedda03ef18d211c6d30446ac6fc1679d61d..ddaad028d5ef84bddb1fba9cabfe21b44342736f 100644 (file)
--- a/drivers/mfd/palmas.c
+++ b/drivers/mfd/palmas.c
PALMAS_USB_ID,
};
+static struct resource palmas_rtc_resources[] = {
+ {
+ .start = PALMAS_RTC_ALARM_IRQ,
+ .end = PALMAS_RTC_ALARM_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
static const struct mfd_cell palmas_children[] = {
{
.name = "palmas-pmic",
{
.name = "palmas-rtc",
.id = PALMAS_RTC_ID,
+ .resources = &palmas_rtc_resources[0],
+ .num_resources = ARRAY_SIZE(palmas_rtc_resources),
},
{
.name = "palmas-pwrbutton",
}
};
+static const struct mfd_cell tps659038_children[] = {
+ {
+ .name = "tps659038-pmic",
+ .id = PALMAS_PMIC_ID,
+ },
+ {
+ .name = "tps659038-gpio",
+ .id = PALMAS_GPIO_ID,
+ },
+ {
+ .name = "tps659038-leds",
+ .id = PALMAS_LEDS_ID,
+ },
+ {
+ .name = "tps659038-wdt",
+ .id = PALMAS_WDT_ID,
+ },
+ {
+ .name = "tps659038-rtc",
+ .id = PALMAS_RTC_ID,
+ },
+ {
+ .name = "tps659038-pwrbutton",
+ .id = PALMAS_PWRBUTTON_ID,
+ },
+ {
+ .name = "tps659038-gpadc",
+ .id = PALMAS_GPADC_ID,
+ },
+ {
+ .name = "tps659038-resource",
+ .id = PALMAS_RESOURCE_ID,
+ },
+ {
+ .name = "tps659038-clk",
+ .id = PALMAS_CLK_ID,
+ },
+ {
+ .name = "tps659038-pwm",
+ .id = PALMAS_PWM_ID,
+ }
+};
+
static const struct regmap_config palmas_regmap_config[PALMAS_NUM_CLIENTS] = {
{
.reg_bits = 8,
return ret;
}
+static struct palmas_pmic_data palmas_data = {
+ .irq_chip = &palmas_irq_chip,
+ .regmap_config = palmas_regmap_config,
+ .mfd_cell = palmas_children,
+ .id = TWL6035,
+ .has_usb = 1,
+};
+
+static struct palmas_pmic_data tps659038_data = {
+ .irq_chip = &palmas_irq_chip,
+ .regmap_config = palmas_regmap_config,
+ .mfd_cell = tps659038_children,
+ .id = TPS659038,
+ .has_usb = 0,
+};
+
+static const struct of_device_id of_palmas_match_tbl[] = {
+ {
+ .compatible = "ti,palmas",
+ .data = &palmas_data,
+ },
+ {
+ .compatible = "ti,tps659038",
+ .data = &tps659038_data,
+ },
+ { },
+};
+
static int palmas_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
unsigned int reg, addr;
int slave;
struct mfd_cell *children;
+ const struct of_device_id *match;
+ const struct palmas_pmic_data *pmic_data;
pdata = dev_get_platdata(&i2c->dev);
i2c_set_clientdata(i2c, palmas);
palmas->dev = &i2c->dev;
- palmas->id = id->driver_data;
+ palmas->palmas_id = id->driver_data;
palmas->irq = i2c->irq;
+ match = of_match_device(of_match_ptr(of_palmas_match_tbl), &i2c->dev);
+
+ if (match) {
+ pmic_data = match->data;
+ palmas->palmas_id = pmic_data->id;
+ } else {
+ return -ENODATA;
+ }
+
for (i = 0; i < PALMAS_NUM_CLIENTS; i++) {
if (i == 0)
palmas->i2c_clients[i] = i2c;
}
}
palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i],
- &palmas_regmap_config[i]);
+ pmic_data->regmap_config + i);
if (IS_ERR(palmas->regmap[i])) {
ret = PTR_ERR(palmas->regmap[i]);
dev_err(palmas->dev,
}
}
- /* Change IRQ into clear on read mode for efficiency */
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL);
- reg = PALMAS_INT_CTRL_INT_CLEAR;
+ /* Avoid irq requesting for TOS659038 as the IRQ line
+ is only connected to a test point */
+ if (palmas->palmas_id != TPS659038) {
+ /* Change IRQ into clear on read mode for efficiency */
+ slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE);
+ addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE,
+ PALMAS_INT_CTRL);
+ reg = PALMAS_INT_CTRL_INT_CLEAR;
- regmap_write(palmas->regmap[slave], addr, reg);
+ regmap_write(palmas->regmap[slave], addr, reg);
- ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
- IRQF_ONESHOT, 0, &palmas_irq_chip,
- &palmas->irq_data);
- if (ret < 0)
- goto err;
+ ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq,
+ IRQF_ONESHOT, 0, pmic_data->irq_chip,
+ &palmas->irq_data);
+ if (ret < 0)
+ goto err;
+ }
slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE);
addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE,
return ret;
}
+ /*
+ * For now all PMICs belonging to palmas family are assumed to get the
+ * same childern as PALMAS
+ */
children = kmemdup(palmas_children, sizeof(palmas_children),
GFP_KERNEL);
if (!children) {
children[PALMAS_RESOURCE_ID].pdata_size =
sizeof(*pdata->resource_pdata);
- children[PALMAS_USB_ID].platform_data = pdata->usb_pdata;
- children[PALMAS_USB_ID].pdata_size = sizeof(*pdata->usb_pdata);
+ /* TPS659038 does not have USB */
+ if (pmic_data->has_usb) {
+ children[PALMAS_USB_ID].platform_data = pdata->usb_pdata;
+ children[PALMAS_USB_ID].pdata_size = sizeof(*pdata->usb_pdata);
+ }
children[PALMAS_CLK_ID].platform_data = pdata->clk_pdata;
children[PALMAS_CLK_ID].pdata_size = sizeof(*pdata->clk_pdata);
ret = mfd_add_devices(palmas->dev, -1,
children, ARRAY_SIZE(palmas_children),
- NULL, regmap_irq_chip_get_base(palmas->irq_data),
- NULL);
+ NULL, 0,
+ regmap_irq_get_domain(palmas->irq_data));
kfree(children);
}
static const struct i2c_device_id palmas_i2c_id[] = {
- { "palmas", },
- { "twl6035", },
- { "twl6037", },
- { "tps65913", },
+ { "palmas", TWL6035},
+ { "twl6035", TWL6035},
+ { "twl6037", TWL6037},
+ { "tps65913", TPS65913},
+ { "tps659038", TPS659038},
{ /* end */ }
};
MODULE_DEVICE_TABLE(i2c, palmas_i2c_id);
-static struct of_device_id of_palmas_match_tbl[] = {
- { .compatible = "ti,palmas", },
- { /* end */ }
-};
-
static struct i2c_driver palmas_i2c_driver = {
.driver = {
.name = "palmas",
index 551a22b075387a0641d37ff9dc1a34e25b65ee9d..acfd69f7e719f1ce3dd7df118843f64839eff84b 100644 (file)
This driver provides support for the voltage regulators on the
AS3711 PMIC
+config REGULATOR_TIAVSCLASS0
+ tristate "Adaptive Voltage Scaling class 0 support for TI SoCs"
+ depends on ARCH_OMAP2PLUS
+ help
+ AVS is a power management technique which finely controls the
+ operating voltage of a device in order to optimize (i.e. reduce)
+ its power consumption.
+ At a given operating point, the voltage is adapted depending on
+ static factors (chip manufacturing process) and this adapted
+ voltage is made available in an efuse offset.
+ AVS is also called SmartReflex on OMAP devices.
+
+ Say Y here to enable Adaptive Voltage Scaling class 0 support.
+
endif
index b802b0c7fb02d7d7bb3bf3c1fa72b95aed899ce4..0ae7c64895c3c59a02ed9f1d949b94c3f6c08d7a 100644 (file)
obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
+obj-$(CONFIG_REGULATOR_TIAVSCLASS0) += ti-avs-class0-regulator.o
ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
index 5a0f54a1b8bdc147ef78a3fe73e8e73427bdcbaa..1a10eeabaa485a212a45b30eb311d0620575f34f 100644 (file)
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
return "";
}
+static void regulator_lock(struct regulator_dev *rdev)
+{
+ struct regulator_dev *locking_rdev = rdev;
+
+ while (locking_rdev->supply)
+ locking_rdev = locking_rdev->supply->rdev;
+
+ if (!mutex_trylock(&locking_rdev->mutex)) {
+ if (locking_rdev->lock_owner == current) {
+ locking_rdev->lock_count++;
+ dev_dbg(&locking_rdev->dev,
+ "Is locked. locking %s (ref=%u)\n",
+ rdev_get_name(rdev),
+ locking_rdev->lock_count);
+ return;
+ }
+ mutex_lock(&locking_rdev->mutex);
+ }
+
+ WARN_ON_ONCE(locking_rdev->lock_owner != NULL);
+ WARN_ON_ONCE(locking_rdev->lock_count != 0);
+
+ locking_rdev->lock_count = 1;
+ locking_rdev->lock_owner = current;
+ dev_dbg(&locking_rdev->dev, "Is locked. locking %s\n",
+ rdev_get_name(rdev));
+}
+
+static void regulator_unlock(struct regulator_dev *rdev)
+{
+ struct regulator_dev *locking_rdev = rdev;
+
+ while (locking_rdev->supply)
+ locking_rdev = locking_rdev->supply->rdev;
+
+ dev_dbg(&locking_rdev->dev, "Is unlocked. unlocking %s (ref=%u)\n",
+ rdev_get_name(rdev), locking_rdev->lock_count);
+
+ if (--locking_rdev->lock_count)
+ return;
+
+ locking_rdev->lock_owner = NULL;
+ mutex_unlock(&locking_rdev->mutex);
+}
+
/**
* of_get_regulator - get a regulator device node based on supply name
* @dev: Device pointer for the consumer (of regulator) device
struct regulator_dev *rdev = dev_get_drvdata(dev);
ssize_t ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = sprintf(buf, "%d\n", _regulator_get_voltage(rdev));
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
struct regulator_dev *rdev = dev_get_drvdata(dev);
ssize_t ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = regulator_print_state(buf, _regulator_is_enabled(rdev));
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
struct regulator *regulator;
int uA = 0;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
list_for_each_entry(regulator, &rdev->consumer_list, list)
uA += regulator->uA_load;
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return sprintf(buf, "%d\n", uA);
}
static DEVICE_ATTR(requested_microamps, 0444, regulator_total_uA_show, NULL);
if (regulator == NULL)
return NULL;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
regulator->rdev = rdev;
list_add(®ulator->list, &rdev->consumer_list);
_regulator_is_enabled(rdev))
regulator->always_on = true;
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return regulator;
overflow_err:
list_del(®ulator->list);
kfree(regulator);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return NULL;
}
struct regulator_dev *rdev;
struct regulator *regulator = ERR_PTR(-EPROBE_DEFER);
const char *devname = NULL;
- int ret;
+ int ret = 0;
if (id == NULL) {
pr_err("get() with no identifier\n");
if (rdev)
goto found;
+ /*
+ * If we have return value from dev_lookup fail, we do not expect to
+ * succeed, so, quit with appropriate error value
+ */
+ if (ret) {
+ regulator = ERR_PTR(ret);
+ goto out;
+ }
+
if (board_wants_dummy_regulator) {
rdev = dummy_regulator_rdev;
goto found;
return ret;
}
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = _regulator_enable(rdev);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (ret != 0 && rdev->supply)
regulator_disable(rdev->supply);
if (regulator->always_on)
return 0;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = _regulator_disable(rdev);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (ret == 0 && rdev->supply)
regulator_disable(rdev->supply);
struct regulator_dev *rdev = regulator->rdev;
int ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
regulator->uA_load = 0;
ret = _regulator_force_disable(regulator->rdev);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (rdev->supply)
while (rdev->open_count--)
disable_work.work);
int count, i, ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
BUG_ON(!rdev->deferred_disables);
rdev_err(rdev, "Deferred disable failed: %d\n", ret);
}
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (rdev->supply) {
for (i = 0; i < count; i++) {
if (!ms)
return regulator_disable(regulator);
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
rdev->deferred_disables++;
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
ret = schedule_delayed_work(&rdev->disable_work,
msecs_to_jiffies(ms));
if (regulator->always_on)
return 1;
- mutex_lock(®ulator->rdev->mutex);
+ regulator_lock(regulator->rdev);
ret = _regulator_is_enabled(regulator->rdev);
- mutex_unlock(®ulator->rdev->mutex);
+ regulator_unlock(regulator->rdev);
return ret;
}
if (!ops->list_voltage || selector >= rdev->desc->n_voltages)
return -EINVAL;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = ops->list_voltage(rdev, selector);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (ret > 0) {
if (ret < rdev->constraints->min_uV)
@@ -2295,7 +2349,7 @@ int regulator_set_voltage(struct regulator *regulator, int min_uV, int max_uV)
struct regulator_dev *rdev = regulator->rdev;
int ret = 0;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* If we're setting the same range as last time the change
* should be a noop (some cpufreq implementations use the same
@@ -2325,7 +2379,7 @@ int regulator_set_voltage(struct regulator *regulator, int min_uV, int max_uV)
ret = _regulator_do_set_voltage(rdev, min_uV, max_uV);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_set_voltage);
struct regulator_dev *rdev = regulator->rdev;
int ret, min_uV, max_uV;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
if (!rdev->desc->ops->set_voltage &&
!rdev->desc->ops->set_voltage_sel) {
ret = _regulator_do_set_voltage(rdev, min_uV, max_uV);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_sync_voltage);
{
int ret;
- mutex_lock(®ulator->rdev->mutex);
+ regulator_lock(regulator->rdev);
ret = _regulator_get_voltage(regulator->rdev);
- mutex_unlock(®ulator->rdev->mutex);
+ regulator_unlock(regulator->rdev);
return ret;
}
struct regulator_dev *rdev = regulator->rdev;
int ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* sanity check */
if (!rdev->desc->ops->set_current_limit) {
ret = rdev->desc->ops->set_current_limit(rdev, min_uA, max_uA);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_set_current_limit);
{
int ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* sanity check */
if (!rdev->desc->ops->get_current_limit) {
ret = rdev->desc->ops->get_current_limit(rdev);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
int ret;
int regulator_curr_mode;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* sanity check */
if (!rdev->desc->ops->set_mode) {
ret = rdev->desc->ops->set_mode(rdev, mode);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_set_mode);
{
int ret;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/* sanity check */
if (!rdev->desc->ops->get_mode) {
ret = rdev->desc->ops->get_mode(rdev);
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
if (rdev->supply)
input_uV = regulator_get_voltage(rdev->supply);
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
/*
* first check to see if we can set modes at all, otherwise just
}
ret = mode;
out:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
EXPORT_SYMBOL_GPL(regulator_set_optimum_mode);
!(rdev->constraints->valid_ops_mask & REGULATOR_CHANGE_BYPASS))
return 0;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
if (enable && !regulator->bypass) {
rdev->bypass_count++;
if (ret == 0)
regulator->bypass = enable;
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
return ret;
}
mutex_lock(®ulator_list_mutex);
list_for_each_entry(rdev, ®ulator_list, list) {
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
ret = suspend_prepare(rdev, state);
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
if (ret < 0) {
rdev_err(rdev, "failed to prepare\n");
list_for_each_entry(rdev, ®ulator_list, list) {
struct regulator_ops *ops = rdev->desc->ops;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
if ((rdev->use_count > 0 || rdev->constraints->always_on) &&
ops->enable) {
error = ops->enable(rdev);
ret = error;
}
unlock:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
}
mutex_unlock(®ulator_list_mutex);
return ret;
if (!ops->disable || (c && c->always_on))
continue;
- mutex_lock(&rdev->mutex);
+ regulator_lock(rdev);
if (rdev->use_count)
goto unlock;
}
unlock:
- mutex_unlock(&rdev->mutex);
+ regulator_unlock(rdev);
}
mutex_unlock(®ulator_list_mutex);
index c6ca8e1a5c65944cbdf1d276d04a65ab7811a816..d59faabe13bec1a2309dc9ef73c2289846ca1d03 100644 (file)
case PALMAS_REG_SMPS457:
if (!pmic->smps457)
continue;
+ case PALMAS_REG_SMPS10:
+ if (palmas->palmas_id == TPS659038)
+ continue;
}
/* Initialise sleep/init values from platform data */
switch (id) {
case PALMAS_REG_SMPS10:
+
pmic->desc[id].n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
pmic->desc[id].ops = &palmas_ops_smps10;
pmic->desc[id].vsel_reg =
static struct of_device_id of_palmas_match_tbl[] = {
{ .compatible = "ti,palmas-pmic", },
+ { .compatible = "ti,tps659038-pmic", },
{ /* end */ }
};
diff --git a/drivers/regulator/ti-avs-class0-regulator.c b/drivers/regulator/ti-avs-class0-regulator.c
--- /dev/null
@@ -0,0 +1,349 @@
+/*
+ * Texas Instrument SmartReflex AVS Class 0 driver
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Nishanth Menon
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#define pr_fmt(fmt) KBUILD_MODNAME ": %s(): " fmt, __func__
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/of_regulator.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+/**
+ * struct tiavs_class0_data - class data for the regulator instance
+ * @desc: regulator descriptor
+ * @reg: regulator that will actually set the voltage
+ * @volt_set_table: voltage to set data table
+ * @current_idx: current index
+ * @voltage_tolerance: % tolerance for voltage(optional)
+ */
+struct tiavs_class0_data {
+ struct regulator_desc desc;
+ struct regulator *reg;
+ unsigned int *volt_set_table;
+ int current_idx;
+ u32 voltage_tolerance;
+};
+
+/**
+ * tiavs_class0_set_voltage_sel() - set voltage
+ * @rdev: regulator device
+ * @sel: set voltage corresponding to selector
+ *
+ * This searches for a best case match and uses the child regulator to set
+ * appropriate voltage
+ *
+ * Return: -ENODEV if no proper regulator data/-EINVAL if no match,bad efuse
+ * else returns regulator set result
+ */
+static int tiavs_class0_set_voltage_sel(struct regulator_dev *rdev,
+ unsigned sel)
+{
+ struct tiavs_class0_data *data = rdev_get_drvdata(rdev);
+ const struct regulator_desc *desc = rdev->desc;
+ struct regulator *reg;
+ int vset, ret, tol;
+
+ if (!data) {
+ pr_err("No regulator drvdata\n");
+ return -ENODEV;
+ }
+
+ reg = data->reg;
+ if (!reg) {
+ pr_err("No regulator\n");
+ return -ENODEV;
+ }
+
+ if (!desc->n_voltages || !data->volt_set_table) {
+ pr_err("No valid voltage table entries?\n");
+ return -EINVAL;
+ }
+
+ if (sel >= desc->n_voltages) {
+ pr_err("sel(%d) > max voltage table entries(%d)\n", sel,
+ desc->n_voltages);
+ return -EINVAL;
+ }
+
+ vset = data->volt_set_table[sel];
+
+ /* Adjust for % tolerance needed */
+ tol = DIV_ROUND_UP(vset * data->voltage_tolerance, 100);
+ ret = regulator_set_voltage_tol(reg, vset, tol);
+ if (!ret)
+ data->current_idx = sel;
+
+ return ret;
+}
+
+/**
+ * tiavs_class0_get_voltage_sel() - Get voltage selector
+ * @rdev: regulator device
+ *
+ * Return: -ENODEV if no proper regulator data/-EINVAL if no data,
+ * else returns current index.
+ */
+static int tiavs_class0_get_voltage_sel(struct regulator_dev *rdev)
+{
+ const struct regulator_desc *desc = rdev->desc;
+ struct tiavs_class0_data *data = rdev_get_drvdata(rdev);
+
+ if (!data) {
+ pr_err("No regulator drvdata\n");
+ return -ENODEV;
+ }
+
+ if (!desc->n_voltages || !data->volt_set_table) {
+ pr_err("No valid voltage table entries?\n");
+ return -EINVAL;
+ }
+
+ if (data->current_idx > desc->n_voltages) {
+ pr_err("Corrupted data structure?? idx(%d) > n_voltages(%d)\n",
+ data->current_idx, desc->n_voltages);
+ return -EINVAL;
+ }
+
+ return data->current_idx;
+}
+
+static struct regulator_ops tiavs_class0_ops = {
+ .list_voltage = regulator_list_voltage_table,
+
+ .set_voltage_sel = tiavs_class0_set_voltage_sel,
+ .get_voltage_sel = tiavs_class0_get_voltage_sel,
+
+};
+
+static const struct of_device_id tiavs_class0_of_match[] = {
+ {.compatible = "ti,avsclass0",},
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, tiavs_class0_of_match);
+
+/**
+ * tiavs_class0_probe() - AVS class 0 probe
+ * @pdev: matching platform device
+ *
+ * We support only device tree provided data here. Once we find a regulator,
+ * efuse offsets, we pick up the efuse register voltages store them per
+ * instance.
+ *
+ * Return: if everything goes through, we return 0, else corresponding error
+ * value is returned.
+ */
+static int tiavs_class0_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct device_node *np = pdev->dev.of_node;
+ struct property *prop;
+ struct resource *res;
+ struct regulator *reg;
+ struct regulator_init_data *initdata = NULL;
+ struct regulator_config config = { };
+ struct regulation_constraints *c;
+ struct regulator_dev *rdev;
+ struct regulator_desc *desc;
+ struct tiavs_class0_data *data;
+ void __iomem *base;
+ const __be32 *val;
+ unsigned int *volt_table;
+ bool efuse_is_uV = false;
+ int proplen, i, ret;
+ int reg_v, min_uV = INT_MAX, max_uV = 0;
+ int best_val = INT_MAX, choice = -EINVAL;
+
+ match = of_match_device(tiavs_class0_of_match, &pdev->dev);
+ if (match)
+ initdata = of_get_regulator_init_data(&pdev->dev, np);
+ if (!initdata) {
+ dev_err(&pdev->dev, "No proper OF?\n");
+ return -ENODEV;
+ }
+
+ /* look for avs-supply */
+ reg = devm_regulator_get(&pdev->dev, "avs");
+ if (IS_ERR(reg)) {
+ ret = PTR_ERR(reg);
+ reg = NULL;
+ dev_err(&pdev->dev, "avs_class0 regulator not available(%d)\n",
+ ret);
+ return ret;
+ }
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data) {
+ dev_err(&pdev->dev, "No memory to alloc data!\n");
+ return -ENOMEM;
+ }
+ data->reg = reg;
+
+ desc = &data->desc;
+ desc->name = dev_name(&pdev->dev);
+ desc->owner = THIS_MODULE;
+ desc->type = REGULATOR_VOLTAGE;
+ desc->ops = &tiavs_class0_ops;
+
+ /* pick up optional properties */
+ of_property_read_u32(np, "voltage-tolerance", &data->voltage_tolerance);
+ efuse_is_uV = of_property_read_bool(np,
+ "ti,avsclass0-microvolt-values");
+
+ /* pick up Efuse based voltages */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Unable to get IO resource\n");
+ return -ENODEV;
+ }
+
+ base = devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res));
+ if (!base) {
+ dev_err(&pdev->dev, "Unable to map Efuse registers\n");
+ return -ENOMEM;
+ }
+
+ /* Fetch efuse-settings. */
+ prop = of_find_property(np, "efuse-settings", NULL);
+ if (!prop) {
+ dev_err(&pdev->dev, "No 'efuse-settings' property found\n");
+ return -EINVAL;
+ }
+
+ proplen = prop->length / sizeof(int);
+
+ data->volt_set_table =
+ devm_kzalloc(&pdev->dev, sizeof(unsigned int) * (proplen / 2),
+ GFP_KERNEL);
+ if (!data->volt_set_table) {
+ dev_err(&pdev->dev, "Unable to Allocate voltage set table\n");
+ return -ENOMEM;
+ }
+
+ volt_table =
+ devm_kzalloc(&pdev->dev, sizeof(unsigned int) * (proplen / 2),
+ GFP_KERNEL);
+ if (!volt_table) {
+ dev_err(&pdev->dev,
+ "Unable to Allocate voltage lookup table\n");
+ return -ENOMEM;
+ }
+
+ val = prop->value;
+ for (i = 0; i < proplen / 2; i++) {
+ u32 efuse_offset;
+
+ volt_table[i] = be32_to_cpup(val++);
+ efuse_offset = be32_to_cpup(val++);
+
+ data->volt_set_table[i] = efuse_is_uV ?
+ readl(base + efuse_offset) :
+ readw(base + efuse_offset) * 1000;
+
+ /* Find min/max for the voltage sets */
+ if (min_uV > volt_table[i])
+ min_uV = volt_table[i];
+ if (max_uV < volt_table[i])
+ max_uV = volt_table[i];
+
+ dev_dbg(&pdev->dev, "[%d] efuse=0x%08x volt_table=%d vset=%d\n",
+ i, efuse_offset, volt_table[i],
+ data->volt_set_table[i]);
+ }
+ desc->n_voltages = i;
+ desc->volt_table = volt_table;
+
+ /* Search for a best match voltage */
+ reg_v = regulator_get_voltage(reg);
+ if (reg_v < 0) {
+ dev_err(&pdev->dev, "Regulator error %d for get_voltage!\n",
+ reg_v);
+ return reg_v;
+ }
+
+ for (i = 0; i < desc->n_voltages; i++)
+ if (data->volt_set_table[i] < best_val &&
+ data->volt_set_table[i] >= reg_v) {
+ best_val = data->volt_set_table[i];
+ choice = i;
+ }
+
+ if (choice == -EINVAL) {
+ dev_err(&pdev->dev, "No match regulator V=%d\n", reg_v);
+ return -EINVAL;
+ }
+ data->current_idx = choice;
+
+ /*
+ * Constrain board-specific capabilities according to what
+ * this driver can actually do.
+ */
+ c = &initdata->constraints;
+ if (desc->n_voltages > 1)
+ c->valid_ops_mask |= REGULATOR_CHANGE_VOLTAGE;
+ c->always_on = true;
+
+ c->min_uV = min_uV;
+ c->max_uV = max_uV;
+
+ config.dev = &pdev->dev;
+ config.init_data = initdata;
+ config.driver_data = data;
+ config.of_node = pdev->dev.of_node;
+
+ rdev = regulator_register(desc, &config);
+ if (IS_ERR(rdev)) {
+ dev_err(&pdev->dev, "can't register %s, %ld\n",
+ desc->name, PTR_ERR(rdev));
+ return PTR_ERR(rdev);
+ }
+ platform_set_drvdata(pdev, rdev);
+
+ return 0;
+}
+
+static int tiavs_class0_remove(struct platform_device *pdev)
+{
+ struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+ regulator_unregister(rdev);
+ return 0;
+}
+
+MODULE_ALIAS("platform:tiavs_class0");
+
+static struct platform_driver tiavs_class0_driver = {
+ .probe = tiavs_class0_probe,
+ .remove = tiavs_class0_remove,
+ .driver = {
+ .name = "tiavs_class0",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(tiavs_class0_of_match),
+ },
+};
+module_platform_driver(tiavs_class0_driver);
+
+MODULE_DESCRIPTION("TI SmartReflex AVS class 0 regulator driver");
+MODULE_AUTHOR("Texas Instruments Inc.");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index f62eab30143817ac008a52b788843d1fbb180a47..f11f746f7a3507bece3c126ce95d4cb73c306029 100644 (file)
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
This driver can also be built as a module. If so, the module
will be called rtc-x1205.
+config RTC_DRV_PALMAS
+ tristate "TI Palmas RTC driver"
+ depends on MFD_PALMAS
+ help
+ If you say yes here you get support for the RTC of TI PALMA series PMIC
+ chips.
+
+ This driver can also be built as a module. If so, the module
+ will be called rtc-palma.
+
config RTC_DRV_PCF8523
tristate "NXP PCF8523"
help
This driver can also be built as a module. If so, the module
will be called rtc-rv3029c2.
-config RTC_DRV_PALMAS
- tristate "Palmas RTC"
- help
- If you say yes here you get support for the RTC on the Palmas
- series of PMICs from TI.
-
endif # I2C
comment "SPI RTC drivers"
index 116a3002ce189ad72339dcd7617cdbd5cfc720d7..a7d5175d29a98f03ff74538e94d4168a80cc3efb 100644 (file)
--- a/drivers/rtc/rtc-palmas.c
+++ b/drivers/rtc/rtc-palmas.c
/*
- * Palmas Real Time Clock interface
+ * rtc-palmas.c -- Palmas Real Time Clock driver.
+
+ * RTC driver for TI Palma series devices like TPS65913,
+ * TPS65914 power management IC.
*
- * Copyright (C) 2012 Texas Instruments
- * Author: Graeme Gregory <gg@slimlogic.co.uk>
+ * Copyright (c) 2012, NVIDIA Corporation.
*
- * Based on rtc-twl.c
- * Copyright (C) 2007 MontaVista Software, Inc
- * Author: Alexandre Rusev <source@mvista.com>
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
*
- * Based on original TI driver twl4030-rtc.c
- * Copyright (C) 2006 Texas Instruments, Inc.
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
*
- * Based on rtc-omap.c
- * Copyright (C) 2003 MontaVista Software, Inc.
- * Author: George G. Davis <gdavis@mvista.com> or <source@mvista.com>
- * Copyright (C) 2006 David Brownell
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
*/
-#include <linux/kernel.h>
+#include <linux/bcd.h>
#include <linux/errno.h>
#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mfd/palmas.h>
#include <linux/module.h>
-#include <linux/types.h>
#include <linux/rtc.h>
-#include <linux/bcd.h>
+#include <linux/types.h>
#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/slab.h>
-#include <linux/mfd/palmas.h>
-
-#define ALL_TIME_REGS 6
+#include <linux/pm.h>
struct palmas_rtc {
- struct palmas *palmas;
- struct device *dev;
- struct rtc_device *rtc;
- unsigned int irq_bits;
- int irq;
+ struct rtc_device *rtc;
+ struct device *dev;
+ unsigned int irq;
};
-static int palmas_rtc_read(struct palmas *palmas, unsigned int reg,
- unsigned int *dest)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RTC_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RTC_BASE, reg);
-
- return regmap_read(palmas->regmap[slave], addr, dest);
-}
-
-static int palmas_rtc_write(struct palmas *palmas, unsigned int reg,
- unsigned int data)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RTC_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RTC_BASE, reg);
-
- return regmap_write(palmas->regmap[slave], addr, data);
-}
-
-static int palmas_rtc_read_block(struct palmas *palmas, unsigned int reg,
- u8 *dest, size_t count)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RTC_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RTC_BASE, reg);
-
- return regmap_bulk_read(palmas->regmap[slave], addr, dest, count);
-}
-
-static int palmas_rtc_write_block(struct palmas *palmas, unsigned int reg,
- u8 *src, size_t count)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RTC_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RTC_BASE, reg);
-
- return regmap_raw_write(palmas->regmap[slave], addr, src, count);
-}
+/* Total number of RTC registers needed to set time*/
+#define PALMAS_NUM_TIME_REGS (PALMAS_YEARS_REG - PALMAS_SECONDS_REG + 1)
-static int palmas_rtc_setbits(struct palmas *palmas, unsigned int reg,
- unsigned int data)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RESOURCE_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, reg);
-
- return regmap_update_bits(palmas->regmap[slave], addr, data, data);
-}
-
-static int palmas_rtc_clrbits(struct palmas *palmas, unsigned int reg,
- unsigned int data)
-{
- unsigned int addr;
- int slave;
-
- slave = PALMAS_BASE_TO_SLAVE(PALMAS_RESOURCE_BASE);
- addr = PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE, reg);
-
- return regmap_update_bits(palmas->regmap[slave], addr, data, 0);
-}
-
-/*
- * Gets current TWL RTC time and date parameters.
- *
- * The RTC's time/alarm representation is not what gmtime(3) requires
- * Linux to use:
- *
- * - Months are 1..12 vs Linux 0-11
- * - Years are 0..99 vs Linux 1900..N (we assume 21st century)
- */
static int palmas_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned char rtc_data[ALL_TIME_REGS];
+ unsigned char rtc_data[PALMAS_NUM_TIME_REGS];
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
int ret;
- ret = palmas_rtc_setbits(palmas, PALMAS_RTC_CTRL_REG,
- PALMAS_RTC_CTRL_REG_GET_TIME);
+ /* Copy RTC counting registers to static registers or latches */
+ ret = palmas_update_bits(palmas, PALMAS_RTC_BASE, PALMAS_RTC_CTRL_REG,
+ PALMAS_RTC_CTRL_REG_GET_TIME, PALMAS_RTC_CTRL_REG_GET_TIME);
if (ret < 0) {
- dev_err(dev, "Failed to update RTC_CTRL %d\n", ret);
- goto out;
+ dev_err(dev, "RTC CTRL reg update failed, err: %d\n", ret);
+ return ret;
}
- ret = palmas_rtc_read_block(palmas,PALMAS_SECONDS_REG, rtc_data,
- ALL_TIME_REGS);
-
+ ret = palmas_bulk_read(palmas, PALMAS_RTC_BASE, PALMAS_SECONDS_REG,
+ rtc_data, PALMAS_NUM_TIME_REGS);
if (ret < 0) {
- dev_err(dev, "Failed to read time block %d\n", ret);
- goto out;
+ dev_err(dev, "RTC_SECONDS reg read failed, err = %d\n", ret);
+ return ret;
}
tm->tm_sec = bcd2bin(rtc_data[0]);
tm->tm_mon = bcd2bin(rtc_data[4]) - 1;
tm->tm_year = bcd2bin(rtc_data[5]) + 100;
- ret = palmas_rtc_clrbits(palmas, PALMAS_RTC_CTRL_REG,
- PALMAS_RTC_CTRL_REG_GET_TIME);
- if (ret < 0)
- dev_err(dev, "Failed to update RTC_CTRL %d\n", ret);
-
-out:
return ret;
}
static int palmas_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned char rtc_data[ALL_TIME_REGS];
+ unsigned char rtc_data[PALMAS_NUM_TIME_REGS];
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
int ret;
rtc_data[0] = bin2bcd(tm->tm_sec);
rtc_data[4] = bin2bcd(tm->tm_mon + 1);
rtc_data[5] = bin2bcd(tm->tm_year - 100);
- /* Stop RTC while updating the TC registers */
- ret = palmas_rtc_clrbits(palmas, PALMAS_RTC_CTRL_REG,
- PALMAS_RTC_CTRL_REG_STOP_RTC);
+ /* Stop RTC while updating the RTC time registers */
+ ret = palmas_update_bits(palmas, PALMAS_RTC_BASE, PALMAS_RTC_CTRL_REG,
+ PALMAS_RTC_CTRL_REG_STOP_RTC, 0);
if (ret < 0) {
- dev_err(dev, "Failed to stop RTC %d\n", ret);
- goto out;
+ dev_err(dev, "RTC stop failed, err = %d\n", ret);
+ return ret;
}
- /* update all the time registers in one shot */
- ret = palmas_rtc_write_block(palmas, PALMAS_SECONDS_REG, rtc_data,
- ALL_TIME_REGS);
+ ret = palmas_bulk_write(palmas, PALMAS_RTC_BASE, PALMAS_SECONDS_REG,
+ rtc_data, PALMAS_NUM_TIME_REGS);
if (ret < 0) {
- dev_err(dev, "Failed to write time block %d\n", ret);
- goto out;
+ dev_err(dev, "RTC_SECONDS reg write failed, err = %d\n", ret);
+ return ret;
}
/* Start back RTC */
- ret = palmas_rtc_setbits(palmas, PALMAS_RTC_CTRL_REG,
- PALMAS_RTC_CTRL_REG_STOP_RTC);
- if (ret < 0) {
- dev_err(dev, "Failed to start RTC %d\n", ret);
- goto out;
- }
-
-out:
+ ret = palmas_update_bits(palmas, PALMAS_RTC_BASE, PALMAS_RTC_CTRL_REG,
+ PALMAS_RTC_CTRL_REG_STOP_RTC, PALMAS_RTC_CTRL_REG_STOP_RTC);
+ if (ret < 0)
+ dev_err(dev, "RTC start failed, err = %d\n", ret);
return ret;
}
static int palmas_rtc_alarm_irq_enable(struct device *dev, unsigned enabled)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- int ret;
-
- if (enabled) {
- ret = palmas_rtc_setbits(palmas, PALMAS_RTC_INTERRUPTS_REG,
- PALMAS_RTC_INTERRUPTS_REG_IT_ALARM);
- if (ret)
- dev_err(palmas_rtc->dev,
- "failed to set RTC alarm IRQ %d\n", ret);
-
- palmas_rtc->irq_bits |= PALMAS_RTC_INTERRUPTS_REG_IT_ALARM;
- } else {
- ret = palmas_rtc_clrbits(palmas, PALMAS_RTC_INTERRUPTS_REG,
- PALMAS_RTC_INTERRUPTS_REG_IT_ALARM);
- if (ret)
- dev_err(palmas_rtc->dev,
- "failed to clear RTC alarm IRQ %d\n", ret);
-
- palmas_rtc->irq_bits &= ~PALMAS_RTC_INTERRUPTS_REG_IT_ALARM;
- }
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
+ u8 val;
- return ret;
+ val = enabled ? PALMAS_RTC_INTERRUPTS_REG_IT_ALARM : 0;
+ return palmas_write(palmas, PALMAS_RTC_BASE,
+ PALMAS_RTC_INTERRUPTS_REG, val);
}
-/*
- * Gets current TWL RTC alarm time.
- */
static int palmas_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned char rtc_data[ALL_TIME_REGS];
+ unsigned char alarm_data[PALMAS_NUM_TIME_REGS];
+ u32 int_val;
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
int ret;
- ret = palmas_rtc_read_block(palmas, PALMAS_ALARM_SECONDS_REG, rtc_data,
- ALL_TIME_REGS);
+ ret = palmas_bulk_read(palmas, PALMAS_RTC_BASE,
+ PALMAS_ALARM_SECONDS_REG,
+ alarm_data, PALMAS_NUM_TIME_REGS);
if (ret < 0) {
- dev_err(dev, "Failed to read alarm block %d\n", ret);
- goto out;
+ dev_err(dev, "RTC_ALARM_SECONDS read failed, err = %d\n", ret);
+ return ret;
}
- /* some of these fields may be wildcard/"match all" */
- alm->time.tm_sec = bcd2bin(rtc_data[0]);
- alm->time.tm_min = bcd2bin(rtc_data[1]);
- alm->time.tm_hour = bcd2bin(rtc_data[2]);
- alm->time.tm_mday = bcd2bin(rtc_data[3]);
- alm->time.tm_mon = bcd2bin(rtc_data[4]) - 1;
- alm->time.tm_year = bcd2bin(rtc_data[5]) + 100;
+ alm->time.tm_sec = bcd2bin(alarm_data[0]);
+ alm->time.tm_min = bcd2bin(alarm_data[1]);
+ alm->time.tm_hour = bcd2bin(alarm_data[2]);
+ alm->time.tm_mday = bcd2bin(alarm_data[3]);
+ alm->time.tm_mon = bcd2bin(alarm_data[4]) - 1;
+ alm->time.tm_year = bcd2bin(alarm_data[5]) + 100;
- /* report cached alarm enable state */
- if (palmas_rtc->irq_bits & PALMAS_RTC_INTERRUPTS_REG_IT_ALARM)
- alm->enabled = 1;
+ ret = palmas_read(palmas, PALMAS_RTC_BASE, PALMAS_RTC_INTERRUPTS_REG,
+ &int_val);
+ if (ret < 0) {
+ dev_err(dev, "RTC_INTERRUPTS reg read failed, err = %d\n", ret);
+ return ret;
+ }
-out:
+ if (int_val & PALMAS_RTC_INTERRUPTS_REG_IT_ALARM)
+ alm->enabled = 1;
return ret;
}
static int palmas_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
{
- struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned char alarm_data[ALL_TIME_REGS];
+ unsigned char alarm_data[PALMAS_NUM_TIME_REGS];
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
int ret;
ret = palmas_rtc_alarm_irq_enable(dev, 0);
- if (ret)
- goto out;
+ if (ret < 0) {
+ dev_err(dev, "Disable RTC alarm failed\n");
+ return ret;
+ }
alarm_data[0] = bin2bcd(alm->time.tm_sec);
alarm_data[1] = bin2bcd(alm->time.tm_min);
alarm_data[4] = bin2bcd(alm->time.tm_mon + 1);
alarm_data[5] = bin2bcd(alm->time.tm_year - 100);
- /* update all the alarm registers in one shot */
- ret = palmas_rtc_write_block(palmas, PALMAS_ALARM_SECONDS_REG,
- alarm_data, ALL_TIME_REGS);
- if (ret) {
- dev_err(dev, "Failed to write alarm block %d\n", ret);
- goto out;
+ ret = palmas_bulk_write(palmas, PALMAS_RTC_BASE,
+ PALMAS_ALARM_SECONDS_REG, alarm_data, PALMAS_NUM_TIME_REGS);
+ if (ret < 0) {
+ dev_err(dev, "ALARM_SECONDS_REG write failed, err = %d\n", ret);
+ return ret;
}
- if (alm->enabled) {
+ if (alm->enabled)
ret = palmas_rtc_alarm_irq_enable(dev, 1);
- }
-
-out:
return ret;
}
-static irqreturn_t palmas_rtc_interrupt(int irq, void *rtc)
+static int palmas_clear_interrupts(struct device *dev)
{
- struct palmas_rtc *palmas_rtc = rtc;
- struct palmas *palmas = palmas_rtc->palmas;
- unsigned long events = 0;
- int ret = IRQ_NONE;
- int res;
- unsigned int rd_reg;
-
- res = palmas_rtc_read(palmas, PALMAS_RTC_STATUS_REG, &rd_reg);
- if (res) {
- dev_err(palmas_rtc->dev, "Failed to read IRQ sts %d\n, res",
- res);
- goto out;
+ struct palmas *palmas = dev_get_drvdata(dev->parent);
+ unsigned int rtc_reg;
+ int ret;
+
+ ret = palmas_read(palmas, PALMAS_RTC_BASE, PALMAS_RTC_STATUS_REG,
+ &rtc_reg);
+ if (ret < 0) {
+ dev_err(dev, "RTC_STATUS read failed, err = %d\n", ret);
+ return ret;
}
- /*
- * Figure out source of interrupt: ALARM or TIMER in RTC_STATUS_REG.
- * only one (ALARM or RTC) interrupt source may be enabled
- * at time, we also could check our results
- * by reading RTS_INTERRUPTS_REGISTER[IT_TIMER,IT_ALARM]
- */
- if (rd_reg & PALMAS_RTC_STATUS_REG_ALARM)
- events |= RTC_IRQF | RTC_AF;
- else
- events |= RTC_IRQF | RTC_UF;
-
- res = palmas_rtc_write(palmas, PALMAS_RTC_STATUS_REG,
- rd_reg | PALMAS_RTC_STATUS_REG_ALARM);
- if (res) {
- dev_err(palmas_rtc->dev, "Failed to clear IRQ sts %d\n, res",
- res);
- goto out;
+ ret = palmas_write(palmas, PALMAS_RTC_BASE, PALMAS_RTC_STATUS_REG,
+ rtc_reg);
+ if (ret < 0) {
+ dev_err(dev, "RTC_STATUS write failed, err = %d\n", ret);
+ return ret;
}
+ return 0;
+}
- /* Notify RTC core on event */
- rtc_update_irq(rtc, 1, events);
+static irqreturn_t palmas_rtc_interrupt(int irq, void *context)
+{
+ struct palmas_rtc *palmas_rtc = context;
+ struct device *dev = palmas_rtc->dev;
+ int ret;
- ret = IRQ_HANDLED;
-out:
- return ret;
+ ret = palmas_clear_interrupts(dev);
+ if (ret < 0) {
+ dev_err(dev, "RTC interrupt clear failed, err = %d\n", ret);
+ return IRQ_NONE;
+ }
+
+ rtc_update_irq(palmas_rtc->rtc, 1, RTC_IRQF | RTC_AF);
+ return IRQ_HANDLED;
}
-static struct rtc_class_ops twl_rtc_ops = {
+static struct rtc_class_ops palmas_rtc_ops = {
.read_time = palmas_rtc_read_time,
.set_time = palmas_rtc_set_time,
.read_alarm = palmas_rtc_read_alarm,
.alarm_irq_enable = palmas_rtc_alarm_irq_enable,
};
-/*----------------------------------------------------------------------*/
-
static int palmas_rtc_probe(struct platform_device *pdev)
{
struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
- struct palmas_rtc *palmas_rtc;
- struct rtc_device *rtc;
- int ret = -EINVAL;
- int irq;
- unsigned int rd_reg;
-
- ret = palmas_rtc_read(palmas, PALMAS_RTC_STATUS_REG, &rd_reg);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to read RTC status %d\n", rd_reg);
- goto out1;
- }
-
- palmas_rtc = kzalloc(sizeof(*palmas_rtc), GFP_KERNEL);
- if (!palmas_rtc) {
- ret = -ENOMEM;
- goto out1;
- }
-
- if (rd_reg & PALMAS_RTC_STATUS_REG_POWER_UP)
- dev_warn(&pdev->dev, "Power up reset detected\n");
+ struct palmas_rtc *palmas_rtc = NULL;
+ int ret;
- if (rd_reg & PALMAS_RTC_STATUS_REG_ALARM)
- dev_warn(&pdev->dev, "Pending Alarm interrupt detected\n");
+ palmas_rtc = devm_kzalloc(&pdev->dev, sizeof(struct palmas_rtc),
+ GFP_KERNEL);
+ if (!palmas_rtc)
+ return -ENOMEM;
- /* Clear RTC Power up reset and pending alarm interrupts */
- ret = palmas_rtc_write(palmas, PALMAS_RTC_STATUS_REG, rd_reg);
+ /* Clear pending interrupts */
+ ret = palmas_clear_interrupts(&pdev->dev);
if (ret < 0) {
- dev_err(&pdev->dev, "Failed to read RTC status %d\n", ret);
- goto out2;
+ dev_err(&pdev->dev, "clear RTC int failed, err = %d\n", ret);
+ return ret;
}
- /* Check RTC module status, Enable if it is off */
- ret = palmas_rtc_read(palmas, PALMAS_RTC_CTRL_REG, &rd_reg);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to read RTC ctrl %d\n", ret);
- goto out2;
- }
-
- if (!(rd_reg & PALMAS_RTC_CTRL_REG_STOP_RTC)) {
- dev_info(&pdev->dev, "Enabling Palmas RTC\n");
- rd_reg = PALMAS_RTC_CTRL_REG_STOP_RTC;
- ret = palmas_rtc_write(palmas, PALMAS_RTC_CTRL_REG, rd_reg);
- if (ret < 0) {
- dev_err(&pdev->dev, "Failed to write RTC ctrl %d\n",
- ret);
- goto out2;
- }
- }
+ palmas_rtc->dev = &pdev->dev;
+ platform_set_drvdata(pdev, palmas_rtc);
- /* init cached IRQ enable bits */
- ret = palmas_rtc_read(palmas, PALMAS_RTC_INTERRUPTS_REG,
- &palmas_rtc->irq_bits);
+ /* Start RTC */
+ ret = palmas_update_bits(palmas, PALMAS_RTC_BASE, PALMAS_RTC_CTRL_REG,
+ PALMAS_RTC_CTRL_REG_STOP_RTC,
+ PALMAS_RTC_CTRL_REG_STOP_RTC);
if (ret < 0) {
- dev_err(&pdev->dev, "Failed to cache IRQ bits %d\n", ret);
- goto out2;
+ dev_err(&pdev->dev, "RTC_CTRL write failed, err = %d\n", ret);
+ return ret;
}
- palmas_rtc->palmas = palmas;
- palmas_rtc->dev = &pdev->dev;
- platform_set_drvdata(pdev, palmas_rtc);
-
- device_init_wakeup(&pdev->dev, 1);
+ palmas_rtc->irq = regmap_irq_get_virq(palmas->irq_data,
+ PALMAS_RTC_ALARM_IRQ);
- rtc = rtc_device_register(pdev->name,
- &pdev->dev, &twl_rtc_ops, THIS_MODULE);
- if (IS_ERR(rtc)) {
- ret = PTR_ERR(rtc);
- dev_err(&pdev->dev, "can't register RTC device, err %d\n",
- ret);
- goto out2;
+ palmas_rtc->rtc = rtc_device_register(pdev->name, &pdev->dev,
+ &palmas_rtc_ops, THIS_MODULE);
+ if (IS_ERR(palmas_rtc->rtc)) {
+ ret = PTR_ERR(palmas_rtc->rtc);
+ dev_err(&pdev->dev, "RTC register failed, err = %d\n", ret);
+ return ret;
}
- irq = regmap_irq_get_virq(palmas->irq_data, PALMAS_RTC_ALARM_IRQ);
- ret = request_threaded_irq(irq, NULL, palmas_rtc_interrupt,
- IRQF_TRIGGER_RISING,
- dev_name(&pdev->dev), palmas_rtc);
+ ret = request_threaded_irq(palmas_rtc->irq, NULL,
+ palmas_rtc_interrupt,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT |
+ IRQF_EARLY_RESUME,
+ dev_name(&pdev->dev), palmas_rtc);
if (ret < 0) {
- dev_err(&pdev->dev, "IRQ is not free\n");
- goto out3;
+ dev_err(&pdev->dev, "IRQ request failed, err = %d\n", ret);
+ rtc_device_unregister(palmas_rtc->rtc);
+ return ret;
}
- palmas_rtc->irq = irq;
-
+ device_set_wakeup_capable(&pdev->dev, 1);
return 0;
-
-out3:
- rtc_device_unregister(rtc);
-out2:
- kfree(palmas_rtc);
-out1:
- return ret;
}
-/*
- * Disable all TWL RTC module interrupts.
- * Sets status flag to free.
- */
static int palmas_rtc_remove(struct platform_device *pdev)
{
struct palmas_rtc *palmas_rtc = platform_get_drvdata(pdev);
- struct rtc_device *rtc = palmas_rtc->rtc;
palmas_rtc_alarm_irq_enable(&pdev->dev, 0);
-
free_irq(palmas_rtc->irq, palmas_rtc);
- rtc_device_unregister(rtc);
- kfree(palmas_rtc);
+ rtc_device_unregister(palmas_rtc->rtc);
+ return 0;
+}
+#ifdef CONFIG_PM_SLEEP
+static int palmas_rtc_suspend(struct device *dev)
+{
+ struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ enable_irq_wake(palmas_rtc->irq);
+ return 0;
+}
+
+static int palmas_rtc_resume(struct device *dev)
+{
+ struct palmas_rtc *palmas_rtc = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ disable_irq_wake(palmas_rtc->irq);
return 0;
}
+#endif
+
+static const struct dev_pm_ops palmas_rtc_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(palmas_rtc_suspend, palmas_rtc_resume)
+};
static struct of_device_id of_palmas_match_tbl[] = {
+ { .compatible = "ti,twl6035-rtc", },
+ { .compatible = "ti,twl6036-rtc", },
+ { .compatible = "ti,twl6037-rtc", },
+ { .compatible = "ti,tps65913-rtc", },
+ { .compatible = "ti,tps65914-rtc", },
+ { .compatible = "ti,tps80032-rtc", },
{ .compatible = "ti,palmas-rtc", },
+ { .compatible = "ti,palmas-charger-rtc", },
{ /* end */ },
};
static struct platform_driver palmas_rtc_driver = {
- .probe = palmas_rtc_probe,
- .remove = palmas_rtc_remove,
- .driver = {
- .owner = THIS_MODULE,
- .name = "palmas-rtc",
+ .probe = palmas_rtc_probe,
+ .remove = palmas_rtc_remove,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "palmas-rtc",
+ .pm = &palmas_rtc_pm_ops,
.of_match_table = of_palmas_match_tbl,
},
};
-static int __init palmas_rtc_init(void)
-{
- return platform_driver_register(&palmas_rtc_driver);
-}
-module_init(palmas_rtc_init);
-
-static void __exit palmas_rtc_exit(void)
-{
- platform_driver_unregister(&palmas_rtc_driver);
-}
-module_exit(palmas_rtc_exit);
+module_platform_driver(palmas_rtc_driver);
-MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
-MODULE_DESCRIPTION("Palmas RTC Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:palmas-rtc");
-MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
+MODULE_ALIAS("platform:palmas_rtc");
+MODULE_DESCRIPTION("TI PALMAS series RTC driver");
+MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
+MODULE_LICENSE("GPL v2");
index e81375fb21552413f3df4689e4c950aab820eb8e..bd4c7beba67915200d6e44c505a49f44a3442978 100644 (file)
This includes alert interrupts generation and also the TSHUT
support.
+
+config DRA752_THERMAL
+ bool "Texas Instruments DRA752 thermal support"
+ depends on TI_SOC_THERMAL
+ depends on SOC_DRA7XX
+ help
+ If you say yes here you get thermal support for the Texas Instruments
+ DRA752 SoC family. The current chip supported are:
+ - DRA752
+
+ This includes alert interrupts generation and also the TSHUT
+ support.
index 0ca034fb419de8dbfa05d5894195f9a4065d5f85..1226b2484e550cba08e6233c6fdb56f02a54fef0 100644 (file)
obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal.o
ti-soc-thermal-y := ti-bandgap.o
ti-soc-thermal-$(CONFIG_TI_THERMAL) += ti-thermal-common.o
+ti-soc-thermal-$(CONFIG_DRA752_THERMAL) += dra752-thermal-data.o
ti-soc-thermal-$(CONFIG_OMAP4_THERMAL) += omap4-thermal-data.o
ti-soc-thermal-$(CONFIG_OMAP5_THERMAL) += omap5-thermal-data.o
diff --git a/drivers/staging/ti-soc-thermal/dra752-bandgap.h b/drivers/staging/ti-soc-thermal/dra752-bandgap.h
--- /dev/null
@@ -0,0 +1,280 @@
+/*
+ * DRA752 bandgap registers, bitfields and temperature definitions
+ *
+ * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Contact:
+ * Eduardo Valentin <eduardo.valentin@ti.com>
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This is an auto generated file.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+#ifndef __DRA752_BANDGAP_H
+#define __DRA752_BANDGAP_H
+
+/**
+ * *** DRA752 ***
+ *
+ * Below, in sequence, are the Register definitions,
+ * the bitfields and the temperature definitions for DRA752.
+ */
+
+/**
+ * DRA752 register definitions
+ *
+ * Registers are defined as offsets. The offsets are
+ * relative to FUSE_OPP_BGAP_GPU on DRA752.
+ * DRA752_BANDGAP_BASE 0x4a0021e0
+ *
+ * Register below are grouped by domain (not necessarily in offset order)
+ */
+
+
+/* DRA752.common register offsets */
+#define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0
+#define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8
+#define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c
+#define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8
+
+/* DRA752.core register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8
+#define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154
+#define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac
+#define DRA752_BANDGAP_TSHUT_CORE_OFFSET 0x1b8
+#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4
+#define DRA752_DTEMP_CORE_0_OFFSET 0x208
+#define DRA752_DTEMP_CORE_1_OFFSET 0x20c
+#define DRA752_DTEMP_CORE_2_OFFSET 0x210
+#define DRA752_DTEMP_CORE_3_OFFSET 0x214
+#define DRA752_DTEMP_CORE_4_OFFSET 0x218
+
+/* DRA752.iva register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388
+#define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398
+#define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4
+#define DRA752_BANDGAP_TSHUT_IVA_OFFSET 0x3ac
+#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4
+#define DRA752_DTEMP_IVA_0_OFFSET 0x3d0
+#define DRA752_DTEMP_IVA_1_OFFSET 0x3d4
+#define DRA752_DTEMP_IVA_2_OFFSET 0x3d8
+#define DRA752_DTEMP_IVA_3_OFFSET 0x3dc
+#define DRA752_DTEMP_IVA_4_OFFSET 0x3e0
+
+/* DRA752.mpu register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4
+#define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c
+#define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4
+#define DRA752_BANDGAP_TSHUT_MPU_OFFSET 0x1b0
+#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc
+#define DRA752_DTEMP_MPU_0_OFFSET 0x1e0
+#define DRA752_DTEMP_MPU_1_OFFSET 0x1e4
+#define DRA752_DTEMP_MPU_2_OFFSET 0x1e8
+#define DRA752_DTEMP_MPU_3_OFFSET 0x1ec
+#define DRA752_DTEMP_MPU_4_OFFSET 0x1f0
+
+/* DRA752.dspeve register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384
+#define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394
+#define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0
+#define DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET 0x3a8
+#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0
+#define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc
+#define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0
+#define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4
+#define DRA752_DTEMP_DSPEVE_3_OFFSET 0x3c8
+#define DRA752_DTEMP_DSPEVE_4_OFFSET 0x3cc
+
+/* DRA752.gpu register offsets */
+#define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0
+#define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150
+#define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8
+#define DRA752_BANDGAP_TSHUT_GPU_OFFSET 0x1b4
+#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0
+#define DRA752_DTEMP_GPU_0_OFFSET 0x1f4
+#define DRA752_DTEMP_GPU_1_OFFSET 0x1f8
+#define DRA752_DTEMP_GPU_2_OFFSET 0x1fc
+#define DRA752_DTEMP_GPU_3_OFFSET 0x200
+#define DRA752_DTEMP_GPU_4_OFFSET 0x204
+
+/**
+ * Register bitfields for DRA752
+ *
+ * All the macros bellow define the required bits for
+ * controlling temperature on DRA752. Bit defines are
+ * grouped by register.
+ */
+
+/* DRA752.BANDGAP_STATUS_1 */
+#define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31)
+#define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5)
+#define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4)
+#define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3)
+#define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2)
+#define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1)
+#define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0)
+
+/* DRA752.BANDGAP_CTRL_2 */
+#define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22)
+#define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21)
+#define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19)
+#define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK BIT(18)
+#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK BIT(16)
+#define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK BIT(15)
+#define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3)
+#define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2)
+#define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1)
+#define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0)
+
+/* DRA752.BANDGAP_STATUS_2 */
+#define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3)
+#define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2)
+#define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1)
+#define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0)
+
+/* DRA752.BANDGAP_CTRL_1 */
+#define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK (0x3 << 30)
+#define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27)
+#define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23)
+#define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22)
+#define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK BIT(20)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK BIT(19)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK BIT(18)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK BIT(17)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK BIT(16)
+#define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK BIT(15)
+#define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5)
+#define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4)
+#define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3)
+#define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2)
+#define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1)
+#define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0)
+
+/* DRA752.TEMP_SENSOR */
+#define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11)
+#define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10)
+#define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0)
+
+/* DRA752.BANDGAP_THRESHOLD */
+#define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16)
+#define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0)
+
+/* DRA752.TSHUT_THRESHOLD */
+#define DRA752_TSHUT_THRESHOLD_MUXCTRL_MASK BIT(31)
+#define DRA752_TSHUT_THRESHOLD_HOT_MASK (0x3ff << 16)
+#define DRA752_TSHUT_THRESHOLD_COLD_MASK (0x3ff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_CORE */
+#define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_IVA */
+#define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK (0xffffffff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_MPU */
+#define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */
+#define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK (0xffffffff << 0)
+
+/* DRA752.BANDGAP_CUMUL_DTEMP_GPU */
+#define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0)
+
+/**
+ * Temperature limits and thresholds for DRA752
+ *
+ * All the macros bellow are definitions for handling the
+ * ADC conversions and representation of temperature limits
+ * and thresholds for DRA752. Definitions are grouped
+ * by temperature domain.
+ */
+
+/* DRA752.common temperature definitions */
+/* ADC conversion table limits */
+#define DRA752_ADC_START_VALUE 540
+#define DRA752_ADC_END_VALUE 945
+
+/* DRA752.GPU temperature definitions */
+/* bandgap clock limits */
+#define DRA752_GPU_MAX_FREQ 1500000
+#define DRA752_GPU_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_GPU_MIN_TEMP -40000
+#define DRA752_GPU_MAX_TEMP 125000
+#define DRA752_GPU_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_GPU_TSHUT_HOT 915
+#define DRA752_GPU_TSHUT_COLD 900
+#define DRA752_GPU_T_HOT 800
+#define DRA752_GPU_T_COLD 795
+
+/* DRA752.MPU temperature definitions */
+/* bandgap clock limits */
+#define DRA752_MPU_MAX_FREQ 1500000
+#define DRA752_MPU_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_MPU_MIN_TEMP -40000
+#define DRA752_MPU_MAX_TEMP 125000
+#define DRA752_MPU_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_MPU_TSHUT_HOT 915
+#define DRA752_MPU_TSHUT_COLD 900
+#define DRA752_MPU_T_HOT 800
+#define DRA752_MPU_T_COLD 795
+
+/* DRA752.CORE temperature definitions */
+/* bandgap clock limits */
+#define DRA752_CORE_MAX_FREQ 1500000
+#define DRA752_CORE_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_CORE_MIN_TEMP -40000
+#define DRA752_CORE_MAX_TEMP 125000
+#define DRA752_CORE_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_CORE_TSHUT_HOT 915
+#define DRA752_CORE_TSHUT_COLD 900
+#define DRA752_CORE_T_HOT 800
+#define DRA752_CORE_T_COLD 795
+
+/* DRA752.DSPEVE temperature definitions */
+/* bandgap clock limits */
+#define DRA752_DSPEVE_MAX_FREQ 1500000
+#define DRA752_DSPEVE_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_DSPEVE_MIN_TEMP -40000
+#define DRA752_DSPEVE_MAX_TEMP 125000
+#define DRA752_DSPEVE_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_DSPEVE_TSHUT_HOT 915
+#define DRA752_DSPEVE_TSHUT_COLD 900
+#define DRA752_DSPEVE_T_HOT 800
+#define DRA752_DSPEVE_T_COLD 795
+
+/* DRA752.IVA temperature definitions */
+/* bandgap clock limits */
+#define DRA752_IVA_MAX_FREQ 1500000
+#define DRA752_IVA_MIN_FREQ 1000000
+/* sensor limits */
+#define DRA752_IVA_MIN_TEMP -40000
+#define DRA752_IVA_MAX_TEMP 125000
+#define DRA752_IVA_HYST_VAL 5000
+/* interrupts thresholds */
+#define DRA752_IVA_TSHUT_HOT 915
+#define DRA752_IVA_TSHUT_COLD 900
+#define DRA752_IVA_T_HOT 800
+#define DRA752_IVA_T_COLD 795
+
+#endif /* __DRA752_BANDGAP_H */
diff --git a/drivers/staging/ti-soc-thermal/dra752-thermal-data.c b/drivers/staging/ti-soc-thermal/dra752-thermal-data.c
--- /dev/null
@@ -0,0 +1,476 @@
+/*
+ * DRA752 thermal data.
+ *
+ * Copyright (C) 2013 Texas Instruments Inc.
+ * Contact:
+ * Eduardo Valentin <eduardo.valentin@ti.com>
+ * Tero Kristo <t-kristo@ti.com>
+ *
+ * This file is partially autogenerated.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "ti-thermal.h"
+#include "ti-bandgap.h"
+#include "dra752-bandgap.h"
+
+/*
+ * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
+ * IVA and DSPEVE need to describe the individual registers and
+ * bit fields.
+ */
+
+/*
+ * DRA752 CORE thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_core_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
+};
+
+/*
+ * DRA752 IVA thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_iva_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
+};
+
+/*
+ * DRA752 MPU thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_mpu_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
+};
+
+/*
+ * DRA752 DSPEVE thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_dspeve_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
+};
+
+/*
+ * DRA752 GPU thermal sensor register offsets and bit-fields
+ */
+static struct temp_sensor_registers
+dra752_gpu_temp_sensor_registers = {
+ .temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
+ .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
+ .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
+ .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
+ .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
+ .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
+ .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
+ .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
+ .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
+ .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
+ .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,
+ .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
+ .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
+ .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
+ .tshut_threshold = DRA752_BANDGAP_TSHUT_GPU_OFFSET,
+ .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
+ .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
+ .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
+ .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
+ .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
+ .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
+ .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET,
+ .ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET,
+ .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
+ .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
+ .ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET,
+ .ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET,
+ .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
+};
+
+/* Thresholds and limits for DRA752 MPU temperature sensor */
+static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
+ .tshut_hot = DRA752_MPU_TSHUT_HOT,
+ .tshut_cold = DRA752_MPU_TSHUT_COLD,
+ .t_hot = DRA752_MPU_T_HOT,
+ .t_cold = DRA752_MPU_T_COLD,
+ .min_freq = DRA752_MPU_MIN_FREQ,
+ .max_freq = DRA752_MPU_MAX_FREQ,
+ .max_temp = DRA752_MPU_MAX_TEMP,
+ .min_temp = DRA752_MPU_MIN_TEMP,
+ .hyst_val = DRA752_MPU_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/* Thresholds and limits for DRA752 GPU temperature sensor */
+static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
+ .tshut_hot = DRA752_GPU_TSHUT_HOT,
+ .tshut_cold = DRA752_GPU_TSHUT_COLD,
+ .t_hot = DRA752_GPU_T_HOT,
+ .t_cold = DRA752_GPU_T_COLD,
+ .min_freq = DRA752_GPU_MIN_FREQ,
+ .max_freq = DRA752_GPU_MAX_FREQ,
+ .max_temp = DRA752_GPU_MAX_TEMP,
+ .min_temp = DRA752_GPU_MIN_TEMP,
+ .hyst_val = DRA752_GPU_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/* Thresholds and limits for DRA752 CORE temperature sensor */
+static struct temp_sensor_data dra752_core_temp_sensor_data = {
+ .tshut_hot = DRA752_CORE_TSHUT_HOT,
+ .tshut_cold = DRA752_CORE_TSHUT_COLD,
+ .t_hot = DRA752_CORE_T_HOT,
+ .t_cold = DRA752_CORE_T_COLD,
+ .min_freq = DRA752_CORE_MIN_FREQ,
+ .max_freq = DRA752_CORE_MAX_FREQ,
+ .max_temp = DRA752_CORE_MAX_TEMP,
+ .min_temp = DRA752_CORE_MIN_TEMP,
+ .hyst_val = DRA752_CORE_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/* Thresholds and limits for DRA752 DSPEVE temperature sensor */
+static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
+ .tshut_hot = DRA752_DSPEVE_TSHUT_HOT,
+ .tshut_cold = DRA752_DSPEVE_TSHUT_COLD,
+ .t_hot = DRA752_DSPEVE_T_HOT,
+ .t_cold = DRA752_DSPEVE_T_COLD,
+ .min_freq = DRA752_DSPEVE_MIN_FREQ,
+ .max_freq = DRA752_DSPEVE_MAX_FREQ,
+ .max_temp = DRA752_DSPEVE_MAX_TEMP,
+ .min_temp = DRA752_DSPEVE_MIN_TEMP,
+ .hyst_val = DRA752_DSPEVE_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/* Thresholds and limits for DRA752 IVA temperature sensor */
+static struct temp_sensor_data dra752_iva_temp_sensor_data = {
+ .tshut_hot = DRA752_IVA_TSHUT_HOT,
+ .tshut_cold = DRA752_IVA_TSHUT_COLD,
+ .t_hot = DRA752_IVA_T_HOT,
+ .t_cold = DRA752_IVA_T_COLD,
+ .min_freq = DRA752_IVA_MIN_FREQ,
+ .max_freq = DRA752_IVA_MAX_FREQ,
+ .max_temp = DRA752_IVA_MAX_TEMP,
+ .min_temp = DRA752_IVA_MIN_TEMP,
+ .hyst_val = DRA752_IVA_HYST_VAL,
+ .update_int1 = 1000,
+ .update_int2 = 2000,
+};
+
+/*
+ * DRA752 : Temperature values in milli degree celsius
+ * ADC code values from 540 to 945
+ */
+static
+int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = {
+ /* Index 540 - 549 */
+ -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
+ -37800,
+ /* Index 550 - 559 */
+ -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
+ -33400,
+ /* Index 560 - 569 */
+ -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
+ -29400,
+ /* Index 570 - 579 */
+ -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
+ -25000,
+ /* Index 580 - 589 */
+ -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400,
+ -21000,
+ /* Index 590 - 599 */
+ -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
+ -16600,
+ /* Index 600 - 609 */
+ -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
+ -12500,
+ /* Index 610 - 619 */
+ -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
+ -8200,
+ /* Index 620 - 629 */
+ -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500,
+ -3900,
+ /* Index 630 - 639 */
+ -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200,
+ 200,
+ /* Index 640 - 649 */
+ 600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900,
+ 4500,
+ /* Index 650 - 659 */
+ 5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200,
+ 8600,
+ /* Index 660 - 669 */
+ 9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200,
+ 12700,
+ /* Index 670 - 679 */
+ 13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600,
+ 17000,
+ /* Index 680 - 689 */
+ 17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600,
+ 21000,
+ /* Index 690 - 699 */
+ 21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000,
+ 25400,
+ /* Index 700 - 709 */
+ 25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000,
+ 29400,
+ /* Index 710 - 719 */
+ 29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400,
+ 33800,
+ /* Index 720 - 729 */
+ 34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400,
+ 37800,
+ /* Index 730 - 739 */
+ 38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400,
+ 41800,
+ /* Index 740 - 749 */
+ 42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800,
+ 46200,
+ /* Index 750 - 759 */
+ 46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800,
+ 50200,
+ /* Index 760 - 769 */
+ 50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800,
+ 54200,
+ /* Index 770 - 779 */
+ 54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200,
+ 58600,
+ /* Index 780 - 789 */
+ 59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200,
+ 62600,
+ /* Index 790 - 799 */
+ 63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
+ 66600,
+ /* Index 800 - 809 */
+ 67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200,
+ 70600,
+ /* Index 810 - 819 */
+ 71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600,
+ 75000,
+ /* Index 820 - 829 */
+ 75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600,
+ 79000,
+ /* Index 830 - 839 */
+ 79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600,
+ 83000,
+ /* Index 840 - 849 */
+ 83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600,
+ 87000,
+ /* Index 850 - 859 */
+ 87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600,
+ 91000,
+ /* Index 860 - 869 */
+ 91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600,
+ 95000,
+ /* Index 870 - 879 */
+ 95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000,
+ 99400,
+ /* Index 880 - 889 */
+ 99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
+ 103400,
+ /* Index 890 - 899 */
+ 103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
+ 107400,
+ /* Index 900 - 909 */
+ 107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
+ 111400,
+ /* Index 910 - 919 */
+ 111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
+ 115400,
+ /* Index 920 - 929 */
+ 115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
+ 119400,
+ /* Index 930 - 939 */
+ 119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000,
+ 123400,
+ /* Index 940 - 945 */
+ 123800, 124200, 124600, 124900, 125000, 125000,
+};
+
+/* DRA752 data */
+const struct ti_bandgap_data dra752_data = {
+ .features = TI_BANDGAP_FEATURE_TSHUT_CONFIG |
+ TI_BANDGAP_FEATURE_FREEZE_BIT |
+ TI_BANDGAP_FEATURE_TALERT |
+ TI_BANDGAP_FEATURE_COUNTER_DELAY |
+ TI_BANDGAP_FEATURE_HISTORY_BUFFER,
+ .fclock_name = "l3instr_ts_gclk_div",
+ .div_ck_name = "l3instr_ts_gclk_div",
+ .conv_table = dra752_adc_to_temp,
+ .adc_start_val = DRA752_ADC_START_VALUE,
+ .adc_end_val = DRA752_ADC_END_VALUE,
+ .expose_sensor = ti_thermal_expose_sensor,
+ .remove_sensor = ti_thermal_remove_sensor,
+ .sensors = {
+ {
+ .registers = &dra752_mpu_temp_sensor_registers,
+ .ts_data = &dra752_mpu_temp_sensor_data,
+ .domain = "cpu",
+ .register_cooling = ti_thermal_register_cpu_cooling,
+ .unregister_cooling = ti_thermal_unregister_cpu_cooling,
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ {
+ .registers = &dra752_gpu_temp_sensor_registers,
+ .ts_data = &dra752_gpu_temp_sensor_data,
+ .domain = "gpu",
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ {
+ .registers = &dra752_core_temp_sensor_registers,
+ .ts_data = &dra752_core_temp_sensor_data,
+ .domain = "core",
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ {
+ .registers = &dra752_dspeve_temp_sensor_registers,
+ .ts_data = &dra752_dspeve_temp_sensor_data,
+ .domain = "dspeve",
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ {
+ .registers = &dra752_iva_temp_sensor_registers,
+ .ts_data = &dra752_iva_temp_sensor_data,
+ .domain = "iva",
+ .slope = DRA752_GRADIENT_SLOPE,
+ .constant = DRA752_GRADIENT_CONST,
+ .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
+ .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
+ },
+ },
+ .sensor_count = 5,
+};
diff --git a/drivers/staging/ti-soc-thermal/ti-bandgap.c b/drivers/staging/ti-soc-thermal/ti-bandgap.c
index 4c25aea26f7d3356260abb20608900626e22622c..16dd07b6850a42ebf55ff51c565337a63114ca70 100644 (file)
.compatible = "ti,omap5430-bandgap",
.data = (void *)&omap5430_data,
},
+#endif
+#ifdef CONFIG_DRA752_THERMAL
+ {
+ .compatible = "ti,dra752-bandgap",
+ .data = (void *)&dra752_data,
+ },
#endif
/* Sentinel */
{ },
diff --git a/drivers/staging/ti-soc-thermal/ti-bandgap.h b/drivers/staging/ti-soc-thermal/ti-bandgap.h
index 5f4794abf58345d5b4b7bc09f8636e203c48c5fd..b3adf72f252d310779e5014b9ee272bf2a499946 100644 (file)
#define omap5430_data NULL
#endif
+#ifdef CONFIG_DRA752_THERMAL
+extern const struct ti_bandgap_data dra752_data;
+#else
+#define dra752_data NULL
+#endif
#endif
diff --git a/drivers/staging/ti-soc-thermal/ti-thermal-common.c b/drivers/staging/ti-soc-thermal/ti-thermal-common.c
index e3c5e677eaa5c7a13007354b9fa3d2f99bc4b125..8e67ebf98404bcc69dad79f146133ba17d52d17e 100644 (file)
/* common data structures */
struct ti_thermal_data {
struct thermal_zone_device *ti_thermal;
+ struct thermal_zone_device *pcb_tz;
struct thermal_cooling_device *cool_dev;
struct ti_bandgap *bgp;
enum thermal_device_mode mode;
static inline int ti_thermal_get_temp(struct thermal_zone_device *thermal,
unsigned long *temp)
{
+ struct thermal_zone_device *pcb_tz = NULL;
struct ti_thermal_data *data = thermal->devdata;
struct ti_bandgap *bgp;
const struct ti_temp_sensor *s;
- int ret, tmp, pcb_temp, slope, constant;
+ int ret, tmp, slope, constant;
+ unsigned long pcb_temp;
if (!data)
return 0;
if (ret)
return ret;
- pcb_temp = 0;
- /* TODO: Introduce pcb temperature lookup */
+ /* Default constants */
+ slope = s->slope;
+ constant = s->constant;
+
+ pcb_tz = data->pcb_tz;
/* In case pcb zone is available, use the extrapolation rule with it */
- if (pcb_temp) {
- tmp -= pcb_temp;
- slope = s->slope_pcb;
- constant = s->constant_pcb;
- } else {
- slope = s->slope;
- constant = s->constant;
+ if (!IS_ERR_OR_NULL(pcb_tz)) {
+ ret = thermal_zone_get_temp(pcb_tz, &pcb_temp);
+ if (!ret) {
+ tmp -= pcb_temp; /* got a valid PCB temp */
+ slope = s->slope_pcb;
+ constant = s->constant_pcb;
+ } else {
+ dev_err(bgp->dev,
+ "Failed to read PCB state. Using defaults\n");
+ }
}
*temp = ti_thermal_hotspot_temperature(tmp, slope, constant);
data->sensor_id = id;
data->bgp = bgp;
data->mode = THERMAL_DEVICE_ENABLED;
+ data->pcb_tz = thermal_zone_get_zone_by_name("pcb");
INIT_WORK(&data->thermal_wq, ti_thermal_work);
return data;
diff --git a/drivers/staging/ti-soc-thermal/ti-thermal.h b/drivers/staging/ti-soc-thermal/ti-thermal.h
index 8e9256d6c65cc65604f648c8ef55a875855c80c4..9e538035690269c1962688e4e7fa71ea114e1035 100644 (file)
#define OMAP_GRADIENT_SLOPE_5430_GPU 117
#define OMAP_GRADIENT_CONST_5430_GPU -2992
+#define DRA752_GRADIENT_SLOPE 0
+#define DRA752_GRADIENT_CONST 2000
+
/* PCB sensor calculation constants */
#define OMAP_GRADIENT_SLOPE_W_PCB_4430 0
#define OMAP_GRADIENT_CONST_W_PCB_4430 20000
#define OMAP_GRADIENT_SLOPE_W_PCB_5430_GPU 464
#define OMAP_GRADIENT_CONST_W_PCB_5430_GPU -5102
+#define DRA752_GRADIENT_SLOPE_W_PCB 0
+#define DRA752_GRADIENT_CONST_W_PCB 2000
+
/* trip points of interest in milicelsius (at hotspot level) */
#define OMAP_TRIP_COLD 100000
#define OMAP_TRIP_HOT 110000
diff --git a/drivers/staging/ti-soc-thermal/ti_soc_thermal.txt b/drivers/staging/ti-soc-thermal/ti_soc_thermal.txt
index a4a33d1a07464a75b0b00e31adcb1b5c159144ce..25697a53a98e19e55d48beb1fcf1b354da06e14f 100644 (file)
0x4a0023C0 0x3c>;
compatible = "ti,omap5430-bandgap";
};
+
+DRA752:
+bandgap {
+ reg = <0x4a0021e0 0xc
+ 0x4a00232c 0xc
+ 0x4a002380 0x2c
+ 0x4a0023C0 0x3c
+ 0x4a002564 0x8
+ 0x4a002574 0x50>;
+ compatible = "ti,dra752-bandgap";
+ interrupts = <0 126 4>; /* talert */
+};
index 1a19a2f4ba2744b7a7d06abe1f949224f83ad3c5..9edf0e321637daf3c532bb7f95e1553dde0a08cc 100644 (file)
{
enum thermal_trend trend;
- if (!tz->ops->get_trend || tz->ops->get_trend(tz, trip, &trend)) {
+ if (tz->emul_temperature || !tz->ops->get_trend ||
+ tz->ops->get_trend(tz, trip, &trend)) {
if (tz->temperature > tz->last_temperature)
trend = THERMAL_TREND_RAISING;
else if (tz->temperature < tz->last_temperature)
monitor_thermal_zone(tz);
}
-static int thermal_zone_get_temp(struct thermal_zone_device *tz,
- unsigned long *temp)
+/**
+ * thermal_zone_get_temp() - returns its the temperature of thermal zone
+ * @tz: a valid pointer to a struct thermal_zone_device
+ * @temp: a valid pointer to where to store the resulting temperature.
+ *
+ * When a valid thermal zone reference is passed, it will fetch its
+ * temperature and fill @temp.
+ *
+ * Return: On success returns 0, an error code otherwise
+ */
+int thermal_zone_get_temp(struct thermal_zone_device *tz, unsigned long *temp)
{
- int ret = 0;
+ int ret = -EINVAL;
#ifdef CONFIG_THERMAL_EMULATION
int count;
unsigned long crit_temp = -1UL;
enum thermal_trip_type type;
#endif
+ if (IS_ERR_OR_NULL(tz))
+ goto exit;
+
mutex_lock(&tz->lock);
ret = tz->ops->get_temp(tz, temp);
skip_emul:
#endif
mutex_unlock(&tz->lock);
+exit:
return ret;
}
+EXPORT_SYMBOL_GPL(thermal_zone_get_temp);
static void update_temperature(struct thermal_zone_device *tz)
{
}
EXPORT_SYMBOL(thermal_zone_device_unregister);
+/**
+ * thermal_zone_get_zone_by_name() - search for a zone and returns its ref
+ * @name: thermal zone name to fetch the temperature
+ *
+ * When only one zone is found with the passed name, returns a reference to it.
+ *
+ * Return: On success returns a reference to an unique thermal zone with
+ * matching name equals to @name, an ERR_PTR otherwise (-EINVAL for invalid
+ * paramenters, -ENODEV for not found and -EEXIST for multiple matches).
+ */
+struct thermal_zone_device *thermal_zone_get_zone_by_name(const char *name)
+{
+ struct thermal_zone_device *pos = NULL, *ref = ERR_PTR(-EINVAL);
+ unsigned int found = 0;
+
+ if (!name)
+ goto exit;
+
+ mutex_lock(&thermal_list_lock);
+ list_for_each_entry(pos, &thermal_tz_list, node)
+ if (!strnicmp(name, pos->type, THERMAL_NAME_LENGTH)) {
+ found++;
+ ref = pos;
+ }
+ mutex_unlock(&thermal_list_lock);
+
+ /* nothing has been found, thus an error code for it */
+ if (found == 0)
+ ref = ERR_PTR(-ENODEV);
+ else if (found > 1)
+ /* Success only when an unique zone is found */
+ ref = ERR_PTR(-EEXIST);
+
+exit:
+ return ref;
+}
+EXPORT_SYMBOL_GPL(thermal_zone_get_zone_by_name);
+
#ifdef CONFIG_NET
static struct genl_family thermal_event_genl_family = {
.id = GENL_ID_GENERATE,
index 46dbfb7f87852e2f8ab6b3de606a6837c20a6f84..bbe280e1343bf9396127bde0933063082bab299e 100644 (file)
int designrev;
int sw_revision;
+ int palmas_id;
/* IRQ Data */
int irq;
u32 irq_mask;
};
+enum pmic_ids {
+ TWL6035,
+ TWL6037,
+ TPS65913,
+ TPS659038,
+};
+
enum palmas_regulators {
/* SMPS regulators */
PALMAS_REG_SMPS12,
enum omap_dwc3_vbus_id_status linkstat;
};
+/**
+ * struct palmas_pmic_data - Maintains the specific data for PMICs of PALMAS
+ * family
+ * @irq_chip: regmap_irq_chip specific to individual members
+ * of PALMAS family.
+ * @regmap_config: regmap_config specific to the individual members
+ * of PALMAS family.
+ * @mfd_cell: mfd cell specific to the individual members of
+ * PALMAS family.
+ * @id: Id of the member of the PALMAS family.
+ * @has_usb: Flag indicating whether PMIC supports USB
+ */
+struct palmas_pmic_data {
+ struct regmap_irq_chip *irq_chip;
+ const struct regmap_config *regmap_config;
+ const struct mfd_cell *mfd_cell;
+ int id;
+ int has_usb;
+};
+
#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
enum usb_irq_events {
#define PALMAS_GPADC_TRIM15 0xE
#define PALMAS_GPADC_TRIM16 0xF
+static inline int palmas_read(struct palmas *palmas, unsigned int base,
+ unsigned int reg, unsigned int *val)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_read(palmas->regmap[slave_id], addr, val);
+}
+
+static inline int palmas_write(struct palmas *palmas, unsigned int base,
+ unsigned int reg, unsigned int value)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_write(palmas->regmap[slave_id], addr, value);
+}
+
+static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
+ unsigned int reg, const void *val, size_t val_count)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_bulk_write(palmas->regmap[slave_id], addr,
+ val, val_count);
+}
+
+static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
+ unsigned int reg, void *val, size_t val_count)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_bulk_read(palmas->regmap[slave_id], addr,
+ val, val_count);
+}
+
+static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
+ unsigned int reg, unsigned int mask, unsigned int val)
+{
+ unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
+ int slave_id = PALMAS_BASE_TO_SLAVE(base);
+
+ return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
+}
+
+static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
+{
+ return regmap_irq_get_virq(palmas->irq_data, irq);
+}
+
#endif /* __LINUX_MFD_PALMAS_H */
index d10bb0f39c5e72fd6bb7747e47761d062f75c981..eea5af05a948b0c2cafa8bc89a0f2c180ad9d4a8 100644 (file)
struct blocking_notifier_head notifier;
struct mutex mutex; /* consumer lock */
+ struct task_struct *lock_owner;
+ int lock_count;
struct module *owner;
struct device dev;
struct regulation_constraints *constraints;
index e3c0ae9bb1faf876afca191701e481ecc30a4f1b..6400245bf3f64b0687cca473cbf37a42240b27cf 100644 (file)
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
struct thermal_cooling_device *thermal_cooling_device_register(char *, void *,
const struct thermal_cooling_device_ops *);
void thermal_cooling_device_unregister(struct thermal_cooling_device *);
+struct thermal_zone_device *thermal_zone_get_zone_by_name(const char *name);
+int thermal_zone_get_temp(struct thermal_zone_device *tz, unsigned long *temp);
int get_tz_trend(struct thermal_zone_device *, int);
struct thermal_instance *get_thermal_instance(struct thermal_zone_device *,