arm: dts: dra7xx: Add gpu data

GPU DT entry for DRA7XX.

Change-Id: I94c9a33f942b590244692001eb2ec8f9c98187c3
Signed-off-by: Hemant Hariyani <hemanthariyani@ti.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 659b3b766312822feae18f3c702418a4b5172151..7f92247a03fc2b9f0ad120249bf8d2a09c5f2f94 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -113,6 +113,31 @@
                        compatible = "ti,omap-clock";
                };
 
+               dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
+               dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
+               dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
+               gpu_core_gclk_mux: gpu_core_gclk_mux {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
+               gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap-clock";
+               };
+
                sdma: dma-controller@4a056000 {
                        compatible = "ti,omap4430-sdma";
                        reg = <0x4a056000 0x1000>;
@@ -360,6 +385,23 @@
                        ti,hwmods = "dmm";
                };
 
+               gpu: gpu@0x56000000 {
+                       compatible = "ti,omap4-gpu";
+                       reg = <0x56000000 0xffff>;
+                       interrupts = <0 21 0x4>;
+                       ti,hwmods = "gpu";
+                       operating-points = <
+                               /* kHz    uV */
+                               425600  1090000
+                               500000  1210000
+                               532000  1280000
+                               >;
+                       clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>,
+                                       <&dpll_gpu_m2_ck>, <&gpu_core_gclk_mux>,
+                                       <&gpu_hyd_gclk_mux>;
+                       clock-names = "core", "per", "gpu", "gpu_core", "gpu_hyd";
+               };
+
                bandgap {
                        reg = <0x4a0021e0 0xc
                                0x4a00232c 0xc