media: ti-vpe: vpe: Add cropping ioctl support
Add crop ioctl ops. For VPE, cropping only makes sense with the input to VPE, or
the V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE buffer type.
For the CAPTURE type, a S_CROP ioctl results in setting the crop region as the
whole image itself, hence making crop dimensions same as the pix dimensions.
Setting the crop successfully should result in re-configuration of those
registers which are affected when either source or destination dimensions
change, set_srcdst_params() is called for thist purpose.
Some standard crop parameter checks are done in __vpe_try_crop().
Change-Id: I9329dee27db526bde54000552b1184e8f061244f
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Add crop ioctl ops. For VPE, cropping only makes sense with the input to VPE, or
the V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE buffer type.
For the CAPTURE type, a S_CROP ioctl results in setting the crop region as the
whole image itself, hence making crop dimensions same as the pix dimensions.
Setting the crop successfully should result in re-configuration of those
registers which are affected when either source or destination dimensions
change, set_srcdst_params() is called for thist purpose.
Some standard crop parameter checks are done in __vpe_try_crop().
Change-Id: I9329dee27db526bde54000552b1184e8f061244f
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
media: vb2: verify data_offset only if nonzero bytesused
verify_planes would fail if the user space fills up the data_offset field
and bytesused is left as zero. Correct this.
When comparing data_offset > bytesused, bypass the check if the
bytesused field is set to zero.
Change-Id: I4c63bc03f6d455ce00a56d63df08c624579bc831
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
verify_planes would fail if the user space fills up the data_offset field
and bytesused is left as zero. Correct this.
When comparing data_offset > bytesused, bypass the check if the
bytesused field is set to zero.
Change-Id: I4c63bc03f6d455ce00a56d63df08c624579bc831
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Merge branch 'p-ti-linux-3.14.y-common/audio-for-next' of git://git.ti.com/android-sdk/kernel-audio into p-ti-linux-3.14.y-common
* 'p-ti-linux-3.14.y-common/audio-for-next' of git://git.ti.com/android-sdk/kernel-audio: (21 commits)
ARM: dts: dra7*-evm: Enable McASP3 DAT port and AFIFO
ARM: dts: DRA7: Use eDMA for McASP3
ARM: dts: DRA7: Add eDMA and eDMA xbar nodes
ARM: dts: DRA7: Update sDMA xbar to new mechanism
ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
ARM: edma: Mark xbar related channels as used
ASoC: davinci-mcasp: Register eDMA platform driver for DRA7xx
dmaengine: ti-dma-crossbar: Add support for eDMA xbar
dmaengine: ti-dma-crossbar: Make idr xbar instance-specific
dmaengine: Add driver for TI DMA crossbar on DRA7x
dmaengine: omap-dma: Reduce the number of virtual channels
dmaengine: omap-dma: Remove mapping between virtual channels and requests
dmaengine: omap-dma: Take DMA request number from DT if it is available
dmaengine: omap-dma: Use defines for dma channels and request count
Documentation: devicetree: dma: Binding documentation for TI DMA crossbar
dmaengine: of_dma: Support for DMA routers
Revert "drivers: dma: omap-dma: Avoid hard-coding of the dma-request channels"
Revert "drivers: dma: omap-dma: Add a seperate xlate function to get router data"
Revert "drivers: omap-dma: Add crossbar line as a resource to omap_chan structure"
Revert "drivers: dma: Add dma crossbar driver"
...
Change-Id: Idf3b559692a62ca766040a683b6ce3eed8a5ff7a
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* 'p-ti-linux-3.14.y-common/audio-for-next' of git://git.ti.com/android-sdk/kernel-audio: (21 commits)
ARM: dts: dra7*-evm: Enable McASP3 DAT port and AFIFO
ARM: dts: DRA7: Use eDMA for McASP3
ARM: dts: DRA7: Add eDMA and eDMA xbar nodes
ARM: dts: DRA7: Update sDMA xbar to new mechanism
ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
ARM: edma: Mark xbar related channels as used
ASoC: davinci-mcasp: Register eDMA platform driver for DRA7xx
dmaengine: ti-dma-crossbar: Add support for eDMA xbar
dmaengine: ti-dma-crossbar: Make idr xbar instance-specific
dmaengine: Add driver for TI DMA crossbar on DRA7x
dmaengine: omap-dma: Reduce the number of virtual channels
dmaengine: omap-dma: Remove mapping between virtual channels and requests
dmaengine: omap-dma: Take DMA request number from DT if it is available
dmaengine: omap-dma: Use defines for dma channels and request count
Documentation: devicetree: dma: Binding documentation for TI DMA crossbar
dmaengine: of_dma: Support for DMA routers
Revert "drivers: dma: omap-dma: Avoid hard-coding of the dma-request channels"
Revert "drivers: dma: omap-dma: Add a seperate xlate function to get router data"
Revert "drivers: omap-dma: Add crossbar line as a resource to omap_chan structure"
Revert "drivers: dma: Add dma crossbar driver"
...
Change-Id: Idf3b559692a62ca766040a683b6ce3eed8a5ff7a
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
ARM: dts: dra7*-evm: Enable McASP3 DAT port and AFIFO
Now that McASP3 is using eDMA, the DAT port and AFIFO can
be safely enabled.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Now that McASP3 is using eDMA, the DAT port and AFIFO can
be safely enabled.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ARM: dts: DRA7: Use eDMA for McASP3
McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead. This
restriction is also applicable for McASP1 and McASP2.
This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.
The addressing mode used in eDMA is INC, so above silicon
limitation doesn't have any impact.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead. This
restriction is also applicable for McASP1 and McASP2.
This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.
The addressing mode used in eDMA is INC, so above silicon
limitation doesn't have any impact.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ARM: dts: DRA7: Add eDMA and eDMA xbar nodes
Add the devicetree nodes for the eDMA and the eDMA
crossbar.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Add the devicetree nodes for the eDMA and the eDMA
crossbar.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ARM: dts: DRA7: Update sDMA xbar to new mechanism
Migrate sDMA crossbar related properties to the new
dra7-dma-crossbar mechanism.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Migrate sDMA crossbar related properties to the new
dra7-dma-crossbar mechanism.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
Add hwmod data for the eDMA blocks:
- TPCC: Third-party channel controller
- TPTC0: Third-party transfer controller 0
- TPTC1: Third-party transfer controller 1
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Add hwmod data for the eDMA blocks:
- TPCC: Third-party channel controller
- TPTC0: Third-party transfer controller 0
- TPTC1: Third-party transfer controller 1
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ARM: edma: Mark xbar related channels as used
eDMA channels not being used in the platform are assumed to
be without event association. The ones detected as 'used'
are those from DT nodes whose "dmas" property have a direct
reference to the eDMA controller node.
However, when a DMA crossbar is present the "dmas" property
actually points to the crossbar node, not to the DMA controller.
The DMA crossbar related channels can be identified in the
controller's translation function and marked as 'used' in
the platform.
Due to the current direct mapping between DMA requests and eDMA
channels, it's possible that the DMA channel corresponding to
the crossbar-translated DMA request might have been already
taken by another client. The conflict might occur if such
client uses memcpy transfer type.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
eDMA channels not being used in the platform are assumed to
be without event association. The ones detected as 'used'
are those from DT nodes whose "dmas" property have a direct
reference to the eDMA controller node.
However, when a DMA crossbar is present the "dmas" property
actually points to the crossbar node, not to the DMA controller.
The DMA crossbar related channels can be identified in the
controller's translation function and marked as 'used' in
the platform.
Due to the current direct mapping between DMA requests and eDMA
channels, it's possible that the DMA channel corresponding to
the crossbar-translated DMA request might have been already
taken by another client. The conflict might occur if such
client uses memcpy transfer type.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ASoC: davinci-mcasp: Register eDMA platform driver for DRA7xx
McASP in DRA7xx SoC family (VERSION_4) can use either sDMA
or eDMA. In order to be able to use either DMA controller
make sure their corresponding platform driver is registered.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
McASP in DRA7xx SoC family (VERSION_4) can use either sDMA
or eDMA. In order to be able to use either DMA controller
make sure their corresponding platform driver is registered.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
dmaengine: ti-dma-crossbar: Add support for eDMA xbar
eDMA crossbar works exactly the same way as sDMA, but sDMA
requires an offset of 1, while no offset is needed for eDMA.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
eDMA crossbar works exactly the same way as sDMA, but sDMA
requires an offset of 1, while no offset is needed for eDMA.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
dmaengine: ti-dma-crossbar: Make idr xbar instance-specific
In preparation for supporting multiple DMA crossbar instances,
make the idr xbar instance specific.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
In preparation for supporting multiple DMA crossbar instances,
make the idr xbar instance specific.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
dmaengine: Add driver for TI DMA crossbar on DRA7x
[ Upstream commit a074ae38f859b90bd259f5df43784834b44412d1 ]
The DRA7x has more peripherals with DMA requests than the sDMA can handle:
205 vs 127. All DMA requests are routed through the DMA crossbar, which can
be configured to route selected incoming DMA requests to specific sDMA
request.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
[ Upstream commit a074ae38f859b90bd259f5df43784834b44412d1 ]
The DRA7x has more peripherals with DMA requests than the sDMA can handle:
205 vs 127. All DMA requests are routed through the DMA crossbar, which can
be configured to route selected incoming DMA requests to specific sDMA
request.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
dmaengine: omap-dma: Reduce the number of virtual channels
[ Upstream commit 8a32222693af0edf4ad0ed2c6c4c9e383fd922dd ]
Since the mapping between the hardware request lines and channels has been
removed it no longer make sense to have too many channels.
Set the number of channels to match with the number of logical channels
supported by sDMA.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
[ Upstream commit 8a32222693af0edf4ad0ed2c6c4c9e383fd922dd ]
Since the mapping between the hardware request lines and channels has been
removed it no longer make sense to have too many channels.
Set the number of channels to match with the number of logical channels
supported by sDMA.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
dmaengine: omap-dma: Remove mapping between virtual channels and requests
[ Upstream commit eea531ea4147f60708c7ee9e53b5735ec387adb6 ]
Do not direct map the virtual channels to sDMA request number. When the
sDMA is behind of a crossbar this direct mapping can cause situations when
certain channel can not be requested since the crossbar request number
will no longer match with the sDMA request line.
The direct mapping for virtual channels with HW request lines will make it
harder to implement MEM_TO_MEM mode for the driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
[ Upstream commit eea531ea4147f60708c7ee9e53b5735ec387adb6 ]
Do not direct map the virtual channels to sDMA request number. When the
sDMA is behind of a crossbar this direct mapping can cause situations when
certain channel can not be requested since the crossbar request number
will no longer match with the sDMA request line.
The direct mapping for virtual channels with HW request lines will make it
harder to implement MEM_TO_MEM mode for the driver.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
dmaengine: omap-dma: Take DMA request number from DT if it is available
[ Upstream commit de506089e78bc7cea77c64a836f6cfc7fa592219 ]
Use the dma-requests property from DT to get the number of DMA requests.
In case of legacy boot or failure to find the property, use the default
127 as number of requests.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
[ Upstream commit de506089e78bc7cea77c64a836f6cfc7fa592219 ]
Use the dma-requests property from DT to get the number of DMA requests.
In case of legacy boot or failure to find the property, use the default
127 as number of requests.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
dmaengine: omap-dma: Use defines for dma channels and request count
[ Upstream commit 341ce712868d90fd68cc4635b7c9963a026f9207 ]
Instead of magic numbers in the code, use define for number of logical DMA
channels and DMA requests.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
[ Upstream commit 341ce712868d90fd68cc4635b7c9963a026f9207 ]
Instead of magic numbers in the code, use define for number of logical DMA
channels and DMA requests.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Documentation: devicetree: dma: Binding documentation for TI DMA crossbar
[ Upstream commit 73f67d35b5b96eaf6c5d90fc10527c15b135eda2 ]
The DRA7x has more peripherals with DMA requests than the sDMA can handle:
205 vs 127. All DMA requests are routed through the DMA crossbar, which can
be configured to route selected incoming DMA requests to specific request
line of the DMA controller.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
[ Upstream commit 73f67d35b5b96eaf6c5d90fc10527c15b135eda2 ]
The DRA7x has more peripherals with DMA requests than the sDMA can handle:
205 vs 127. All DMA requests are routed through the DMA crossbar, which can
be configured to route selected incoming DMA requests to specific request
line of the DMA controller.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
dmaengine: of_dma: Support for DMA routers
[ Upstream commit 56f13c0d9524c5816f5dc9c91b9d766d6b1064ca ]
DMA routers are transparent devices used to mux DMA requests from
peripherals to DMA controllers. They are used when the SoC integrates more
devices with DMA requests then their controller can handle.
DRA7x is one example of such SoC, where the sDMA can hanlde 128 DMA request
lines, but in SoC level it has 205 DMA requests.
The of_dma_router will be registered as of_dma_controller with special
xlate function and additional parameters. The driver for the router is
responsible to craft the dma_spec (in the of_dma_route_allocate callback)
which can be used to requests a DMA channel from the real DMA controller.
This way the router can be transparent for the system while remaining generic
enough to be used in different environments.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
[ Upstream commit 56f13c0d9524c5816f5dc9c91b9d766d6b1064ca ]
DMA routers are transparent devices used to mux DMA requests from
peripherals to DMA controllers. They are used when the SoC integrates more
devices with DMA requests then their controller can handle.
DRA7x is one example of such SoC, where the sDMA can hanlde 128 DMA request
lines, but in SoC level it has 205 DMA requests.
The of_dma_router will be registered as of_dma_controller with special
xlate function and additional parameters. The driver for the router is
responsible to craft the dma_spec (in the of_dma_route_allocate callback)
which can be used to requests a DMA channel from the real DMA controller.
This way the router can be transparent for the system while remaining generic
enough to be used in different environments.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Revert "drivers: dma: omap-dma: Avoid hard-coding of the dma-request channels"
This reverts commit 732de18cbd4cc7f1b03ed26790ef4e4868d98f16.
This reverts commit 732de18cbd4cc7f1b03ed26790ef4e4868d98f16.
Revert "drivers: dma: omap-dma: Add a seperate xlate function to get router data"
This reverts commit 6e4c8621eb1a69c015ceb2a0d9589dd24fa5b01e.
This reverts commit 6e4c8621eb1a69c015ceb2a0d9589dd24fa5b01e.
Revert "drivers: omap-dma: Add crossbar line as a resource to omap_chan structure"
This reverts commit bcda43ed1153d6701a97ba72313c59d0fdab14ac.
This reverts commit bcda43ed1153d6701a97ba72313c59d0fdab14ac.
Revert "drivers: dma: Add dma crossbar driver"
This reverts commit 4abc176c4500b580d19e03e5c7c6bb9efbc85be5.
This reverts commit 4abc176c4500b580d19e03e5c7c6bb9efbc85be5.
Revert "drivers: dma: of-dma: Add support for dma-request line routers"
This reverts commit dd5cdc95cd8de84150f65732dccbf59b73488a05.
This reverts commit dd5cdc95cd8de84150f65732dccbf59b73488a05.
drm: remove automatic load of omapdrm_pvr
omapdrm plugin patch automatically tries to load the SGX (omapdrm_pvr) kernel
module as part of dev_open. The name of SGX kernel module in Android is
pvrsrvkm.
This patch removes the auto-load of omapdrm_pvr kernel module to ensure common
code base across Linux and Android.
Change-Id: I03d7e92b9e6f9addd41e83614e8878d8cfc244b7
Signed-off-by: Anand Balagopalakrishnan <anandb@ti.com>
omapdrm plugin patch automatically tries to load the SGX (omapdrm_pvr) kernel
module as part of dev_open. The name of SGX kernel module in Android is
pvrsrvkm.
This patch removes the auto-load of omapdrm_pvr kernel module to ensure common
code base across Linux and Android.
Change-Id: I03d7e92b9e6f9addd41e83614e8878d8cfc244b7
Signed-off-by: Anand Balagopalakrishnan <anandb@ti.com>
drm/omap: Add omapdrm plugin API
This work is based on Rob Clark's patch :
http://dev.omapzoom.org/?p=integration/kernel-ubuntu.git;a=commit;h=6a42bc1660b06464f9da796604ecd4934bb31acd
WIP: drm/omap: V2: add plugin API
from the GLP kernel tree available at
http://dev.omapzoom.org/?p=integration/kernel-ubuntu.git;a=summary
Omapdrm is fixed so that it can accept plugins.
Plugin add functions like load/unload etc are added in omap_drv.c
In omap_gem.c GEM object mapping functions has been added
This patch is required for gfx driver to be built as a drm plugin
Subhajit : k3.12: removed const from ioctls table
Anand : k3.14 : rebased with LCPD baseline
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
Signed-off-by: Anand Balagopalakrishnan <anandb@ti.com>
Conflicts:
drivers/gpu/drm/omapdrm/omap_drv.c
drivers/gpu/drm/omapdrm/omap_drv.h
Change-Id: I72133ad08ddd4682320fa2e7f5f4dd017ee92dae
Signed-off-by: Anand Balagopalakrishnan <anandb@ti.com>
This work is based on Rob Clark's patch :
http://dev.omapzoom.org/?p=integration/kernel-ubuntu.git;a=commit;h=6a42bc1660b06464f9da796604ecd4934bb31acd
WIP: drm/omap: V2: add plugin API
from the GLP kernel tree available at
http://dev.omapzoom.org/?p=integration/kernel-ubuntu.git;a=summary
Omapdrm is fixed so that it can accept plugins.
Plugin add functions like load/unload etc are added in omap_drv.c
In omap_gem.c GEM object mapping functions has been added
This patch is required for gfx driver to be built as a drm plugin
Subhajit : k3.12: removed const from ioctls table
Anand : k3.14 : rebased with LCPD baseline
Signed-off-by: Rob Clark <rob@ti.com>
Signed-off-by: Subhajit Paul <subhajit_paul@ti.com>
Signed-off-by: Anand Balagopalakrishnan <anandb@ti.com>
Conflicts:
drivers/gpu/drm/omapdrm/omap_drv.c
drivers/gpu/drm/omapdrm/omap_drv.h
Change-Id: I72133ad08ddd4682320fa2e7f5f4dd017ee92dae
Signed-off-by: Anand Balagopalakrishnan <anandb@ti.com>
ARM: dts: dra7xx-jamr3: Reserve memory for RingIO SR0
Reserve 1MB for RingIO SR0.
Change-Id: Ie1af67266e61f3eb8ad69ea4a3b8bda3a66f7ebf
Signed-off-by: Kishor Jm <kishor.jinde@ti.com>
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Reserve 1MB for RingIO SR0.
Change-Id: Ie1af67266e61f3eb8ad69ea4a3b8bda3a66f7ebf
Signed-off-by: Kishor Jm <kishor.jinde@ti.com>
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ARM: dts: DRA7: add a new dts file to support late attach on IPU2
The 'late attach' functionality has the remote processors configured,
programmed and booted even before the kernel is booted. This includes
loading the necessary firmware into memory, programming the IOMMU,
configuring the required timers, and programming the corresponding
device's clocks and resets.
The omap hwmod init sequence includes resetting all the hwmods and
idling them to put the devices in sane states to make them independent
of bootloader and corresponding drivers. The "ti,no-idle-on-init" and
"ti,no-reset-on-init" attributes are added to specific omap_hwmod's
associated with the IPU2 processor subsystems to support the 'late
attach' feature on these devices, and change the omap hwmod init
behavior.
The "ti,no-reset-on-init" attribute is needed to allow the omap_hwmod
layer to not perform a reset (and thereby reset the programming done
prior to kernel boot). The "ti,no-reset-on-init" is needed to leave the
modules/device in enabled state (and thereby avoid any disabling of the
clocks/modules).
The "ti,late-attach" attribute indicates that the remotecore has already
been loaded and configured and IPU2, MMU_IPU2 and the timers should not
be reconfigured or reset.
These attributes are added in a separate dts file, and includes the
original dts file so that the default configuration stays untouched.
The user can switch the regular dtb file to the dtb generated from
this file to enable the "late attach" functionality.
TODO:
Evaluate if setting of the right attributes for late attach can be achieved
directly from the boot loader. If so, the need for maintaining a separate
dts file for normal operation and 'late attach' operation can be eliminated.
Change-Id: I5c5526816fe94fc80077fcf2554c8cf940b7aaac
Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
The 'late attach' functionality has the remote processors configured,
programmed and booted even before the kernel is booted. This includes
loading the necessary firmware into memory, programming the IOMMU,
configuring the required timers, and programming the corresponding
device's clocks and resets.
The omap hwmod init sequence includes resetting all the hwmods and
idling them to put the devices in sane states to make them independent
of bootloader and corresponding drivers. The "ti,no-idle-on-init" and
"ti,no-reset-on-init" attributes are added to specific omap_hwmod's
associated with the IPU2 processor subsystems to support the 'late
attach' feature on these devices, and change the omap hwmod init
behavior.
The "ti,no-reset-on-init" attribute is needed to allow the omap_hwmod
layer to not perform a reset (and thereby reset the programming done
prior to kernel boot). The "ti,no-reset-on-init" is needed to leave the
modules/device in enabled state (and thereby avoid any disabling of the
clocks/modules).
The "ti,late-attach" attribute indicates that the remotecore has already
been loaded and configured and IPU2, MMU_IPU2 and the timers should not
be reconfigured or reset.
These attributes are added in a separate dts file, and includes the
original dts file so that the default configuration stays untouched.
The user can switch the regular dtb file to the dtb generated from
this file to enable the "late attach" functionality.
TODO:
Evaluate if setting of the right attributes for late attach can be achieved
directly from the boot loader. If so, the need for maintaining a separate
dts file for normal operation and 'late attach' operation can be eliminated.
Change-Id: I5c5526816fe94fc80077fcf2554c8cf940b7aaac
Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
remoteproc/omap: add "late attach" support
Add the necessary support in the OMAP remoteproc driver to enable the
"late attach" functionality. The 'late attach' functionality has the
processors already loaded and running by the time the kernel has booted.
The 'late attach' support in OMAP remoteproc driver is added through
minimal changes like skipping the releasing of the processor reset.
The processor reset is skipped as this relies on the omap_hwmod /
omap_device API which perform a module disable/enable sequence in
addition to the reset programming. Other required functionality is
achieved through the late attach support in the remoteproc driver core.
During late attach, we use non-zeroing dma ops to prevent the kernel
from overwriting already loaded code and data segments. When shutting
down the processor, we restore the normal zeroing dma ops. This allows
the kernel to clear memory when loading a new remoteproc binary or
during error recovery with the current remoteproc binary.
The 'late attach' capability is announced through a "ti,late-attach"
property on the respective remoteproc node in the device tree blob.
The corresponding IOMMU and timer nodes should also have this property
set. All the nodes should also have the "ti,no-idle-on-init" and
"ti,no-reset-on-init" properties set to prevent omap_hwmod from
resetting and idling these devices on boot.
The parsed property is stored in a .late_attach field in the rproc
data structure. The field is used for differentiating a normal boot
from a late-attach boot. The "ti,late-attach" feature is relevant only
for the first time boot of the kernel, and is therefore removed from
the remoteproc device-tree node on the first probe. This prevents the
.late_attach flag from being set for subsequent probes of the remoteproc
node. The flag is also reset during the stopping of the remoteproc,
so that any error recovery results in a regular boot.
Change-Id: If52e3e3980fe0bc76725ef94c0ffce415cfee138
Signed-off-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Add the necessary support in the OMAP remoteproc driver to enable the
"late attach" functionality. The 'late attach' functionality has the
processors already loaded and running by the time the kernel has booted.
The 'late attach' support in OMAP remoteproc driver is added through
minimal changes like skipping the releasing of the processor reset.
The processor reset is skipped as this relies on the omap_hwmod /
omap_device API which perform a module disable/enable sequence in
addition to the reset programming. Other required functionality is
achieved through the late attach support in the remoteproc driver core.
During late attach, we use non-zeroing dma ops to prevent the kernel
from overwriting already loaded code and data segments. When shutting
down the processor, we restore the normal zeroing dma ops. This allows
the kernel to clear memory when loading a new remoteproc binary or
during error recovery with the current remoteproc binary.
The 'late attach' capability is announced through a "ti,late-attach"
property on the respective remoteproc node in the device tree blob.
The corresponding IOMMU and timer nodes should also have this property
set. All the nodes should also have the "ti,no-idle-on-init" and
"ti,no-reset-on-init" properties set to prevent omap_hwmod from
resetting and idling these devices on boot.
The parsed property is stored in a .late_attach field in the rproc
data structure. The field is used for differentiating a normal boot
from a late-attach boot. The "ti,late-attach" feature is relevant only
for the first time boot of the kernel, and is therefore removed from
the remoteproc device-tree node on the first probe. This prevents the
.late_attach flag from being set for subsequent probes of the remoteproc
node. The flag is also reset during the stopping of the remoteproc,
so that any error recovery results in a regular boot.
Change-Id: If52e3e3980fe0bc76725ef94c0ffce415cfee138
Signed-off-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
remoteproc: add "late attach" support
The remoteproc driver core is, in general, responsible for allocating
the memory for firmware segments, parsing and loading the firmware
segments into the allocated memory regions, mapping these memory
regions into associated IOMMUs, starting/releasing the processors
from reset, and finally establishing IPC between the host and the
remote processors.
The "late attach" feature refers to a model wherein a remote processor
has already been configured, loaded and started by some external entity
prior to kernel boot (u-boot, for example), and the remoteproc driver
needs to be configured to 'attach' or establish a connection with the
currently running code on the remote processor without resetting or
reconfiguring the device and associated peripherals. The feature is
being added to support specific use-cases (eg: "early camera" or "early
video"), requiring certain KPI criteria. The feature is currently based
on having a remote processor perform all the necessary activities to
achieve the required KPI in a stand-alone mode without having to rely
on communicating with the MPU or perform any IPC activities until the
remoteproc driver is up.
The "late attach" support in the remoteproc driver core is currently
designed to not perform the loading of the firmware segments, or
programming of the IOMMUs. The driver though still goes through the
sequence of processing the firmware to set up the correct virtio
based IPC transports, and allocating the required memory segments
to mark these memory regions as used/reserved from kernel in the
corresponding rproc device's CMA pools. The driver expects the
allocator to not perform any memory initialization, to avoid wiping
out the pre-loaded code. Virtio-based IPC with the remote processors
is established once the driver completes processing the firmware,
just as in a regular boot.
Signed-off-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Change-Id: I90ba599373523d29a5ea72eaf0e8e43ba0bf3095
Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
The remoteproc driver core is, in general, responsible for allocating
the memory for firmware segments, parsing and loading the firmware
segments into the allocated memory regions, mapping these memory
regions into associated IOMMUs, starting/releasing the processors
from reset, and finally establishing IPC between the host and the
remote processors.
The "late attach" feature refers to a model wherein a remote processor
has already been configured, loaded and started by some external entity
prior to kernel boot (u-boot, for example), and the remoteproc driver
needs to be configured to 'attach' or establish a connection with the
currently running code on the remote processor without resetting or
reconfiguring the device and associated peripherals. The feature is
being added to support specific use-cases (eg: "early camera" or "early
video"), requiring certain KPI criteria. The feature is currently based
on having a remote processor perform all the necessary activities to
achieve the required KPI in a stand-alone mode without having to rely
on communicating with the MPU or perform any IPC activities until the
remoteproc driver is up.
The "late attach" support in the remoteproc driver core is currently
designed to not perform the loading of the firmware segments, or
programming of the IOMMUs. The driver though still goes through the
sequence of processing the firmware to set up the correct virtio
based IPC transports, and allocating the required memory segments
to mark these memory regions as used/reserved from kernel in the
corresponding rproc device's CMA pools. The driver expects the
allocator to not perform any memory initialization, to avoid wiping
out the pre-loaded code. Virtio-based IPC with the remote processors
is established once the driver completes processing the firmware,
just as in a regular boot.
Signed-off-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Change-Id: I90ba599373523d29a5ea72eaf0e8e43ba0bf3095
Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
ARM: dma-mapping: create non-zeroing dma_map_ops
A new dma_ops, 'arm_dma_m_ops', is created from a copy of the
standard 'arm_dma_ops' but with a new non-zeroing .alloc method.
These ops are added mainly to support a 'late attach' feature in
the OMAP remoteproc driver. When remoteproc does a 'late attach'
to a remote processor, it does not load any firmware contents into
memory, but it still needs to allocate the processor's CMA memory
to mark the memory as reserved/used from the kernel. The standard
'arm_dma_ops' contains an .alloc method that zeroes out the memory,
thereby overwriting the firmware code/data in the memory that was
pre-loaded before the Linux kernel has booted.
This scenario is handled by adding a new non-zeroing allocation
function and using it as the .alloc method in a copy of the
'arm_dma_ops'. The so created 'arm_dma_m_ops' will be assigned
as the rproc device's dma_ops when supporting the 'late attach'
functionality.
Signed-off-by: Martin Ambrose <martin@ti.com>
Signed-off-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Change-Id: Ib7437e482a34c94446a85c3b328d067baa439dab
A new dma_ops, 'arm_dma_m_ops', is created from a copy of the
standard 'arm_dma_ops' but with a new non-zeroing .alloc method.
These ops are added mainly to support a 'late attach' feature in
the OMAP remoteproc driver. When remoteproc does a 'late attach'
to a remote processor, it does not load any firmware contents into
memory, but it still needs to allocate the processor's CMA memory
to mark the memory as reserved/used from the kernel. The standard
'arm_dma_ops' contains an .alloc method that zeroes out the memory,
thereby overwriting the firmware code/data in the memory that was
pre-loaded before the Linux kernel has booted.
This scenario is handled by adding a new non-zeroing allocation
function and using it as the .alloc method in a copy of the
'arm_dma_ops'. The so created 'arm_dma_m_ops' will be assigned
as the rproc device's dma_ops when supporting the 'late attach'
functionality.
Signed-off-by: Martin Ambrose <martin@ti.com>
Signed-off-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Amarinder Bindra <a-bindra@ti.com>
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Change-Id: Ib7437e482a34c94446a85c3b328d067baa439dab
ARM: OMAP: dmtimer: Add support to handle late attach of rproc timers
During late attach, the dmtimers used by remote processors would already
have been configured and running. To prevent the kernel from resetting or
reconfiguring the timers,
- Parse the late attach attribute from device tree on probe and set a
flag in the omap_dm_timer data structure. Clear the late attach
attribute from the device tree as it is only valid on boot.
- If late attach flag is set, increment the dmtimer's usage counter
immediately on probe and maintain this state until remoteproc starts
the timer. This prevents kernel power management functionality from
idling and disabling the dmtimers.
- If late attach flag is set, also prevent the dmtimer configuration
code from modifying the dmtimer registers.
The late attach flag in the omap_dm_timer structure is cleared on timer
start to allow normal operation to resume.
Change-Id: Ibc612df92e4d8ec157c7eeb6bcac4a3aa53c35f2
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
During late attach, the dmtimers used by remote processors would already
have been configured and running. To prevent the kernel from resetting or
reconfiguring the timers,
- Parse the late attach attribute from device tree on probe and set a
flag in the omap_dm_timer data structure. Clear the late attach
attribute from the device tree as it is only valid on boot.
- If late attach flag is set, increment the dmtimer's usage counter
immediately on probe and maintain this state until remoteproc starts
the timer. This prevents kernel power management functionality from
idling and disabling the dmtimers.
- If late attach flag is set, also prevent the dmtimer configuration
code from modifying the dmtimer registers.
The late attach flag in the omap_dm_timer structure is cleared on timer
start to allow normal operation to resume.
Change-Id: Ibc612df92e4d8ec157c7eeb6bcac4a3aa53c35f2
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
iommu/omap: add support for performing a "late attach"
The remoteproc module has a concept of "late attach" whereby a remote
core is loaded externally to remoteproc, for which remoteproc must
attach to the core without disrupting its existing state. Introduce an
iommu-based "late attach" model for the same use case.
In the "late attach" model, the iommu subsystem is mostly unused since
the external loader will have programmed the remote core's mmu, but
certain "attach" functionality must be performed so that subsequent
"detach" functionality can complete.
This logic is detected in the driver through a "ti,late-attach" property
set on the IOMMU node in the device tree. The IOMMU node should also have
the "ti,no-init-on-reset" and "ti,no-init-on-idle" so that the omap_hwmod
and omap_device layers do not reset and idle/disable the device during
the initial kernel boot. This "ti,late-attach" is therefore removed from
the device tree on the first probe so that further probes or remoteproc
recovery boots treat the IOMMU device normally.
Change-Id: Id288932641a99378f7ca4b0addc3edbcc3d29ed4
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
The remoteproc module has a concept of "late attach" whereby a remote
core is loaded externally to remoteproc, for which remoteproc must
attach to the core without disrupting its existing state. Introduce an
iommu-based "late attach" model for the same use case.
In the "late attach" model, the iommu subsystem is mostly unused since
the external loader will have programmed the remote core's mmu, but
certain "attach" functionality must be performed so that subsequent
"detach" functionality can complete.
This logic is detected in the driver through a "ti,late-attach" property
set on the IOMMU node in the device tree. The IOMMU node should also have
the "ti,no-init-on-reset" and "ti,no-init-on-idle" so that the omap_hwmod
and omap_device layers do not reset and idle/disable the device during
the initial kernel boot. This "ti,late-attach" is therefore removed from
the device tree on the first probe so that further probes or remoteproc
recovery boots treat the IOMMU device normally.
Change-Id: Id288932641a99378f7ca4b0addc3edbcc3d29ed4
Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com>
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
OMAPDSS: Reorder the Makefile so that LCD is loaded before HDMI
To comply with Android UI assumption of LCD being the primary display,
the display driver initialization sequence is reordered for LCD driver
initialization to occur before ALL other diplays.
This is necessary now that pinmux config occurs in bootloader.
Without this change hdmi could be initialized and set as primary display
thereby violating the Android UI assumption.
Change-Id: I215b55a3136201bbed7cc554cc7375b41f9e8706
Signed-off-by: Marcus Cooksey <mcooksey@ti.com>
To comply with Android UI assumption of LCD being the primary display,
the display driver initialization sequence is reordered for LCD driver
initialization to occur before ALL other diplays.
This is necessary now that pinmux config occurs in bootloader.
Without this change hdmi could be initialized and set as primary display
thereby violating the Android UI assumption.
Change-Id: I215b55a3136201bbed7cc554cc7375b41f9e8706
Signed-off-by: Marcus Cooksey <mcooksey@ti.com>
Revert "TEMP: ARM: dts: dra7-evm: add i2c2 pinmux back in kernel"
This reverts commit 1ee4618aeb746e98b8cbc279564d306d1045ace4.
Change-Id: Icb4909078708bea01f5dc4254e71c491a28a4788
Signed-off-by: Marcus Cooksey <mcooksey@ti.com>
This reverts commit 1ee4618aeb746e98b8cbc279564d306d1045ace4.
Change-Id: Icb4909078708bea01f5dc4254e71c491a28a4788
Signed-off-by: Marcus Cooksey <mcooksey@ti.com>
i2c: tvp5158: Enabling the enum_framesizes subdev op
This patch allows the VIP driver to call the enum_framsizes subdev
'op' so that it can return the corresct set of supported preview
sizes of the sensor.
Change-Id: I3aca8d913ba30c2cf82678f58bdb83d934d0a610
Signed-off-by: Rakesh Movva <r-movva@ti.com>
This patch allows the VIP driver to call the enum_framsizes subdev
'op' so that it can return the corresct set of supported preview
sizes of the sensor.
Change-Id: I3aca8d913ba30c2cf82678f58bdb83d934d0a610
Signed-off-by: Rakesh Movva <r-movva@ti.com>
ARM: dts: dra7-evm: Add TVP5158 node
Adding the TVP5158 analog video decoder support which generates
BT656 embedded sync video. Add the device tree node and the
corresponding endpoint pair.
Change-Id: Id6d4df16fedbf321396b3fb4ee350f965f4b7367
Signed-off-by: Rakesh Movva <r-movva@ti.com>
Adding the TVP5158 analog video decoder support which generates
BT656 embedded sync video. Add the device tree node and the
corresponding endpoint pair.
Change-Id: Id6d4df16fedbf321396b3fb4ee350f965f4b7367
Signed-off-by: Rakesh Movva <r-movva@ti.com>
ti_fragments: audio_display: Make VIP/VPE/TVP5158 a built-in
VIP/VPE/TVP5158 are made as a built-in feature.
Change-Id: I348c221ca912480310abaa38650fdce6481809c6
Signed-off-by: Rakesh Movva <r-movva@ti.com>
VIP/VPE/TVP5158 are made as a built-in feature.
Change-Id: I348c221ca912480310abaa38650fdce6481809c6
Signed-off-by: Rakesh Movva <r-movva@ti.com>
i2c: tvp5158: Analog camera decoder driver
Add support for TVP5158 video decoder. This driver
does the default initialization for single channel
NTSC decode. It is tested with NTSC camera source.
Change-Id: Ia5f6bd038a5bcd5e7571afdc5447acbf575a97ef
Signed-off-by: Sathishkumar S <sathish.omap@gmail.com>
[Added multi channel support]
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Add support for TVP5158 video decoder. This driver
does the default initialization for single channel
NTSC decode. It is tested with NTSC camera source.
Change-Id: Ia5f6bd038a5bcd5e7571afdc5447acbf575a97ef
Signed-off-by: Sathishkumar S <sathish.omap@gmail.com>
[Added multi channel support]
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Merge branch 'p-ti-linux-3.14.y-common/audio-for-next' of git://git.ti.com/android-sdk/kernel-audio into p-ti-linux-3.14.y-common
* 'p-ti-linux-3.14.y-common/audio-for-next' of git://git.ti.com/android-sdk/kernel-audio:
ASoC: davinci-mcasp: Logic low for inactive output slots
Signed-off-by: Subramaniam Chanderashekarapuram <subramaniam.ca@ti.com>
* 'p-ti-linux-3.14.y-common/audio-for-next' of git://git.ti.com/android-sdk/kernel-audio:
ASoC: davinci-mcasp: Logic low for inactive output slots
Signed-off-by: Subramaniam Chanderashekarapuram <subramaniam.ca@ti.com>
ARM: dts: dra72-evm: Set MMC host controller capability properties
Added properties in device tree to indicate the MMC controller support
SDR12, SDR25 and DDR50 modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Added properties in device tree to indicate the MMC controller support
SDR12, SDR25 and DDR50 modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: dts: dra7-evm: Add IODELAY values for the UHS MMC modes
Add IODELAY values for sdr12, sdr25, ddr50 and mmc ddr52 modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Add IODELAY values for sdr12, sdr25, ddr50 and mmc ddr52 modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
mmc: omap_hsmmc: Add support to set IODELAY values for MMC DDR52
commit e81ae6df66 (mmc: host: omap_hsmmc: Set appropriate
IODELAY values for various MMC modes) added support to set IODELAY
values for various MMC modes but failed to add support for
DDR52.
Add support to set IODELAY values for MMC DDR52 mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
commit e81ae6df66 (mmc: host: omap_hsmmc: Set appropriate
IODELAY values for various MMC modes) added support to set IODELAY
values for various MMC modes but failed to add support for
DDR52.
Add support to set IODELAY values for MMC DDR52 mode.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
ARM: dts: dra7-evm: MMC2 in DDR52 mode
MMC2 was using high-speed timing by default which has lower
throughput than DDR52, which is also supported. So switch
MMC2 to DDR52 mode.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
MMC2 was using high-speed timing by default which has lower
throughput than DDR52, which is also supported. So switch
MMC2 to DDR52 mode.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
mmc: omap_hsmmc: Set MMC DDR52 also from dt property
All other controller capabilities were set from dt property
but MMC DDR52 was missing.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
All other controller capabilities were set from dt property
but MMC DDR52 was missing.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
mmc: omap_hsmmc: Fix MMC DDR52 support
MMC DDR52 mode also requires the DDR bit set.
This fix is pretty much what's done in upstream commit 903101a
"mmc: omap_hsmmc: Fix UHS card with DDR50 support", except
that in ti-kernel-3.14 MMC DDR52 was broken, not UHS DDR50.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
MMC DDR52 mode also requires the DDR bit set.
This fix is pretty much what's done in upstream commit 903101a
"mmc: omap_hsmmc: Fix UHS card with DDR50 support", except
that in ti-kernel-3.14 MMC DDR52 was broken, not UHS DDR50.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ASoC: davinci-mcasp: Logic low for inactive output slots
The default state when serializers are in inactive slots is Hi-Z.
In some cases, there are no additional components driving the data
lines to a safe state so they might have noise.
While in inactive slots, the McASP AXR pins configured as outputs
can be driven low through the serializer pin drive mode setting
(DISMOD) to prevent such noise.
Change-Id: I945a806fe1ad77a5f3d09e9fa039ae0366a5b088
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
The default state when serializers are in inactive slots is Hi-Z.
In some cases, there are no additional components driving the data
lines to a safe state so they might have noise.
While in inactive slots, the McASP AXR pins configured as outputs
can be driven low through the serializer pin drive mode setting
(DISMOD) to prevent such noise.
Change-Id: I945a806fe1ad77a5f3d09e9fa039ae0366a5b088
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ARM: OMAP: Add function to install alternate secure dispatcher
This change adds the function omap_secure_dispatcher_switch
which is used to setup an alternate implemention of the function
omap_secure_dispatcher in omap-secure.c
Change-Id: Ib4b2579a5e5bef3e35adc3bce4f11f739c5a3851
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
This change adds the function omap_secure_dispatcher_switch
which is used to setup an alternate implemention of the function
omap_secure_dispatcher in omap-secure.c
Change-Id: Ib4b2579a5e5bef3e35adc3bce4f11f739c5a3851
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
ARM: DRA7: hwmod: register timer12 only for GP device type
This update separates out timer12 into a different list
registered for GP devices only. On a HS device, timer12
is used in secure world and is not available for linux.
Change-Id: I6629680debbb399c8932d20ee860103211197843
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
This update separates out timer12 into a different list
registered for GP devices only. On a HS device, timer12
is used in secure world and is not available for linux.
Change-Id: I6629680debbb399c8932d20ee860103211197843
Signed-off-by: Harinarayan Bhatta <harinarayan@ti.com>
Merge branch 'ti-linux-3.14.y' of git://git.ti.com/ti-linux-kernel/ti-linux-kernel into p-ti-linux-3.14.y-common
* 'ti-linux-3.14.y' of git://git.ti.com/ti-linux-kernel/ti-linux-kernel:
TI-Integration: usb: musb: fix botched up merge (again)
Change-Id: I8f5adc9e1e1e37c731e1d6405a071012e6064ebc
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* 'ti-linux-3.14.y' of git://git.ti.com/ti-linux-kernel/ti-linux-kernel:
TI-Integration: usb: musb: fix botched up merge (again)
Change-Id: I8f5adc9e1e1e37c731e1d6405a071012e6064ebc
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
TI-Integration: usb: musb: fix botched up merge (again)
Merge bc058ac090e8 ("Merge tag 'v3.14.42' of
http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into
ti-linux-3.14.y") was a botched up merge.
commit df47ad1ce42b ("TI-Integration: Fix merge conflict
on musb_core.c") tried to fix it up but only did it
partially.
commit d0f5c460aac2 ("TI-Integration: Cherry picking this
commit to fix merge issue") tried to finish the job by
cherry-picking commit 889ad3b60f9c ("usb: musb: try a race-free
wakeup") which was the commit introducing code botched up by
original merge.
While doing this it was missed that a later commit 1007020e37f9
("usb: musb: fix device hotplug behind hub") had made further
fixes which now got reverted due to the cherry-pick. So,
cherry-picking an older commit to fix a bad merge was a bad idea.
This patch finally brings back code to where it should have
been after original merge bc058ac090e8.
Fixes: d0f5c460aac2 ("TI-Integration: Cherry picking this commit to fix merge issue")
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge bc058ac090e8 ("Merge tag 'v3.14.42' of
http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into
ti-linux-3.14.y") was a botched up merge.
commit df47ad1ce42b ("TI-Integration: Fix merge conflict
on musb_core.c") tried to fix it up but only did it
partially.
commit d0f5c460aac2 ("TI-Integration: Cherry picking this
commit to fix merge issue") tried to finish the job by
cherry-picking commit 889ad3b60f9c ("usb: musb: try a race-free
wakeup") which was the commit introducing code botched up by
original merge.
While doing this it was missed that a later commit 1007020e37f9
("usb: musb: fix device hotplug behind hub") had made further
fixes which now got reverted due to the cherry-pick. So,
cherry-picking an older commit to fix a bad merge was a bad idea.
This patch finally brings back code to where it should have
been after original merge bc058ac090e8.
Fixes: d0f5c460aac2 ("TI-Integration: Cherry picking this commit to fix merge issue")
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Merge branch 'p-ti-linux-3.14.y-common/audio-for-next' of git://git.ti.com/android-sdk/kernel-audio into p-ti-linux-3.14.y-common
* 'p-ti-linux-3.14.y-common/audio-for-next' of git://git.ti.com/android-sdk/kernel-audio:
ARM: dtsi: dra7xx-jamr3: McASP2 is shared with DSP
ARM: dts: dra72-evm: TEMP: Add pinmux for radio
ARM: dts: dra72-evm: TEMP: Add pinmux for UART3
Change-Id: I5a700c1fe78ac6e730ebf1f07dd8265322ee46c2
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* 'p-ti-linux-3.14.y-common/audio-for-next' of git://git.ti.com/android-sdk/kernel-audio:
ARM: dtsi: dra7xx-jamr3: McASP2 is shared with DSP
ARM: dts: dra72-evm: TEMP: Add pinmux for radio
ARM: dts: dra72-evm: TEMP: Add pinmux for UART3
Change-Id: I5a700c1fe78ac6e730ebf1f07dd8265322ee46c2
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
ARM: dtsi: dra7xx-jamr3: McASP2 is shared with DSP
McASP2 is configured and used from the DSP side, with the
exception of the PM resources that are taken care on the
MPU side.
Change-Id: If133a69de6c50b3aeb7a31edb557725b0753f39d
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
McASP2 is configured and used from the DSP side, with the
exception of the PM resources that are taken care on the
MPU side.
Change-Id: If133a69de6c50b3aeb7a31edb557725b0753f39d
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ARM: dts: dra72-evm: TEMP: Add pinmux for radio
Add pinmux settings for radio related modules (McASP2, McASP6, i2c4,
etc). This is a temporary patch as all padconf settings are expected
to be moved to the bootloader, as already done for J6 / dra7-evm.
Change-Id: I6c59ce7446c40f2d8db9c017f095f070754e6c1d
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Add pinmux settings for radio related modules (McASP2, McASP6, i2c4,
etc). This is a temporary patch as all padconf settings are expected
to be moved to the bootloader, as already done for J6 / dra7-evm.
Change-Id: I6c59ce7446c40f2d8db9c017f095f070754e6c1d
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
ARM: dts: dra72-evm: TEMP: Add pinmux for UART3
Add pinmux settings for UART3 used in Bluetooth. This is a
temporary patch as all padconf settings are expected to be
moved to the bootloader, as already done for J6 / dra7-evm.
Change-Id: Idb861390be182eb296e2dc6e8aee7d6458a6543a
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Add pinmux settings for UART3 used in Bluetooth. This is a
temporary patch as all padconf settings are expected to be
moved to the bootloader, as already done for J6 / dra7-evm.
Change-Id: Idb861390be182eb296e2dc6e8aee7d6458a6543a
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
arm: dtsi: dra7x: Add Vision application board device tree
Vision app board is an application board which is designed
to work with TI dra7xx-evm specifically for multi camera use cases.
This board consists of:-
OV10635 8bit camera with parallel interface.
* HDMI video receiver chip
* 3 GPIO expanders for configuring the video deserializers
* 6 video deserializers ( using FPDlink III)
Each deserializer allows to connect one OV10635 camera via a video
serializer connected over LVDS
* 6 serializer chips one each on the deserializer i2c bus
* 6 OV10635 cameras one each on the deserializer i2c bus
* There are some CPLD muxes on the board which control the data
routing of multiple video cameras. These muxes are controlled using
gpio pins
Create a skeleton DTS file for vision app board.
Also add the device tree files for dra7-evm and dra72-evm with vision
app board.
Change-Id: I113857832c82d4ce4112911a3c7e4ad0adab73ad
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Vision app board is an application board which is designed
to work with TI dra7xx-evm specifically for multi camera use cases.
This board consists of:-
OV10635 8bit camera with parallel interface.
* HDMI video receiver chip
* 3 GPIO expanders for configuring the video deserializers
* 6 video deserializers ( using FPDlink III)
Each deserializer allows to connect one OV10635 camera via a video
serializer connected over LVDS
* 6 serializer chips one each on the deserializer i2c bus
* 6 OV10635 cameras one each on the deserializer i2c bus
* There are some CPLD muxes on the board which control the data
routing of multiple video cameras. These muxes are controlled using
gpio pins
Create a skeleton DTS file for vision app board.
Also add the device tree files for dra7-evm and dra72-evm with vision
app board.
Change-Id: I113857832c82d4ce4112911a3c7e4ad0adab73ad
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
video: serdes: Add TI FPDlink3 video (de)serializer driver
Add necessary documentation, Makefile, Kconfig and header files
Add support for DS90UB914Q/913Q 12bit video (de)serializer
Add support for DS90UB925/928 12bit video (de)serializer
- Register gpio chip for local gpios
- Register i2c adapter for remote bus
- Act as i2c bridge for all remote slave devices
Change-Id: Ic8046018fea04ed9faca8808a2519c1ea4754248
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Add necessary documentation, Makefile, Kconfig and header files
Add support for DS90UB914Q/913Q 12bit video (de)serializer
Add support for DS90UB925/928 12bit video (de)serializer
- Register gpio chip for local gpios
- Register i2c adapter for remote bus
- Act as i2c bridge for all remote slave devices
Change-Id: Ic8046018fea04ed9faca8808a2519c1ea4754248
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
Merge branch 'ti-linux-3.14.y' of git://git.ti.com/ti-linux-kernel/ti-linux-kernel into p-ti-linux-3.14.y-common
* 'ti-linux-3.14.y' of git://git.ti.com/ti-linux-kernel/ti-linux-kernel: (74 commits)
TI-Integration: Cherry picking this commit to fix merge issue
TI-Integration: Fix merge conflict on musb_core.c
remoteproc/omap: add support for system suspend/resume
ARM: dts: am57xx-beagle-x15: use palmas-usb for USB2
extcon: palmas: Support GPIO based USB ID detection
usb: gadget: use $(srctree) instead of $(PWD) for includes
ARM: dts: DRA7: Add standby info for IPU & DSPs
ARM: dts: OMAP5: Add standby info for IPU and DSP
ARM: dts: OMAP4: Add standby info for IPU and DSP
Documentation: dt: update omap remoteproc binding for suspend
remoteproc/omap: use consistent match data structures for all SoCs
iommu/omap: add support for runtime auto suspend/resume
iommu/omap: add logic to save/restore locked TLBs
iommu/omap: introduce new API for suspend/resume
iommu/omap: streamline enable/disable through runtime pm callbacks
ARM: OMAP2+: add pdata-quirks for OMAP3 ISP IOMMU
ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
ARM: OMAP2+: plug in device_enable/idle ops for IOMMUs
iommu/omap: add pdata ops for omap_device_enable/idle
Linux 3.14.43
...
Change-Id: I93e347ad013ffa4aeeb5c1d088d79e0efc0c80e7
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
* 'ti-linux-3.14.y' of git://git.ti.com/ti-linux-kernel/ti-linux-kernel: (74 commits)
TI-Integration: Cherry picking this commit to fix merge issue
TI-Integration: Fix merge conflict on musb_core.c
remoteproc/omap: add support for system suspend/resume
ARM: dts: am57xx-beagle-x15: use palmas-usb for USB2
extcon: palmas: Support GPIO based USB ID detection
usb: gadget: use $(srctree) instead of $(PWD) for includes
ARM: dts: DRA7: Add standby info for IPU & DSPs
ARM: dts: OMAP5: Add standby info for IPU and DSP
ARM: dts: OMAP4: Add standby info for IPU and DSP
Documentation: dt: update omap remoteproc binding for suspend
remoteproc/omap: use consistent match data structures for all SoCs
iommu/omap: add support for runtime auto suspend/resume
iommu/omap: add logic to save/restore locked TLBs
iommu/omap: introduce new API for suspend/resume
iommu/omap: streamline enable/disable through runtime pm callbacks
ARM: OMAP2+: add pdata-quirks for OMAP3 ISP IOMMU
ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
ARM: OMAP2+: plug in device_enable/idle ops for IOMMUs
iommu/omap: add pdata ops for omap_device_enable/idle
Linux 3.14.43
...
Change-Id: I93e347ad013ffa4aeeb5c1d088d79e0efc0c80e7
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
TI-Integration: Cherry picking this commit to fix merge issue
Cherry picking this commit to the top of the tree to fix a
merge of the stable that broke this file. Half of the
issue was the merge conflict resolution the other half
was gits auto merging of the file.
usb: musb: try a race-free wakeup
Attaching a keyboard, using it as a wakeup via
|for f in $(find /sys/devices/ocp.3/47400000.usb -name wakeup)
|do
| echo enabled > $f
|done
going into standby
| echo standby > /sys/power/state
and now a wake up by a pressing a key.
What happens is that the system wakes up but the USB device is dead. The
USB stack tries to send a few control URBs but nothing comes back.
Eventually it gaves up and the device remains dead:
|[ 632.559678] PM: Wakeup source USB1_PHY
|[ 632.581074] PM: noirq resume of devices complete after 21.261 msecs
|[ 632.607521] PM: early resume of devices complete after 10.360 msecs
|[ 632.616854] net eth2: initializing cpsw version 1.12 (0)
|[ 632.704126] net eth2: phy found : id is : 0x4dd074
|[ 636.704048] libphy: 4a101000.mdio:00 - Link is Up - 1000/Full
|[ 638.444620] usb 1-1: reset low-speed USB device number 2 using musb-hdrc
|[ 653.713435] usb 1-1: device descriptor read/64, error -110
|[ 669.093435] usb 1-1: device descriptor read/64, error -110
|[ 669.473424] usb 1-1: reset low-speed USB device number 2 using musb-hdrc
|[ 684.743436] usb 1-1: device descriptor read/64, error -110
|[ 690.065097] PM: resume of devices complete after 57450.744 msecs
|[ 690.076601] PM: Finishing wakeup.
|[ 690.076627] Restarting tasks ...
It seems that since we got woken up via MUSB_INTR_RESUME the
musb_host_finish_resume() callback is executed before the
resume-callbacks of the PHY and glue layer are invoked. If I delay it
until the glue layer resumed then I don't see this problem.
I also move musb_host_resume_root_hub() into that callback since I don't
see any reason in doing anything resume-link if there are still pieces
not restored.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Conflicts:
drivers/usb/musb/musb_core.c
Cherry picking this commit to the top of the tree to fix a
merge of the stable that broke this file. Half of the
issue was the merge conflict resolution the other half
was gits auto merging of the file.
usb: musb: try a race-free wakeup
Attaching a keyboard, using it as a wakeup via
|for f in $(find /sys/devices/ocp.3/47400000.usb -name wakeup)
|do
| echo enabled > $f
|done
going into standby
| echo standby > /sys/power/state
and now a wake up by a pressing a key.
What happens is that the system wakes up but the USB device is dead. The
USB stack tries to send a few control URBs but nothing comes back.
Eventually it gaves up and the device remains dead:
|[ 632.559678] PM: Wakeup source USB1_PHY
|[ 632.581074] PM: noirq resume of devices complete after 21.261 msecs
|[ 632.607521] PM: early resume of devices complete after 10.360 msecs
|[ 632.616854] net eth2: initializing cpsw version 1.12 (0)
|[ 632.704126] net eth2: phy found : id is : 0x4dd074
|[ 636.704048] libphy: 4a101000.mdio:00 - Link is Up - 1000/Full
|[ 638.444620] usb 1-1: reset low-speed USB device number 2 using musb-hdrc
|[ 653.713435] usb 1-1: device descriptor read/64, error -110
|[ 669.093435] usb 1-1: device descriptor read/64, error -110
|[ 669.473424] usb 1-1: reset low-speed USB device number 2 using musb-hdrc
|[ 684.743436] usb 1-1: device descriptor read/64, error -110
|[ 690.065097] PM: resume of devices complete after 57450.744 msecs
|[ 690.076601] PM: Finishing wakeup.
|[ 690.076627] Restarting tasks ...
It seems that since we got woken up via MUSB_INTR_RESUME the
musb_host_finish_resume() callback is executed before the
resume-callbacks of the PHY and glue layer are invoked. If I delay it
until the glue layer resumed then I don't see this problem.
I also move musb_host_resume_root_hub() into that callback since I don't
see any reason in doing anything resume-link if there are still pieces
not restored.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Conflicts:
drivers/usb/musb/musb_core.c
Merge branch 'rpmsg-ti-linux-3.14.y' of git://git.ti.com/rpmsg/rpmsg into ti-linux-3.14.y
TI-Feature: rpmsg
TI-Tree: git://git.ti.com/rpmsg/rpmsg.git
TI-Branch: rpmsg-ti-linux-3.14.y
* 'rpmsg-ti-linux-3.14.y' of git://git.ti.com/rpmsg/rpmsg:
remoteproc/omap: add support for system suspend/resume
ARM: dts: DRA7: Add standby info for IPU & DSPs
ARM: dts: OMAP5: Add standby info for IPU and DSP
ARM: dts: OMAP4: Add standby info for IPU and DSP
Documentation: dt: update omap remoteproc binding for suspend
remoteproc/omap: use consistent match data structures for all SoCs
iommu/omap: add support for runtime auto suspend/resume
iommu/omap: add logic to save/restore locked TLBs
iommu/omap: introduce new API for suspend/resume
iommu/omap: streamline enable/disable through runtime pm callbacks
ARM: OMAP2+: add pdata-quirks for OMAP3 ISP IOMMU
ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
ARM: OMAP2+: plug in device_enable/idle ops for IOMMUs
iommu/omap: add pdata ops for omap_device_enable/idle
mailbox/omap: check for any unread messages during suspend
mailbox/omap: add support for suspend/resume
mailbox/omap: store mailbox interrupt type in omap_mbox_device
Signed-off-by: Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
TI-Feature: rpmsg
TI-Tree: git://git.ti.com/rpmsg/rpmsg.git
TI-Branch: rpmsg-ti-linux-3.14.y
* 'rpmsg-ti-linux-3.14.y' of git://git.ti.com/rpmsg/rpmsg:
remoteproc/omap: add support for system suspend/resume
ARM: dts: DRA7: Add standby info for IPU & DSPs
ARM: dts: OMAP5: Add standby info for IPU and DSP
ARM: dts: OMAP4: Add standby info for IPU and DSP
Documentation: dt: update omap remoteproc binding for suspend
remoteproc/omap: use consistent match data structures for all SoCs
iommu/omap: add support for runtime auto suspend/resume
iommu/omap: add logic to save/restore locked TLBs
iommu/omap: introduce new API for suspend/resume
iommu/omap: streamline enable/disable through runtime pm callbacks
ARM: OMAP2+: add pdata-quirks for OMAP3 ISP IOMMU
ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
ARM: OMAP2+: plug in device_enable/idle ops for IOMMUs
iommu/omap: add pdata ops for omap_device_enable/idle
mailbox/omap: check for any unread messages during suspend
mailbox/omap: add support for suspend/resume
mailbox/omap: store mailbox interrupt type in omap_mbox_device
Signed-off-by: Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
Merge branch 'rproc-linux-3.14.y' of git://git.ti.com/rpmsg/remoteproc into rpmsg-ti-linux-3.14.y
Pull in the updated remoteproc feature branch that adds the support for
system suspend/resume for the IPU and DSP remote processors on OMAP4, OMAP5
and DRA7 (only IPUs). The feature branch also pulls in automatically the
dependent mailbox and iommu feature branches with suspend/resume support.
* 'rproc-linux-3.14.y' of git://git.ti.com/rpmsg/remoteproc:
remoteproc/omap: add support for system suspend/resume
ARM: dts: DRA7: Add standby info for IPU & DSPs
ARM: dts: OMAP5: Add standby info for IPU and DSP
ARM: dts: OMAP4: Add standby info for IPU and DSP
Documentation: dt: update omap remoteproc binding for suspend
remoteproc/omap: use consistent match data structures for all SoCs
iommu/omap: add support for runtime auto suspend/resume
iommu/omap: add logic to save/restore locked TLBs
iommu/omap: introduce new API for suspend/resume
iommu/omap: streamline enable/disable through runtime pm callbacks
ARM: OMAP2+: add pdata-quirks for OMAP3 ISP IOMMU
ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
ARM: OMAP2+: plug in device_enable/idle ops for IOMMUs
iommu/omap: add pdata ops for omap_device_enable/idle
mailbox/omap: check for any unread messages during suspend
mailbox/omap: add support for suspend/resume
mailbox/omap: store mailbox interrupt type in omap_mbox_device
Signed-off-by: Suman Anna <s-anna@ti.com>
Pull in the updated remoteproc feature branch that adds the support for
system suspend/resume for the IPU and DSP remote processors on OMAP4, OMAP5
and DRA7 (only IPUs). The feature branch also pulls in automatically the
dependent mailbox and iommu feature branches with suspend/resume support.
* 'rproc-linux-3.14.y' of git://git.ti.com/rpmsg/remoteproc:
remoteproc/omap: add support for system suspend/resume
ARM: dts: DRA7: Add standby info for IPU & DSPs
ARM: dts: OMAP5: Add standby info for IPU and DSP
ARM: dts: OMAP4: Add standby info for IPU and DSP
Documentation: dt: update omap remoteproc binding for suspend
remoteproc/omap: use consistent match data structures for all SoCs
iommu/omap: add support for runtime auto suspend/resume
iommu/omap: add logic to save/restore locked TLBs
iommu/omap: introduce new API for suspend/resume
iommu/omap: streamline enable/disable through runtime pm callbacks
ARM: OMAP2+: add pdata-quirks for OMAP3 ISP IOMMU
ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
ARM: OMAP2+: plug in device_enable/idle ops for IOMMUs
iommu/omap: add pdata ops for omap_device_enable/idle
mailbox/omap: check for any unread messages during suspend
mailbox/omap: add support for suspend/resume
mailbox/omap: store mailbox interrupt type in omap_mbox_device
Signed-off-by: Suman Anna <s-anna@ti.com>
TI-Integration: Fix merge conflict on musb_core.c
Fix merge conflict resolution on musb_core.c file
where the hard coded time out delayed was taken
over the defined delay that was introduced in patch
889ad3b60f9c5f9cf6bd722603ed63d75a83af27
usb: musb: try a race-free wakeup
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Fix merge conflict resolution on musb_core.c file
where the hard coded time out delayed was taken
over the defined delay that was introduced in patch
889ad3b60f9c5f9cf6bd722603ed63d75a83af27
usb: musb: try a race-free wakeup
Signed-off-by: Dan Murphy <dmurphy@ti.com>
dts: Adding entry for GC320.
GC320 entry is added to the dts file. Using crossbar index number
for interrupt mapping.
Change-Id: I3ff5644fbcc2ec74db40af945caac8436bafe3aa
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
GC320 entry is added to the dts file. Using crossbar index number
for interrupt mapping.
Change-Id: I3ff5644fbcc2ec74db40af945caac8436bafe3aa
Signed-off-by: Gowtham Tammana <g-tammana@ti.com>
remoteproc/omap: add support for system suspend/resume
This patch adds the support for system suspend/resume to the
OMAP remoteproc driver so that the OMAP remoteproc devices can
be suspended/resumed during a system suspend/resume. The support
is added through the driver PM .suspend/.resume callbacks, and
requires appropriate support from the OS running on the remote
processors.
The IPU & DSP remote processors typically have their own private
modules like registers, internal memories, caches etc. The context
of these modules need to be saved and restored properly for a
suspend/resume to work. There are in general not accessible from
the MPU, so the remote processors themselves have to implement
the logic for the context save & restore of these modules.
The OMAP remoteproc driver initiates a suspend by sending a mailbox
message requesting the remote processor to save its context and
enter into an idle/standby state. The remote processor should
usually stop whatever processing it is doing to switch to a context
save mode. The OMAP remoteproc driver detects the completion of
the context save by checking the module standby status for the
remoteproc device. It also stops any resources used by the remote
processors like the timers. The timers need to be running only when
when the processor is active and executing, and need to be stopped
otherwise to allow the timer driver to reach low-power states. The
IOMMUs are also suspended by the remoteproc driver, and the suspend
process is completed by putting the remote processors into reset,
after which the Linux kernel can put the domain into further lower
power states as possible.
The resume sequence undoes the operations performed in the PM suspend
callback, by restoring the IOMMUs, starting the timers and finally
releasing the processors from reset. This requires that the remote
processor side OS be able to distinguish a power-resume boot from a
power-on/cold boot, restore the context of its private modules saved
during the suspend phase, and resume executing code from where it
was suspended.
The remote processors should save their context into System RAM (DDR),
as any internal memories are not guaranteed to retain context as it
depends on the lowest power domain that the remote processor device\
is put into. The management of the DDR contents will be managed by
the Linux kernel.
Signed-off-by: Suman Anna <s-anna@ti.com>
This patch adds the support for system suspend/resume to the
OMAP remoteproc driver so that the OMAP remoteproc devices can
be suspended/resumed during a system suspend/resume. The support
is added through the driver PM .suspend/.resume callbacks, and
requires appropriate support from the OS running on the remote
processors.
The IPU & DSP remote processors typically have their own private
modules like registers, internal memories, caches etc. The context
of these modules need to be saved and restored properly for a
suspend/resume to work. There are in general not accessible from
the MPU, so the remote processors themselves have to implement
the logic for the context save & restore of these modules.
The OMAP remoteproc driver initiates a suspend by sending a mailbox
message requesting the remote processor to save its context and
enter into an idle/standby state. The remote processor should
usually stop whatever processing it is doing to switch to a context
save mode. The OMAP remoteproc driver detects the completion of
the context save by checking the module standby status for the
remoteproc device. It also stops any resources used by the remote
processors like the timers. The timers need to be running only when
when the processor is active and executing, and need to be stopped
otherwise to allow the timer driver to reach low-power states. The
IOMMUs are also suspended by the remoteproc driver, and the suspend
process is completed by putting the remote processors into reset,
after which the Linux kernel can put the domain into further lower
power states as possible.
The resume sequence undoes the operations performed in the PM suspend
callback, by restoring the IOMMUs, starting the timers and finally
releasing the processors from reset. This requires that the remote
processor side OS be able to distinguish a power-resume boot from a
power-on/cold boot, restore the context of its private modules saved
during the suspend phase, and resume executing code from where it
was suspended.
The remote processors should save their context into System RAM (DDR),
as any internal memories are not guaranteed to retain context as it
depends on the lowest power domain that the remote processor device\
is put into. The management of the DDR contents will be managed by
the Linux kernel.
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'connectivity-ti-linux-3.14.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel into ti-linux-3.14.y
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-3.14.y
* 'connectivity-ti-linux-3.14.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
ARM: dts: am57xx-beagle-x15: use palmas-usb for USB2
extcon: palmas: Support GPIO based USB ID detection
usb: gadget: use $(srctree) instead of $(PWD) for includes
Signed-off-by: Dan Murphy <DMurphy@ti.com>
TI-Feature: connectivity
TI-Tree: git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel.git
TI-Branch: connectivity-ti-linux-3.14.y
* 'connectivity-ti-linux-3.14.y' of git://git.ti.com/connectivity-integration-tree/connectivity-ti-linux-kernel:
ARM: dts: am57xx-beagle-x15: use palmas-usb for USB2
extcon: palmas: Support GPIO based USB ID detection
usb: gadget: use $(srctree) instead of $(PWD) for includes
Signed-off-by: Dan Murphy <DMurphy@ti.com>
ARM: dts: am57xx-beagle-x15: use palmas-usb for USB2
The VBUS line of USB2 is connected to VBUS detect logic on
the PMIC. Use the palmas-usb driver to report VBUS events
to the USB driver.
As the palmas-usb driver supports GPIO based ID reporting
provide the GPIO for ID pin as well.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The VBUS line of USB2 is connected to VBUS detect logic on
the PMIC. Use the palmas-usb driver to report VBUS events
to the USB driver.
As the palmas-usb driver supports GPIO based ID reporting
provide the GPIO for ID pin as well.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
extcon: palmas: Support GPIO based USB ID detection
Some palmas based chip variants do not have OTG based ID logic.
For these variants we rely on GPIO based USB ID detection.
These chips do have VBUS comparator for VBUS detection so we
continue to use the old way of detecting VBUS.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Some palmas based chip variants do not have OTG based ID logic.
For these variants we rely on GPIO based USB ID detection.
These chips do have VBUS comparator for VBUS detection so we
continue to use the old way of detecting VBUS.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
usb: gadget: use $(srctree) instead of $(PWD) for includes
[ Upstream commit fa31409a82ee050e52caad9e4c483fe3edca163a ]
Using $(PWD) breaks builds when make was invoked from outside
of the kernel tree.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
[ Upstream commit fa31409a82ee050e52caad9e4c483fe3edca163a ]
Using $(PWD) breaks builds when make was invoked from outside
of the kernel tree.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
ARM: dts: DRA7: Add standby info for IPU & DSPs
Add the data for the "ti,rproc-standby-info" property for all
the DSP and IPU remoteproc processor nodes on DRA7xx family of
SoCs. This data is same for all DRA7 boards, and is required
by the OMAP remoteproc driver to implement suspend/resume for
the IPU & DSP remoteproc devices on DRA7 SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add the data for the "ti,rproc-standby-info" property for all
the DSP and IPU remoteproc processor nodes on DRA7xx family of
SoCs. This data is same for all DRA7 boards, and is required
by the OMAP remoteproc driver to implement suspend/resume for
the IPU & DSP remoteproc devices on DRA7 SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: dts: OMAP5: Add standby info for IPU and DSP
Add the data for the "ti,rproc-standby-info" property for
the DSP and IPU remoteproc processor nodes, applicable to
all OMAP5 boards. This is required by the OMAP remoteproc
driver to implement suspend/resume for the OMAP5 remoteproc
devices.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add the data for the "ti,rproc-standby-info" property for
the DSP and IPU remoteproc processor nodes, applicable to
all OMAP5 boards. This is required by the OMAP remoteproc
driver to implement suspend/resume for the OMAP5 remoteproc
devices.
Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: dts: OMAP4: Add standby info for IPU and DSP
Add the data for the "ti,rproc-standby-info" property for
the DSP and IPU remoteproc processor nodes. This data is
common to all OMAP4 boards, and is required by the OMAP
remoteproc driver to implement suspend/resume for the OMAP4
remoteproc devices.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add the data for the "ti,rproc-standby-info" property for
the DSP and IPU remoteproc processor nodes. This data is
common to all OMAP4 boards, and is required by the OMAP
remoteproc driver to implement suspend/resume for the OMAP4
remoteproc devices.
Signed-off-by: Suman Anna <s-anna@ti.com>
Documentation: dt: update omap remoteproc binding for suspend
The OMAP remoteproc binding has been updated to add an additional
property, "ti,rproc-standby-info". The property is used to define
the standby register address required by the OMAP remoteproc driver
to check that a remote proessor has entered standby and ready to
be suspended during a system suspend or a runtime auto-suspend of
the corresponding remoteproc device.
Signed-off-by: Suman Anna <s-anna@ti.com>
The OMAP remoteproc binding has been updated to add an additional
property, "ti,rproc-standby-info". The property is used to define
the standby register address required by the OMAP remoteproc driver
to check that a remote proessor has entered standby and ready to
be suspended during a system suspend or a runtime auto-suspend of
the corresponding remoteproc device.
Signed-off-by: Suman Anna <s-anna@ti.com>
remoteproc/omap: use consistent match data structures for all SoCs
The OMAP remoteproc code currently stores the firmware names directly
in the match data fields for the OMAP4 & OMAP5 SoCs, while a separate
data structure (omap_rproc_fw_data) containing the device name and
firmware name is used for the processors on DRA7xx SoC family.
Switch the OMAP4 and OMAP5 SoCs also to use the same style as DRA7
SoCs for consistency. This also allows to easily add additional data
fields to this structure in the future if needed.
Signed-off-by: Suman Anna <s-anna@ti.com>
The OMAP remoteproc code currently stores the firmware names directly
in the match data fields for the OMAP4 & OMAP5 SoCs, while a separate
data structure (omap_rproc_fw_data) containing the device name and
firmware name is used for the processors on DRA7xx SoC family.
Switch the OMAP4 and OMAP5 SoCs also to use the same style as DRA7
SoCs for consistency. This also allows to easily add additional data
fields to this structure in the future if needed.
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'iommu-linux-3.14.y' of git://git.ti.com/rpmsg/iommu into rproc-linux-3.14.y
Merge in the updated iommu feature branch into remoteproc tree to
pull in the suspend/resume support in the OMAP IOMMU driver. The
following are the main changes:
- improvements in the OMAP iommu to perform the enabling &
disabling of the IOMMU from within the runtime pm callbacks
- two new API that needs to be invoked from the OMAP remoteproc
driver to suspend/resume the IOMMU.
- locked TLB save & restore logic
- add needed pdata quirks to all supported IOMMUs
* 'iommu-linux-3.14.y' of git://git.ti.com/rpmsg/iommu:
iommu/omap: add support for runtime auto suspend/resume
iommu/omap: add logic to save/restore locked TLBs
iommu/omap: introduce new API for suspend/resume
iommu/omap: streamline enable/disable through runtime pm callbacks
ARM: OMAP2+: add pdata-quirks for OMAP3 ISP IOMMU
ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
ARM: OMAP2+: plug in device_enable/idle ops for IOMMUs
iommu/omap: add pdata ops for omap_device_enable/idle
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge in the updated iommu feature branch into remoteproc tree to
pull in the suspend/resume support in the OMAP IOMMU driver. The
following are the main changes:
- improvements in the OMAP iommu to perform the enabling &
disabling of the IOMMU from within the runtime pm callbacks
- two new API that needs to be invoked from the OMAP remoteproc
driver to suspend/resume the IOMMU.
- locked TLB save & restore logic
- add needed pdata quirks to all supported IOMMUs
* 'iommu-linux-3.14.y' of git://git.ti.com/rpmsg/iommu:
iommu/omap: add support for runtime auto suspend/resume
iommu/omap: add logic to save/restore locked TLBs
iommu/omap: introduce new API for suspend/resume
iommu/omap: streamline enable/disable through runtime pm callbacks
ARM: OMAP2+: add pdata-quirks for OMAP3 ISP IOMMU
ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
ARM: OMAP2+: plug in device_enable/idle ops for IOMMUs
iommu/omap: add pdata ops for omap_device_enable/idle
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge branch 'mailbox-linux-3.14.y' of git://git.ti.com/rpmsg/mailbox into rproc-linux-3.14.y
Pull in the updated mailbox feature branch into the remoteproc tree,
this includes the suspend/resume support in the OMAP mailbox driver.
* 'mailbox-linux-3.14.y' of git://git.ti.com/rpmsg/mailbox:
mailbox/omap: check for any unread messages during suspend
mailbox/omap: add support for suspend/resume
mailbox/omap: store mailbox interrupt type in omap_mbox_device
Signed-off-by: Suman Anna <s-anna@ti.com>
Pull in the updated mailbox feature branch into the remoteproc tree,
this includes the suspend/resume support in the OMAP mailbox driver.
* 'mailbox-linux-3.14.y' of git://git.ti.com/rpmsg/mailbox:
mailbox/omap: check for any unread messages during suspend
mailbox/omap: add support for suspend/resume
mailbox/omap: store mailbox interrupt type in omap_mbox_device
Signed-off-by: Suman Anna <s-anna@ti.com>
iommu/omap: add support for runtime auto suspend/resume
This patches adds the support for the OMAP IOMMUs to be suspended
during the auto suspend/resume of the OMAP remoteproc devices. The
remote processors are auto suspended after a certain time of idle
or inactivity period. This is done by extending the suspend/resume
API added with an additional flag to indicate the auto-suspend.
The runtime auto-suspend simply decrements and increments the
runtime usage count of the IOMMU devices and let the context be
saved/restored using the existing runtime pm callbacks.
Signed-off-by: Suman Anna <s-anna@ti.com>
This patches adds the support for the OMAP IOMMUs to be suspended
during the auto suspend/resume of the OMAP remoteproc devices. The
remote processors are auto suspended after a certain time of idle
or inactivity period. This is done by extending the suspend/resume
API added with an additional flag to indicate the auto-suspend.
The runtime auto-suspend simply decrements and increments the
runtime usage count of the IOMMU devices and let the context be
saved/restored using the existing runtime pm callbacks.
Signed-off-by: Suman Anna <s-anna@ti.com>
iommu/omap: add logic to save/restore locked TLBs
The MMUs provide a mechanism to lock TLB entries to avoid
eviction and fetching of frequently used page table entries.
These TLBs lose context when the MMUs are turned OFF. Add the
logic to save and restore these locked TLBS during suspend
and resume respectively. There are no locked TLBs during
initial power ON, and they need not be saved during final
shutdown.
Signed-off-by: Suman Anna <s-anna@ti.com>
The MMUs provide a mechanism to lock TLB entries to avoid
eviction and fetching of frequently used page table entries.
These TLBs lose context when the MMUs are turned OFF. Add the
logic to save and restore these locked TLBS during suspend
and resume respectively. There are no locked TLBs during
initial power ON, and they need not be saved during final
shutdown.
Signed-off-by: Suman Anna <s-anna@ti.com>
iommu/omap: introduce new API for suspend/resume
The MMU registers for the remote processors lose their context
in Open Switch Retention (OSWR) or device OFF modes. Hence, the
context of the IOMMU needs to be saved before it is put to these
lower power state (OSWR/OFF) and restored before it is powered
up to ON again. The IOMMUs need to be active as long as the
client devices that are present behind the IOMMU are active.
This patch introduces two new API, omap_iommu_domain_suspend()
and omap_iommu_domain_resume() to allow the client users of the
IOMMU devices to suspend & resume the IOMMU devices during their
suspend/resume operations. The API leverages the pm runtime
framework API to implement suspend/resume functionality, and
invoke the runtime PM callbacks. The PM runtime_suspend and
runtime_callbacks already are used to enable, configure and
disable the IOMMUs during the attaching and detaching of the
client devices to the IOMMUs, and this code is reused during
suspend/resume.
NOTE:
There are two other existing API, omap_iommu_save_ctx() and
omap_iommu_restore_ctx(). These are left as is to support
suspend/resume of devices on legacy OMAP3 SoC.
Signed-off-by: Suman Anna <s-anna@ti.com>
The MMU registers for the remote processors lose their context
in Open Switch Retention (OSWR) or device OFF modes. Hence, the
context of the IOMMU needs to be saved before it is put to these
lower power state (OSWR/OFF) and restored before it is powered
up to ON again. The IOMMUs need to be active as long as the
client devices that are present behind the IOMMU are active.
This patch introduces two new API, omap_iommu_domain_suspend()
and omap_iommu_domain_resume() to allow the client users of the
IOMMU devices to suspend & resume the IOMMU devices during their
suspend/resume operations. The API leverages the pm runtime
framework API to implement suspend/resume functionality, and
invoke the runtime PM callbacks. The PM runtime_suspend and
runtime_callbacks already are used to enable, configure and
disable the IOMMUs during the attaching and detaching of the
client devices to the IOMMUs, and this code is reused during
suspend/resume.
NOTE:
There are two other existing API, omap_iommu_save_ctx() and
omap_iommu_restore_ctx(). These are left as is to support
suspend/resume of devices on legacy OMAP3 SoC.
Signed-off-by: Suman Anna <s-anna@ti.com>
iommu/omap: streamline enable/disable through runtime pm callbacks
The OMAP IOMMU devices are typically present within the respective
client processor subsystem and have their own dedicated hard-reset
line. Enabling an IOMMU requires the reset line be deasserted and
the clocks be enabled before programming the necessary IOMMU
registers. The IOMMU disable sequence follow the reverse order of
enabling. The OMAP IOMMU driver programs the reset lines through
pdata ops to invoke the omap_device_assert/deassert_hardreset API.
The clocks are managed through the pm_runtime framework, and the
callbacks associated with the device's pm_domain, implemented in
the omap_device layer.
Streamline the enable and disable sequences in the OMAP IOMMU
driver by implementing all the above operations within the
runtime pm callbacks. All the OMAP devices have device pm_domain
callbacks plugged in the omap_device layer for automatic runtime
management of the clocks. Invoking the reset management functions
within the runtime pm callbacks in OMAP IOMMU driver therefore
requires that the default device's pm domain callbacks in the
omap_device layer be reset, as the ordering sequence for managing
the reset lines and clocks from the pm_domain callbacks don't gel
well with the implementation in the IOMMU driver callbacks. The
omap_device_enable/omap_device_idle functions are invoked through
the newly added pdata ops.
Consolidating all the device management sequences within the
runtime pm callbacks allows the driver to easily support both
system suspend/resume and runtime suspend/resume using common
code.
Signed-off-by: Suman Anna <s-anna@ti.com>
The OMAP IOMMU devices are typically present within the respective
client processor subsystem and have their own dedicated hard-reset
line. Enabling an IOMMU requires the reset line be deasserted and
the clocks be enabled before programming the necessary IOMMU
registers. The IOMMU disable sequence follow the reverse order of
enabling. The OMAP IOMMU driver programs the reset lines through
pdata ops to invoke the omap_device_assert/deassert_hardreset API.
The clocks are managed through the pm_runtime framework, and the
callbacks associated with the device's pm_domain, implemented in
the omap_device layer.
Streamline the enable and disable sequences in the OMAP IOMMU
driver by implementing all the above operations within the
runtime pm callbacks. All the OMAP devices have device pm_domain
callbacks plugged in the omap_device layer for automatic runtime
management of the clocks. Invoking the reset management functions
within the runtime pm callbacks in OMAP IOMMU driver therefore
requires that the default device's pm domain callbacks in the
omap_device layer be reset, as the ordering sequence for managing
the reset lines and clocks from the pm_domain callbacks don't gel
well with the implementation in the IOMMU driver callbacks. The
omap_device_enable/omap_device_idle functions are invoked through
the newly added pdata ops.
Consolidating all the device management sequences within the
runtime pm callbacks allows the driver to easily support both
system suspend/resume and runtime suspend/resume using common
code.
Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: OMAP2+: add pdata-quirks for OMAP3 ISP IOMMU
The OMAP3 ISP IOMMU does not have any reset lines, so it didn't
need any pdata. The OMAP IOMMU driver now requires the platform
data ops for device_enable/idle on all the IOMMU devices to be
able to enable/disable the clocks and maintain the reference
count and the omap_hwmod state machine. So, add the iommu pdata
quirks for the OMAP3 ISP IOMMU.
Signed-off-by: Suman Anna <s-anna@ti.com>
The OMAP3 ISP IOMMU does not have any reset lines, so it didn't
need any pdata. The OMAP IOMMU driver now requires the platform
data ops for device_enable/idle on all the IOMMU devices to be
able to enable/disable the clocks and maintain the reference
count and the omap_hwmod state machine. So, add the iommu pdata
quirks for the OMAP3 ISP IOMMU.
Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: OMAP2+: Add iommu pdata-quirks for DRA7 DSP EDMA MMUs
The DSP processor subsystems in DRA7xx have two MMUs, one for the
processor port and another for an EDMA port. Both these MMUs share
a common reset line, and the reset management is done through the
pdata quirks for the MMU associated with the processor port, so the
DSP EDMA MMUs didn't need any pdata ops. The OMAP IOMMU driver now
requires the device_enable/idle platform data ops on all the IOMMU
devices to be able to enable/disable the clocks and maintain the
reference count and the omap_hwmod state machine. So, add the iommu
pdata quirks for the DSP EDMA MMUs.
Signed-off-by: Suman Anna <s-anna@ti.com>
The DSP processor subsystems in DRA7xx have two MMUs, one for the
processor port and another for an EDMA port. Both these MMUs share
a common reset line, and the reset management is done through the
pdata quirks for the MMU associated with the processor port, so the
DSP EDMA MMUs didn't need any pdata ops. The OMAP IOMMU driver now
requires the device_enable/idle platform data ops on all the IOMMU
devices to be able to enable/disable the clocks and maintain the
reference count and the omap_hwmod state machine. So, add the iommu
pdata quirks for the DSP EDMA MMUs.
Signed-off-by: Suman Anna <s-anna@ti.com>
ARM: OMAP2+: plug in device_enable/idle ops for IOMMUs
The OMAP IOMMU driver requires the device_enable/idle platform
data ops on all the IOMMU devices to be able to enable and disable
the clocks. Plug in these pdata ops for all the existing IOMMUs,
both for non-DT devices, and for DT-devices through pdata quirks.
Signed-off-by: Suman Anna <s-anna@ti.com>
The OMAP IOMMU driver requires the device_enable/idle platform
data ops on all the IOMMU devices to be able to enable and disable
the clocks. Plug in these pdata ops for all the existing IOMMUs,
both for non-DT devices, and for DT-devices through pdata quirks.
Signed-off-by: Suman Anna <s-anna@ti.com>
iommu/omap: add pdata ops for omap_device_enable/idle
Add two new platform data ops to allow the OMAP iommu driver to
be able to invoke the omap_device_enable and omap_device_idle
from within the driver. These are being added to streamline the
sequence between managing the hard reset lines and the clocks
during the suspend path, as the default device pm_domain callback
sequences in omap_device layer are not conducive for the OMAP
IOMMU driver.
This could have been done by expanding the existing pdata ops
for reset management (like in the OMAP remoteproc driver), but
this was chosen to avoid adding new code in a separate file in
the mach-omap2 layer.
Signed-off-by: Suman Anna <s-anna@ti.com>
Add two new platform data ops to allow the OMAP iommu driver to
be able to invoke the omap_device_enable and omap_device_idle
from within the driver. These are being added to streamline the
sequence between managing the hard reset lines and the clocks
during the suspend path, as the default device pm_domain callback
sequences in omap_device layer are not conducive for the OMAP
IOMMU driver.
This could have been done by expanding the existing pdata ops
for reset management (like in the OMAP remoteproc driver), but
this was chosen to avoid adding new code in a separate file in
the mach-omap2 layer.
Signed-off-by: Suman Anna <s-anna@ti.com>
Merge tag 'v3.14.43' of http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable into ti-linux-3.14.y
This is the 3.14.43 stable release
* tag 'v3.14.43' of http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable: (52 commits)
Linux 3.14.43
kvm: arm64: vgic: fix hyp panic with 64k pages on juno platform
arm64: kvm: use inner-shareable barriers for inner-shareable maintenance
KVM: ARM: vgic: Fix the overlap check action about setting the GICD & GICC base address.
KVM: arm/arm64: vgic: fix GICD_ICFGR register accesses
ARM: KVM: trap VM system registers until MMU and caches are ON
ARM: KVM: add world-switch for AMAIR{0,1}
ARM: KVM: introduce per-vcpu HYP Configuration Register
ARM: KVM: fix ordering of 64bit coprocessor accesses
ARM: KVM: fix handling of trapped 64bit coprocessor accesses
ARM: KVM: force cache clean on page fault when caches are off
arm64: KVM: flush VM pages before letting the guest enable caches
ARM: KVM: introduce kvm_p*d_addr_end
arm64: KVM: trap VM system registers until MMU and caches are ON
arm64: KVM: allows discrimination of AArch32 sysreg access
arm64: KVM: force cache clean on page fault when caches are off
deal with deadlock in d_walk()
ACPICA: Utilities: Cleanup to remove useless ACPI_PRINTF/FORMAT_xxx helpers.
ACPICA: Utilities: Cleanup to convert physical address printing formats.
ACPICA: Utilities: Cleanup to enforce ACPI_PHYSADDR_TO_PTR()/ACPI_PTR_TO_PHYSADDR().
...
Signed-off-by: Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
This is the 3.14.43 stable release
* tag 'v3.14.43' of http://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable: (52 commits)
Linux 3.14.43
kvm: arm64: vgic: fix hyp panic with 64k pages on juno platform
arm64: kvm: use inner-shareable barriers for inner-shareable maintenance
KVM: ARM: vgic: Fix the overlap check action about setting the GICD & GICC base address.
KVM: arm/arm64: vgic: fix GICD_ICFGR register accesses
ARM: KVM: trap VM system registers until MMU and caches are ON
ARM: KVM: add world-switch for AMAIR{0,1}
ARM: KVM: introduce per-vcpu HYP Configuration Register
ARM: KVM: fix ordering of 64bit coprocessor accesses
ARM: KVM: fix handling of trapped 64bit coprocessor accesses
ARM: KVM: force cache clean on page fault when caches are off
arm64: KVM: flush VM pages before letting the guest enable caches
ARM: KVM: introduce kvm_p*d_addr_end
arm64: KVM: trap VM system registers until MMU and caches are ON
arm64: KVM: allows discrimination of AArch32 sysreg access
arm64: KVM: force cache clean on page fault when caches are off
deal with deadlock in d_walk()
ACPICA: Utilities: Cleanup to remove useless ACPI_PRINTF/FORMAT_xxx helpers.
ACPICA: Utilities: Cleanup to convert physical address printing formats.
ACPICA: Utilities: Cleanup to enforce ACPI_PHYSADDR_TO_PTR()/ACPI_PTR_TO_PHYSADDR().
...
Signed-off-by: Texas Instruments Auto Merger <lcpd_integration@list.ti.com>
Linux 3.14.43
kvm: arm64: vgic: fix hyp panic with 64k pages on juno platform
commit 63afbe7a0ac184ef8485dac4914e87b211b5bfaa upstream.
If the physical address of GICV isn't page-aligned, then we end up
creating a stage-2 mapping of the page containing it, which causes us to
map neighbouring memory locations directly into the guest.
As an example, consider a platform with GICV at physical 0x2c02f000
running a 64k-page host kernel. If qemu maps this into the guest at
0x80010000, then guest physical addresses 0x80010000 - 0x8001efff will
map host physical region 0x2c020000 - 0x2c02efff. Accesses to these
physical regions may cause UNPREDICTABLE behaviour, for example, on the
Juno platform this will cause an SError exception to EL3, which brings
down the entire physical CPU resulting in RCU stalls / HYP panics / host
crashing / wasted weeks of debugging.
SBSA recommends that systems alias the 4k GICV across the bounding 64k
region, in which case GICV physical could be described as 0x2c020000 in
the above scenario.
This patch fixes the problem by failing the vgic probe if the physical
base address or the size of GICV aren't page-aligned. Note that this
generated a warning in dmesg about freeing enabled IRQs, so I had to
move the IRQ enabling later in the probe.
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Joel Schopp <joel.schopp@amd.com>
Cc: Don Dutile <ddutile@redhat.com>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Joel Schopp <joel.schopp@amd.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 63afbe7a0ac184ef8485dac4914e87b211b5bfaa upstream.
If the physical address of GICV isn't page-aligned, then we end up
creating a stage-2 mapping of the page containing it, which causes us to
map neighbouring memory locations directly into the guest.
As an example, consider a platform with GICV at physical 0x2c02f000
running a 64k-page host kernel. If qemu maps this into the guest at
0x80010000, then guest physical addresses 0x80010000 - 0x8001efff will
map host physical region 0x2c020000 - 0x2c02efff. Accesses to these
physical regions may cause UNPREDICTABLE behaviour, for example, on the
Juno platform this will cause an SError exception to EL3, which brings
down the entire physical CPU resulting in RCU stalls / HYP panics / host
crashing / wasted weeks of debugging.
SBSA recommends that systems alias the 4k GICV across the bounding 64k
region, in which case GICV physical could be described as 0x2c020000 in
the above scenario.
This patch fixes the problem by failing the vgic probe if the physical
base address or the size of GICV aren't page-aligned. Note that this
generated a warning in dmesg about freeing enabled IRQs, so I had to
move the IRQ enabling later in the probe.
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Gleb Natapov <gleb@kernel.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Joel Schopp <joel.schopp@amd.com>
Cc: Don Dutile <ddutile@redhat.com>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Joel Schopp <joel.schopp@amd.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arm64: kvm: use inner-shareable barriers for inner-shareable maintenance
commit ee9e101c11478680d579bd20bb38a4d3e2514fe3 upstream.
In order to ensure completion of inner-shareable maintenance instructions
(cache and TLB) on AArch64, we can use the -ish suffix to the dsb
instruction.
This patch relaxes our dsb sy instructions to dsb ish where possible.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit ee9e101c11478680d579bd20bb38a4d3e2514fe3 upstream.
In order to ensure completion of inner-shareable maintenance instructions
(cache and TLB) on AArch64, we can use the -ish suffix to the dsb
instruction.
This patch relaxes our dsb sy instructions to dsb ish where possible.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
KVM: ARM: vgic: Fix the overlap check action about setting the GICD & GICC base address.
commit 30c2117085bc4e05d091cee6eba79f069b41a9cd upstream.
Currently below check in vgic_ioaddr_overlap will always succeed,
because the vgic dist base and vgic cpu base are still kept UNDEF
after initialization. The code as follows will be return forever.
if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
return 0;
So, before invoking the vgic_ioaddr_overlap, it needs to set the
corresponding base address firstly.
Signed-off-by: Haibin Wang <wanghaibin.wang@huawei.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 30c2117085bc4e05d091cee6eba79f069b41a9cd upstream.
Currently below check in vgic_ioaddr_overlap will always succeed,
because the vgic dist base and vgic cpu base are still kept UNDEF
after initialization. The code as follows will be return forever.
if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
return 0;
So, before invoking the vgic_ioaddr_overlap, it needs to set the
corresponding base address firstly.
Signed-off-by: Haibin Wang <wanghaibin.wang@huawei.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
KVM: arm/arm64: vgic: fix GICD_ICFGR register accesses
commit f2ae85b2ab3776b9e4e42e5b6fa090f40d396794 upstream.
Since KVM internally represents the ICFGR registers by stuffing two
of them into one word, the offset for accessing the internal
representation and the one for the MMIO based access are different.
So keep the original offset around, but adjust the internal array
offset by one bit.
Reported-by: Haibin Wang <wanghaibin.wang@huawei.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit f2ae85b2ab3776b9e4e42e5b6fa090f40d396794 upstream.
Since KVM internally represents the ICFGR registers by stuffing two
of them into one word, the offset for accessing the internal
representation and the one for the MMIO based access are different.
So keep the original offset around, but adjust the internal array
offset by one bit.
Reported-by: Haibin Wang <wanghaibin.wang@huawei.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: KVM: trap VM system registers until MMU and caches are ON
commit 8034699a42d68043b495c7e0cfafccd920707ec8 upstream.
In order to be able to detect the point where the guest enables
its MMU and caches, trap all the VM related system registers.
Once we see the guest enabling both the MMU and the caches, we
can go back to a saner mode of operation, which is to leave these
registers in complete control of the guest.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 8034699a42d68043b495c7e0cfafccd920707ec8 upstream.
In order to be able to detect the point where the guest enables
its MMU and caches, trap all the VM related system registers.
Once we see the guest enabling both the MMU and the caches, we
can go back to a saner mode of operation, which is to leave these
registers in complete control of the guest.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: KVM: add world-switch for AMAIR{0,1}
commit af20814ee927ed888288d98917a766b4179c4fe0 upstream.
HCR.TVM traps (among other things) accesses to AMAIR0 and AMAIR1.
In order to minimise the amount of surprise a guest could generate by
trying to access these registers with caches off, add them to the
list of registers we switch/handle.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit af20814ee927ed888288d98917a766b4179c4fe0 upstream.
HCR.TVM traps (among other things) accesses to AMAIR0 and AMAIR1.
In order to minimise the amount of surprise a guest could generate by
trying to access these registers with caches off, add them to the
list of registers we switch/handle.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: KVM: introduce per-vcpu HYP Configuration Register
commit ac30a11e8e92a03dbe236b285c5cbae0bf563141 upstream.
So far, KVM/ARM used a fixed HCR configuration per guest, except for
the VI/VF/VA bits to control the interrupt in absence of VGIC.
With the upcoming need to dynamically reconfigure trapping, it becomes
necessary to allow the HCR to be changed on a per-vcpu basis.
The fix here is to mimic what KVM/arm64 already does: a per vcpu HCR
field, initialized at setup time.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit ac30a11e8e92a03dbe236b285c5cbae0bf563141 upstream.
So far, KVM/ARM used a fixed HCR configuration per guest, except for
the VI/VF/VA bits to control the interrupt in absence of VGIC.
With the upcoming need to dynamically reconfigure trapping, it becomes
necessary to allow the HCR to be changed on a per-vcpu basis.
The fix here is to mimic what KVM/arm64 already does: a per vcpu HCR
field, initialized at setup time.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: KVM: fix ordering of 64bit coprocessor accesses
commit 547f781378a22b65c2ab468f235c23001b5924da upstream.
Commit 240e99cbd00a (ARM: KVM: Fix 64-bit coprocessor handling)
added an ordering dependency for the 64bit registers.
The order described is: CRn, CRm, Op1, Op2, 64bit-first.
Unfortunately, the implementation is: CRn, 64bit-first, CRm...
Move the 64bit test to be last in order to match the documentation.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 547f781378a22b65c2ab468f235c23001b5924da upstream.
Commit 240e99cbd00a (ARM: KVM: Fix 64-bit coprocessor handling)
added an ordering dependency for the 64bit registers.
The order described is: CRn, CRm, Op1, Op2, 64bit-first.
Unfortunately, the implementation is: CRn, 64bit-first, CRm...
Move the 64bit test to be last in order to match the documentation.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: KVM: fix handling of trapped 64bit coprocessor accesses
commit 46c214dd595381c880794413facadfa07fba5c95 upstream.
Commit 240e99cbd00a (ARM: KVM: Fix 64-bit coprocessor handling)
changed the way we match the 64bit coprocessor access from
user space, but didn't update the trap handler for the same
set of registers.
The effect is that a trapped 64bit access is never matched, leading
to a fault being injected into the guest. This went unnoticed as we
didn't really trap any 64bit register so far.
Placing the CRm field of the access into the CRn field of the matching
structure fixes the problem. Also update the debug feature to emit the
expected string in case of failing match.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 46c214dd595381c880794413facadfa07fba5c95 upstream.
Commit 240e99cbd00a (ARM: KVM: Fix 64-bit coprocessor handling)
changed the way we match the 64bit coprocessor access from
user space, but didn't update the trap handler for the same
set of registers.
The effect is that a trapped 64bit access is never matched, leading
to a fault being injected into the guest. This went unnoticed as we
didn't really trap any 64bit register so far.
Placing the CRm field of the access into the CRn field of the matching
structure fixes the problem. Also update the debug feature to emit the
expected string in case of failing match.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: KVM: force cache clean on page fault when caches are off
commit 159793001d7d85af17855630c94f0a176848e16b upstream.
In order for a guest with caches disabled to observe data written
contained in a given page, we need to make sure that page is
committed to memory, and not just hanging in the cache (as guest
accesses are completely bypassing the cache until it decides to
enable it).
For this purpose, hook into the coherent_cache_guest_page
function and flush the region if the guest SCTLR
register doesn't show the MMU and caches as being enabled.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 159793001d7d85af17855630c94f0a176848e16b upstream.
In order for a guest with caches disabled to observe data written
contained in a given page, we need to make sure that page is
committed to memory, and not just hanging in the cache (as guest
accesses are completely bypassing the cache until it decides to
enable it).
For this purpose, hook into the coherent_cache_guest_page
function and flush the region if the guest SCTLR
register doesn't show the MMU and caches as being enabled.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arm64: KVM: flush VM pages before letting the guest enable caches
commit 9d218a1fcf4c6b759d442ef702842fae92e1ea61 upstream.
When the guest runs with caches disabled (like in an early boot
sequence, for example), all the writes are diectly going to RAM,
bypassing the caches altogether.
Once the MMU and caches are enabled, whatever sits in the cache
becomes suddenly visible, which isn't what the guest expects.
A way to avoid this potential disaster is to invalidate the cache
when the MMU is being turned on. For this, we hook into the SCTLR_EL1
trapping code, and scan the stage-2 page tables, invalidating the
pages/sections that have already been mapped in.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 9d218a1fcf4c6b759d442ef702842fae92e1ea61 upstream.
When the guest runs with caches disabled (like in an early boot
sequence, for example), all the writes are diectly going to RAM,
bypassing the caches altogether.
Once the MMU and caches are enabled, whatever sits in the cache
becomes suddenly visible, which isn't what the guest expects.
A way to avoid this potential disaster is to invalidate the cache
when the MMU is being turned on. For this, we hook into the SCTLR_EL1
trapping code, and scan the stage-2 page tables, invalidating the
pages/sections that have already been mapped in.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: KVM: introduce kvm_p*d_addr_end
commit a3c8bd31af260a17d626514f636849ee1cd1f63e upstream.
The use of p*d_addr_end with stage-2 translation is slightly dodgy,
as the IPA is 40bits, while all the p*d_addr_end helpers are
taking an unsigned long (arm64 is fine with that as unligned long
is 64bit).
The fix is to introduce 64bit clean versions of the same helpers,
and use them in the stage-2 page table code.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit a3c8bd31af260a17d626514f636849ee1cd1f63e upstream.
The use of p*d_addr_end with stage-2 translation is slightly dodgy,
as the IPA is 40bits, while all the p*d_addr_end helpers are
taking an unsigned long (arm64 is fine with that as unligned long
is 64bit).
The fix is to introduce 64bit clean versions of the same helpers,
and use them in the stage-2 page table code.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arm64: KVM: trap VM system registers until MMU and caches are ON
commit 4d44923b17bff283c002ed961373848284aaff1b upstream.
In order to be able to detect the point where the guest enables
its MMU and caches, trap all the VM related system registers.
Once we see the guest enabling both the MMU and the caches, we
can go back to a saner mode of operation, which is to leave these
registers in complete control of the guest.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 4d44923b17bff283c002ed961373848284aaff1b upstream.
In order to be able to detect the point where the guest enables
its MMU and caches, trap all the VM related system registers.
Once we see the guest enabling both the MMU and the caches, we
can go back to a saner mode of operation, which is to leave these
registers in complete control of the guest.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arm64: KVM: allows discrimination of AArch32 sysreg access
commit 2072d29c46b73e39b3c6c56c6027af77086f45fd upstream.
The current handling of AArch32 trapping is slightly less than
perfect, as it is not possible (from a handler point of view)
to distinguish it from an AArch64 access, nor to tell a 32bit
from a 64bit access either.
Fix this by introducing two additional flags:
- is_aarch32: true if the access was made in AArch32 mode
- is_32bit: true if is_aarch32 == true and a MCR/MRC instruction
was used to perform the access (as opposed to MCRR/MRRC).
This allows a handler to cover all the possible conditions in which
a system register gets trapped.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 2072d29c46b73e39b3c6c56c6027af77086f45fd upstream.
The current handling of AArch32 trapping is slightly less than
perfect, as it is not possible (from a handler point of view)
to distinguish it from an AArch64 access, nor to tell a 32bit
from a 64bit access either.
Fix this by introducing two additional flags:
- is_aarch32: true if the access was made in AArch32 mode
- is_32bit: true if is_aarch32 == true and a MCR/MRC instruction
was used to perform the access (as opposed to MCRR/MRRC).
This allows a handler to cover all the possible conditions in which
a system register gets trapped.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arm64: KVM: force cache clean on page fault when caches are off
commit 2d58b733c87689d3d5144e4ac94ea861cc729145 upstream.
In order for the guest with caches off to observe data written
contained in a given page, we need to make sure that page is
committed to memory, and not just hanging in the cache (as
guest accesses are completely bypassing the cache until it
decides to enable it).
For this purpose, hook into the coherent_icache_guest_page
function and flush the region if the guest SCTLR_EL1
register doesn't show the MMU and caches as being enabled.
The function also get renamed to coherent_cache_guest_page.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
commit 2d58b733c87689d3d5144e4ac94ea861cc729145 upstream.
In order for the guest with caches off to observe data written
contained in a given page, we need to make sure that page is
committed to memory, and not just hanging in the cache (as
guest accesses are completely bypassing the cache until it
decides to enable it).
For this purpose, hook into the coherent_icache_guest_page
function and flush the region if the guest SCTLR_EL1
register doesn't show the MMU and caches as being enabled.
The function also get renamed to coherent_cache_guest_page.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>