Remove remaining bionic support for TARGET_CPU_SMP being false.

[android-sdk/platform-bionic.git] / libc / private / bionic_atomic_x86.h

diff --git a/libc/private/bionic_atomic_x86.h b/libc/private/bionic_atomic_x86.h
index aca0c4b56707a6d18fa85996e37da8e4f9ddd4de..e63df93848d9297183712cd6969fa0b5aadfc190 100644 (file)
--- a/libc/private/bionic_atomic_x86.h
+++ b/libc/private/bionic_atomic_x86.h
@@ -19,28 +19,15 @@
 /* Define a full memory barrier, this is only needed if we build the
  * platform for a multi-core device.
  */
-#if defined(ANDROID_SMP) && ANDROID_SMP == 1
-__ATOMIC_INLINE__ void
-__bionic_memory_barrier()
-{
-    __asm__ __volatile__ ( "mfence" : : : "memory" );
+__ATOMIC_INLINE__ void __bionic_memory_barrier() {
+  __asm__ __volatile__ ( "mfence" : : : "memory" );
 }
-#else
-__ATOMIC_INLINE__ void
-__bionic_memory_barrier()
-{
-    /* A simple compiler barrier */
-    __asm__ __volatile__ ( "" : : : "memory" );
-}
-#endif
 
 /* Compare-and-swap, without any explicit barriers. Note that this function
  * returns 0 on success, and 1 on failure. The opposite convention is typically
  * used on other platforms.
  */
-__ATOMIC_INLINE__ int
-__bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
-{
+__ATOMIC_INLINE__ int __bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr) {
     int32_t prev;
     __asm__ __volatile__ ("lock; cmpxchgl %1, %2"
                           : "=a" (prev)
@@ -49,40 +36,23 @@ __bionic_cmpxchg(int32_t old_value, int32_t new_value, volatile int32_t* ptr)
     return prev != old_value;
 }
 
-
-/* Swap, without any explicit barriers */
-__ATOMIC_INLINE__ int32_t
-__bionic_swap(int32_t new_value, volatile int32_t *ptr)
-{
-    __asm__ __volatile__ ("xchgl %1, %0"
-                          : "=r" (new_value)
-                          : "m" (*ptr), "0" (new_value)
-                          : "memory");
-    return new_value;
-}
-
-/* Atomic increment, without explicit barriers */
-__ATOMIC_INLINE__ int32_t
-__bionic_atomic_inc(volatile int32_t *ptr)
-{
-    int increment = 1;
-    __asm__ __volatile__ ("lock; xaddl %0, %1"
-                          : "+r" (increment), "+m" (*ptr)
-                          : : "memory");
-    /* increment now holds the old value of *ptr */
-    return increment;
+/* Swap, without any explicit barriers. */
+__ATOMIC_INLINE__ int32_t __bionic_swap(int32_t new_value, volatile int32_t *ptr) {
+  __asm__ __volatile__ ("xchgl %1, %0"
+                        : "=r" (new_value)
+                        : "m" (*ptr), "0" (new_value)
+                        : "memory");
+  return new_value;
 }
 
-/* Atomic decrement, without explicit barriers */
-__ATOMIC_INLINE__ int32_t
-__bionic_atomic_dec(volatile int32_t *ptr)
-{
-    int increment = -1;
-    __asm__ __volatile__ ("lock; xaddl %0, %1"
-                          : "+r" (increment), "+m" (*ptr)
-                          : : "memory");
-    /* increment now holds the old value of *ptr */
-    return increment;
+/* Atomic decrement, without explicit barriers. */
+__ATOMIC_INLINE__ int32_t __bionic_atomic_dec(volatile int32_t* ptr) {
+  int increment = -1;
+  __asm__ __volatile__ ("lock; xaddl %0, %1"
+                        : "+r" (increment), "+m" (*ptr)
+                        : : "memory");
+  /* increment now holds the old value of *ptr */
+  return increment;
 }
 
 #endif /* BIONIC_ATOMIC_X86_H */