android-sdk/u-boot.git
7 years agoboard: dra7xxx: modfiy mux data. master ti-u-boot-2013.04+ ti2013.04.02
Sourav Poddar [Fri, 7 Jun 2013 11:46:15 +0000 (17:16 +0530)]
board: dra7xxx: modfiy mux data.

Modify qspi pin configuartions

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoFix offset detail and add sysboot settings
Sourav Poddar [Fri, 7 Jun 2013 16:32:48 +0000 (22:02 +0530)]
Fix offset detail and add sysboot settings

Fix u-bot offset details and add qspi sysboot setings.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoREADME: qspi usecase and testing documentation.
Sourav Poddar [Fri, 7 Jun 2013 16:32:48 +0000 (22:02 +0530)]
README: qspi usecase and testing documentation.

Contains documentation and testing details for qspi flash
interface.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agodrivers: mtd: spi: Modify read/write command for sfl256s flash.
Sourav Poddar [Fri, 7 Jun 2013 16:32:47 +0000 (22:02 +0530)]
drivers: mtd: spi: Modify read/write command for sfl256s flash.

Reading using the already supported read command is causing regression
even while reading 4k bytes, as a result doing a page by page read.

At the end of the write sequence, write enable latch should be disabled and
re enabled while doing the next page programming.

Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agodra7xx_evm: add SPL API, QSPI, and serial flash support
Matt Porter [Fri, 7 Jun 2013 16:32:46 +0000 (22:02 +0530)]
dra7xx_evm: add SPL API, QSPI, and serial flash support

Enables support for SPI SPL, QSPI and Spansion serial flash device
on the EVM. Configures pin muxes for QSPI mode.

Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agospi: add TI QSPI driver
Matt Porter [Fri, 7 Jun 2013 16:32:45 +0000 (22:02 +0530)]
spi: add TI QSPI driver

Adds a SPI master driver for the TI QSPI peripheral.

Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoomap5: add qspi support
Matt Porter [Fri, 7 Jun 2013 16:32:44 +0000 (22:02 +0530)]
omap5: add qspi support

Add QSPI definitions and clock configuration support.

Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
7 years agoARM: DRA7xx: EMIF: Change settings required for EVM board
Sricharan R [Tue, 28 May 2013 11:52:25 +0000 (17:22 +0530)]
ARM: DRA7xx: EMIF: Change settings required for EVM board

DRA7 EVM board has the below configuration. Adding the
settings for the same here.

   2Gb_1_35V_DDR3L part * 2 on EMIF1
   2Gb_1_35V_DDR3L part * 4 on EMIF2

Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: DRA7xx: clocks: Update PLL values
Lokesh Vutla [Tue, 28 May 2013 04:28:11 +0000 (09:58 +0530)]
ARM: DRA7xx: clocks: Update PLL values

Update PLL values.
SYS_CLKSEL value for 20MHz is changed to 2. In other platforms
SYS_CLKSEL value 2 represents reserved. But in sys_clk array
ind 1 is used for 13Mhz. Since other platforms are not using
13Mhz, reusing index 1 for 20MHz.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: DRA7xx: Update pinmux data
Lokesh Vutla [Wed, 22 May 2013 06:43:29 +0000 (12:13 +0530)]
ARM: DRA7xx: Update pinmux data

Updating pinmux data as specified in the latest DM

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Balaji T K <balajitk@ti.com>
7 years agommc: omap_hsmmc: add mmc1 pbias, ldo1
Balaji T K [Fri, 3 May 2013 09:28:08 +0000 (14:58 +0530)]
mmc: omap_hsmmc: add mmc1 pbias, ldo1

add dra mmc pbias support and ldo1 power on

Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: DRA7xx: Correct SRAM END address
Sricharan R [Tue, 28 May 2013 05:28:25 +0000 (10:58 +0530)]
ARM: DRA7xx: Correct SRAM END address

NON SECURE SRAM is 512KB in DRA7xx devices.
So fixing it here.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: DRA7xx: Correct the SYS_CLK to 20MHZ
Sricharan R [Tue, 28 May 2013 05:02:23 +0000 (10:32 +0530)]
ARM: DRA7xx: Correct the SYS_CLK to 20MHZ

The sys_clk on the dra evm board is 20MHZ.
Changing the configuration for the same.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: DRA7xx: Change the Debug UART to UART1
Sricharan R [Tue, 28 May 2013 04:57:46 +0000 (10:27 +0530)]
ARM: DRA7xx: Change the Debug UART to UART1

Serial UART is connected to UART1. So add the change
for the same.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's
Lokesh Vutla [Tue, 28 May 2013 04:36:08 +0000 (10:06 +0530)]
ARM: DRA7xx: Do not enable srcomp for DRA7xx Soc's

Slew rate compensation cells are not present for DRA7xx
Soc's. So return from function srcomp_enable() if soc is not
OMAP54xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP5: DRA7xx: support class 0 optimized voltages
Nishanth Menon [Thu, 4 Apr 2013 13:16:24 +0000 (18:46 +0530)]
ARM: OMAP5: DRA7xx: support class 0 optimized voltages

DRA752 now uses AVS Class 0 voltages which are voltages in efuse.

This means that we can now use the optimized voltages which are
stored as mV values in efuse and program PMIC accordingly.

This allows us to go with higher OPP as needed in the system without
the need for implementing complex AVS logic.

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agoARM: DRA7xx: clocks: Fixing i2c_init for PMIC
Lokesh Vutla [Tue, 28 May 2013 04:40:56 +0000 (10:10 +0530)]
ARM: DRA7xx: clocks: Fixing i2c_init for PMIC

In DRA7xx Soc's voltage scaling is done using GPI2C.
So i2c_init should happen before scaling. I2C driver
uses __udelay which needs timer to be initialized.
So moving timer_init just before voltage scaling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: DRA7xx: power Add support for tps659038 PMIC
Lokesh Vutla [Tue, 2 Apr 2013 03:55:31 +0000 (09:25 +0530)]
ARM: DRA7xx: power Add support for tps659038 PMIC

TPS659038 is the power IC used in DRA7XX boards.
Adding support for this and also adding pmic data
for DRA7XX boards.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: DRA7xx: Add control id code for DRA7xx
Lokesh Vutla [Thu, 21 Mar 2013 11:30:34 +0000 (17:00 +0530)]
ARM: DRA7xx: Add control id code for DRA7xx

The registers that are used for device identification
are changed from OMAP5 to DRA7xx.
Using the correct registers for DRA7xx.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP4+: pmic: Make generic bus init and write functions
Lokesh Vutla [Wed, 22 May 2013 06:05:04 +0000 (11:35 +0530)]
ARM: OMAP4+: pmic: Make generic bus init and write functions

Voltage scaling can be done in two ways:
-> Using SR I2C
-> Using GP I2C
In order to support both, have a function pointer in pmic_data
so that we can call as per our requirement.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP5: clocks: Do not enable sgx clocks
Sricharan R [Wed, 1 May 2013 13:58:54 +0000 (19:28 +0530)]
ARM: OMAP5: clocks: Do not enable sgx clocks

SGX clocks should be enabled only for OMAP5 ES1.0.
So this can be removed.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: OMAP4+: Cleanup header files
Lokesh Vutla [Wed, 22 May 2013 05:55:34 +0000 (11:25 +0530)]
ARM: OMAP4+: Cleanup header files

After having the u-boot clean up series, there are
many definitions that are unused in header files.
Removing all those unused ones.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agoARM: OMAP: Add arch_cpu_init function
SRICHARAN R [Wed, 24 Apr 2013 00:41:25 +0000 (00:41 +0000)]
ARM: OMAP: Add arch_cpu_init function

The boot parameters passed from SPL to UBOOT
must be saved as a part of uboot's gd data
as early as possible, before we will inadvertently
overwrite it. So adding a arch_cpu_init for the required
Socs to save it.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
7 years agoARM: OMAP: Cleanup boot parameters usage
SRICHARAN R [Wed, 24 Apr 2013 00:41:24 +0000 (00:41 +0000)]
ARM: OMAP: Cleanup boot parameters usage

The boot parameters are read from individual variables
assigned for each of them. This been corrected and now
they are stored as a part of the global data 'gd'
structure. So read them from 'gd' instead.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
[trini: Add igep0033 hunk]
Signed-off-by: Tom Rini <trini@ti.com>
7 years agoARM: OMAP: Correct save_boot_params and replace with 'C' function
SRICHARAN R [Wed, 24 Apr 2013 00:41:23 +0000 (00:41 +0000)]
ARM: OMAP: Correct save_boot_params and replace with 'C' function

Currently save_boot_params saves the boot parameters passed
from romcode. But this is not stored in a writable location
consistently. So the current code would not work for a
'XIP' boot. Change this by saving the boot parameters in
'gd' which is always writable. Also add a 'C' function
instead of an assembly code that is more readable.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common
SRICHARAN R [Wed, 24 Apr 2013 00:41:22 +0000 (00:41 +0000)]
ARM: OMAP4/5: Make OMAPx_SRAM_SCRATCH_ defines common

These defines are same across OMAP4/5. So move them to
omap_common.h. This is required for the patches that
follow.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoARM: OMAP: Make omap_boot_parameters common across socs
SRICHARAN R [Wed, 24 Apr 2013 00:41:21 +0000 (00:41 +0000)]
ARM: OMAP: Make omap_boot_parameters common across socs

omap_boot_parameters is same and defined for each
soc. So move this to a common place to reuse it
across socs.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
7 years agoam33xx: Fix warning with CONFIG_DISPLAY_CPUINFO
Tom Rini [Thu, 25 Apr 2013 20:46:04 +0000 (16:46 -0400)]
am33xx: Fix warning with CONFIG_DISPLAY_CPUINFO

The arm_freq and ddr_freq variables are unused, so remove.  Fixup
whitespace slightly while in here.

Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Tom Rini <trini@ti.com>
7 years agodavinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK
Eric Benard [Mon, 22 Apr 2013 05:55:00 +0000 (05:55 +0000)]
davinci: handle CONFIG_SYS_CLE_MASK and CONFIG_SYS_ALE_MASK

these variables are curently defined in several config files but the
driver doesn't use them and defaults to hardcoded values in
nand_defs.h

It's interesting to be able to change this hardcoded valude when the
hardware is not using the default adress signals to drive ALE and CLE
and two configuration defines already exist for this purpose so use
them.

Signed-off-by: Eric Bénard <eric@eukrea.com>
7 years agoda850: provide davinci_enable_uart0
Eric Benard [Mon, 22 Apr 2013 05:54:59 +0000 (05:54 +0000)]
da850: provide davinci_enable_uart0

this is needed to bring UART0 out of reset but this function
currently only exists for dm644x/355/365/646x when da850 (at
least am1808 also need it).

Signed-off-by: Eric Bénard <eric@eukrea.com>
7 years agocm-t35: update config file
Igor Grinberg [Mon, 22 Apr 2013 01:06:55 +0000 (01:06 +0000)]
cm-t35: update config file

Several minor updates to the cm-t35 config file.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
7 years agoMAINTAINERS: fix the cm-t35 board name
Igor Grinberg [Mon, 22 Apr 2013 01:06:54 +0000 (01:06 +0000)]
MAINTAINERS: fix the cm-t35 board name

"cm-t35" in U-Boot source code is called "cm_t35".
Make the change "cm-t35" -> "cm_t35" for better greppability.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
7 years agocm-t35: move cm-t35 to live in compulab directory
Igor Grinberg [Mon, 22 Apr 2013 01:06:53 +0000 (01:06 +0000)]
cm-t35: move cm-t35 to live in compulab directory

Currently the cm-t35 support code lives under board/cm_t35 directory.
Some of the code can be shared with other/future CompuLab boards,
so move the cm-t35 to live under board/compulab/cm_t35 directory.

Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Tested-by: Nikita Kiryanov <nikita@compulab.co.il>
7 years agoARM: Panda: Add flag to allow runtime enviroment varibale mods
Dan Murphy [Thu, 18 Apr 2013 06:29:54 +0000 (06:29 +0000)]
ARM: Panda: Add flag to allow runtime enviroment varibale mods

Add the flag to allow runtime enviroment variable modifications.
This is being added so that the board-name can be modified at runtime
to indicate either a panda(4430) or a panda-es(4460)

Signed-off-by: Dan Murphy <dmurphy@ti.com>
7 years agoARM:Panda:Fix device tree loading for the panda-es
Dan Murphy [Thu, 18 Apr 2013 06:29:53 +0000 (06:29 +0000)]
ARM:Panda:Fix device tree loading for the panda-es

Fix the device tree loading for panda(4430) and panda-es(4460)

Modify the board name if a 4460 panda or panda-es is detected
at run time.
In the findfdt add a check for the panda-es board name and load
the panda-es device tree blob.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
7 years agoARM: OMAP5: Fix warm reset with USB cable connected
Lokesh Vutla [Wed, 17 Apr 2013 20:49:40 +0000 (20:49 +0000)]
ARM: OMAP5: Fix warm reset with USB cable connected

Warm reset on OMAP5 freezes when USB cable is connected.
Fix requires PRM_RSTTIME.RSTTIME1 to be programmed
with the time for which reset should be held low for the
voltages and the oscillator to reach stable state.

There are 3 parameters to be considered for calculating
the time, which are mostly board and PMIC dependent.
-1- Time taken by the Oscillator to shut + restart
-2- PMIC OTP times
-3- Voltage rail ramp times, which inturn depends on the
PMIC slew rate and value of the voltage ramp needed.

In order to keep the code in u-boot simple, have a way
for boards to specify a pre computed time directly using
the 'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'
option. If boards fail to specify the time, use a default
as specified by 'CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC' instead.
Using the default value translates into some ~22ms and should work in
all cases.
However in order to avoid this large delay hiding other bugs,
its recommended that all boards look at their respective data
sheets and specify a pre computed and optimal value using
'CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC'

In order to help future board additions to compute this
config option value, add a README at doc/README.omap-reset-time
which explains how to compute the value. Also update the toplevel
README with the additional option and pointers to
doc/README.omap-reset-time.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
[rnayak@ti.com: Updated changelog and added the README]
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
7 years agoRemove duplicate / unused #defines on AM335x boards
Mark Jackson [Wed, 17 Apr 2013 08:22:47 +0000 (08:22 +0000)]
Remove duplicate / unused #defines on AM335x boards

As part of a review of a recent patch to add a new AM335x board, Tom
found several duplicate and/or unused #defines.

This patch simply removes them.

The two affected configs have been recompiled to check nothing was
broken (from a compilation point of view !!)

Reported-by: Tom Rini <trini@ti.com>
Signed-off-by: Mark Jackson <mpfj-list@mimc.co.uk>
7 years agoomap5_common: Add optargs variable for kernel command line args
Tom Rini [Thu, 11 Apr 2013 05:22:10 +0000 (05:22 +0000)]
omap5_common: Add optargs variable for kernel command line args

Add 'optargs' variable to be set to additional kernel arguments, similar
to omap3*/am3* usage.

Cc: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
7 years agoOMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work
Lubomir Popov [Thu, 11 Apr 2013 00:08:51 +0000 (00:08 +0000)]
OMAP5: USB: hsusbtll_clkctrl has to be in hw_auto for USB to work

USB TLL clocks do not support 'explicit_en', only 'hw_auto'
control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be
moved to the clk_modules_hw_auto_essential[] array in order
to make the clock work.

This fix is needed (but not sufficient) for USB EHCI operation
in U-Boot.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
7 years agoARM: Add support for IGEP COM AQUILA/CYGNUS
Enric Balletbo i Serra [Thu, 4 Apr 2013 22:27:58 +0000 (22:27 +0000)]
ARM: Add support for IGEP COM AQUILA/CYGNUS

The IGEP COM AQUILA and CYGNUS are industrial processors modules with
following highlights:

  o AM3352/AM3354 Texas Instruments processor
  o Cortex-A8 ARM CPU
  o 3.3 volts Inputs / Outputs use industrial
  o 256 MB DDR3 SDRAM / 128 Megabytes FLASH
  o MicroSD card reader on-board
  o Ethernet controller on-board
  o JTAG debug connector available
  o Designed for industrial range purposes

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
7 years agoAdd DDR3 support for IGEP COM AQUILA/CYGNUS.
Enric Balletbo i Serra [Thu, 4 Apr 2013 22:27:57 +0000 (22:27 +0000)]
Add DDR3 support for IGEP COM AQUILA/CYGNUS.

These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM.

Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com>
7 years agoarm: omap: emif: Fix DDR3 init after warm reset
Lokesh Vutla [Wed, 27 Mar 2013 20:24:42 +0000 (20:24 +0000)]
arm: omap: emif: Fix DDR3 init after warm reset

EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.

Tested on OMAP5432 ES2.0

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
7 years agobeagleboard: Update comment in get_board_rev()
Tom Rini [Tue, 16 Apr 2013 20:31:20 +0000 (16:31 -0400)]
beagleboard: Update comment in get_board_rev()

We are able to tell the difference between xM Rev Ax/Bx and xM Rev Cx,
and have been for some time.  The comment above the function however did
not list this, so update.

Signed-off-by: Tom Rini <trini@ti.com>
7 years agoOMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5
Lubomir Popov [Mon, 8 Apr 2013 21:49:43 +0000 (21:49 +0000)]
OMAP5: I2C: Set I2C_BUS_MAX to 5 to enable I2C4 and I2C5

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
In order to be able to select one of these buses however, I2C_BUS_MAX
has to be set to 5; do this here.

Please note that for working bus selection, a fix to the i2c driver
is required as well (subject of a separate patch).

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
7 years agoOMAP5: I2C: Add I2C4 and I2C5 bases
Lubomir Popov [Mon, 8 Apr 2013 21:49:40 +0000 (21:49 +0000)]
OMAP5: I2C: Add I2C4 and I2C5 bases

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The I2C4 and I2C5 base addresses were however not defined; do this
here.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
7 years agoOMAP5: I2C: Enable i2c5 clocks
Lubomir Popov [Mon, 8 Apr 2013 21:49:37 +0000 (21:49 +0000)]
OMAP5: I2C: Enable i2c5 clocks

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The i2c5 clock was however not enabled; do this here.

Signed-off-by: Lubomir Popov <lpopov@mm-sol.com>
7 years agopalmas: add header guard
Nishanth Menon [Tue, 26 Mar 2013 05:20:58 +0000 (05:20 +0000)]
palmas: add header guard

Add an header guard to common header file to prevent multiple
includes messing things up.

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agopalmas: use palmas_i2c_[read|write]_u8
Nishanth Menon [Tue, 26 Mar 2013 05:20:57 +0000 (05:20 +0000)]
palmas: use palmas_i2c_[read|write]_u8

commit 21144298 (power: twl6035: add palmas PMIC support)
introduced twl6035_i2c_[read|write]_u8
Then, commit dd23e59d (omap5: pbias ldo9 turn on)
introduced palmas_[read|write]_u8 for precisely the same access
function. TWL6035 belongs to the palmas family, so instead of having
an twl6035 API, we could use an generic palmas API instead.

To stay consistent with the function naming of twl4030,6030 accessors,
we use palmas_i2c_[read|write]_u8

Cc: Balaji T K <balajitk@ti.com>
Cc: Sricharan R <r.sricharan@ti.com>
Reported-by: Ruchika Kharwar <ruchika@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agopalmas: rename twl6035_mmc1_poweron_ldo with an palmas generic function
Nishanth Menon [Tue, 26 Mar 2013 05:20:56 +0000 (05:20 +0000)]
palmas: rename twl6035_mmc1_poweron_ldo with an palmas generic function

Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_mmc1_poweron_ldo by a more generic palmas_mmc1_poweron_ldo
function.

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agopalmas: rename init_settings to an generic palmas init
Nishanth Menon [Tue, 26 Mar 2013 05:20:55 +0000 (05:20 +0000)]
palmas: rename init_settings to an generic palmas init

Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_init_settings with an more generic palmas_init_settings

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agotwl6035: rename to palmas
Nishanth Menon [Tue, 26 Mar 2013 05:20:54 +0000 (05:20 +0000)]
twl6035: rename to palmas

TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs
Rename twl6035 to palmas to allow reuse across multiple current and
future platforms

As part of this change, change the CONFIG_TWL6035_POWER to
CONFIG_PALMAS_POWER and update usage of header file accordingly.

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agotwl6030: add header guard
Nishanth Menon [Tue, 26 Mar 2013 05:20:53 +0000 (05:20 +0000)]
twl6030: add header guard

Add an header guard to common header file to prevent multiple includes
messing things up.

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agotwl6030: move twl6030 register access functions to common header file
Nishanth Menon [Tue, 26 Mar 2013 05:20:52 +0000 (05:20 +0000)]
twl6030: move twl6030 register access functions to common header file

twl6030_i2c_[read|write]_u8 can be used else where to access
multi-function device such as twl6030, so move the register access
functions to the common twl6030.h header file.

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agotwl6030: twl6030_i2c_[read|write]_u8 prototype consistent
Nishanth Menon [Tue, 26 Mar 2013 05:20:51 +0000 (05:20 +0000)]
twl6030: twl6030_i2c_[read|write]_u8 prototype consistent

u-boot standard i2c register access prototype is
i2c_read(addr, reg, 1, &buf, 1)
i2c_reg_write(u8 addr, u8 reg, u8 val)

twl6030_i2c_read_u8(u8 addr, u8 *val, u8 reg)
twl6030_i2c_write_u8(u8 addr, u8 val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl6030_i2c_read_u8(u8 addr, u8 reg, u8 *val)
twl6030_i2c_write_u8(u8 addr, u8 reg, u8 val)

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agotwl4030: make twl4030_i2c_read_u8 prototype consistent
Nishanth Menon [Tue, 26 Mar 2013 05:20:50 +0000 (05:20 +0000)]
twl4030: make twl4030_i2c_read_u8 prototype consistent

u-boot standard i2c read prototype is
i2c_read(addr, reg, 1, &buf, 1)

twl4030_i2c_read_u8(u8 addr, u8 *val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_read_u8(u8 addr, u8 reg, u8 *val)

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agotwl4030: make twl4030_i2c_write_u8 prototype consistent
Nishanth Menon [Tue, 26 Mar 2013 05:20:49 +0000 (05:20 +0000)]
twl4030: make twl4030_i2c_write_u8 prototype consistent

u-boot standard i2c register write prototype is
i2c_reg_write(u8 addr, u8 reg, u8 val)

twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val)

Signed-off-by: Nishanth Menon <nm@ti.com>
7 years agoti814x_evm: enable CPSW support
Matt Porter [Wed, 20 Mar 2013 05:38:14 +0000 (05:38 +0000)]
ti814x_evm: enable CPSW support

Adds CPSW support to the TI814X EVM configured with
an ET1011C PHY in GMII mode.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agophy: add support for ET1011C phys
Matt Porter [Wed, 20 Mar 2013 05:38:13 +0000 (05:38 +0000)]
phy: add support for ET1011C phys

Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agocpsw: add support for TI814x slave_regs differences
Matt Porter [Wed, 20 Mar 2013 05:38:12 +0000 (05:38 +0000)]
cpsw: add support for TI814x slave_regs differences

TI814x's version 1 CPSW has a different slave_regs layout.
Add support for the differing registers.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agoam33xx: add pll and clock support for TI814x CPSW
Matt Porter [Wed, 20 Mar 2013 05:38:11 +0000 (05:38 +0000)]
am33xx: add pll and clock support for TI814x CPSW

Enables required PLLs and clocks for CPSW on TI814x.

Signed-off-by: Matt Porter <mporter@ti.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agoi2c: zynq: Add support for Xilinx Zynq
Michal Simek [Mon, 22 Apr 2013 13:21:33 +0000 (15:21 +0200)]
i2c: zynq: Add support for Xilinx Zynq

Support Xilinx Zynq i2c controller.

Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agommc: Add support for Xilinx Zynq sdhci controller
Michal Simek [Mon, 22 Apr 2013 12:56:49 +0000 (14:56 +0200)]
mmc: Add support for Xilinx Zynq sdhci controller

Add support for SD, MMC and eMMC card on Xilinx Zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agonet: gem: Add support for phy autodetection
Michal Simek [Mon, 22 Apr 2013 12:41:09 +0000 (14:41 +0200)]
net: gem: Add support for phy autodetection

Autodetect phy if phyaddress is setup to -1.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agonet: gem: Preserve clk on emio interface
David Andrey [Fri, 5 Apr 2013 15:24:24 +0000 (17:24 +0200)]
net: gem: Preserve clk on emio interface

Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO

Do not enable emio for this standard board configuration for now.

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agonet: gem: Pass phy address to init
David Andrey [Thu, 4 Apr 2013 17:13:07 +0000 (19:13 +0200)]
net: gem: Pass phy address to init

Pass the PHY address to the driver init to
allow parallel use of both interfaces

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agozynq: Move macros to hardware.h
Michal Simek [Fri, 12 Apr 2013 14:33:08 +0000 (16:33 +0200)]
zynq: Move macros to hardware.h

Add all fixed addresses to hardware.h and change petalinux
configuration to support this.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agonet: gem: Fix gem driver on 1Gbps LAN
Michal Simek [Mon, 15 Oct 2012 12:01:23 +0000 (14:01 +0200)]
net: gem: Fix gem driver on 1Gbps LAN

The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agonet: gem: Do not initialize BDs again
Michal Simek [Thu, 24 Jan 2013 12:04:12 +0000 (13:04 +0100)]
net: gem: Do not initialize BDs again

BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.

This patch solves the problem with repeatable tftp transfers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agonet: gem: Simplify return path in zynq_gem_recv
Michal Simek [Fri, 25 Jan 2013 07:24:18 +0000 (08:24 +0100)]
net: gem: Simplify return path in zynq_gem_recv

Remove one return from the code.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agonet: gem: Remove WRAP bit from TX buffer description
Michal Simek [Wed, 17 Oct 2012 09:03:40 +0000 (11:03 +0200)]
net: gem: Remove WRAP bit from TX buffer description

Removing this bit causes that frame is sent only once.
(With wrap big one packet has been sent several times
which dramatically decrease throughput)

TRM: (Table 16-3: Tx Buffer Descriptor Entry)

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agonet: phy: Define Marvell 88e1518 phy
Michal Simek [Mon, 15 Oct 2012 12:03:00 +0000 (14:03 +0200)]
net: phy: Define Marvell 88e1518 phy

This phy is used on zedboard (xilinx zynq platform).

Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agozynq: Move scutimer baseaddr to hardware.h
Michal Simek [Fri, 12 Apr 2013 14:21:26 +0000 (16:21 +0200)]
zynq: Move scutimer baseaddr to hardware.h

Move baseaddr to hardware.h to be shared between
configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agoarm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addresses
Michal Simek [Tue, 23 Apr 2013 09:35:18 +0000 (11:35 +0200)]
arm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addresses

XPSS prefix was used in past and it is obsolete for quite
some time. Let's use correct SoC name which is Zynq.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agoarm: zynq: U-Boot udelay < 1000 FIX
David Andrey [Fri, 7 Dec 2012 15:51:32 +0000 (16:51 +0100)]
arm: zynq: U-Boot udelay < 1000 FIX

Rework the __udelay function of U-Boot Zynq Arch to handle
delay < 1000 usec

Signed-off-by: David Andrey <david.andrey@netmodule.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
7 years agoPrepare v2013.04 v2013.04
Tom Rini [Fri, 19 Apr 2013 14:25:43 +0000 (10:25 -0400)]
Prepare v2013.04

Signed-off-by: Tom Rini <trini@ti.com>
7 years agocrc32: Correct endianness of crc32 result
Simon Glass [Thu, 18 Apr 2013 10:25:51 +0000 (10:25 +0000)]
crc32: Correct endianness of crc32 result

When crc32 is handled by the hash library, it requires the data to be in
big-endian format, since it reads it byte-wise. Thus at present the 'crc32'
command reports incorrect data. For example, previously we might see:

Peach # crc32 40000000 100
CRC32 for 40000000 ... 400000ff ==> 0d968558

but instead with the hash library we see:

Peach # crc32 40000000 100
CRC32 for 40000000 ... 400000ff ==> 5885960d

Correct this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
7 years agopatman: fix gitutil for decorations
Andreas Bießmann [Mon, 15 Apr 2013 23:52:18 +0000 (23:52 +0000)]
patman: fix gitutil for decorations

The git config parameter log.decorate is quite useful when working with git.
Patman, however can not handle the decorated output when parsing the commit.
To prevent this use the '--no-decorate' switch for git-log.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Simon Glass <sjg@chromium.org>
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm into HEAD
Tom Rini [Thu, 18 Apr 2013 20:16:01 +0000 (16:16 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm into HEAD

Quick manual fixup to merge the USB boot related defines and TPM related
defines.

Conflicts:
include/configs/exynos5250-dt.h

Signed-off-by: Tom Rini <trini@ti.com>
7 years agofdt: Ensure that libfdt_env.h comes from U-Boot
Simon Glass [Mon, 11 Mar 2013 06:30:27 +0000 (06:30 +0000)]
fdt: Ensure that libfdt_env.h comes from U-Boot

When building host utilities, we include libfdt.h from the host, not from
U-Boot. This in turn brings in libfdt_env.h from the host, which can mess
up the types and cause a build failure, depending on the host environment.
To fix this, force inclusion of U-Boot's libfdt_env.h so that the types
are correct.

Another way to fix this is to use -nostdinc and -idirafter to ensure that
system includes are included after U-Boot ones. Unfortunately this means
that U-Boot's errno.h gets included instead of the system one. This in
turn requires a hack to errno.h to redirect things, so all in all the
solution in this patch is probably cleaner.

Signed-off-by: Simon Glass <sjg@chromium.org>
7 years agommc: check the revision for sd3.0
Jaehoon Chung [Tue, 29 Jan 2013 22:58:16 +0000 (22:58 +0000)]
mmc: check the revision for sd3.0

Support to check whether the SD3.0 or not.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Rommel Custodio <sessyargc@gmail.com>
7 years agommc: support the correct card version for eMMC
Jaehoon Chung [Tue, 29 Jan 2013 19:31:16 +0000 (19:31 +0000)]
mmc: support the correct card version for eMMC

eMMC vesrion is supported up to v4.5.
But bootloader isn't saw the exact eMMC version.
After applied this patch,
if use the mmcinfo command, then can see the exactly mmc version.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Rommel Custodio <sessyargc@gmail.com>
7 years agoprintenv: Correct out-of-memory condition check.
Maxime Larocque [Fri, 28 Sep 2012 05:00:13 +0000 (05:00 +0000)]
printenv: Correct out-of-memory condition check.

In common/cmd_nvedit.c, en env_print(), the wrong type is used for len.
hexport_r() returns -1 on error (like OOM), which is converted to
0xffffffff when put in an unsigned. Said value is obviously bigger then
0, and as a result an uninitialized string is then displayed. Other
usages of hexport_r() in the code correctly uses ssize_t to keep its
return value.

Signed-off-by: Maxime Larocque <maxmtl2002@yahoo.ca>
7 years agoexynos: fdt: Add TMU node for snow
Simon Glass [Sat, 13 Apr 2013 04:26:42 +0000 (04:26 +0000)]
exynos: fdt: Add TMU node for snow

Snow is missing a TMU node, and with TMU support this is not allowed, so it
fails to boot. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoexynos: Correct use of 64-bit division
Simon Glass [Sat, 13 Apr 2013 04:26:41 +0000 (04:26 +0000)]
exynos: Correct use of 64-bit division

The current code is causing errors like this on my toolchains:

/usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/
ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/
armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o)

Use do_div() to avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
7 years agoExynos5: Add support for USB download boot mode
Vivek Gautam [Mon, 28 Jan 2013 00:39:59 +0000 (00:39 +0000)]
Exynos5: Add support for USB download boot mode

Exynos5250 supports secondary USB device boot mode. If the iROM fails
to download u-boot from the primary boot device (such as SD or eMMC),
it will try to retrieve from the secondary boot device (such as USB).

Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
8 years agoMerge branch 'master' of git://git.denx.de/u-boot-x86
Tom Rini [Tue, 16 Apr 2013 20:12:33 +0000 (16:12 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-x86

8 years agoMerge branch 'master' of git://git.denx.de/u-boot-arm
Tom Rini [Tue, 16 Apr 2013 14:56:55 +0000 (10:56 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-arm

8 years agox86: config: Init PCI before SPI
Simon Glass [Mon, 15 Apr 2013 11:25:21 +0000 (11:25 +0000)]
x86: config: Init PCI before SPI

Since the ICH SPI controller uses PCI, we must ensure that PCI is available
before it is inited.

This fixes the current "ICH SPI: Cannot find device" message on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agox86: Allow setup code to manage its own global data
Simon Glass [Mon, 15 Apr 2013 11:25:20 +0000 (11:25 +0000)]
x86: Allow setup code to manage its own global data

Currently x86 has its own means of managing the global data and board data
(bd_t), and this code resides in start.S. With generic board, we need to
ensure that we leave this alone - i.e. don't clear it as we do on other
archs.

This fixes a problem where the memory init data is cleared which causes
the video driver to operate very slowly.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agox86: Fix DRAM bank size init with generic board
Simon Glass [Mon, 15 Apr 2013 11:22:49 +0000 (11:22 +0000)]
x86: Fix DRAM bank size init with generic board

The intention of the memory init code is that it should work the same with
CONFIG_SYS_GENERIC_BOARD and without. This is tricky because dram_init()
is called prior to relocation with generic board (matching other archs)
and after relocation without generic board.

Adjust the init sequence so that dram_init() is not called in the generic
board case, which seems like the easiest fix for now. Also ensure that
relocation addresses are still calculated.

Signed-off-by: Simon Glass <sjg@chromium.org>
8 years agoTegra: T30: Beaver board support.
Tom Warren [Fri, 12 Apr 2013 18:20:51 +0000 (11:20 -0700)]
Tegra: T30: Beaver board support.

Beaver is a Tegra30 board that is nearly 100% compatible w/Cardhu.
Add a Beaver build so it can begin to be differentiated, if need be.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agoTegra: Split tegra_get_chip_type() into soc & sku funcs
Tom Warren [Wed, 10 Apr 2013 17:32:32 +0000 (10:32 -0700)]
Tegra: Split tegra_get_chip_type() into soc & sku funcs

As suggested by Stephen Warren, use tegra_get_chip() to return
the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for
Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true
function, i.e. tegra_get_chip_sku(), which returns an ID like
TEGRA_SOC_T25, TEGRA_SOC_T33, etc.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agoTegra: Fix MSELECT clock divisors for T30/T114.
Tom Warren [Wed, 3 Apr 2013 21:39:30 +0000 (14:39 -0700)]
Tegra: Fix MSELECT clock divisors for T30/T114.

A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agoTegra114: Initialize System Counter (TSC) with osc frequency
Tom Warren [Mon, 1 Apr 2013 22:48:54 +0000 (15:48 -0700)]
Tegra114: Initialize System Counter (TSC) with osc frequency

T114 needs the SYSCTR0 counter initialized so the TSC can be
read by the kernel. Do it in the bootloader since it's a write-once
deal (secure/non-secure mode dependent).

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agoTegra: Configure L2 cache control reg properly.
Tom Warren [Mon, 25 Mar 2013 23:22:26 +0000 (16:22 -0700)]
Tegra: Configure L2 cache control reg properly.

Without this change, kernel fails at calling function cache_clean_flush
during kernel early boot.

Aprocryphally, intended for T114 only, so I check for a T114 SoC.
Works (i.e. dalmore 3.8 kernel now starts printing to console).

Signed-off-by: Tom Warren <twarren@nvidia.com>
8 years agoTegra: TEC: Enable boot script support
Thierry Reding [Wed, 3 Apr 2013 04:52:45 +0000 (04:52 +0000)]
Tegra: TEC: Enable boot script support

Boot script support brings TEC in line with other Tegra boards. To
enable booting a Linux kernel with initial ramdisk, also include support
for the new FIT image type.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agoTegra: Plutux: Enable NAND and boot script support
Thierry Reding [Wed, 3 Apr 2013 04:52:44 +0000 (04:52 +0000)]
Tegra: Plutux: Enable NAND and boot script support

Boot script support brings Plutux in line with other Tegra boards. In
order to enable booting a Linux kernel with initial ramdisk, also add
support for the new FIT image type.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agoTegra: Medcom-Wide: Enable NAND and boot script support
Thierry Reding [Wed, 3 Apr 2013 04:52:43 +0000 (04:52 +0000)]
Tegra: Medcom-Wide: Enable NAND and boot script support

Boot script support brings Medcom-Wide in line with other Tegra boards.
In order to enable booting a Linux kernel with initial ramdisk, also add
support for the new FIT image type.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agoTegra: All Tamonten-derived boards use onboard NAND
Thierry Reding [Wed, 3 Apr 2013 04:52:42 +0000 (04:52 +0000)]
Tegra: All Tamonten-derived boards use onboard NAND

Move the nand-controller node to the tegra20-tamonten.dtsi so that it
can be shared between all derived boards.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
8 years agoTegra: Restore cp15 VBAR _start vector write for ARMv7
Tom Warren [Thu, 28 Mar 2013 17:03:22 +0000 (10:03 -0700)]
Tegra: Restore cp15 VBAR _start vector write for ARMv7

A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53),
and caused the old monilithic Tegra builds to hang due to an undefined
instruction trap. Previously, the code needed to run on both the
AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register.
I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but
now that we use SPL, and boot the AVP w/o any ARMv7 code, I can
revert my change, and make Aneesh's change apply to Tegra.

Signed-off-by: Tom Warren <twarren@nvidia.com>