1 /* ============================================================================
2 * Copyright (c) 2016 Texas Instruments Incorporated.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 ===============================================================================*/
33 #ifndef _PLL_CONTROL_H_
34 #define _PLL_CONTROL_H_
36 #include "csl_types.h"
38 /* PLL frequency setting options -- all options use RTC clock as input */
39 typedef enum
40 {
41 PLL_FREQ_16P384MHZ = 0,
42 PLL_FREQ_32P768MHZ,
43 PLL_FREQ_40MHZ,
44 PLL_FREQ_50MHZ,
45 PLL_FREQ_60MHZ,
46 PLL_FREQ_75MHZ,
47 PLL_FREQ_100MHZ,
48 PLL_FREQ_120MHZ
49 } EPllFreq;
51 /* Sets PLL to desired output frequency =
52 {32.768, 40, 50, 60, 75, 100, 120} MHZ.
53 Default is 60 MHz.
54 Assumes CPU core voltage is set appropriately for requested output frequency. */
55 CSL_Status pll_sample(
56 EPllFreq pllFreq
57 );
59 #endif /* _PLL_CONTROL_H_ */