1 /*
2 * Copyright (c) 2012-2016, Texas Instruments Incorporated
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
24 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
25 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
27 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
33 /*
34 * ======== rsc_table_vayu_ipu.h ========
35 *
36 * Define the resource table entries for all IPU cores. This will be
37 * incorporated into corresponding base images, and used by the remoteproc
38 * on the host-side to allocated/reserve resources.
39 *
40 */
42 #ifndef _RSC_TABLE_VAYU_IPU_H_
43 #define _RSC_TABLE_VAYU_IPU_H_
45 #define VAYU_IPU_1
46 #include "rsc_types.h"
48 /* IPU Memory Map */
49 #define L4_DRA7XX_BASE 0x4A000000
51 /* L4_CFG & L4_WKUP */
52 #define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
53 #define IPU_PERIPHERAL_L4CFG 0x6A000000
55 #define L4_PERIPHERAL_L4PER1 0x48000000
56 #define IPU_PERIPHERAL_L4PER1 0x68000000
58 #define L4_PERIPHERAL_L4PER2 0x48400000
59 #define IPU_PERIPHERAL_L4PER2 0x68400000
61 #define L4_PERIPHERAL_L4PER3 0x48800000
62 #define IPU_PERIPHERAL_L4PER3 0x68800000
64 #define L4_PERIPHERAL_L4EMU 0x54000000
65 #define IPU_PERIPHERAL_L4EMU 0x74000000
67 #define L3_PERIPHERAL_PRUSS 0x4B200000
68 #define IPU_PERIPHERAL_PRUSS 0x6B200000
70 #define L3_PERIPHERAL_DMM 0x4E000000
71 #define IPU_PERIPHERAL_DMM 0x6E000000
73 #define L3_IVAHD_CONFIG 0x5A000000
74 #define IPU_IVAHD_CONFIG 0x7A000000
76 #define L3_IVAHD_SL2 0x5B000000
77 #define IPU_IVAHD_SL2 0x7B000000
79 #define L3_TILER_MODE_0_1 0x60000000
80 #define IPU_TILER_MODE_0_1 0xA0000000
82 #define L3_TILER_MODE_2 0x70000000
83 #define IPU_TILER_MODE_2 0xB0000000
85 #define L3_TILER_MODE_3 0x78000000
86 #define IPU_TILER_MODE_3 0xB8000000
88 #define L3_OCMC_RAM 0x40300000
89 #define IPU_OCMC_RAM 0x60300000
91 #define L3_EMIF_SDRAM 0xA0000000
92 #define IPU_EMIF_SDRAM 0x10000000
94 #define IPU_MEM_TEXT 0x0
95 #define IPU_MEM_DATA 0x80000000
97 #define IPU_MEM_IOBUFS 0x90000000
99 #define IPU_MEM_IPC_DATA 0x9F000000
100 #define IPU_MEM_IPC_VRING 0x60000000
101 #define IPU_MEM_RPMSG_VRING0 0x60000000
102 #define IPU_MEM_RPMSG_VRING1 0x60004000
103 #define IPU_MEM_VRING_BUFS0 0x60040000
104 #define IPU_MEM_VRING_BUFS1 0x60080000
106 #define IPU_MEM_IPC_VRING_SIZE SZ_1M
107 #define IPU_MEM_IPC_DATA_SIZE SZ_1M
109 #if defined(VAYU_IPU_1)
110 #define IPU_MEM_TEXT_SIZE (SZ_1M)
111 #elif defined(VAYU_IPU_2)
112 #define IPU_MEM_TEXT_SIZE (SZ_1M * 6)
113 #endif
115 #if defined(VAYU_IPU_1)
116 #define IPU_MEM_DATA_SIZE (SZ_1M * 5)
117 #elif defined(VAYU_IPU_2)
118 #define IPU_MEM_DATA_SIZE (SZ_1M * 48)
119 #endif
121 #define IPU_MEM_IOBUFS_SIZE (SZ_1M * 90)
123 /*
124 * Assign fixed RAM addresses to facilitate a fixed MMU table.
125 * PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together.
126 */
127 /* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
128 #if defined(VAYU_IPU_1)
129 #define PHYS_MEM_IPC_VRING 0x9D000000
130 #elif defined (VAYU_IPU_2)
131 #define PHYS_MEM_IPC_VRING 0x95800000
132 #endif
134 #define PHYS_MEM_IOBUFS 0xBA300000
136 /*
137 * Sizes of the virtqueues (expressed in number of buffers supported,
138 * and must be power of 2)
139 */
140 #define IPU_RPMSG_VQ0_SIZE 256
141 #define IPU_RPMSG_VQ1_SIZE 256
143 /* flip up bits whose indices represent features we support */
144 #define RPMSG_IPU_C0_FEATURES 1
146 struct my_resource_table {
147 struct resource_table base;
149 UInt32 offset[21]; /* Should match 'num' in actual definition */
151 /* rpmsg vdev entry */
152 struct fw_rsc_vdev rpmsg_vdev;
153 struct fw_rsc_vdev_vring rpmsg_vring0;
154 struct fw_rsc_vdev_vring rpmsg_vring1;
156 /* text carveout entry */
157 struct fw_rsc_carveout text_cout;
159 /* data carveout entry */
160 struct fw_rsc_carveout data_cout;
162 /* ipcdata carveout entry */
163 struct fw_rsc_carveout ipcdata_cout;
165 /* trace entry */
166 struct fw_rsc_trace trace;
168 /* devmem entry */
169 struct fw_rsc_devmem devmem0;
171 /* devmem entry */
172 struct fw_rsc_devmem devmem1;
174 /* devmem entry */
175 struct fw_rsc_devmem devmem2;
177 /* devmem entry */
178 struct fw_rsc_devmem devmem3;
180 /* devmem entry */
181 struct fw_rsc_devmem devmem4;
183 /* devmem entry */
184 struct fw_rsc_devmem devmem5;
186 /* devmem entry */
187 struct fw_rsc_devmem devmem6;
189 /* devmem entry */
190 struct fw_rsc_devmem devmem7;
192 /* devmem entry */
193 struct fw_rsc_devmem devmem8;
195 /* devmem entry */
196 struct fw_rsc_devmem devmem9;
198 /* devmem entry */
199 struct fw_rsc_devmem devmem10;
201 /* devmem entry */
202 struct fw_rsc_devmem devmem11;
204 /* devmem entry */
205 struct fw_rsc_devmem devmem12;
207 /* devmem entry */
208 struct fw_rsc_devmem devmem13;
210 /* devmem entry */
211 struct fw_rsc_devmem devmem14;
213 /* devmem entry */
214 struct fw_rsc_devmem devmem15;
215 };
216 extern char ti_trace_SysMin_Module_State_0_outbuf__A;
217 #define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
219 #pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
220 #pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
222 struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
223 1, /* we're the first version that implements this */
224 21, /* number of entries in the table */
225 0, 0, /* reserved, must be zero */
226 /* offsets to entries */
227 {
228 offsetof(struct my_resource_table, rpmsg_vdev),
229 offsetof(struct my_resource_table, text_cout),
230 offsetof(struct my_resource_table, data_cout),
231 offsetof(struct my_resource_table, ipcdata_cout),
232 offsetof(struct my_resource_table, trace),
233 offsetof(struct my_resource_table, devmem0),
234 offsetof(struct my_resource_table, devmem1),
235 offsetof(struct my_resource_table, devmem2),
236 offsetof(struct my_resource_table, devmem3),
237 offsetof(struct my_resource_table, devmem4),
238 offsetof(struct my_resource_table, devmem5),
239 offsetof(struct my_resource_table, devmem6),
240 offsetof(struct my_resource_table, devmem7),
241 offsetof(struct my_resource_table, devmem8),
242 offsetof(struct my_resource_table, devmem9),
243 offsetof(struct my_resource_table, devmem10),
244 offsetof(struct my_resource_table, devmem11),
245 offsetof(struct my_resource_table, devmem12),
246 offsetof(struct my_resource_table, devmem13),
247 offsetof(struct my_resource_table, devmem14),
248 offsetof(struct my_resource_table, devmem15),
249 },
251 /* rpmsg vdev entry */
252 {
253 TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
254 RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
255 /* no config data */
256 },
257 /* the two vrings */
258 { IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 },
259 { IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 },
261 {
262 TYPE_CARVEOUT,
263 IPU_MEM_TEXT, 0,
264 IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT",
265 },
267 {
268 TYPE_CARVEOUT,
269 IPU_MEM_DATA, 0,
270 IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA",
271 },
273 {
274 TYPE_CARVEOUT,
275 IPU_MEM_IPC_DATA, 0,
276 IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA",
277 },
279 {
280 TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:sysm3",
281 },
283 {
284 TYPE_DEVMEM,
285 IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
286 IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING",
287 },
289 {
290 TYPE_DEVMEM,
291 IPU_MEM_IOBUFS, PHYS_MEM_IOBUFS,
292 IPU_MEM_IOBUFS_SIZE, 0, 0, "IPU_MEM_IOBUFS",
293 },
295 {
296 TYPE_DEVMEM,
297 IPU_TILER_MODE_0_1, L3_TILER_MODE_0_1,
298 SZ_256M, 0, 0, "IPU_TILER_MODE_0_1",
299 },
301 {
302 TYPE_DEVMEM,
303 IPU_TILER_MODE_2, L3_TILER_MODE_2,
304 SZ_128M, 0, 0, "IPU_TILER_MODE_2",
305 },
307 {
308 TYPE_DEVMEM,
309 IPU_TILER_MODE_3, L3_TILER_MODE_3,
310 SZ_128M, 0, 0, "IPU_TILER_MODE_3",
311 },
313 {
314 TYPE_DEVMEM,
315 IPU_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
316 SZ_16M, 0, 0, "IPU_PERIPHERAL_L4CFG",
317 },
319 {
320 TYPE_DEVMEM,
321 IPU_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
322 SZ_2M, 0, 0, "IPU_PERIPHERAL_L4PER1",
323 },
325 {
326 TYPE_DEVMEM,
327 IPU_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
328 SZ_4M, 0, 0, "IPU_PERIPHERAL_L4PER2",
329 },
331 {
332 TYPE_DEVMEM,
333 IPU_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
334 SZ_8M, 0, 0, "IPU_PERIPHERAL_L4PER3",
335 },
337 {
338 TYPE_DEVMEM,
339 IPU_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
340 SZ_16M, 0, 0, "IPU_PERIPHERAL_L4EMU",
341 },
343 {
344 TYPE_DEVMEM,
345 IPU_PERIPHERAL_PRUSS, L3_PERIPHERAL_PRUSS,
346 SZ_1M, 0, 0, "IPU_PERIPHERAL_PRUSS",
347 },
349 {
350 TYPE_DEVMEM,
351 IPU_IVAHD_CONFIG, L3_IVAHD_CONFIG,
352 SZ_16M, 0, 0, "IPU_IVAHD_CONFIG",
353 },
355 {
356 TYPE_DEVMEM,
357 IPU_IVAHD_SL2, L3_IVAHD_SL2,
358 SZ_16M, 0, 0, "IPU_IVAHD_SL2",
359 },
361 {
362 TYPE_DEVMEM,
363 IPU_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
364 SZ_1M, 0, 0, "IPU_PERIPHERAL_DMM",
365 },
367 {
368 TYPE_DEVMEM,
369 IPU_OCMC_RAM, L3_OCMC_RAM,
370 SZ_4M, 0, 0, "IPU_OCMC_RAM",
371 },
373 {
374 TYPE_DEVMEM,
375 IPU_EMIF_SDRAM, L3_EMIF_SDRAM,
376 SZ_256M, 0, 0, "IPU_EMIF_SDRAM",
377 },
379 };
381 #endif /* _RSC_TABLE_VAYU_IPU_H_ */