initial release master
authorGarrett Ding <g-ding@ti.com>
Mon, 2 May 2016 17:57:18 +0000 (13:57 -0400)
committerGarrett Ding <g-ding@ti.com>
Mon, 2 May 2016 17:57:18 +0000 (13:57 -0400)
Signed-off-by: Garrett Ding <g-ding@ti.com>
40 files changed:
dsp1/Dsp1.cfg [new file with mode: 0644]
dsp1/MainDsp1.c [new file with mode: 0644]
dsp1/Server.c [new file with mode: 0644]
dsp1/Server.h [new file with mode: 0644]
dsp1/makefile [new file with mode: 0644]
dsp2/Dsp2.cfg [new file with mode: 0644]
dsp2/MainDsp2.c [new file with mode: 0644]
dsp2/Server.c [new file with mode: 0644]
dsp2/Server.h [new file with mode: 0644]
dsp2/makefile [new file with mode: 0644]
host/App.c [new file with mode: 0644]
host/App.h [new file with mode: 0644]
host/goose [new file with mode: 0644]
host/main_host.c [new file with mode: 0644]
host/makefile [new file with mode: 0644]
ipu1/Ipu1.cfg [new file with mode: 0644]
ipu1/IpuAmmu.cfg [new file with mode: 0644]
ipu1/MainIpu1.c [new file with mode: 0644]
ipu1/PktProcEng.c [new file with mode: 0644]
ipu1/PktSwitch.c [new file with mode: 0644]
ipu1/Server.c [new file with mode: 0644]
ipu1/Server.h [new file with mode: 0644]
ipu1/icss_emacDrv.c [new file with mode: 0644]
ipu1/icss_emacDrv.h [new file with mode: 0644]
ipu1/makefile [new file with mode: 0644]
ipu1/rsc_table_vayu_ipu.h [new file with mode: 0644]
ipu1/rsc_types.h [new file with mode: 0644]
ipu2/Ipu2.cfg [new file with mode: 0644]
ipu2/IpuAmmu.cfg [new file with mode: 0644]
ipu2/MainIpu2.c [new file with mode: 0644]
ipu2/Server.c [new file with mode: 0644]
ipu2/Server.h [new file with mode: 0644]
ipu2/makefile [new file with mode: 0644]
makefile [new file with mode: 0644]
manifest.htm [new file with mode: 0755]
products.mak [new file with mode: 0644]
readme.txt [new file with mode: 0644]
shared/AppCommon.h [new file with mode: 0644]
shared/config.bld [new file with mode: 0644]
shared/ipc.cfg.xs [new file with mode: 0644]

diff --git a/dsp1/Dsp1.cfg b/dsp1/Dsp1.cfg
new file mode 100644 (file)
index 0000000..3a51ed3
--- /dev/null
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2013-2015 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Dsp1.cfg ========
+ *  Platform: DRA7XX_linux_elf
+ *  Target: ti.targets.elf.C66
+ */
+
+/* root of the configuration object model */
+var Program = xdc.useModule('xdc.cfg.Program');
+
+/* application uses the following modules and packages */
+xdc.useModule('xdc.runtime.Assert');
+xdc.useModule('xdc.runtime.Diags');
+xdc.useModule('xdc.runtime.Error');
+xdc.useModule('xdc.runtime.Log');
+xdc.useModule('xdc.runtime.Registry');
+
+xdc.useModule('ti.sysbios.knl.Semaphore');
+xdc.useModule('ti.sysbios.knl.Task');
+
+/*
+ *  ======== IPC Configuration ========
+ */
+xdc.useModule('ti.ipc.ipcmgr.IpcMgr');
+
+/* load the configuration shared across cores  */
+Program.global.procName = "DSP1";
+var ipc_cfg = xdc.loadCapsule("../shared/ipc.cfg.xs");
+
+var BIOS        = xdc.useModule('ti.sysbios.BIOS');
+BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');
+
+/*
+ *  ======== SYS/BIOS Configuration ========
+ */
+if (Program.build.profile == "debug") {
+    BIOS.libType = BIOS.LibType_Debug;
+} else {
+    BIOS.libType = BIOS.LibType_Custom;
+}
+
+/* no rts heap */
+Program.argSize = 100;  /* minimum size */
+Program.stack = 0x1000;
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.common$.namedInstance = true;
+
+/* default memory heap */
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var heapMemParams = new HeapMem.Params();
+heapMemParams.size = 0x8000;
+Memory.defaultHeapInstance = HeapMem.create(heapMemParams);
+
+/* create a heap for MessageQ messages */
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var params = new HeapBuf.Params;
+params.align = 8;
+params.blockSize = 512;
+params.numBlocks = 256;
+var msgHeap = HeapBuf.create(params);
+
+var MessageQ  = xdc.useModule('ti.sdo.ipc.MessageQ');
+MessageQ.registerHeapMeta(msgHeap, 0);
+
+/* Setup MessageQ transport */
+var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
+MessageQ.SetupTransportProxy = VirtioSetup;
+
+/* Setup NameServer remote proxy */
+var NameServer = xdc.useModule("ti.sdo.utils.NameServer");
+var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
+NameServer.SetupProxy = NsRemote;
+
+/* Enable Memory Translation module that operates on the BIOS Resource Table */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.loadSegment = "EXT_CODE";
+
+/*  Use SysMin because trace buffer address is required for Linux/QNX
+ *  trace debug driver, plus provides better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('ti.trace.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize  = 0x8000;
+
+Program.sectMap[".tracebuf"] = "TRACE_BUF";
+Program.sectMap[".errorbuf"] = "EXC_DATA";
+
+/* --------------------------- TICK --------------------------------------*/
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+Clock.tickSource = Clock.TickSource_NULL;
+//Clock.tickSource = Clock.TickSource_USER;
+/* Configure BIOS clock source as GPTimer5 */
+//Clock.timerId = 0;
+
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+
+/* Skip the Timer frequency verification check. Need to remove this later */
+Timer.checkFrequency = false;
+
+/* Match this to the SYS_CLK frequency sourcing the dmTimers.
+ * Not needed once the SYS/BIOS family settings is updated. */
+Timer.intFreq.hi = 0;
+Timer.intFreq.lo = 19200000;
+
+//var timerParams = new Timer.Params();
+//timerParams.period = Clock.tickPeriod;
+//timerParams.periodType = Timer.PeriodType_MICROSECS;
+/* Switch off Software Reset to make the below settings effective */
+//timerParams.tiocpCfg.softreset = 0x0;
+/* Smart-idle wake-up-capable mode */
+//timerParams.tiocpCfg.idlemode = 0x3;
+/* Wake-up generation for Overflow */
+//timerParams.twer.ovf_wup_ena = 0x1;
+//Timer.create(Clock.timerId, Clock.doTick, timerParams);
+
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+var Deh = xdc.useModule('ti.deh.Deh');
+
+/* Must be placed before pwr mgmt */
+Idle.addFunc('&ti_deh_Deh_idleBegin');
+/*
+ *  ======== Instrumentation Configuration ========
+ */
+
+/* system logger */
+var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
+var LoggerSysParams = new LoggerSys.Params();
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
+
+/* enable runtime Diags_setMask() for non-XDC spec'd modules */
+var Diags = xdc.useModule('xdc.runtime.Diags');
+Diags.setMaskEnabled = true;
+
+/* override diags mask for selected modules */
+xdc.useModule('xdc.runtime.Main');
+Diags.setMaskMeta("xdc.runtime.Main",
+    Diags.ENTRY | Diags.EXIT | Diags.INFO, Diags.RUNTIME_ON);
+
+var Registry = xdc.useModule('xdc.runtime.Registry');
+Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF;
+Registry.common$.diags_EXIT  = Diags.RUNTIME_OFF;
+Registry.common$.diags_INFO  = Diags.RUNTIME_OFF;
+Registry.common$.diags_USER1 = Diags.RUNTIME_OFF;
+Registry.common$.diags_LIFECYCLE = Diags.RUNTIME_OFF;
+Registry.common$.diags_STATUS = Diags.RUNTIME_OFF;
+
+var Main = xdc.useModule('xdc.runtime.Main');
+Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
+Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
diff --git a/dsp1/MainDsp1.c b/dsp1/MainDsp1.c
new file mode 100644 (file)
index 0000000..bdec50e
--- /dev/null
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== main_Dsp1.c ========
+ *
+ */
+
+/* xdctools header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/Log.h>
+#include <xdc/runtime/System.h>
+
+/* package header files */
+#include <ti/ipc/Ipc.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+
+/* local header files */
+#include "Server.h"
+
+/* private functions */
+static Void smain(UArg arg0, UArg arg1);
+
+
+/*
+ *  ======== main ========
+ */
+Int main(Int argc, Char* argv[])
+{
+    Error_Block     eb;
+    Task_Params     taskParams;
+
+    Log_print0(Diags_ENTRY, "--> main:");
+
+    /* must initialize the error block before using it */
+    Error_init(&eb);
+
+    /* create main thread (interrupts not enabled in main on BIOS) */
+    Task_Params_init(&taskParams);
+    taskParams.instance->name = "smain";
+    taskParams.arg0 = (UArg)argc;
+    taskParams.arg1 = (UArg)argv;
+    taskParams.stackSize = 0x1000;
+    Task_create(smain, &taskParams, &eb);
+
+    if (Error_check(&eb)) {
+        System_abort("main: failed to create application startup thread");
+    }
+
+    /* start scheduler, this never returns */
+    BIOS_start();
+
+    /* should never get here */
+    Log_print0(Diags_EXIT, "<-- main:");
+    return (0);
+}
+
+
+/*
+ *  ======== smain ========
+ */
+Void smain(UArg arg0, UArg arg1)
+{
+    Int                 status = 0;
+    Error_Block         eb;
+    Bool                running = TRUE;
+
+    Log_print0(Diags_ENTRY | Diags_INFO, "--> smain:");
+
+    Error_init(&eb);
+
+    /* initialize modules */
+    Server_init();
+
+    /* turn on Diags_INFO trace */
+    Diags_setMask("Server+F");
+
+    /* loop forever */
+    while (running) {
+
+        /* BEGIN server phase */
+
+        /* server setup phase */
+        status = Server_create();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* server execute phase */
+        status = Server_exec();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* server shutdown phase */
+        status = Server_delete();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* END server phase */
+
+    } /* while (running) */
+
+    /* finalize modules */
+    Server_exit();
+
+leave:
+    Log_print1(Diags_EXIT, "<-- smain: %d", (IArg)status);
+    return;
+}
diff --git a/dsp1/Server.c b/dsp1/Server.c
new file mode 100644 (file)
index 0000000..3d83084
--- /dev/null
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Server.c ========
+ *
+ */
+
+/* this define must precede inclusion of any xdc header file */
+#define Registry_CURDESC Test__Desc
+#define MODULE_NAME "Server"
+
+/* xdctools header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Assert.h>
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Log.h>
+#include <xdc/runtime/Registry.h>
+
+#include <stdio.h>
+
+/* package header files */
+#include <ti/ipc/MessageQ.h>
+#include <ti/ipc/MultiProc.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+
+/* local header files */
+#include "../shared/AppCommon.h"
+
+/* module header file */
+#include "Server.h"
+
+/* module structure */
+typedef struct {
+    UInt16              hostProcId;         // host processor id
+    MessageQ_Handle     slaveQue;           // created locally
+} Server_Module;
+
+/* private data */
+Registry_Desc               Registry_CURDESC;
+static Server_Module        Module;
+
+
+/*
+ *  ======== Server_init ========
+ */
+Void Server_init(Void)
+{
+    Registry_Result result;
+
+    /* register with xdc.runtime to get a diags mask */
+    result = Registry_addModule(&Registry_CURDESC, MODULE_NAME);
+    Assert_isTrue(result == Registry_SUCCESS, (Assert_Id)NULL);
+
+    /* initialize module object state */
+    Module.hostProcId = MultiProc_getId("HOST");
+}
+
+
+/*
+ *  ======== Server_create ========
+ */
+Int Server_create()
+{
+    Int                 status = 0;
+    MessageQ_Params     msgqParams;
+    char                msgqName[32];
+
+    /* enable some log events */
+    Diags_setMask(MODULE_NAME"+EXF");
+
+    /* create local message queue (inbound messages) */
+    MessageQ_Params_init(&msgqParams);
+    sprintf(msgqName, App_SlaveMsgQueName, MultiProc_getName(MultiProc_self()));
+    Module.slaveQue = MessageQ_create(msgqName, &msgqParams);
+
+    if (Module.slaveQue == NULL) {
+        status = -1;
+        goto leave;
+    }
+
+    Log_print0(Diags_INFO,"Server_create: server is ready");
+
+leave:
+    Log_print1(Diags_EXIT, "<-- Server_create: %d", (IArg)status);
+    return (status);
+}
+
+
+
+
+/*
+ *  ======== Server_exec ========
+ */
+Int Server_exec()
+{
+    Int                 status;
+    Bool                running = TRUE;
+    App_Msg *           msg;
+    MessageQ_QueueId    queId;
+
+    Log_print0(Diags_ENTRY | Diags_INFO, "--> Server_exec:");
+
+    while (running) {
+
+        /* wait for inbound message */
+        status = MessageQ_get(Module.slaveQue, (MessageQ_Msg *)&msg,
+            MessageQ_FOREVER);
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        if (msg->cmd == App_CMD_SHUTDOWN) {
+            running = FALSE;
+        }
+
+        /* process the message */
+        Log_print1(Diags_INFO, "Server_exec: processed cmd=0x%x", msg->cmd);
+
+        /* send message back */
+        queId = MessageQ_getReplyQueue(msg); /* type-cast not needed */
+        MessageQ_put(queId, (MessageQ_Msg)msg);
+    } /* while (running) */
+
+leave:
+    Log_print1(Diags_EXIT, "<-- Server_exec: %d", (IArg)status);
+    return(status);
+}
+
+/*
+ *  ======== Server_delete ========
+ */
+
+Int Server_delete()
+{
+    Int         status;
+
+    Log_print0(Diags_ENTRY, "--> Server_delete:");
+
+    /* delete the video message queue */
+    status = MessageQ_delete(&Module.slaveQue);
+
+    if (status < 0) {
+        goto leave;
+    }
+
+leave:
+    if (status < 0) {
+        Log_error1("Server_finish: error=0x%x", (IArg)status);
+    }
+
+    /* disable log events */
+    Log_print1(Diags_EXIT, "<-- Server_delete: %d", (IArg)status);
+    Diags_setMask(MODULE_NAME"-EXF");
+
+    return(status);
+}
+
+/*
+ *  ======== Server_exit ========
+ */
+
+Void Server_exit(Void)
+{
+    /*
+     * Note that there isn't a Registry_removeModule() yet:
+     *     https://bugs.eclipse.org/bugs/show_bug.cgi?id=315448
+     *
+     * ... but this is where we'd call it.
+     */
+}
diff --git a/dsp1/Server.h b/dsp1/Server.h
new file mode 100644 (file)
index 0000000..5278f23
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+#  Copyright (c) 2012-2014 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Server.h ========
+ */
+
+#ifndef Server__include
+#define Server__include
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+
+Void Server_init(Void);
+Void Server_exit(Void);
+
+Int Server_create(Void);
+Int Server_exec(Void);
+Int Server_delete(Void);
+
+
+#if defined (__cplusplus)
+}
+#endif /* defined (__cplusplus) */
+#endif /* Server__include */
diff --git a/dsp1/makefile b/dsp1/makefile
new file mode 100644 (file)
index 0000000..9207a6c
--- /dev/null
@@ -0,0 +1,147 @@
+#
+#  Copyright (c) 2012-2015 Texas Instruments Incorporated - http://www.ti.com
+#  All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#
+#  *  Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#
+#  *  Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  *  Neither the name of Texas Instruments Incorporated nor the names of
+#     its contributors may be used to endorse or promote products derived
+#     from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+#  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+#  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+#  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+#  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+#  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+#  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+#  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+#  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+#  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+#  ======== makefile ========
+#
+
+EXBASE = ..
+include $(EXBASE)/products.mak
+
+srcs = MainDsp1.c Server.c
+objs = $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.oe66,$(srcs)))
+CONFIG = bin/$(PROFILE)/configuro
+
+PKGPATH := $(BIOS_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(IPC_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(XDC_INSTALL_DIR)/packages
+
+-include $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.oe66.dep,$(srcs)))
+
+.PRECIOUS: %/compiler.opt %/linker.cmd
+
+all: debug release
+
+debug:
+       $(MAKE) PROFILE=debug PROCLIST="$(PROCLIST)" server_dsp1.x
+
+release:
+       $(MAKE) PROFILE=release PROCLIST="$(PROCLIST)" server_dsp1.x
+
+server_dsp1.x: bin/$(PROFILE)/server_dsp1.xe66
+bin/$(PROFILE)/server_dsp1.xe66: $(objs) $(libs) $(CONFIG)/linker.cmd
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(LD) $(LDFLAGS) -o $@ $(objs) \
+            $(addprefix -l ,$(libs)) $(CONFIG)/linker.cmd $(LDLIBS)
+
+bin/$(PROFILE)/obj/%.oe66: %.c $(CONFIG)/compiler.opt
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(CC) $(CPPFLAGS) $(CFLAGS) --output_file=$@ -fc $<
+
+%/linker.cmd %/compiler.opt: $(CONFIG)/.config ;
+$(CONFIG)/.config: Dsp1.cfg ../shared/config.bld
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(XDC_INSTALL_DIR)/xs --xdcpath="$(subst +,;,$(PKGPATH))" \
+            xdc.tools.configuro -o $(CONFIG) \
+            -t ti.targets.elf.C66 \
+            -c $(ti.targets.elf.C66) \
+            -p ti.platforms.evmDRA7XX:dsp1 \
+            -b ../shared/config.bld -r $(PROFILE) \
+            Dsp1.cfg
+       @$(ECHO) "" > $@
+
+install:
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       @$(MKDIR) $(EXEC_DIR)/debug
+       $(CP) bin/debug/server_dsp1.xe66 $(EXEC_DIR)/debug
+       @$(MKDIR) $(EXEC_DIR)/release
+       $(CP) bin/release/server_dsp1.xe66 $(EXEC_DIR)/release
+
+help:
+       @$(ECHO) "make                   # build executable"
+       @$(ECHO) "make clean             # clean everything"
+
+clean::
+       $(RMDIR) bin
+
+#  ======== install validation ========
+ifeq (install,$(MAKECMDGOALS))
+ifeq (,$(EXEC_DIR))
+$(error must specify EXEC_DIR)
+endif
+endif
+
+#  ======== toolchain macros ========
+CGTOOLS = $(ti.targets.elf.C66)
+
+CC = $(CGTOOLS)/bin/cl6x -c
+LD = $(CGTOOLS)/bin/cl6x -z
+
+CPPFLAGS =
+CFLAGS = -qq -pdsw225 -ppd=$@.dep -ppa $(CCPROFILE_$(PROFILE)) -@$(CONFIG)/compiler.opt -I.
+
+# entry point is set to an aligned address so that IPC can load the slave
+LDFLAGS = -w -q -u _c_int00 -c -m $(@D)/obj/$(@F).map
+LDLIBS = -l $(CGTOOLS)/lib/libc.a
+
+CCPROFILE_debug = -D_DEBUG_=1 --symdebug:dwarf
+CCPROFILE_release = -O2
+
+#  ======== standard macros ========
+ifneq (,$(wildcard $(XDC_INSTALL_DIR)/xdc.exe))
+    # use these on Windows
+    CP      = $(XDC_INSTALL_DIR)/bin/cp
+    ECHO    = $(XDC_INSTALL_DIR)/bin/echo
+    MKDIR   = $(XDC_INSTALL_DIR)/bin/mkdir -p
+    RM      = $(XDC_INSTALL_DIR)/bin/rm -f
+    RMDIR   = $(XDC_INSTALL_DIR)/bin/rm -rf
+else
+    # use these on Linux
+    CP      = cp
+    ECHO    = echo
+    MKDIR   = mkdir -p
+    RM      = rm -f
+    RMDIR   = rm -rf
+endif
+
+#  ======== create output directories ========
+ifneq (clean,$(MAKECMDGOALS))
+ifneq (,$(PROFILE))
+ifeq (,$(wildcard bin/$(PROFILE)/obj))
+    $(shell $(MKDIR) -p bin/$(PROFILE)/obj)
+endif
+endif
+endif
diff --git a/dsp2/Dsp2.cfg b/dsp2/Dsp2.cfg
new file mode 100644 (file)
index 0000000..38a0cec
--- /dev/null
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2013-2015 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Dsp2.cfg ========
+ *  Platform: DRA7XX_linux_elf
+ *  Target: ti.targets.elf.C66
+ */
+
+/* root of the configuration object model */
+var Program = xdc.useModule('xdc.cfg.Program');
+
+/* application uses the following modules and packages */
+xdc.useModule('xdc.runtime.Assert');
+xdc.useModule('xdc.runtime.Diags');
+xdc.useModule('xdc.runtime.Error');
+xdc.useModule('xdc.runtime.Log');
+xdc.useModule('xdc.runtime.Registry');
+
+xdc.useModule('ti.sysbios.knl.Semaphore');
+xdc.useModule('ti.sysbios.knl.Task');
+
+/*
+ *  ======== IPC Configuration ========
+ */
+xdc.useModule('ti.ipc.ipcmgr.IpcMgr');
+
+/* load the configuration shared across cores  */
+Program.global.procName = "DSP2";
+var ipc_cfg = xdc.loadCapsule("../shared/ipc.cfg.xs");
+
+var BIOS        = xdc.useModule('ti.sysbios.BIOS');
+BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');
+
+/*
+ *  ======== SYS/BIOS Configuration ========
+ */
+if (Program.build.profile == "debug") {
+    BIOS.libType = BIOS.LibType_Debug;
+} else {
+    BIOS.libType = BIOS.LibType_Custom;
+}
+
+/* no rts heap */
+Program.argSize = 100;  /* minimum size */
+Program.stack = 0x1000;
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.common$.namedInstance = true;
+
+/* default memory heap */
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var heapMemParams = new HeapMem.Params();
+heapMemParams.size = 0x8000;
+Memory.defaultHeapInstance = HeapMem.create(heapMemParams);
+
+/* create a heap for MessageQ messages */
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var params = new HeapBuf.Params;
+params.align = 8;
+params.blockSize = 512;
+params.numBlocks = 256;
+var msgHeap = HeapBuf.create(params);
+
+var MessageQ  = xdc.useModule('ti.sdo.ipc.MessageQ');
+MessageQ.registerHeapMeta(msgHeap, 0);
+
+/* Setup MessageQ transport */
+var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
+MessageQ.SetupTransportProxy = VirtioSetup;
+
+/* Setup NameServer remote proxy */
+var NameServer = xdc.useModule("ti.sdo.utils.NameServer");
+var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
+NameServer.SetupProxy = NsRemote;
+
+/* Enable Memory Translation module that operates on the BIOS Resource Table */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.loadSegment = "EXT_CODE";
+
+/*  Use SysMin because trace buffer address is required for Linux/QNX
+ *  trace debug driver, plus provides better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('ti.trace.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize  = 0x8000;
+
+Program.sectMap[".tracebuf"] = "TRACE_BUF";
+Program.sectMap[".errorbuf"] = "EXC_DATA";
+
+/* --------------------------- TICK --------------------------------------*/
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+Clock.tickSource = Clock.TickSource_NULL;
+//Clock.tickSource = Clock.TickSource_USER;
+/* Configure BIOS clock source as GPTimer5 */
+//Clock.timerId = 0;
+
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+
+/* Skip the Timer frequency verification check. Need to remove this later */
+Timer.checkFrequency = false;
+
+/* Match this to the SYS_CLK frequency sourcing the dmTimers.
+ * Not needed once the SYS/BIOS family settings is updated. */
+Timer.intFreq.hi = 0;
+Timer.intFreq.lo = 19200000;
+
+//var timerParams = new Timer.Params();
+//timerParams.period = Clock.tickPeriod;
+//timerParams.periodType = Timer.PeriodType_MICROSECS;
+/* Switch off Software Reset to make the below settings effective */
+//timerParams.tiocpCfg.softreset = 0x0;
+/* Smart-idle wake-up-capable mode */
+//timerParams.tiocpCfg.idlemode = 0x3;
+/* Wake-up generation for Overflow */
+//timerParams.twer.ovf_wup_ena = 0x1;
+//Timer.create(Clock.timerId, Clock.doTick, timerParams);
+
+/*
+ *  ======== Instrumentation Configuration ========
+ */
+
+/* system logger */
+var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
+var LoggerSysParams = new LoggerSys.Params();
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
+
+/* enable runtime Diags_setMask() for non-XDC spec'd modules */
+var Diags = xdc.useModule('xdc.runtime.Diags');
+Diags.setMaskEnabled = true;
+
+/* override diags mask for selected modules */
+xdc.useModule('xdc.runtime.Main');
+Diags.setMaskMeta("xdc.runtime.Main",
+    Diags.ENTRY | Diags.EXIT | Diags.INFO, Diags.RUNTIME_ON);
+
+var Registry = xdc.useModule('xdc.runtime.Registry');
+Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF;
+Registry.common$.diags_EXIT  = Diags.RUNTIME_OFF;
+Registry.common$.diags_INFO  = Diags.RUNTIME_OFF;
+Registry.common$.diags_USER1 = Diags.RUNTIME_OFF;
+Registry.common$.diags_LIFECYCLE = Diags.RUNTIME_OFF;
+Registry.common$.diags_STATUS = Diags.RUNTIME_OFF;
+
+var Main = xdc.useModule('xdc.runtime.Main');
+Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
+Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
diff --git a/dsp2/MainDsp2.c b/dsp2/MainDsp2.c
new file mode 100644 (file)
index 0000000..a5ed37a
--- /dev/null
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== main_Dsp2.c ========
+ *
+ */
+
+/* xdctools header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/Log.h>
+#include <xdc/runtime/System.h>
+
+/* package header files */
+#include <ti/ipc/Ipc.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+
+/* local header files */
+#include "Server.h"
+
+/* private functions */
+static Void smain(UArg arg0, UArg arg1);
+
+
+/*
+ *  ======== main ========
+ */
+Int main(Int argc, Char* argv[])
+{
+    Error_Block     eb;
+    Task_Params     taskParams;
+
+    Log_print0(Diags_ENTRY, "--> main:");
+
+    /* must initialize the error block before using it */
+    Error_init(&eb);
+
+    /* create main thread (interrupts not enabled in main on BIOS) */
+    Task_Params_init(&taskParams);
+    taskParams.instance->name = "smain";
+    taskParams.arg0 = (UArg)argc;
+    taskParams.arg1 = (UArg)argv;
+    taskParams.stackSize = 0x1000;
+    Task_create(smain, &taskParams, &eb);
+
+    if (Error_check(&eb)) {
+        System_abort("main: failed to create application startup thread");
+    }
+
+    /* start scheduler, this never returns */
+    BIOS_start();
+
+    /* should never get here */
+    Log_print0(Diags_EXIT, "<-- main:");
+    return (0);
+}
+
+
+/*
+ *  ======== smain ========
+ */
+Void smain(UArg arg0, UArg arg1)
+{
+    Int                 status = 0;
+    Error_Block         eb;
+    Bool                running = TRUE;
+
+    Log_print0(Diags_ENTRY | Diags_INFO, "--> smain:");
+
+    Error_init(&eb);
+
+    /* initialize modules */
+    Server_init();
+
+    /* turn on Diags_INFO trace */
+    Diags_setMask("Server+F");
+
+    /* loop forever */
+    while (running) {
+
+        /* BEGIN server phase */
+
+        /* server setup phase */
+        status = Server_create();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* server execute phase */
+        status = Server_exec();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* server shutdown phase */
+        status = Server_delete();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* END server phase */
+
+    } /* while (running) */
+
+    /* finalize modules */
+    Server_exit();
+
+leave:
+    Log_print1(Diags_EXIT, "<-- smain: %d", (IArg)status);
+    return;
+}
diff --git a/dsp2/Server.c b/dsp2/Server.c
new file mode 100644 (file)
index 0000000..3d83084
--- /dev/null
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Server.c ========
+ *
+ */
+
+/* this define must precede inclusion of any xdc header file */
+#define Registry_CURDESC Test__Desc
+#define MODULE_NAME "Server"
+
+/* xdctools header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Assert.h>
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Log.h>
+#include <xdc/runtime/Registry.h>
+
+#include <stdio.h>
+
+/* package header files */
+#include <ti/ipc/MessageQ.h>
+#include <ti/ipc/MultiProc.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+
+/* local header files */
+#include "../shared/AppCommon.h"
+
+/* module header file */
+#include "Server.h"
+
+/* module structure */
+typedef struct {
+    UInt16              hostProcId;         // host processor id
+    MessageQ_Handle     slaveQue;           // created locally
+} Server_Module;
+
+/* private data */
+Registry_Desc               Registry_CURDESC;
+static Server_Module        Module;
+
+
+/*
+ *  ======== Server_init ========
+ */
+Void Server_init(Void)
+{
+    Registry_Result result;
+
+    /* register with xdc.runtime to get a diags mask */
+    result = Registry_addModule(&Registry_CURDESC, MODULE_NAME);
+    Assert_isTrue(result == Registry_SUCCESS, (Assert_Id)NULL);
+
+    /* initialize module object state */
+    Module.hostProcId = MultiProc_getId("HOST");
+}
+
+
+/*
+ *  ======== Server_create ========
+ */
+Int Server_create()
+{
+    Int                 status = 0;
+    MessageQ_Params     msgqParams;
+    char                msgqName[32];
+
+    /* enable some log events */
+    Diags_setMask(MODULE_NAME"+EXF");
+
+    /* create local message queue (inbound messages) */
+    MessageQ_Params_init(&msgqParams);
+    sprintf(msgqName, App_SlaveMsgQueName, MultiProc_getName(MultiProc_self()));
+    Module.slaveQue = MessageQ_create(msgqName, &msgqParams);
+
+    if (Module.slaveQue == NULL) {
+        status = -1;
+        goto leave;
+    }
+
+    Log_print0(Diags_INFO,"Server_create: server is ready");
+
+leave:
+    Log_print1(Diags_EXIT, "<-- Server_create: %d", (IArg)status);
+    return (status);
+}
+
+
+
+
+/*
+ *  ======== Server_exec ========
+ */
+Int Server_exec()
+{
+    Int                 status;
+    Bool                running = TRUE;
+    App_Msg *           msg;
+    MessageQ_QueueId    queId;
+
+    Log_print0(Diags_ENTRY | Diags_INFO, "--> Server_exec:");
+
+    while (running) {
+
+        /* wait for inbound message */
+        status = MessageQ_get(Module.slaveQue, (MessageQ_Msg *)&msg,
+            MessageQ_FOREVER);
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        if (msg->cmd == App_CMD_SHUTDOWN) {
+            running = FALSE;
+        }
+
+        /* process the message */
+        Log_print1(Diags_INFO, "Server_exec: processed cmd=0x%x", msg->cmd);
+
+        /* send message back */
+        queId = MessageQ_getReplyQueue(msg); /* type-cast not needed */
+        MessageQ_put(queId, (MessageQ_Msg)msg);
+    } /* while (running) */
+
+leave:
+    Log_print1(Diags_EXIT, "<-- Server_exec: %d", (IArg)status);
+    return(status);
+}
+
+/*
+ *  ======== Server_delete ========
+ */
+
+Int Server_delete()
+{
+    Int         status;
+
+    Log_print0(Diags_ENTRY, "--> Server_delete:");
+
+    /* delete the video message queue */
+    status = MessageQ_delete(&Module.slaveQue);
+
+    if (status < 0) {
+        goto leave;
+    }
+
+leave:
+    if (status < 0) {
+        Log_error1("Server_finish: error=0x%x", (IArg)status);
+    }
+
+    /* disable log events */
+    Log_print1(Diags_EXIT, "<-- Server_delete: %d", (IArg)status);
+    Diags_setMask(MODULE_NAME"-EXF");
+
+    return(status);
+}
+
+/*
+ *  ======== Server_exit ========
+ */
+
+Void Server_exit(Void)
+{
+    /*
+     * Note that there isn't a Registry_removeModule() yet:
+     *     https://bugs.eclipse.org/bugs/show_bug.cgi?id=315448
+     *
+     * ... but this is where we'd call it.
+     */
+}
diff --git a/dsp2/Server.h b/dsp2/Server.h
new file mode 100644 (file)
index 0000000..5278f23
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+#  Copyright (c) 2012-2014 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Server.h ========
+ */
+
+#ifndef Server__include
+#define Server__include
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+
+Void Server_init(Void);
+Void Server_exit(Void);
+
+Int Server_create(Void);
+Int Server_exec(Void);
+Int Server_delete(Void);
+
+
+#if defined (__cplusplus)
+}
+#endif /* defined (__cplusplus) */
+#endif /* Server__include */
diff --git a/dsp2/makefile b/dsp2/makefile
new file mode 100644 (file)
index 0000000..50c08fa
--- /dev/null
@@ -0,0 +1,147 @@
+#
+#  Copyright (c) 2012-2015 Texas Instruments Incorporated - http://www.ti.com
+#  All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#
+#  *  Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#
+#  *  Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  *  Neither the name of Texas Instruments Incorporated nor the names of
+#     its contributors may be used to endorse or promote products derived
+#     from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+#  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+#  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+#  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+#  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+#  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+#  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+#  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+#  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+#  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+#  ======== makefile ========
+#
+
+EXBASE = ..
+include $(EXBASE)/products.mak
+
+srcs = MainDsp2.c Server.c
+objs = $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.oe66,$(srcs)))
+CONFIG = bin/$(PROFILE)/configuro
+
+PKGPATH := $(BIOS_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(IPC_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(XDC_INSTALL_DIR)/packages
+
+-include $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.oe66.dep,$(srcs)))
+
+.PRECIOUS: %/compiler.opt %/linker.cmd
+
+all: debug release
+
+debug:
+       $(MAKE) PROFILE=debug PROCLIST="$(PROCLIST)" server_dsp2.x
+
+release:
+       $(MAKE) PROFILE=release PROCLIST="$(PROCLIST)" server_dsp2.x
+
+server_dsp2.x: bin/$(PROFILE)/server_dsp2.xe66
+bin/$(PROFILE)/server_dsp2.xe66: $(objs) $(libs) $(CONFIG)/linker.cmd
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(LD) $(LDFLAGS) -o $@ $(objs) \
+            $(addprefix -l ,$(libs)) $(CONFIG)/linker.cmd $(LDLIBS)
+
+bin/$(PROFILE)/obj/%.oe66: %.c $(CONFIG)/compiler.opt
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(CC) $(CPPFLAGS) $(CFLAGS) --output_file=$@ -fc $<
+
+%/linker.cmd %/compiler.opt: $(CONFIG)/.config ;
+$(CONFIG)/.config: Dsp2.cfg ../shared/config.bld
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(XDC_INSTALL_DIR)/xs --xdcpath="$(subst +,;,$(PKGPATH))" \
+            xdc.tools.configuro -o $(CONFIG) \
+            -t ti.targets.elf.C66 \
+            -c $(ti.targets.elf.C66) \
+            -p ti.platforms.evmDRA7XX:dsp2 \
+            -b ../shared/config.bld -r $(PROFILE) \
+            Dsp2.cfg
+       @$(ECHO) "" > $@
+
+install:
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       @$(MKDIR) $(EXEC_DIR)/debug
+       $(CP) bin/debug/server_dsp2.xe66 $(EXEC_DIR)/debug
+       @$(MKDIR) $(EXEC_DIR)/release
+       $(CP) bin/release/server_dsp2.xe66 $(EXEC_DIR)/release
+
+help:
+       @$(ECHO) "make                   # build executable"
+       @$(ECHO) "make clean             # clean everything"
+
+clean::
+       $(RMDIR) bin
+
+#  ======== install validation ========
+ifeq (install,$(MAKECMDGOALS))
+ifeq (,$(EXEC_DIR))
+$(error must specify EXEC_DIR)
+endif
+endif
+
+#  ======== toolchain macros ========
+CGTOOLS = $(ti.targets.elf.C66)
+
+CC = $(CGTOOLS)/bin/cl6x -c
+LD = $(CGTOOLS)/bin/cl6x -z
+
+CPPFLAGS =
+CFLAGS = -qq -pdsw225 -ppd=$@.dep -ppa $(CCPROFILE_$(PROFILE)) -@$(CONFIG)/compiler.opt -I.
+
+# entry point is set to an aligned address so that IPC can load the slave
+LDFLAGS = -w -q -u _c_int00 -c -m $(@D)/obj/$(@F).map
+LDLIBS = -l $(CGTOOLS)/lib/libc.a
+
+CCPROFILE_debug = -D_DEBUG_=1 --symdebug:dwarf
+CCPROFILE_release = -O2
+
+#  ======== standard macros ========
+ifneq (,$(wildcard $(XDC_INSTALL_DIR)/xdc.exe))
+    # use these on Windows
+    CP      = $(XDC_INSTALL_DIR)/bin/cp
+    ECHO    = $(XDC_INSTALL_DIR)/bin/echo
+    MKDIR   = $(XDC_INSTALL_DIR)/bin/mkdir -p
+    RM      = $(XDC_INSTALL_DIR)/bin/rm -f
+    RMDIR   = $(XDC_INSTALL_DIR)/bin/rm -rf
+else
+    # use these on Linux
+    CP      = cp
+    ECHO    = echo
+    MKDIR   = mkdir -p
+    RM      = rm -f
+    RMDIR   = rm -rf
+endif
+
+#  ======== create output directories ========
+ifneq (clean,$(MAKECMDGOALS))
+ifneq (,$(PROFILE))
+ifeq (,$(wildcard bin/$(PROFILE)/obj))
+    $(shell $(MKDIR) -p bin/$(PROFILE)/obj)
+endif
+endif
+endif
diff --git a/host/App.c b/host/App.c
new file mode 100644 (file)
index 0000000..80789fc
--- /dev/null
@@ -0,0 +1,513 @@
+/*
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== App.c ========
+ *
+ */
+
+/* host header files */
+#include <stdio.h>
+#include <unistd.h>
+#include <string.h>
+
+/* package header files */
+#include <ti/ipc/Std.h>
+#include <ti/ipc/MessageQ.h>
+#include <ti/cmem.h>
+
+/* local header files */
+#include "../shared/AppCommon.h"
+#include "App.h"
+
+#include <time.h>
+
+/* module structure */
+typedef struct {
+       MessageQ_Handle         hostQue;    // created locally
+       MessageQ_QueueId        slaveQue;   // opened remotely
+       UInt16                  heapId;     // MessageQ heapId
+       UInt32                  msgSize;
+} App_Module;
+
+/* private data */
+static App_Module Module;
+
+
+typedef struct  bufmgrDesc_s {
+       UInt32 physAddr;            /* physical address */
+       char *userAddr;             /* Host user space Virtual address */
+       UInt32 length;              /* Length of host buffer */
+
+} bufmgrDesc_t;
+
+
+#define MAX_TEST_MSG_NUM  256
+
+#define TEST_PORT 0
+#define MAX_MII_PORTS_NUM 3
+#define MAX_PACKET_FRAME_SIZE 1536 
+
+//#define GOOSE_FILTER_DISABLE
+#define GOOSE_PARA_LEN 1024
+
+/* testing packets from host if needed */
+#define TEST_PKT_SIZE       64
+static const char test_pkt[2][TEST_PKT_SIZE] = {
+       {
+               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* broadcast mac */
+               0x01, 0x55, 0x55, 0x55, 0x55, 0x55,
+               0x08, 0x06, 0x00, 0x01,
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+       {
+               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* broadcast mac */
+               0x01, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
+               0x08, 0x06, 0x00, 0x01,
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       }
+};
+
+CMEM_AllocParams  alloc_params;
+bufmgrDesc_t  cmem_buf_desc;
+
+bufmgrDesc_t  RxPacketBuf[MAX_MII_PORTS_NUM][2];
+bufmgrDesc_t  TxPacketBuf[MAX_MII_PORTS_NUM][2];
+bufmgrDesc_t  GoosePara;
+
+char *pGoosePara;
+
+/*
+ *  ======== parse /etc/goose if available for filtering parameters ========
+ */
+Void Read_Goose_para()
+{
+       FILE *fp;
+       unsigned int gooseFlag;
+       unsigned char destMacAddr[4][6];
+       unsigned short appId[4];
+       int i;
+
+
+       fp = fopen("/etc/goose", "r");
+       if(fp == NULL) {
+               printf("/etc/goose doesn't exsit," 
+                               "use default goose parameters\n");
+               return;
+       }
+
+       fscanf(fp, "%x", &gooseFlag);
+
+       pGoosePara = GoosePara.userAddr;
+       memcpy(pGoosePara, &gooseFlag, 4);
+
+       for (i=0; i<4; i++)
+               fscanf(fp, "%x %x %x %x %x %x", 
+                               (unsigned int *)&destMacAddr[i][0],
+                               (unsigned int *)&destMacAddr[i][1],
+                               (unsigned int *)&destMacAddr[i][2],
+                               (unsigned int *)&destMacAddr[i][3],
+                               (unsigned int *)&destMacAddr[i][4],
+                               (unsigned int *)&destMacAddr[i][5]);
+       memcpy(pGoosePara + 4, &destMacAddr[0][0], 24);
+
+       fscanf(fp, "%x %x %x %x", (unsigned int *)&appId[0],
+                       (unsigned int *)&appId[1],
+                       (unsigned int *)&appId[2],
+                       (unsigned int *)&appId[3]);
+
+       memcpy(pGoosePara + 28, &appId[0], 16);
+
+       printf("GooseFlag = 0x%x\n", *(unsigned int *)pGoosePara);
+
+       for(i=0; i<4; i++)
+               printf("Goose destMacAddr[%d] =" 
+                               "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", i, 
+                               *(pGoosePara + i*6 + 4),
+                               *(pGoosePara + i*6 + 5),
+                               *(pGoosePara + i*6 + 6),
+                               *(pGoosePara + i*6 + 7),
+                               *(pGoosePara + i*6 + 8),
+                               *(pGoosePara + i*6 + 9));
+
+       printf("Goose AppID = 0x%x 0x%x 0x%x 0x%x\n", 
+                       *(unsigned short *)(pGoosePara + 28),
+                       *(unsigned short *)(pGoosePara + 30),
+                       *(unsigned short *)(pGoosePara + 32),
+                       *(unsigned short *)(pGoosePara + 34));
+       fclose(fp);                                             
+}
+
+/*
+ *  ======== initialize CMEM buffers ========
+ */
+Void initCmemBufs()
+{
+       CMEM_AllocParams  alloc_params;
+       Int i;
+
+       printf("--->App_Create: CMEM_allocPhys and map\n");
+       alloc_params.flags = CMEM_NONCACHED;
+       alloc_params.type = CMEM_POOL;
+       alloc_params.alignment = 0;
+       if(CMEM_init() != 0)
+               printf("--->App_Create: ERROR: CMEM_init()\n");
+
+       cmem_buf_desc.physAddr = CMEM_allocPhys(4 * MAX_MII_PORTS_NUM * 
+                       MAX_PACKET_FRAME_SIZE + GOOSE_PARA_LEN, &alloc_params);
+
+       if(cmem_buf_desc.physAddr == 0 )
+               printf("--->App_Create: ERROR: CMEM_allocPhys()\n");
+       else
+               printf("--->App_Create: cmem_buf_desc.physAddr = 0x%x\n", 
+                               cmem_buf_desc.physAddr);
+
+       cmem_buf_desc.length = 4 * MAX_MII_PORTS_NUM * MAX_PACKET_FRAME_SIZE + 
+               GOOSE_PARA_LEN;
+
+       cmem_buf_desc.userAddr = CMEM_map((UInt32)cmem_buf_desc.physAddr, 
+                       cmem_buf_desc.length);
+       if(cmem_buf_desc.userAddr == NULL)
+               printf("--->App_Create: ERROR: CMEM_map()\n");
+
+       for (i = 0; i < MAX_MII_PORTS_NUM; i++)
+       { 
+               RxPacketBuf[i][0].length = MAX_PACKET_FRAME_SIZE;
+               RxPacketBuf[i][0].userAddr = 
+                       (char *)((UInt32)(cmem_buf_desc.userAddr + 
+                                               (i*4+0)*MAX_PACKET_FRAME_SIZE));
+
+               RxPacketBuf[i][0].physAddr = (UInt32)((cmem_buf_desc.physAddr +
+                                       (i*4+0)*MAX_PACKET_FRAME_SIZE));
+
+               RxPacketBuf[i][1].length = MAX_PACKET_FRAME_SIZE;
+               RxPacketBuf[i][1].userAddr = 
+                       (char *)((UInt32)(cmem_buf_desc.userAddr + 
+                                               (i*4+1)*MAX_PACKET_FRAME_SIZE));
+
+               RxPacketBuf[i][1].physAddr = (UInt32)((cmem_buf_desc.physAddr +
+                                       (i*4+1)*MAX_PACKET_FRAME_SIZE));
+
+               TxPacketBuf[i][0].length = MAX_PACKET_FRAME_SIZE;
+               TxPacketBuf[i][0].userAddr = 
+                       (char *)((UInt32)cmem_buf_desc.userAddr + 
+                                       (i*4+2)*MAX_PACKET_FRAME_SIZE);
+
+               TxPacketBuf[i][0].physAddr = (UInt32)((cmem_buf_desc.physAddr + 
+                                       (i*4+2)*MAX_PACKET_FRAME_SIZE)); 
+
+
+               TxPacketBuf[i][1].length = MAX_PACKET_FRAME_SIZE;
+               TxPacketBuf[i][1].userAddr = 
+                       (char *)((UInt32)cmem_buf_desc.userAddr + 
+                                       (i*4+3)*MAX_PACKET_FRAME_SIZE);
+
+               TxPacketBuf[i][1].physAddr = (UInt32)((cmem_buf_desc.physAddr + 
+                                       (i*4+3)*MAX_PACKET_FRAME_SIZE)); 
+
+       }
+
+       GoosePara.length = GOOSE_PARA_LEN;
+       GoosePara.userAddr = (char *)((UInt32)cmem_buf_desc.userAddr + 
+                       MAX_MII_PORTS_NUM*4*MAX_PACKET_FRAME_SIZE);
+       GoosePara.physAddr = (UInt32)(cmem_buf_desc.physAddr + 
+                       MAX_MII_PORTS_NUM*4*MAX_PACKET_FRAME_SIZE); 
+
+       Read_Goose_para();
+}
+
+/*
+ *  ======== App_create ========
+ */
+
+Int App_create(UInt16 remoteProcId)
+{
+       Int                 status = 0;
+       MessageQ_Params     msgqParams;
+       char                msgqName[32];
+
+       printf("--> App_create:\n");
+
+       /* setting default values */
+       Module.hostQue = NULL;
+       Module.slaveQue = MessageQ_INVALIDMESSAGEQ;
+       Module.heapId = App_MsgHeapId;
+       Module.msgSize = sizeof(App_Msg);
+
+       initCmemBufs();
+       /* create local message queue (inbound messages) */
+       MessageQ_Params_init(&msgqParams);
+
+       Module.hostQue = MessageQ_create(App_HostMsgQueName, &msgqParams);
+
+       if (Module.hostQue == NULL) {
+               printf("App_create: Failed creating MessageQ\n");
+               status = -1;
+               goto leave;
+       }
+
+       /* open the remote message queue */
+       sprintf(msgqName, App_SlaveMsgQueName, MultiProc_getName(remoteProcId));
+
+       do {
+               status = MessageQ_open(msgqName, &Module.slaveQue);
+               sleep(1);
+       } while (status == MessageQ_E_NOTFOUND);
+
+       if (status < 0) {
+               printf("App_create: Failed opening MessageQ\n");
+               goto leave;
+       }
+
+       printf("App_create: Host is ready\n");
+
+leave:
+       printf("<-- App_create:\n");
+       return(status);
+}
+
+
+/*
+ *  ======== App_delete ========
+ */
+Int App_delete(Void)
+{
+       Int         status;
+
+       printf("--> App_delete:\n");
+
+       /* close remote resources */
+       status = MessageQ_close(&Module.slaveQue);
+
+       if (status < 0) {
+               goto leave;
+       }
+
+       /* delete the host message queue */
+       status = MessageQ_delete(&Module.hostQue);
+
+       if (status < 0) {
+               goto leave;
+       }
+
+leave:
+       printf("<-- App_delete:\n");
+       return(status);
+}
+
+
+/*
+ *  ======== App_exec ========
+ */
+Int App_exec(Void)
+{
+       Int         status;
+       Int     ethPort, nPktBuf, pktLen;
+       char    *pRxPkt;
+       char    *pTxPkt, *pTxPkt0, *pTxPkt1;
+       Int         i,j;
+       App_Msg *   msg;
+
+       printf("--> App_exec:\n");
+
+       /* fill process pipeline */
+       for (i = 1; i <= 4; i++) {
+               printf("App_exec: sending message %d\n", i);
+
+               /* allocate message */
+               msg = (App_Msg *)MessageQ_alloc(Module.heapId, Module.msgSize);
+
+               if (msg == NULL) {
+                       status = -1;
+                       goto leave;
+               }
+
+               /* set the return address in the message header */
+               MessageQ_setReplyQueue(Module.hostQue, (MessageQ_Msg)msg);
+
+               /* fill in message payload */
+               msg->cmd = App_CMD_NOP;
+
+#ifdef GOOSE_FILTER_DISABLE    
+               /* disable Goose filtering */
+               if (i == 3) 
+                       msg->cmd = App_CMD_GOOSE_DISABLE;
+#endif
+
+               if (i == 4) {
+                       msg->cmd = App_CMD_CMEMBUF;
+                       msg->port = 0;
+                       msg->nRxBuf = 0;
+                       for (j = 0; j < MAX_MII_PORTS_NUM; j++) {
+                               msg->RxPhysAddr[j][0] = 
+                                       RxPacketBuf[j][0].physAddr;
+                               msg->RxPktLen[j][0] = 0;
+
+                               msg->RxPhysAddr[j][1] = 
+                                       RxPacketBuf[j][1].physAddr;
+                               msg->RxPktLen[j][1] = 0;
+
+                               msg->TxPhysAddr[j][0] = 
+                                       TxPacketBuf[j][0].physAddr;
+                               msg->TxPktLen[j][0] = 0;
+
+                               msg->TxPhysAddr[j][1] = 
+                                       TxPacketBuf[j][1].physAddr;
+                               msg->TxPktLen[j][1] = 0;
+                       }
+                       msg->GooseParaPhysAddr = GoosePara.physAddr;
+
+                       pTxPkt0 = TxPacketBuf[TEST_PORT][0].userAddr;
+                       pTxPkt1 = TxPacketBuf[TEST_PORT][1].userAddr;
+                       pTxPkt = pTxPkt0;
+               }
+
+               /* send message */
+               MessageQ_put(Module.slaveQue, (MessageQ_Msg)msg);
+       }
+
+       /* process steady state (keep pipeline full) */
+       for (i = 5; i <= MAX_TEST_MSG_NUM; i++) {
+
+               /* wait for return message */
+               status = MessageQ_get(Module.hostQue, (MessageQ_Msg *)&msg,
+                               MessageQ_FOREVER);
+
+               if (status < 0) {
+                       goto leave;
+               }
+
+               /* extract message payload */
+               if(msg->cmd == App_CMD_PACKET)
+               {
+                       printf("App_exec: packet received: \n");
+                       ethPort = msg->port;
+                       nPktBuf = msg->nRxBuf;
+                       pktLen = msg->RxPktLen[ethPort][nPktBuf];
+
+                       pRxPkt = (char *)RxPacketBuf[ethPort][nPktBuf].userAddr;
+
+                       for(j=0; j<msg->RxPktLen[ethPort][nPktBuf]; j++)
+                               printf("%02x", *(pRxPkt+j));
+
+                       printf("\nreceived packet frame size: %d\n", pktLen);
+               }
+
+               /* free the message */
+               MessageQ_free((MessageQ_Msg)msg);
+
+               printf("\nApp_exec: message received, sending message %d\n", i);
+
+               /* allocate message */
+               msg = (App_Msg *)MessageQ_alloc(Module.heapId, Module.msgSize);
+
+               if (msg == NULL) {
+                       status = -1;
+                       goto leave;
+               }
+
+               /* set the return address in the message header */
+               MessageQ_setReplyQueue(Module.hostQue, (MessageQ_Msg)msg);
+
+               /* fill in message payload */
+               if (i == MAX_TEST_MSG_NUM) {
+                       /* Last message will tell the slave to shutdown */
+                       msg->cmd = App_CMD_SHUTDOWN;
+               }
+               else {
+                       msg->cmd = App_CMD_PACKET;
+               }
+
+               /* send message */
+               if(pTxPkt == pTxPkt0) {
+                       msg->TxPktLen[TEST_PORT][0] = TEST_PKT_SIZE;
+                       memcpy(pTxPkt, test_pkt[0], TEST_PKT_SIZE);
+                       msg->nTxBuf = 0;
+                       pTxPkt = pTxPkt1;
+               }
+               else {
+                       msg->TxPktLen[TEST_PORT][1] = TEST_PKT_SIZE;
+                       memcpy(pTxPkt, test_pkt[1], TEST_PKT_SIZE);
+                       msg->nTxBuf = 1;
+                       pTxPkt = pTxPkt0;
+               }
+               MessageQ_put(Module.slaveQue, (MessageQ_Msg)msg);
+       }
+
+       /* drain process pipeline */
+       for (i = 1; i <= 4; i++) {
+               printf("App_exec: message received\n");
+
+               /* wait for return message */
+               status = MessageQ_get(Module.hostQue, (MessageQ_Msg *)&msg,
+                               MessageQ_FOREVER);
+
+               if (status < 0) {
+                       goto leave;
+               }
+
+               /* extract message payload */
+               if(msg->cmd == App_CMD_PACKET)
+               {
+                       printf("App_exec: packet received: \n");
+                       ethPort = msg->port;
+                       nPktBuf = msg->nRxBuf;
+                       pktLen = msg->RxPktLen[ethPort][nPktBuf];
+
+                       pRxPkt = (char *)RxPacketBuf[ethPort][nPktBuf].userAddr;
+
+                       for(j=0; j<msg->RxPktLen[ethPort][nPktBuf]; j++)
+                               printf("%02x", *(pRxPkt+j));
+
+                       printf("\nreceived packet frame size: %d\n", pktLen);
+
+               }
+
+               /* free the message */
+               MessageQ_free((MessageQ_Msg)msg);
+       }
+
+leave:
+       CMEM_unmap(cmem_buf_desc.userAddr, cmem_buf_desc.length);
+       CMEM_freePhys(cmem_buf_desc.physAddr, &alloc_params);
+
+       printf("<-- App_exec: %d\n", status);
+       return(status);
+}
diff --git a/host/App.h b/host/App.h
new file mode 100644 (file)
index 0000000..f3659fc
--- /dev/null
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== App.h ========
+ *
+ */
+
+#ifndef App__include
+#define App__include
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+Int App_create(UInt16 remoteProcId);
+Int App_delete();
+Int App_exec();
+
+
+#if defined (__cplusplus)
+}
+#endif /* defined (__cplusplus) */
+#endif /* App__include */
diff --git a/host/goose b/host/goose
new file mode 100644 (file)
index 0000000..0cf36e3
--- /dev/null
@@ -0,0 +1,6 @@
+BEEFBEEF
+11 22 33 44 55 66
+22 33 44 55 66 77
+33 44 55 66 77 88
+44 55 66 77 88 99
+1111 2222 3333 4444
diff --git a/host/main_host.c b/host/main_host.c
new file mode 100644 (file)
index 0000000..7d3736e
--- /dev/null
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2013-2015 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== main_host.c ========
+ *
+ */
+
+/* cstdlib header files */
+#include <stdio.h>
+#include <stdlib.h>
+
+/* package header files */
+#include <ti/ipc/Std.h>
+#include <ti/ipc/Ipc.h>
+#include <ti/ipc/transports/TransportRpmsg.h>
+
+#include <ti/ipc/MultiProc.h>
+
+/* local header files */
+#include "App.h"
+
+/* private functions */
+static Int Main_main(Void);
+static Int Main_parseArgs(Int argc, Char *argv[]);
+
+
+#define Main_USAGE "\
+Usage:\n\
+    app_host [options] procName\n\
+\n\
+Arguments:\n\
+    procName      : the name of the remote processor\n\
+\n\
+Options:\n\
+    h   : print this help message\n\
+    l   : list the available remote names\n\
+\n\
+Examples:\n\
+    app_host IPU1\n\
+    app_host -l\n\
+    app_host -h\n\
+\n"
+
+/* private data */
+static String   Main_remoteProcName = NULL;
+
+
+/*
+ *  ======== main ========
+ */
+Int main(Int argc, Char* argv[])
+{
+    Int status;
+
+    printf("--> main:\n");
+
+    /* parse command line */
+    status = Main_parseArgs(argc, argv);
+
+    if (status < 0) {
+        goto leave;
+    }
+    /* configure the transport factory */
+    Ipc_transportConfig(&TransportRpmsg_Factory);
+
+    /* Ipc initialization */
+    status = Ipc_start();
+
+    if (status >= 0) {
+        /* application create, exec, delete */
+        status = Main_main();
+
+        /* Ipc finalization */
+        Ipc_stop();
+    }
+    else {
+        printf("Ipc_start failed: status = %d\n", status);
+        goto leave;
+    }
+
+leave:
+    printf("<-- main:\n");
+    status = (status >= 0 ? 0 : status);
+
+    return (status);
+}
+
+
+/*
+ *  ======== Main_main ========
+ */
+Int Main_main(Void)
+{
+    UInt16      remoteProcId;
+    Int         status = 0;
+
+    printf("--> Main_main:\n");
+
+    remoteProcId = MultiProc_getId(Main_remoteProcName);
+
+    /* application create phase */
+    status = App_create(remoteProcId);
+
+    if (status < 0) {
+        goto leave;
+    }
+
+    /* application execute phase */
+    status = App_exec();
+
+    if (status < 0) {
+        goto leave;
+    }
+
+    /* application delete phase */
+    status = App_delete();
+
+    if (status < 0) {
+        goto leave;
+    }
+
+leave:
+    printf("<-- Main_main:\n");
+
+    status = (status >= 0 ? 0 : status);
+    return (status);
+}
+
+
+/*
+ *  ======== Main_parseArgs ========
+ */
+Int Main_parseArgs(Int argc, Char *argv[])
+{
+    Int             x, cp, opt, argNum;
+    UInt16          i, numProcs;
+    String          name;
+    Int             status = 0;
+
+
+    /* parse the command line options */
+    for (opt = 1; (opt < argc) && (argv[opt][0] == '-'); opt++) {
+        for (x = 0, cp = 1; argv[opt][cp] != '\0'; cp++) {
+            x = (x << 8) | (int)argv[opt][cp];
+        }
+
+        switch (x) {
+            case 'h': /* -h */
+                printf("%s", Main_USAGE);
+                exit(0);
+                break;
+
+            case 'l': /* -l */
+                printf("Processor List\n");
+                status = Ipc_start();
+                if (status >= 0) {
+                    numProcs = MultiProc_getNumProcessors();
+                    for (i = 0; i < numProcs; i++) {
+                        name = MultiProc_getName(i);
+                        printf("    procId=%d, procName=%s\n", i, name);
+                    }
+                    Ipc_stop();
+                }
+                else {
+                    printf(
+                        "Error: %s, line %d: Ipc_start failed\n",
+                        __FILE__, __LINE__);
+                    goto leave;
+                }
+                exit(0);
+                break;
+
+            default:
+                printf(
+                    "Error: %s, line %d: invalid option, %c\n",
+                    __FILE__, __LINE__, (Char)x);
+                printf("%s", Main_USAGE);
+                status = -1;
+                goto leave;
+        }
+    }
+
+    /* parse the command line arguments */
+    for (argNum = 1; opt < argc; argNum++, opt++) {
+
+        switch (argNum) {
+            case 1: /* name of proc #1 */
+                Main_remoteProcName = argv[opt];
+                break;
+
+            default:
+                printf(
+                    "Error: %s, line %d: too many arguments\n",
+                    __FILE__, __LINE__);
+                printf("%s", Main_USAGE);
+                status = -1;
+                goto leave;
+        }
+    }
+
+    /* validate command line arguments */
+    if (Main_remoteProcName == NULL) {
+        printf("Error: missing procName argument\n");
+        printf("%s", Main_USAGE);
+        status = -1;
+        goto leave;
+    }
+
+leave:
+    return(status);
+}
diff --git a/host/makefile b/host/makefile
new file mode 100644 (file)
index 0000000..eb288d5
--- /dev/null
@@ -0,0 +1,141 @@
+#
+#  Copyright (c) 2013-2015 Texas Instruments Incorporated - http://www.ti.com
+#  All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#
+#  *  Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#
+#  *  Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  *  Neither the name of Texas Instruments Incorporated nor the names of
+#     its contributors may be used to endorse or promote products derived
+#     from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+#  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+#  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+#  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+#  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+#  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+#  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+#  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+#  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+#  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+#  ======== Makefile ========
+#
+
+srcs = main_host.c App.c
+
+EXBASE = ..
+include $(EXBASE)/products.mak
+-include $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.ov7A.dep,$(srcs)))
+
+objs = $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.ov7A,$(srcs)))
+libs = $(IPC_INSTALL_DIR)/linux/src/transport/.libs/libtitransportrpmsg.a \
+       $(IPC_INSTALL_DIR)/linux/src/api/.libs/libtiipc.a \
+       $(IPC_INSTALL_DIR)/linux/src/utils/.libs/libtiipcutils.a \
+       $(CMEM_INSTALL_DIR)/lib/libticmem.a
+
+
+# Use dynamic or shared libs
+#libs = $(IPC_INSTALL_DIR)/linux/src/api/.libs/libtiipc.so \
+#       $(IPC_INSTALL_DIR)/linux/src/utils/.libs/libtiipcutils.so \
+#       $(IPC_INSTALL_DIR)/linux/src/transport/.libs/libtitransportrpmsg.so
+
+all:
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(MAKE) PROFILE=debug app_host
+       $(MAKE) PROFILE=release app_host
+
+help:
+       @$(ECHO) "make                  # build executables"
+       @$(ECHO) "make clean            # clean everything"
+
+install:
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       @$(MKDIR) $(EXEC_DIR)/debug
+       $(CP) bin/debug/app_host $(EXEC_DIR)/debug
+       @$(MKDIR) $(EXEC_DIR)/release
+       $(CP) bin/release/app_host $(EXEC_DIR)/release
+
+clean::
+       $(RMDIR) bin
+
+
+#
+#  ======== rules ========
+#
+app_host: bin/$(PROFILE)/app_host
+bin/$(PROFILE)/app_host: $(objs) $(libs)
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(LD) $(LDFLAGS) -o $@ $^ $(LDLIBS)
+
+bin/$(PROFILE)/obj/%.ov7A: %.c
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(CC) $(CPPFLAGS) $(CFLAGS) -o $@ $<
+
+#  ======== install validation ========
+ifeq (install,$(MAKECMDGOALS))
+ifeq (,$(EXEC_DIR))
+$(error must specify EXEC_DIR)
+endif
+endif
+
+#  ======== toolchain macros ========
+CC = $(TOOLCHAIN_PREFIX)gcc -c -MD -MF $@.dep
+AR = $(TOOLCHAIN_PREFIX)ar cr
+LD = $(TOOLCHAIN_PREFIX)gcc
+
+CPPFLAGS = -D_REENTRANT
+
+CFLAGS = -D_FILE_OFFSET_BITS=64 -Wall -ffloat-store -fPIC -Wunused -Dfar= $(CCPROFILE_$(PROFILE)) \
+    -I. -I.. -I $(IPC_INSTALL_DIR)/linux/include -I $(IPC_INSTALL_DIR)/packages -I $(CMEM_INSTALL_DIR)/include
+
+LDFLAGS = $(LDPROFILE_$(PROFILE)) -Wall -Wl,-Map=$@.map
+LDLIBS = -lpthread -lc -lrt
+
+CCPROFILE_debug = -ggdb -D DEBUG
+CCPROFILE_release = -O3 -D NDEBUG
+
+LDPROFILE_debug = -ggdb
+LDPROFILE_release = -O3
+
+#  ======== standard macros ========
+ifneq (,$(wildcard $(XDC_INSTALL_DIR)/bin/echo.exe))
+    # use these on Windows
+    CP      = $(XDC_INSTALL_DIR)/bin/cp
+    ECHO    = $(XDC_INSTALL_DIR)/bin/echo
+    MKDIR   = $(XDC_INSTALL_DIR)/bin/mkdir -p
+    RM      = $(XDC_INSTALL_DIR)/bin/rm -f
+    RMDIR   = $(XDC_INSTALL_DIR)/bin/rm -rf
+else
+    # use these on Linux
+    CP      = cp
+    ECHO    = echo
+    MKDIR   = mkdir -p
+    RM      = rm -f
+    RMDIR   = rm -rf
+endif
+
+#  ======== create output directories ========
+ifneq (clean,$(MAKECMDGOALS))
+ifneq (,$(PROFILE))
+ifeq (,$(wildcard bin/$(PROFILE)/obj))
+    $(shell $(MKDIR) -p bin/$(PROFILE)/obj)
+endif
+endif
+endif
diff --git a/ipu1/Ipu1.cfg b/ipu1/Ipu1.cfg
new file mode 100644 (file)
index 0000000..54a4f37
--- /dev/null
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2013-2016 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Ipu1.cfg ========
+ *  Platform: DRA7XX_linux_elf
+ *  Target: ti.targets.arm.elf.M4
+ */
+
+/* root of the configuration object model */
+var Program = xdc.useModule('xdc.cfg.Program');
+
+/* build arguments for this executable */
+var cfgArgs = Program.build.cfgArgs;
+var configBld = xdc.loadCapsule(cfgArgs.configBld);
+
+/* application uses the following modules and packages */
+xdc.useModule('xdc.runtime.Assert');
+xdc.useModule('xdc.runtime.Diags');
+xdc.useModule('xdc.runtime.Error');
+xdc.useModule('xdc.runtime.Log');
+xdc.useModule('xdc.runtime.Registry');
+
+xdc.useModule('ti.sysbios.gates.GateHwi');
+xdc.useModule('ti.sysbios.knl.Semaphore');
+xdc.useModule('ti.sysbios.knl.Task');
+
+/*
+ *  ======== IPC Configuration ========
+ */
+xdc.useModule('ti.ipc.ipcmgr.IpcMgr');
+
+Program.global.procName = "IPU1";
+var ipc_cfg = xdc.loadCapsule("../shared/ipc.cfg.xs");
+
+var BIOS        = xdc.useModule('ti.sysbios.BIOS');
+BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');
+
+/*
+ *  ======== SYS/BIOS Configuration ========
+ */
+if (Program.build.profile == "debug") {
+    BIOS.libType = BIOS.LibType_Debug;
+} else {
+    BIOS.libType = BIOS.LibType_Custom;
+}
+BIOS.smpEnabled = true; /* only support SMP mode on IPU */
+
+var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.ipuId = 1;
+
+/* no rts heap */
+Program.argSize = 100;  /* minimum size */
+Program.stack = 0x1000;
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.common$.namedInstance = true;
+
+/* Remap the interrupt xbar mmr base address to match AMMU settings */
+var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');
+IntXbar.mmrBaseAddr = 0x6A002000;
+
+/* default memory heap */
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var heapMemParams = new HeapMem.Params();
+heapMemParams.size = 0x10000;
+Memory.defaultHeapInstance = HeapMem.create(heapMemParams);
+
+/* create a heap for MessageQ messages */
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var params = new HeapBuf.Params;
+params.align = 8;
+params.blockSize = 512;
+params.numBlocks = 256;
+var msgHeap = HeapBuf.create(params);
+
+var MessageQ  = xdc.useModule('ti.sdo.ipc.MessageQ');
+MessageQ.registerHeapMeta(msgHeap, 0);
+
+/* Setup MessageQ transport */
+var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
+MessageQ.SetupTransportProxy = VirtioSetup;
+
+/* Setup NameServer remote proxy */
+var NameServer = xdc.useModule("ti.sdo.utils.NameServer");
+var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
+NameServer.SetupProxy = NsRemote;
+
+/* Enable Memory Translation module that operates on the BIOS Resource Table */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.customTable = true;
+
+/*  Use SysMin because trace buffer address is required for Linux/QNX
+ *  trace debug driver, plus provides better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('ti.trace.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize  = 0x8000;
+
+Program.sectMap[".tracebuf"] = "TRACE_BUF";
+Program.sectMap[".errorbuf"] = "EXC_DATA";
+
+/*  Configure external timer base address to match resource table mapping.
+ */
+var dmTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+/* dmTimer 0 mapped to GPT1 */
+dmTimer.timerSettings[0].baseAddr = 0x6AE18000;
+/* dmTimer 1 mapped to GPT2 */
+dmTimer.timerSettings[1].baseAddr = 0x68032000;
+/* dmTimer 2 mapped to GPT3 */
+dmTimer.timerSettings[2].baseAddr = 0x68034000;
+/* dmTimer 3 mapped to GPT4 */
+dmTimer.timerSettings[3].baseAddr = 0x68036000;
+/* dmTimer 4 mapped to GPT5 */
+dmTimer.timerSettings[4].baseAddr = 0x68820000;
+/* dmTimer 5 mapped to GPT6 */
+dmTimer.timerSettings[5].baseAddr = 0x68822000;
+/* dmTimer 6 mapped to GPT7 */
+dmTimer.timerSettings[6].baseAddr = 0x68034000;
+/* dmTimer 7 mapped to GPT8 */
+dmTimer.timerSettings[7].baseAddr = 0x68036000;
+/* dmTimer 8 mapped to GPT9 */
+dmTimer.timerSettings[8].baseAddr = 0x6803E000;
+/* dmTimer 9 mapped to GPT10 */
+dmTimer.timerSettings[9].baseAddr = 0x68086000;
+/* dmTimer 10 mapped to GPT11 */
+dmTimer.timerSettings[10].baseAddr = 0x68088000;
+/* dmTimer 11 mapped to GPT12 */
+dmTimer.timerSettings[11].baseAddr = 0x6AE20000;
+/* dmTimer 12 mapped to GPT13 */
+dmTimer.timerSettings[12].baseAddr = 0x68828000;
+/* dmTimer 13 mapped to GPT14 */
+dmTimer.timerSettings[13].baseAddr = 0x6882A000;
+/* dmTimer 14 mapped to GPT15 */
+dmTimer.timerSettings[14].baseAddr = 0x6882C000;
+/* dmTimer 15 mapped to GPT16 */
+dmTimer.timerSettings[15].baseAddr = 0x6882E000;
+
+/* use external timers because they keep running when IPU is not */
+var halTimer = xdc.useModule('ti.sysbios.hal.Timer');
+halTimer.TimerProxy = dmTimer;
+
+/* ----------------------------- TICK ---------------------------------------*/
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+Clock.tickSource = Clock.TickSource_USER;
+/* Configure GPTimer11 as BIOS clock source */
+Clock.timerId = 10;
+
+var WD = xdc.useModule('ti.deh.Watchdog');
+WD.timerIds.length = 2;
+WD.timerSettings.length = 2;
+WD.timerIds[0] = "GPTimer7";
+WD.timerSettings[0].intNum = 60;
+WD.timerSettings[0].eventId = -1;
+WD.timerIds[1] = "GPTimer8";
+WD.timerSettings[1].intNum = 61;
+WD.timerSettings[1].eventId = -1;
+
+var Xbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');
+Xbar.connectIRQMeta(60, 38);
+Xbar.connectIRQMeta(61, 39);
+
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+var timerParams = new Timer.Params();
+timerParams.period = Clock.tickPeriod;
+timerParams.periodType = Timer.PeriodType_MICROSECS;
+/* Smart-idle wake-up-capable mode */
+timerParams.tiocpCfg.idlemode = 0x3;
+/* Wake-up generation for Overflow */
+timerParams.twer.ovf_wup_ena = 0x1;
+Timer.create(Clock.timerId, Clock.doTick, timerParams);
+
+/* configure the IPU AMMU */
+xdc.loadCapsule("IpuAmmu.cfg");
+
+
+/* idle functions */
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+
+/* function to flush unicache on each core */
+Idle.addCoreFunc('&VirtQueue_cacheWb', 0);
+Idle.addCoreFunc('&VirtQueue_cacheWb', 1);
+
+var Deh = xdc.useModule('ti.deh.Deh');
+
+/* Watchdog detection functions in each core */
+/* Must be placed before pwr mgmt */
+Idle.addCoreFunc('&ti_deh_Deh_idleBegin', 0);
+Idle.addCoreFunc('&ti_deh_Deh_idleBegin', 1);
+
+/*
+ *  ======== Instrumentation Configuration ========
+ */
+
+/* system logger */
+var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
+var LoggerSysParams = new LoggerSys.Params();
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
+
+/* enable runtime Diags_setMask() for non-XDC spec'd modules */
+var Diags = xdc.useModule('xdc.runtime.Diags');
+Diags.setMaskEnabled = true;
+
+/* override diags mask for selected modules */
+xdc.useModule('xdc.runtime.Main');
+Diags.setMaskMeta("xdc.runtime.Main",
+    Diags.ENTRY | Diags.EXIT | Diags.INFO, Diags.RUNTIME_ON);
+
+var Registry = xdc.useModule('xdc.runtime.Registry');
+Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF;
+Registry.common$.diags_EXIT  = Diags.RUNTIME_OFF;
+Registry.common$.diags_INFO  = Diags.RUNTIME_OFF;
+Registry.common$.diags_USER1 = Diags.RUNTIME_OFF;
+Registry.common$.diags_LIFECYCLE = Diags.RUNTIME_OFF;
+Registry.common$.diags_STATUS = Diags.RUNTIME_OFF;
+
+var Main = xdc.useModule('xdc.runtime.Main');
+Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
+Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
+
+var Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+Hwi.nvicCCR.DIV_0_TRP = 1;
+
+/* Load the OSAL package */
+var osType = "tirtos"
+var Osal = xdc.useModule('ti.osal.Settings');
+Osal.osType = osType;
+
+var Pruss               = xdc.loadPackage('ti.drv.pruss');
+var Icss_Emac           = xdc.loadPackage('ti.drv.icss_emac');
+
diff --git a/ipu1/IpuAmmu.cfg b/ipu1/IpuAmmu.cfg
new file mode 100644 (file)
index 0000000..7585b31
--- /dev/null
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2012-2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* -------------------------------- Cache ----------------------------------*/
+var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+Cache.enableCache = true;
+
+/* -------------------------------- AMMU -----------------------------------*/
+var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+/*********************** Small Pages *************************/
+/* smallPages[0] & smallPages[1] are auto-programmed by h/w */
+
+/* Overwrite smallPage[1] so that 16K is covered. H/w reset value configures
+ * only 4K */
+AMMU.smallPages[1].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[1].logicalAddress = 0x40000000;
+AMMU.smallPages[1].translatedAddress = 0x55080000;
+AMMU.smallPages[1].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[1].size = AMMU.Small_16K;
+
+/* L2RAM: 64K mapped using 4 smallPages(16K); cacheable; translated */
+/* config small page[2] to map 16K VA 0x20000000 to PA 0x55020000  */
+AMMU.smallPages[2].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[2].logicalAddress = 0x20000000;
+AMMU.smallPages[2].translatedAddress = 0x55020000;
+AMMU.smallPages[2].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[2].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+AMMU.smallPages[2].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+AMMU.smallPages[2].L1_posted = AMMU.PostedPolicy_POSTED;
+AMMU.smallPages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.smallPages[2].size = AMMU.Small_16K;
+
+/* config small page[3] to map 16K VA 0x20004000 to PA 0x55024000 */
+AMMU.smallPages[3].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[3].logicalAddress = 0x20004000;
+AMMU.smallPages[3].translatedAddress = 0x55024000;
+AMMU.smallPages[3].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[3].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+AMMU.smallPages[3].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+AMMU.smallPages[3].L1_posted = AMMU.PostedPolicy_POSTED;
+AMMU.smallPages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.smallPages[3].size = AMMU.Small_16K;
+
+/* config small page[4] to map 16K VA 0x20008000 to PA 0x55028000 */
+AMMU.smallPages[4].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[4].logicalAddress = 0x20008000;
+AMMU.smallPages[4].translatedAddress = 0x55028000;
+AMMU.smallPages[4].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[4].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+AMMU.smallPages[4].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+AMMU.smallPages[4].L1_posted = AMMU.PostedPolicy_POSTED;
+AMMU.smallPages[4].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.smallPages[4].size = AMMU.Small_16K;
+
+/* config small page[5] to map 16K VA 0x2000C000 to PA 0x5502C000 */
+AMMU.smallPages[5].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[5].logicalAddress = 0x2000C000;
+AMMU.smallPages[5].translatedAddress = 0x5502C000;
+AMMU.smallPages[5].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[5].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+AMMU.smallPages[5].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+AMMU.smallPages[5].L1_posted = AMMU.PostedPolicy_POSTED;
+AMMU.smallPages[5].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.smallPages[5].size = AMMU.Small_16K;
+
+/* ISS: Use 3 small pages(1 4K and 2 16K) for various ISP registers; non-cacheable; translated */
+/* config small page[6] to map 16K VA 0x50000000 to PA 0x55040000 */
+/* non cacheable by default */
+AMMU.smallPages[6].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[6].logicalAddress = 0x50000000;
+AMMU.smallPages[6].translatedAddress = 0x55040000;
+AMMU.smallPages[6].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[6].size = AMMU.Small_16K;
+
+/* config small page[7] to map 16K VA 0x50010000 to PA 0x55050000 */
+/* non cacheable by default */
+AMMU.smallPages[7].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[7].logicalAddress = 0x50010000;
+AMMU.smallPages[7].translatedAddress = 0x55050000;
+AMMU.smallPages[7].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[7].size = AMMU.Small_16K;
+
+/* config small page[8] to map 4K VA 0x50020000 to PA 0x55060000 */
+/* non cacheable by default */
+AMMU.smallPages[8].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[8].logicalAddress = 0x50020000;
+AMMU.smallPages[8].translatedAddress = 0x55060000;
+AMMU.smallPages[8].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[8].size = AMMU.Small_4K;
+
+/*********************** Medium Pages *************************/
+/* ISS: The entire ISS register space using a medium page (256K); cacheable; translated */
+/* config medium page[0] to map 256K VA 0x50000000 to PA 0x55040000 */
+/* Make it L1 cacheable */
+AMMU.mediumPages[0].pageEnabled = AMMU.Enable_YES;
+AMMU.mediumPages[0].logicalAddress = 0x50000000;
+AMMU.mediumPages[0].translatedAddress = 0x55040000;
+AMMU.mediumPages[0].translationEnabled = AMMU.Enable_YES;
+AMMU.mediumPages[0].size = AMMU.Medium_256K;
+AMMU.mediumPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.mediumPages[0].L1_posted = AMMU.PostedPolicy_POSTED;
+
+
+/*********************** Large Pages *************************/
+/* Instruction Code: Large page  (512M); cacheable */
+/* config large page[0] to map 512MB VA 0x0 to L3 0x0 */
+AMMU.largePages[0].pageEnabled = AMMU.Enable_YES;
+AMMU.largePages[0].logicalAddress = 0x0;
+AMMU.largePages[0].translationEnabled = AMMU.Enable_NO;
+AMMU.largePages[0].size = AMMU.Large_512M;
+AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_POSTED;
+
+/* Peripheral regions: Large Page (512M); non-cacheable */
+/* config large page[1] to map 512MB VA 0x60000000 to L3 0x60000000 */
+AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
+AMMU.largePages[1].logicalAddress = 0x60000000;
+AMMU.largePages[1].translationEnabled = AMMU.Enable_NO;
+AMMU.largePages[1].size = AMMU.Large_512M;
+AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED;
+
+/* Private, Shared and IPC Data regions: Large page (512M); cacheable */
+/* config large page[2] to map 512MB VA 0x80000000 to L3 0x80000000 */
+AMMU.largePages[2].pageEnabled = AMMU.Enable_YES;
+AMMU.largePages[2].logicalAddress = 0x80000000;
+AMMU.largePages[2].translationEnabled = AMMU.Enable_NO;
+AMMU.largePages[2].size = AMMU.Large_512M;
+AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_POSTED;
+
+/* TILER & DMM regions: Large page (512M); cacheable */
+/* config large page[3] to map 512MB VA 0xA0000000 to L3 0xA0000000 */
+AMMU.largePages[3].pageEnabled = AMMU.Enable_YES;
+AMMU.largePages[3].logicalAddress = 0xA0000000;
+AMMU.largePages[3].translationEnabled = AMMU.Enable_NO;
+AMMU.largePages[3].size = AMMU.Large_512M;
+AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_POSTED;
diff --git a/ipu1/MainIpu1.c b/ipu1/MainIpu1.c
new file mode 100644 (file)
index 0000000..b0a2d49
--- /dev/null
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== main_Ipu1.c ========
+ *
+ */
+
+/* xdctools header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/Log.h>
+#include <xdc/runtime/System.h>
+
+/* package header files */
+#include <ti/ipc/Ipc.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+
+/* local header files */
+#include "Server.h"
+#include "rsc_table_vayu_ipu.h"
+
+/* private functions */
+static Void smain(UArg arg0, UArg arg1);
+
+extern int pru_icss();
+
+/*
+ *  ======== main ========
+ */
+Int main(Int argc, Char* argv[])
+{
+    Error_Block     eb;
+    Task_Params     taskParams;
+
+    Log_print0(Diags_ENTRY, "--> main:");
+
+    /* must initialize the error block before using it */
+    Error_init(&eb);
+
+    /* create main thread (interrupts not enabled in main on BIOS) */
+    Task_Params_init(&taskParams);
+    taskParams.priority = 1;
+    taskParams.instance->name = "smain";
+    taskParams.arg0 = (UArg)argc;
+    taskParams.arg1 = (UArg)argv;
+    taskParams.stackSize = 0x1000;
+    Task_create(smain, &taskParams, &eb);
+
+    if (Error_check(&eb)) {
+        System_abort("main: failed to create application startup thread");
+    }
+
+    if(pru_icss()) {
+        System_abort("main: failed to initialize PRU_ICSS thread");
+    }
+
+    /* start scheduler, this never returns */
+    BIOS_start();
+
+    /* should never get here */
+    Log_print0(Diags_EXIT, "<-- main:");
+    return (0);
+}
+
+
+/*
+ *  ======== smain ========
+ */
+Void smain(UArg arg0, UArg arg1)
+{
+    Int                 status = 0;
+    Error_Block         eb;
+    Bool                running = TRUE;
+
+    Log_print0(Diags_ENTRY | Diags_INFO, "--> smain:");
+
+    Error_init(&eb);
+
+    /* initialize modules */
+    Server_init();
+
+    /* turn on Diags_INFO trace */
+    Diags_setMask("Server+F");
+
+    /* loop forever */
+    while (running) {
+
+        /* BEGIN server phase */
+
+        /* server setup phase */
+        status = Server_create();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* server execute phase */
+        status = Server_exec();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* server shutdown phase */
+        status = Server_delete();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* END server phase */
+
+    } /* while (running) */
+
+    /* finalize modules */
+    Server_exit();
+
+leave:
+    Log_print1(Diags_EXIT, "<-- smain: %d", (IArg)status);
+    return;
+}
diff --git a/ipu1/PktProcEng.c b/ipu1/PktProcEng.c
new file mode 100644 (file)
index 0000000..3e5057c
--- /dev/null
@@ -0,0 +1,954 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ * 
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <xdc/std.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/knl/Cache.h>
+
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Log.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/hal/Core.h>
+
+#include <ti/csl/src/ip/icss/V0/cslr_icss_intc.h>
+
+#include <ti/drv/pruss/soc/pruicss_v1.h>
+
+#include <icss_emacDrv.h>
+
+#ifdef SOC_AM572x
+#include <ti/drv/icss_emac/firmware/am57x/v1_0/icss_emac_pru0_bin.h>
+#include <ti/drv/icss_emac/firmware/am57x/v1_0/icss_emac_pru1_bin.h>
+#include <ti/drv/pruss/soc/am572x/pruicss_device.c>
+#include <ti/drv/icss_emac/soc/am572x/icss_emacSoc.c>
+#include <ti/csl/soc/am572x/src/csl_device_xbar.h>
+#define PRU0_FIRMWARE_V1_0_NAME      PRU0_FIRMWARE_V1_0 
+#define PRU1_FIRMWARE_V1_1_NAME      PRU1_FIRMWARE_V1_0 
+
+#include <ti/drv/icss_emac/firmware/am57x/v2_1/icss_emac_pru0_bin.h>
+#include <ti/drv/icss_emac/firmware/am57x/v2_1/icss_emac_pru1_bin.h>
+#define PRU0_FIRMWARE_NAME      PRU0_FIRMWARE
+#define PRU1_FIRMWARE_NAME      PRU1_FIRMWARE
+#endif
+
+#ifdef SOC_AM571x
+#include <ti/drv/icss_emac/firmware/am57x/v2_1/icss_emac_pru0_bin.h>
+#include <ti/drv/icss_emac/firmware/am57x/v2_1/icss_emac_pru1_bin.h>
+#include <ti/drv/pruss/soc/am571x/pruicss_device.c>
+#include <ti/drv/icss_emac/soc/am571x/icss_emacSoc.c>
+#include <ti/csl/soc/am571x/src/csl_device_xbar.h>
+#define PRU0_FIRMWARE_NAME      PRU0_FIRMWARE
+#define PRU1_FIRMWARE_NAME      PRU1_FIRMWARE
+#endif
+#include <ti/drv/icss_emac/test/src/tiemac_pruss_intc_mapping.h>
+
+#include <ti/drv/icss_emac/test/src/icss_switch_emac.h>
+#include <ti/drv/icss_emac/test/src/test_mdio.c>
+#include <ti/drv/icss_emac/test/src/icss_switch_emac.c>
+#include <ti/drv/icss_emac/test/src/icss_emac_osal.c>
+
+#include "Server.h"
+
+PRUICSS_Handle pruIcssHandle;
+ICSS_EmacHandle emachandle;
+ICSS_EmacHandle emachandle1;
+
+void SOCCtrlGetPortMacAddr(uint32_t portNum, uint8_t *pMacAddr);
+void ICSSEmacDRVInit(ICSS_EmacHandle handle, uint8_t instance);
+extern ICSS_EmacBaseAddrCfgParams icss_EmacBaseAddrCfgParams[3];
+void InterruptInit(ICSS_EmacHandle icssEmacHandle);
+void InterruptEnd(ICSS_EmacHandle icssEmacHandle);
+static void EnableEMACInterrupts(ICSS_EmacHandle icssemacHandle);
+void DisableEMACInterrupts(ICSS_EmacHandle icssemacHandle);
+inline void clearLink0ISR(ICSS_EmacHandle icssemacHandle);
+inline void clearLink1ISR(ICSS_EmacHandle icssemacHandle);
+
+#define MAX_TEST_PKT_NUM        12
+#define TEST_PKT_SIZE           256
+
+#define GOOSE_ENABLE           0xBEEFBEEF
+#define GOOSE_DISABLE          0xDEADDEAD
+
+uint32_t packetLength = 0;
+uint32_t testNum = 0;
+
+void *icssRxSem;
+void *icssRxSem1;
+extern uint32_t *pRxPkt;
+extern uint32_t *pTxPkt;
+
+extern uint32_t *pGoosePara;
+extern uint32_t bGooseFilter;
+
+uint8_t lclMac[6];
+uint8_t lclMac1[6];
+
+uint32_t GooseBuf[MAX_PKT_FRAME_SIZE];
+uint32_t PtpBuf[MAX_PKT_FRAME_SIZE];
+uint32_t GarbageBuf[MAX_PKT_FRAME_SIZE];
+
+char GooseDestMacAddr[DEST_MAC_NUM][ETH_ALEN] = {
+       {0x11, 0x22, 0x33, 0x44, 0x55, 0x66},
+       {0x22, 0x33, 0x44, 0x55, 0x66, 0x77},
+       {0x33, 0x44, 0x55, 0x66, 0x77, 0x88},
+       {0x44, 0x55, 0x66, 0x77, 0x88, 0x99},
+};
+uint16_t GooseAPPID[ACCEPT_APPID_NUM] = {0x1111, 0x2222, 0x3333, 0x4444};
+
+char ptpMulDest1MacAddr[ETH_ALEN] = {0x01, 0x1b, 0x19, 0x00, 0x00, 0x00};
+char ptpMulDest2MacAddr[ETH_ALEN] = {0x01, 0x80, 0x02, 0x00, 0x00, 0x0F};
+
+static const uint8_t test_pkt[MAX_TEST_PKT_NUM][TEST_PKT_SIZE] = {
+       {
+               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* broadcast mac */
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x08, 0x06, 0x00, 0x01, /* ARP, accept, route to A15 */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+       {
+               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* broadcast mac, Goose*/
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x88, 0xb8, 0x00, 0x01, /* Goose 0x88b8, to A15,not match mac */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+
+       {
+               0x11, 0x22, 0x33, 0x44, 0x55, 0x66, /* Goose mac*/
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x88, 0xb8, 0x00, 0x01, /* Goose 0x88b8, drop,not match APPID */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+
+       {
+               0x01, 0x1b, 0x19, 0x00, 0x00, 0x00, /* multi-cast 01-1b mac */
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x88, 0xf7, 0x00, 0x01, /* 1588, accept */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+
+       {
+               0x01, 0x80, 0x02, 0x00, 0x00, 0x0f, /* multi-cast 01-80 mac */
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x88, 0xf7, 0x00, 0x01, /* 1588, accept */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+       {
+               0x11, 0x80, 0x02, 0x00, 0x00, 0x0f, /* multi-cast 11-80 mac */
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x88, 0xf7, 0x00, 0x01, /* 1588, drop */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+       {
+               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* broadcast mac, SV*/
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x88, 0xba, 0x00, 0x01, /* IEC61850, SV, drop*/
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+       {
+               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* broadcast mac */
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x08, 0x06, 0x00, 0x01, /* ARP, accept, route to A15 */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+       },
+       {
+               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* broadcast mac, to A15 */
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x81, 0x00, /* type - VLAN */
+               0x00, 0x00, /* VLAN tag - TCI */
+               0x88, 0xb8, /* VLAN tag - Goose */
+               0x11, 0x11,     /* APPID, type 1 */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+
+       {
+               0x11, 0x22, 0x33, 0x44, 0x55, 0x66, /* goose mac, accept */
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x81, 0x00, /* type - VLAN */
+               0x00, 0x00, /* VLAN tag - TCI */
+               0x88, 0xb8, /* VLAN tag - Goose */
+               0x11, 0x11,     /* APPID, type 1 */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+
+       {
+               0x11, 0x22, 0x33, 0x44, 0x55, 0x66, /* goose dest mac, accept */
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x81, 0x00, /* type - VLAN */
+               0x00, 0x00, /* VLAN tag - TCI */
+               0x88, 0xb8, /* VLAN tag - Goose */
+               0x44, 0x44,     /* APPID, type 1A */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+
+       {
+               0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* broadcast mac, to A15 */
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0x81, 0x00, /* type - VLAN */
+               0x00, 0x00, /* VLAN tag - TCI */
+               0x88, 0xb8, /* VLAN tag - Goose */
+               0x11, 0x22,     /* APPID, reject */
+               0x08, 0x00, 0x06, 0x04, 0x00,0x01,
+               0x01, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+               0xc0, 0xa8, 0x01, 0x16,
+               0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+               0xc0, 0xa8,0x01, 0x02
+       },
+};
+
+/**
+ * @brief configures GOOSE filter parameters is enabled
+ *
+ * @param none
+ *
+ * @retval none
+ */
+void Goose_para_config()
+{
+       uint32_t *pTempAddr;
+       uint32_t len;
+       int i;
+
+       if(*pGoosePara == GOOSE_ENABLE) {
+               Log_print0(Diags_INFO, "Enable/configure Goose filtering...");
+               bGooseFilter = 1;
+               pTempAddr = pGoosePara + 1;
+               len = DEST_MAC_NUM * ETH_ALEN;
+               memcpy(GooseDestMacAddr, pTempAddr, len);
+
+               for(i=0; i<6; i++)
+                       Log_print1(Diags_INFO, "Dest Mac Addr[0] = 0x%x\n", 
+                                       GooseDestMacAddr[0][i]);
+
+               pTempAddr = pGoosePara + 1 + len/4;
+               len = ACCEPT_APPID_NUM * 2;
+               memcpy(GooseAPPID, pTempAddr, len);
+
+               for(i=0; i<4; i++)
+                       Log_print1(Diags_INFO, "GooseAPPID = 0x%x", 
+                                       GooseAPPID[i]);
+       }
+       else if(*pGoosePara == GOOSE_DISABLE) {
+               Log_print0(Diags_INFO, "Disable Goose filtering");
+               bGooseFilter = 0;
+       }
+       else
+               Log_print0(Diags_INFO, "Use default Goose filtering config");
+
+       /* clear Goose Flag */
+       *pGoosePara = 0;
+}
+
+/**
+ * @brief transmit packets from IPU
+ *
+ * @param none
+ *
+ * @retval none
+ */
+void icss_tx()
+{
+       ICSS_EmacTxArgument txArgs;
+
+       /* Send out test packet for loopback */
+       txArgs.icssEmacHandle = emachandle;
+       txArgs.lengthOfPacket = TEST_PKT_SIZE;
+       txArgs.portNumber = 1;
+       txArgs.queuePriority = 3;
+       txArgs.srcAddress = &test_pkt[testNum][0];
+
+       ICSS_EmacTxPacket(&txArgs, NULL);
+       testNum++;
+       if ( testNum >= MAX_TEST_PKT_NUM)
+               testNum = 0;
+}
+
+/**
+ * @brief transmit packets received from host MPU
+ *
+ * @param pTxPacket: trasmit packet buffer pointer
+ *        TxPacketLen: trasmit packet size
+ *
+ * @retval none
+ */
+void icss_tx_mpu(UInt32 *pTxPacket, Int TxPacketLen)
+{
+       ICSS_EmacTxArgument txArgs;
+
+       Log_print0(Diags_INFO, "Sending packet from A15...");
+
+       txArgs.icssEmacHandle = emachandle;
+       txArgs.lengthOfPacket = TxPacketLen;
+       txArgs.portNumber = 1;
+       txArgs.queuePriority = 3;
+       txArgs.srcAddress = (const uint8_t *)pTxPacket;
+
+       ICSS_EmacTxPacket(&txArgs, NULL);
+}
+
+/**
+ * @brief post semaphore when a packet is received
+ *
+ * @param none
+ *
+ * @retval none
+ */
+void icss_rx()
+{
+       SemaphoreP_pend(icssRxSem, SemaphoreP_WAIT_FOREVER);
+       Log_print0(Diags_INFO, "Packet Received!");
+}
+
+
+/**
+ * @brief packet reception callback function
+ *
+ * @param queueNum: receive queue number
+ *        ICSS_EmacSubSysHandle: ICSS_EMAC handler
+ *
+ * @retval none
+ */
+void testCallbackRxPacket(uint32_t *queueNum, uint32_t ICSS_EmacSubSysHandle)
+{
+       int32_t         port;
+       uint32_t        queue;
+       int32_t         pkt_proc;
+       int32_t         pktLen;
+       uint32_t        *pProcRxPkt;
+       ICSS_EmacRxArgument rxArgs;
+
+       queue = (*queueNum);
+       packetLength = 0;
+
+       pktLen = ICSS_EmacRxPktInfo((ICSS_EmacHandle)ICSS_EmacSubSysHandle, 
+                                       &port, (int32_t *)&queue, &pkt_proc);
+
+       if(pktLen > 0) {
+               if(pkt_proc == PKT_PROC_MPU) {
+                       Log_print0(Diags_INFO, "place packet in A15 queue");
+                       pProcRxPkt = pRxPkt;
+                       packetLength = pktLen;
+               }
+               else if(pkt_proc == PKT_PROC_GOOSE) {
+                       Log_print0(Diags_INFO, "place packet in Goose buffer");
+                       pProcRxPkt = &GooseBuf[0];
+               }
+               else if(pkt_proc == PKT_PROC_PTP) {
+                       Log_print0(Diags_INFO, "place packet in PTP buffer");
+                       pProcRxPkt = &PtpBuf[0];
+               }
+               else if(pkt_proc == PKT_PROC_SV) {
+                       Log_print0(Diags_INFO, "place packet in SV buffer");
+                       pProcRxPkt = &GarbageBuf[0];
+               }
+               else {
+                       Log_print0(Diags_INFO, "place packet in garbage buffer");
+                       pProcRxPkt = &GarbageBuf[0];
+               }
+
+               rxArgs.icssEmacHandle = (ICSS_EmacHandle)ICSS_EmacSubSysHandle;
+               rxArgs.destAddress =  (uint32_t)pProcRxPkt;
+               rxArgs.queueNumber = *((uint32_t *)(queueNum));
+               rxArgs.more = 0;
+               rxArgs.port = 0;
+               ICSS_EmacRxPktGet(&rxArgs, NULL);
+       }
+
+       if((ICSS_EmacHandle)ICSS_EmacSubSysHandle == emachandle) {
+               SemaphoreP_post(icssRxSem);
+       }
+       else if((ICSS_EmacHandle)ICSS_EmacSubSysHandle == emachandle1)
+       {
+               SemaphoreP_post(icssRxSem1);
+       }
+}
+
+/*
+ *    ---task to initialize PRU---
+ */
+Void taskPruss(UArg a0, UArg a1)
+{
+       Uint8 firmwareLoad_done = FALSE;
+
+       Log_print0(Diags_INFO, "start task PRU-ICSS\n");
+
+       uint32_t pgVersion = (VHW_RD_REG32(
+                               CSL_MPU_CTRL_MODULE_WKUP_CORE_REGISTERS_REGS + 
+                               CTRL_WKUP_ID_CODE) & 0xf0000000) >> 28;
+       PRUICSS_pruDisable(pruIcssHandle, ICSS_EMAC_PORT_1-1);
+       PRUICSS_pruDisable(pruIcssHandle, ICSS_EMAC_PORT_2-1);
+
+#ifdef SOC_AM572x
+       if (pgVersion >= 2)
+       {
+               Log_print0(Diags_INFO, "taskPruss: Load FW to PG2.0 AM572x\n");
+               if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(0), 0,
+                                       (uint32_t *) PRU0_FIRMWARE_NAME,
+                                       sizeof(PRU0_FIRMWARE_NAME)))
+               {
+                       if(PRUICSS_pruWriteMemory(pruIcssHandle,
+                                               PRU_ICSS_IRAM(1), 0,
+                                               (uint32_t *) PRU1_FIRMWARE_NAME,
+                                               sizeof(PRU1_FIRMWARE_NAME)))
+                               firmwareLoad_done = TRUE;
+               }
+       }
+       else
+       {
+               if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(0), 0,
+                                       (uint32_t *) PRU0_FIRMWARE_V1_0_NAME,
+                                       sizeof(PRU0_FIRMWARE_V1_0_NAME)))
+               {
+                       if(PRUICSS_pruWriteMemory(pruIcssHandle,
+                                       PRU_ICSS_IRAM(1), 0,
+                                       (uint32_t *) PRU1_FIRMWARE_V1_1_NAME,
+                                       sizeof(PRU1_FIRMWARE_V1_1_NAME)))
+                               firmwareLoad_done = TRUE;
+               }
+       }
+#else
+       if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(0) ,0,
+                               (uint32_t *) PRU0_FIRMWARE_NAME,
+                               sizeof(PRU0_FIRMWARE_NAME)))
+       {
+               if(PRUICSS_pruWriteMemory(pruIcssHandle,PRU_ICSS_IRAM(1) ,0,
+                                       (uint32_t *) PRU1_FIRMWARE_NAME,
+                                       sizeof(PRU1_FIRMWARE_NAME)))
+                       firmwareLoad_done = TRUE;
+       }
+#endif
+
+       if( firmwareLoad_done)
+       {
+               PRUICSS_pruEnable(pruIcssHandle, ICSS_EMAC_PORT_1-1);
+               PRUICSS_pruEnable(pruIcssHandle, ICSS_EMAC_PORT_2-1);
+       }
+
+       while (!(((ICSS_EmacObject*)emachandle->object)->linkStatus[0] | 
+                       ((ICSS_EmacObject*)emachandle1->object)->linkStatus[0]))
+       {
+               Log_print0(Diags_INFO, "taskPruss: link down\n");
+               Task_sleep(200);
+       }
+
+       Log_print0(Diags_INFO, "link is finally up \n");
+
+       ICSS_EmacRegisterHwIntRx(emachandle, (ICSS_EmacCallBack)testCallbackRxPacket);
+       //ICSS_EmacRegisterHwIntRx(emachandle1, testCallbackRxPacket);
+}
+
+/**
+ * @brief initialize PRU & ICSS_EMAC config parameters due to MMU in IPU
+ *
+ * @param none
+ *
+ * @retval none
+ */
+void initPruIcssEmacCfg()
+{
+       uint32_t i;
+
+       /* phys. to virt translation for prussInitCfg[0], [1]*/
+       for(i=0; i<sizeof(PRUICSS_HwAttrs)/2; i++)
+               *((uint32_t *)prussInitCfg + i) += VIRT0;
+
+       prussInitCfg[0].version = 0;
+       prussInitCfg[1].version = 0;
+
+       /* phys. to virt translation for ICSS_EmacBaseAddrCfgParams[0], [1]*/
+       for(i=0; i<sizeof(ICSS_EmacBaseAddrCfgParams)/2; i++)
+               *((uint32_t *)icss_EmacBaseAddrCfgParams + i) += VIRT0;
+}
+
+/**
+ * @brief PRU & ICSS_EMAC initialization
+ *
+ * @param none
+ *
+ * @retval 0: success
+ *         -1: rx semaphore creation failed
+ *        -2: rx task creation failed
+ */
+int pru_icss()
+{
+
+       Error_Block eb;
+       Task_Params taskParams;
+       SemaphoreP_Params semParams;
+
+       Error_init(&eb);
+
+#ifdef EVM_INIT
+       Log_print0(Diags_INFO, "AM57x_setup");
+       AM57x_setup();
+#endif
+       /* Pin Mux completed in U-boot */
+       Log_print0(Diags_INFO, "Pin Mux Config parameters address mapping");
+
+       initPruIcssEmacCfg();
+
+       pruIcssHandle = PRUICSS_create(pruss_config,2);
+
+       Task_Params_init(&taskParams);
+       taskParams.priority = 15;
+       taskParams.instance->name = "SwitchTask";
+       Task_create(taskPruss, &taskParams, &eb);
+
+       /*ETH0 initializations*/
+       emachandle = (ICSS_EmacHandle)malloc(sizeof(ICSS_EmacConfig));
+
+       ICSS_EmacInitConfig* switchEmacCfg;
+       switchEmacCfg = (ICSS_EmacInitConfig*)
+               malloc(sizeof(ICSS_EmacInitConfig));
+       switchEmacCfg->phyAddr[0]=0;
+       switchEmacCfg->portMask = ICSS_EMAC_MODE_MAC1;
+       switchEmacCfg->ethPrioQueue = ICSS_EMAC_QUEUE1;
+
+       /* Crosssbar confiiguration */
+       *(unsigned int*)(0x4A0027E8U + VIRT0) =(unsigned int)(0x00C400CA);
+       *(unsigned int*)(0x4A0027ECU + VIRT0) =(unsigned int)(0x00CB00C5);
+
+       switchEmacCfg->halfDuplexEnable = 1;
+       switchEmacCfg->enableIntrPacing = ICSS_EMAC_ENABLE_PACING;
+       switchEmacCfg->ICSS_EmacIntrPacingMode = ICSS_EMAC_INTR_PACING_MODE1;
+       switchEmacCfg->pacingThreshold = 100;
+       switchEmacCfg->learningEn = 0;
+       SOCCtrlGetPortMacAddr(0,lclMac);
+       switchEmacCfg->macId = lclMac;
+
+       ICSSEmacDRVInit(emachandle, 2); 
+
+       switchEmacCfg->rxIntNum = 28;
+       switchEmacCfg->linkIntNum=27;
+
+       ((ICSS_EmacObject*)emachandle->object)->pruIcssHandle = pruIcssHandle;
+       ((ICSS_EmacObject*)emachandle->object)->emacInitcfg = switchEmacCfg;
+
+       /*ETH1 initializations*/
+       emachandle1 = (ICSS_EmacHandle)malloc(sizeof(ICSS_EmacConfig));
+
+       ICSS_EmacInitConfig* switchEmacCfg1;
+       switchEmacCfg1 = (ICSS_EmacInitConfig*)
+               malloc(sizeof(ICSS_EmacInitConfig));
+       switchEmacCfg1->phyAddr[0]= 1;
+
+       switchEmacCfg1->portMask = ICSS_EMAC_MODE_MAC2;
+       switchEmacCfg1->ethPrioQueue = ICSS_EMAC_QUEUE3;
+       switchEmacCfg1->enableIntrPacing = ICSS_EMAC_DISABLE_PACING;
+       switchEmacCfg1->pacingThreshold = 100;
+
+       switchEmacCfg1->learningEn = 0;
+
+       SOCCtrlGetPortMacAddr(1,lclMac1);
+       switchEmacCfg1->macId = lclMac1;
+
+       ICSSEmacDRVInit(emachandle1, 2);
+       switchEmacCfg1->rxIntNum = 30;;
+       switchEmacCfg1->linkIntNum=29;
+
+       ((ICSS_EmacObject*)emachandle1->object)->pruIcssHandle = pruIcssHandle;
+       ((ICSS_EmacObject*)emachandle1->object)->emacInitcfg = switchEmacCfg1;
+
+       PRUICSS_IntcInitData pruss_intc_initdata = PRUSS_INTC_INITDATA;
+       ICSS_EmacInit(emachandle,&pruss_intc_initdata,ICSS_EMAC_MODE_MAC1);
+
+       ICSS_EmacInit(emachandle1,&pruss_intc_initdata,ICSS_EMAC_MODE_MAC2);
+
+       Task_Params_init(&taskParams);
+       taskParams.priority = 10;
+       taskParams.instance->name = (char*)"port0_rxTaskFnc";
+       taskParams.stackSize = 0x1000;
+       taskParams.arg0 = (UArg)emachandle;
+       ((ICSS_EmacObject*)emachandle->object)->rxTaskHandle = 
+               Task_create(ICSS_EMacOsRxTaskFnc, &taskParams, NULL);
+
+       if(((ICSS_EmacObject*)emachandle->object)->rxTaskHandle==NULL)
+               return -2;
+
+       Task_Params_init(&taskParams);
+       taskParams.priority = 10;
+       taskParams.instance->name = (char*)"port1_rxTaskFnc";
+       taskParams.stackSize = 0x1000;
+       taskParams.arg0 = (UArg)emachandle1;
+       ((ICSS_EmacObject*)emachandle1->object)->rxTaskHandle = 
+               Task_create(ICSS_EMacOsRxTaskFnc, &taskParams, NULL);
+
+       if(((ICSS_EmacObject*)emachandle1->object)->rxTaskHandle==NULL)
+               return -2;
+
+       PRUICSS_pinMuxConfig(pruIcssHandle, 0x0); 
+       InterruptInit(emachandle);
+       InterruptInit(emachandle1);
+
+       EMACOpen(emachandle, 2);
+
+       EnableEMACInterrupts(emachandle);
+       EnableEMACInterrupts(emachandle1);
+
+       semParams.mode = SemaphoreP_Mode_COUNTING;
+       semParams.name= "icss_rxSemaphore";
+       icssRxSem =  SemaphoreP_create(0,&semParams);;
+       if(icssRxSem == NULL)
+               return -1;
+
+       semParams.mode = SemaphoreP_Mode_COUNTING;
+       semParams.name= "icss_rxSemaphore1";
+       icssRxSem1 =  SemaphoreP_create(0,&semParams);;
+       if(icssRxSem1 == NULL)
+               return -1;
+
+       Log_print0(Diags_INFO, "main_pruss: initialization done!");
+       return(0);
+}
+
+/**
+ * @brief Get MAC address
+ *
+ * @param portNum: port number
+ *        pMacAddr: MAC address data pointer
+ *
+ * @retval none
+ */
+void SOCCtrlGetPortMacAddr(uint32_t portNum, uint8_t *pMacAddr)
+{
+       if(portNum == 0) {
+               pMacAddr[5U] =  (VHW_RD_REG32(0x4A002514)
+                               >> 0U) & 0xFFU;
+               pMacAddr[4U] =  (VHW_RD_REG32(0x4A002514)
+                               >> 8U) & 0xFF;
+               pMacAddr[3U] =  (VHW_RD_REG32(0x4A002514)
+                               >> 16U) & 0xFFU;
+               pMacAddr[2U] =  (VHW_RD_REG32(0x4A002518)
+                               >> 0U) & 0xFFU;
+               pMacAddr[1U] =  (VHW_RD_REG32(0x4A002518)
+                               >> 8U) & 0xFFU;
+               pMacAddr[0U] =  (VHW_RD_REG32(0x4A002518)
+                               >> 16U) & 0xFFU;
+       }
+       else {
+               pMacAddr[5U] =  (VHW_RD_REG32(0x4A00251c)
+                               >> 0U) & 0xFFU;
+               pMacAddr[4U] =  (VHW_RD_REG32(0x4A00251c)
+                               >> 8U) & 0xFF;
+               pMacAddr[3U] =  (VHW_RD_REG32(0x4A00251c)
+                               >> 16U) & 0xFFU;
+               pMacAddr[2U] =  (VHW_RD_REG32(0x4A002520)
+                               >> 0U) & 0xFFU;
+               pMacAddr[1U] =  (VHW_RD_REG32(0x4A002520)
+                               >> 8U) & 0xFFU;
+               pMacAddr[0U] =  (VHW_RD_REG32(0x4A002520)
+                               >> 16U) & 0xFFU;
+       }
+}
+
+
+/**
+ * @brief ICSS_EMAC driver initialization
+ *
+ * @param handle: ICSS_EMAC handler
+ *        instance: PRU instance number
+ *
+ * @retval none
+ */
+void ICSSEmacDRVInit(ICSS_EmacHandle handle, uint8_t instance) 
+{
+       /* LLD attributes mallocs */
+       handle->object = (ICSS_EmacObject*)malloc(sizeof(ICSS_EmacObject));
+       handle->hwAttrs= (ICSS_EmacHwAttrs*)malloc(sizeof(ICSS_EmacHwAttrs));
+
+       /* Callback mallocs */
+       ICSS_EmacCallBackObject* callBackObj = (ICSS_EmacCallBackObject*)
+               malloc(sizeof(ICSS_EmacCallBackObject));
+
+       callBackObj->learningExCallBack=(ICSS_EmacCallBackConfig*)
+               malloc(sizeof(ICSS_EmacCallBackConfig));
+       callBackObj->rxRTCallBack=(ICSS_EmacCallBackConfig*)
+               malloc(sizeof(ICSS_EmacCallBackConfig));
+       callBackObj->rxCallBack=(ICSS_EmacCallBackConfig*)
+               malloc(sizeof(ICSS_EmacCallBackConfig));
+       callBackObj->txCallBack=(ICSS_EmacCallBackConfig*)
+               malloc(sizeof(ICSS_EmacCallBackConfig));
+       ((ICSS_EmacObject*)handle->object)->callBackHandle = callBackObj;
+
+       /*Allocate memory for learning*/
+       ((ICSS_EmacObject*)handle->object)->macTablePtr = (HashTable_t*)
+               malloc(NUM_PORTS * sizeof(HashTable_t));
+
+       /*Allocate memory for PRU Statistics*/
+       ((ICSS_EmacObject*)handle->object)->pruStat = 
+               (ICSS_EmacPruStatistics_t*)malloc(NUM_PORTS * 
+                               sizeof(ICSS_EmacPruStatistics_t));
+
+       /*Allocate memory for Host Statistics*/
+       ((ICSS_EmacObject*)handle->object)->hostStat = 
+               (ICSS_EmacHostStatistics_t*)malloc(NUM_PORTS * 
+                               sizeof(ICSS_EmacHostStatistics_t));
+
+       /*Allocate memory for Storm Prevention*/
+       ((ICSS_EmacObject*)handle->object)->stormPrevPtr = 
+               (stormPrevention_t*)malloc(NUM_PORTS * 
+                               sizeof(stormPrevention_t));
+
+       /* Base address initialization */
+       if(NULL == ((ICSS_EmacHwAttrs*)handle->hwAttrs)->emacBaseAddrCfg) {
+               ((ICSS_EmacHwAttrs*)handle->hwAttrs)->emacBaseAddrCfg =
+                       (ICSS_EmacBaseAddressHandle_T)
+                       malloc(sizeof(ICSS_EmacBaseAddrCfgParams));
+       }
+       ICSS_EmacBaseAddressHandle_T emacBaseAddr = 
+               ((ICSS_EmacHwAttrs*)handle->hwAttrs)->emacBaseAddrCfg;
+
+       if(instance == 2)
+       {
+               emacBaseAddr->dataRam0BaseAddr = 
+                       icss_EmacBaseAddrCfgParams[instance-1].dataRam0BaseAddr;
+               emacBaseAddr->dataRam1BaseAddr = 
+                       icss_EmacBaseAddrCfgParams[instance-1].dataRam1BaseAddr;
+               emacBaseAddr->l3OcmcBaseAddr =  
+                       icss_EmacBaseAddrCfgParams[instance-1].l3OcmcBaseAddr;
+               emacBaseAddr->prussCfgRegs =  
+                       icss_EmacBaseAddrCfgParams[instance-1].prussCfgRegs;
+               emacBaseAddr->prussIepRegs =  
+                       icss_EmacBaseAddrCfgParams[instance-1].prussIepRegs;
+               emacBaseAddr->prussIntcRegs = 
+                       icss_EmacBaseAddrCfgParams[instance-1].prussIntcRegs;
+               emacBaseAddr->prussMiiMdioRegs = 
+                       icss_EmacBaseAddrCfgParams[instance-1].prussMiiMdioRegs;
+               emacBaseAddr->prussMiiRtCfgRegsBaseAddr = 
+                       icss_EmacBaseAddrCfgParams[instance-1].prussMiiRtCfgRegsBaseAddr;
+               emacBaseAddr->prussPru0CtrlRegs = 
+                       icss_EmacBaseAddrCfgParams[instance-1].prussPru0CtrlRegs;
+               emacBaseAddr->prussPru1CtrlRegs = 
+                       icss_EmacBaseAddrCfgParams[instance-1].prussPru1CtrlRegs;
+               emacBaseAddr->sharedDataRamBaseAddr = 
+                       icss_EmacBaseAddrCfgParams[instance-1].sharedDataRamBaseAddr;
+       }
+}
+
+/**
+ * @internal
+ * @brief Registering Interrupts and Enabling global interrupts
+ *
+ * @param icssEmacHandle: ICSS_EMAC handler
+ *
+ * @retval none
+ */
+void InterruptInit(ICSS_EmacHandle icssEmacHandle)
+{
+       HwiP_Handle rxHwiHandle;
+       HwiP_Handle linkHwiHandle;
+       static uint32_t cookie = 0;
+       uint8_t linkIntrN = (((ICSS_EmacObject*)
+                       icssEmacHandle->object)->emacInitcfg)->linkIntNum;
+       uint8_t rxIntrN = (((ICSS_EmacObject*)
+                       icssEmacHandle->object)->emacInitcfg)->rxIntNum;
+
+       cookie = ICSS_EMAC_osalHardwareIntDisable();
+
+       HwiP_Params hwiParams;
+
+       ICSS_EMAC_osalHwiParamsInit(&hwiParams);
+
+       hwiParams.arg = (uintptr_t)icssEmacHandle;
+       hwiParams.evtId = rxIntrN;
+       hwiParams.priority = 0x20; 
+       rxHwiHandle = ICSS_EMAC_osalRegisterInterrupt(rxIntrN, 
+                       (HwiP_Fxn)ICSS_EmacRxInterruptHandler, &hwiParams);
+       if (rxHwiHandle == NULL )
+               return;
+
+       hwiParams.arg = (uintptr_t)icssEmacHandle;
+       hwiParams.evtId = linkIntrN;
+       hwiParams.priority = 0x20;
+       linkHwiHandle = ICSS_EMAC_osalRegisterInterrupt(linkIntrN,
+                       (HwiP_Fxn)ICSS_EmacLinkISR, &hwiParams);
+       if (linkHwiHandle == NULL)
+               return;
+
+       ((ICSS_EmacObject*)icssEmacHandle->object)->rxintHandle = rxHwiHandle;
+       ((ICSS_EmacObject*)icssEmacHandle->object)->linkintHandle = 
+               linkHwiHandle;
+
+       ICSS_EMAC_osalHardwareIntRestore(cookie);
+}
+/**
+ * @internal
+ * @brief De-registering the interrupts and disabling global interrupts
+ *
+ * @param none
+ *
+ * @retval none
+ */
+void InterruptEnd(ICSS_EmacHandle icssEmacHandle)
+{
+       ICSS_EMAC_osalHardwareIntDestruct((HwiP_Handle)(((ICSS_EmacObject*)
+                               icssEmacHandle->object)->rxintHandle));
+
+       ICSS_EMAC_osalHardwareIntDestruct((HwiP_Handle)(((ICSS_EmacObject*)
+                               icssEmacHandle->object)->linkintHandle));
+}
+/**
+ * @internal
+ * @brief This function enables the EMAC interrupts
+ *
+ * @param none
+ *
+ * @retval none
+ */
+static void EnableEMACInterrupts(ICSS_EmacHandle icssemacHandle)
+{
+       uint32_t key = 0;
+
+       ICSS_EmacHandle handle = icssemacHandle;
+       key = ICSS_EMAC_osalHardwareIntDisable();
+
+       ICSS_EMAC_osalHardwareInterruptEnable((((ICSS_EmacObject*)
+                               handle->object)->emacInitcfg)->linkIntNum);
+       ICSS_EMAC_osalHardwareInterruptEnable((((ICSS_EmacObject*)
+                               handle->object)->emacInitcfg)->rxIntNum);
+
+       ICSS_EMAC_osalHardwareIntRestore(key);
+}
+/**
+ * @brief This function disables the EMAC interrupts
+ * @internal
+ * @param none
+ *
+ * @retval none
+ */
+void DisableEMACInterrupts(ICSS_EmacHandle icssemacHandle)
+{
+       uint32_t key;
+       ICSS_EmacHandle handle = icssemacHandle;
+       key = ICSS_EMAC_osalHardwareIntDisable();
+
+       ICSS_EMAC_osalHardwareInterruptDisable((((ICSS_EmacObject*)
+                               handle->object)->emacInitcfg)->linkIntNum);
+       ICSS_EMAC_osalHardwareInterruptDisable((((ICSS_EmacObject*)
+                               handle->object)->emacInitcfg)->rxIntNum);
+
+       ICSS_EMAC_osalHardwareIntRestore(key);
+}
+
+/**
+ * @brief Clears Link interrupt for Port0
+ * @internal
+ * @param pruIcssHandle Provides PRUSS memory map
+ *
+ * @retval none
+ */
+inline void clearLink0ISR(ICSS_EmacHandle icssemacHandle)
+{
+       HW_WR_FIELD32(((((ICSS_EmacHwAttrs *)icssemacHandle->hwAttrs)
+                       ->emacBaseAddrCfg)->prussIntcRegs + CSL_ICSSINTC_SECR1),
+                       CSL_ICSSINTC_SECR1_ENA_STATUS_63_32, 0x200);
+}
+
+/**
+ * @brief Clears Link interrupt for ICSS_EMAC_PORT_1
+ * @internal
+ * @param pruIcssHandle Provides PRUSS memory map
+ *
+ * @retval none
+ */
+inline void clearLink1ISR(ICSS_EmacHandle icssemacHandle)
+{
+       HW_WR_FIELD32(((((ICSS_EmacHwAttrs *)icssemacHandle->hwAttrs)
+                       ->emacBaseAddrCfg)->prussIntcRegs + CSL_ICSSINTC_SECR1),
+                       CSL_ICSSINTC_SECR1_ENA_STATUS_63_32, 0x200000);
+}
diff --git a/ipu1/PktSwitch.c b/ipu1/PktSwitch.c
new file mode 100644 (file)
index 0000000..d41efd3
--- /dev/null
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+#include "ti/csl/cslr_device.h"
+
+#include <icss_emacDrv.h>
+
+#define BYTESWAP16(x)  ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8))
+#define ETH_ALEN       6
+#define ETH_VLAN       0x8100
+#define ETH_TYPE_GOOSE 0x88B8
+#define ETH_TYPE_PTP   0x88F7
+#define ETH_TYPE_SV    0x88BA
+
+#define ACCEPT_APPID_NUM       4
+#define DEST_MAC_NUM           4
+
+char vlan;
+extern uint32_t bGooseFilter;
+extern char ptpMulDest1MacAddr[ETH_ALEN];
+extern char ptpMulDest2MacAddr[ETH_ALEN];
+extern char GooseDestMacAddr[DEST_MAC_NUM][ETH_ALEN];
+extern uint16_t GooseAPPID[ACCEPT_APPID_NUM];
+
+/**
+* @internal
+* @brief GOOSE filtering algorithm
+*
+* @param pIcssRxPkt: received packet data pointer
+*
+* @retval packet type 
+*/
+
+int32_t GooseProc(char *pIcssRxPkt)
+{
+       int32_t i, appId;
+       int32_t bMac;
+
+       if(vlan == 1)
+               appId = *(uint16_t *)((char *)pIcssRxPkt + 2 * 
+                               ETH_ALEN + 2 + 4); 
+       else 
+               appId = *(uint16_t *)((char *)pIcssRxPkt + 2 * 
+                               ETH_ALEN + 2); 
+
+       appId = BYTESWAP16(appId);
+
+       if (bGooseFilter == 1) {
+               bMac = 0;
+               for ( i = 0; i < DEST_MAC_NUM; i++ ) {
+                       if (memcmp(pIcssRxPkt, GooseDestMacAddr[i], 
+                                               ETH_ALEN) == 0) {
+                               bMac = 1;
+                               break;
+                       }
+               }
+
+               if (bMac == 1) {
+                       /* Drop a GOOSE packet not having APPID from the list of
+                          acceptable APPIDs */
+                       for (i = 0; i < ACCEPT_APPID_NUM; i++) {
+                               if((appId == GooseAPPID[i]) && (appId < 0x3FFF))
+                                       return PKT_PROC_GOOSE;
+                               else if (appId == GooseAPPID[i]) 
+                                       return PKT_PROC_GOOSE;
+                       }
+                       return PKT_PROC_NONE;
+               }
+               else return PKT_PROC_MPU;
+       }
+
+       else
+               if (appId < 0x3FFF)
+                       return PKT_PROC_GOOSE;
+               else 
+                       return PKT_PROC_GOOSE;  
+
+}
+
+int32_t PtpProc(char *pIcssRxPkt)
+{
+       if((memcmp(pIcssRxPkt, ptpMulDest1MacAddr, ETH_ALEN) == 0) ||
+               (memcmp(pIcssRxPkt, ptpMulDest2MacAddr, ETH_ALEN) == 0))
+               return PKT_PROC_PTP;
+        else
+               return PKT_PROC_NONE;
+
+}
+
+int32_t SvProc(char *pIcssRxPkt)
+{
+       //Log_print0(Diags_INFO, "Placeholder for SV packet filtering");
+       return PKT_PROC_NONE;   
+}
+
+int32_t Filter2(char *pIcssRxPkt)
+{
+       //Log_print0(Diags_INFO, "Placeholder for additional filtering");
+       return PKT_PROC_NONE;   
+}
+
+/**
+* @internal
+* @brief packet switch logic
+*
+* @param pIcssRxPkt: received packet data pointer
+*
+* @retval packet type 
+*/
+int32_t PruSwitch(char *pIcssRxPkt)
+{
+       uint16_t ethType;
+
+       ethType = *(uint16_t *)(pIcssRxPkt  +  2 * ETH_ALEN);
+       ethType = BYTESWAP16(ethType);
+
+       if (ethType == ETH_VLAN) {
+               vlan = 1;
+               ethType = *(uint16_t *)((char *)pIcssRxPkt  +  2 * 
+                               ETH_ALEN + 2 + 2);
+       }       
+       else {
+               vlan = 0;
+               ethType = *(uint16_t *)((char *)pIcssRxPkt  +  2 * ETH_ALEN);
+       }
+       ethType = BYTESWAP16(ethType);
+
+       switch (ethType) {
+               case ETH_TYPE_GOOSE: 
+                       return GooseProc(pIcssRxPkt);
+               case ETH_TYPE_PTP:
+                       return PtpProc(pIcssRxPkt);
+               case ETH_TYPE_SV:
+                       return SvProc(pIcssRxPkt);
+               default: 
+                       Filter2(pIcssRxPkt);
+                       return PKT_PROC_MPU;
+       }
+}
+
diff --git a/ipu1/Server.c b/ipu1/Server.c
new file mode 100644 (file)
index 0000000..718f0c4
--- /dev/null
@@ -0,0 +1,280 @@
+/*
+ * Copyright (c) 2013-2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Server.c ========
+ *
+ */
+
+/* this define must precede inclusion of any xdc header file */
+#define Registry_CURDESC Test__Desc
+#define MODULE_NAME "Server"
+
+/* xdctools header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Assert.h>
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Log.h>
+#include <xdc/runtime/Registry.h>
+
+#include <stdio.h>
+#include <string.h>
+
+/* package header files */
+#include <ti/ipc/MessageQ.h>
+#include <ti/ipc/MultiProc.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/hal/Cache.h>
+#include "ti/osal/SemaphoreP.h"
+
+/* local header files */
+#include "../shared/AppCommon.h"
+
+/* module header file */
+#include "Server.h"
+
+#define VIRT1 (-0x90000000U) /* PA 0xA0000000<->VA 0x10000000, see RSC table */
+/* module structure */
+typedef struct {
+       UInt16              hostProcId;         // host processor id
+       MessageQ_Handle     slaveQue;           // created locally
+} Server_Module;
+
+/* private data */
+Registry_Desc               Registry_CURDESC;
+static Server_Module        Module;
+
+#define TEST_PORT 0
+
+UInt32 *pRxPkt;
+extern UInt32 packetLength;
+
+UInt32 *pGoosePara;
+UInt32 bGooseFilter = 1;
+extern void Goose_para_config();
+
+extern void *icssRxSem;
+extern void icss_rx();
+
+extern void icss_tx();
+extern void icss_tx_mpu(UInt32 *PTxPacket, Int TxPacketLen);
+
+/*
+ *  ======== Server_init ========
+ */
+Void Server_init(Void)
+{
+       Registry_Result result;
+
+       /* register with xdc.runtime to get a diags mask */
+       result = Registry_addModule(&Registry_CURDESC, MODULE_NAME);
+       Assert_isTrue(result == Registry_SUCCESS, (Assert_Id)NULL);
+
+       /* initialize module object state */
+       Module.hostProcId = MultiProc_getId("HOST");
+}
+
+
+/*
+ *  ======== Server_create ========
+ */
+Int Server_create()
+{
+       Int                 status = 0;
+       MessageQ_Params     msgqParams;
+       char                msgqName[32];
+
+       /* enable some log events */
+       Diags_setMask(MODULE_NAME"+EXF");
+
+       /* create local message queue (inbound messages) */
+       MessageQ_Params_init(&msgqParams);
+       sprintf(msgqName, App_SlaveMsgQueName, MultiProc_getName(MultiProc_self()));
+       Module.slaveQue = MessageQ_create(msgqName, &msgqParams);
+
+       if (Module.slaveQue == NULL) {
+               status = -1;
+               goto leave;
+       }
+
+       Log_print0(Diags_INFO,"Server_create: server is ready");
+
+leave:
+       Log_print1(Diags_EXIT, "<-- Server_create: %d", (IArg)status);
+       return (status);
+}
+
+
+
+
+/*
+ *  ======== Server_exec ========
+ */
+Int Server_exec()
+{
+       Int                 status;
+       Bool                running = TRUE;
+       App_Msg *           msg;
+       MessageQ_QueueId    queId;
+       UInt32              *pRxPkt0, *pRxPkt1;
+
+#ifdef TX_FROM_A15
+       UInt32              *pTxPkt0, *pTxPkt1;
+#endif
+
+       Log_print0(Diags_ENTRY | Diags_INFO, "--> Server_exec:");
+
+       while (running) {
+
+               /* wait for inbound message */
+               status = MessageQ_get(Module.slaveQue, (MessageQ_Msg *)&msg,
+                               MessageQ_FOREVER);
+
+               if (status < 0) {
+                       goto leave;
+               }
+               if (msg->cmd == App_CMD_GOOSE_DISABLE)
+                       bGooseFilter = 0;
+
+               if (msg->cmd == App_CMD_CMEMBUF) {
+
+                       pRxPkt0 = (UInt32 *)(msg->RxPhysAddr[TEST_PORT][0] + VIRT1);
+                       pRxPkt1 = (UInt32 *)(msg->RxPhysAddr[TEST_PORT][1] + VIRT1);
+
+                       pRxPkt = pRxPkt0;
+
+#ifdef TX_FROM_A15
+                       pTxPkt0 = (UInt32 *)(msg->TxPhysAddr[TEST_PORT][0] + VIRT1);
+                       pTxPkt1 = (UInt32 *)(msg->TxPhysAddr[TEST_PORT][1] + VIRT1);
+#endif
+                       pGoosePara = (UInt32 *)(msg->GooseParaPhysAddr + VIRT1);
+
+                       Goose_para_config();
+               }
+
+               if (msg->cmd == App_CMD_SHUTDOWN) {
+                       running = FALSE;
+               }
+
+               /* process the message */
+               Log_print1(Diags_INFO, "Server_exec: processed cmd=0x%x", msg->cmd);
+
+               /* send message back */
+               queId = MessageQ_getReplyQueue(msg); /* type-cast not needed */
+               if(msg->cmd == App_CMD_PACKET)
+               {
+#ifdef TX_FROM_A15
+                       /* send packets from host A15 */
+                       numBuf = msg->nTxBuf;
+                       TxPktLen = msg->TxPktLen[TEST_PORT][numBuf];
+
+                       if(TxPktLen != 0 ) {
+                               if(numBuf == 0) {
+                                       icss_tx_mpu(pTxPkt0, TxPktLen);
+                               }
+                               else {
+                                       icss_tx_mpu(pTxPkt1, TxPktLen);
+                               }
+                       }
+#endif
+
+                       icss_tx();
+
+                       icss_rx();
+
+                       if (pRxPkt == pRxPkt0) {
+                               pRxPkt = pRxPkt1;
+                               msg->RxPktLen[TEST_PORT][0] = packetLength;
+                               msg->nRxBuf = 0;
+                       } else {
+                               pRxPkt = pRxPkt0;
+                               msg->RxPktLen[TEST_PORT][1] = packetLength;
+                               msg->nRxBuf = 1;
+                       }
+#ifdef MONITOR_RECV_PACKET
+                       /* log received packets */
+                       for(j=0; j<packetLength; j++)
+                               Log_print1(Diags_INFO, "%2x", *((char*)pRxPkt+j));
+#endif
+                       msg->port = TEST_PORT;
+               }
+               MessageQ_put(queId, (MessageQ_Msg)msg);
+       } /* while (running) */
+
+leave:
+       Log_print1(Diags_EXIT, "<-- Server_exec: %d", (IArg)status);
+       return(status);
+}
+
+/*
+ *  ======== Server_delete ========
+ */
+
+Int Server_delete()
+{
+       Int         status;
+
+       Log_print0(Diags_ENTRY, "--> Server_delete:");
+
+       /* delete the video message queue */
+       status = MessageQ_delete(&Module.slaveQue);
+
+       if (status < 0) {
+               goto leave;
+       }
+
+leave:
+       if (status < 0) {
+               Log_error1("Server_finish: error=0x%x", (IArg)status);
+       }
+
+       /* disable log events */
+       Log_print1(Diags_EXIT, "<-- Server_delete: %d", (IArg)status);
+       Diags_setMask(MODULE_NAME"-EXF");
+
+       return(status);
+}
+
+/*
+ *  ======== Server_exit ========
+ */
+
+Void Server_exit(Void)
+{
+        /* Note that there isn't a Registry_removeModule() yet:
+        *     https://bugs.eclipse.org/bugs/show_bug.cgi?id=315448
+        *
+        * ... but this is where we'd call it.
+        */
+}
diff --git a/ipu1/Server.h b/ipu1/Server.h
new file mode 100644 (file)
index 0000000..570df03
--- /dev/null
@@ -0,0 +1,64 @@
+/*
+#  Copyright (c) 2012-2016 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Server.h ========
+ */
+
+#ifndef Server__include
+#define Server__include
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+#define SOC_AM571x
+#define VIRT0 (0x20000000U)
+#define VHW_RD_REG32(x) HW_RD_REG32(x+VIRT0)
+
+#define MAX_PKT_FRAME_SIZE      1536
+#define ETH_ALEN                6
+#define ACCEPT_APPID_NUM        4
+#define DEST_MAC_NUM            4
+
+Void Server_init(Void);
+Void Server_exit(Void);
+
+Int Server_create(Void);
+Int Server_exec(Void);
+Int Server_delete(Void);
+
+
+#if defined (__cplusplus)
+}
+#endif /* defined (__cplusplus) */
+#endif /* Server__include */
diff --git a/ipu1/icss_emacDrv.c b/ipu1/icss_emacDrv.c
new file mode 100644 (file)
index 0000000..029e3ab
--- /dev/null
@@ -0,0 +1,2048 @@
+/**
+ * @file icss_emacDrv.c
+ * @brief Contains the Rx and Tx functions for packet processing on ARM including the ISR for two PRU
+ *
+ */
+
+/* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 
+*
+*   Redistribution and use in source and binary forms, with or without 
+*   modification, are permitted provided that the following conditions 
+*   are met:
+*
+*     Redistributions of source code must retain the above copyright 
+*     notice, this list of conditions and the following disclaimer.
+*
+*     Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in the 
+*     documentation and/or other materials provided with the   
+*     distribution.
+*
+*     Neither the name of Texas Instruments Incorporated nor the names of
+*     its contributors may be used to endorse or promote products derived
+*     from this software without specific prior written permission.
+*
+*   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <stdint.h>
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <xdc/std.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/knl/Cache.h>
+
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Log.h>
+
+#include <ti/csl/src/ip/icss/V0/cslr_icss_intc.h>
+#include <ti/csl/src/ip/mdio/V2/cslr_mdio.h>
+#include <ti/csl/src/ip/mdio/V2/csl_mdio.h>
+#include <ti/csl/src/ip/mdio/V2/csl_mdioAux.h>
+
+#include <ti/drv/pruss/pruicss.h>
+
+//#include <ti/drv/icss_emac/icss_emacDrv.h>
+#include <icss_emacDrv.h>
+#include <ti/drv/icss_emac/icss_emacCommon.h>
+#include <ti/drv/icss_emac/icss_emacStatistics.h>
+#include <ti/drv/icss_emac/icss_emacStormControl.h>
+#include <ti/drv/icss_emac/icss_emacLearning.h>
+#include <ti/drv/icss_emac/icss_emacFwInit.h>
+#include <ti/drv/icss_emac/icss_emac_osal.h>
+
+extern int32_t PruSwitch(char *pIcssRxPkt);
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+/**This value in the MDIO Reg means 10 mbps mode is enabled*/
+#define Ten_Mbps  0xa
+/**This value in the MDIO Reg means 100 mbps mode is enabled*/
+#define Hundread_Mbps 0x64
+/**Minimum supported size of Ethernet frame*/
+#define ETHERNET_FRAME_SIZE_60 60
+
+#define LINK0_PRU_EVT_MASK  (0x200U)
+#define LINK1_PRU_EVT_MASK  (0x200000U)
+/**Pacing timer Value*/
+#define DEFAULT_PACING_TIMER_VAL 100
+
+#define ENABLE_TIMER_SUPPORT
+
+/**Timer Handle for pacing*/
+#ifdef ENABLE_TIMER_SUPPORT
+void* pacingTimerHandle;
+#endif
+
+#define PHY_LINK_STATUS                   (0x0004u)
+#define PHY_BSR                           (1u)
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+
+/** Variable containing list of implemented protocols*/
+uint16_t numImplementedProtocols = NUM_PROTOCOLS_IMPLEMENTED;
+/**list of identified protocol types, rest initialized to zero*/
+uint16_t protocol_impl[MAX_NUM_PROTOCOL_IMPLEMENTED] = {IP4_PROT_TYPE, ARP_PROT_TYPE,0,0,0,0, 0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,
+                                                        0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0};
+/** port params for three ports, two physical and one for host*/
+//ICSS_EmacPortParams switchPort[3];
+/**Number of collisions occured*/
+int32_t num_of_collision_occured = 0;
+/**Number of packets dropped as a result of collision not resolved*/
+int32_t collision_pkt_dropped =0;
+/** @brief User specific data HW Port 0 Link ISR*/
+
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+/**
+ *  \name ICSS_EmacClearRxIrq
+ *  @brief Clears Rx interrupt
+ *
+ *  @param none
+ *
+ *  @retval none
+ *
+ */
+inline void ICSS_EmacClearRxIrq(ICSS_EmacHandle icssemacHandle);   /* for misra warning*/
+inline void ICSS_EmacClearRxIrq(ICSS_EmacHandle icssemacHandle)
+{
+    if((((ICSS_EmacObject*)icssemacHandle->object)->emacInitcfg)->portMask == ICSS_EMAC_MODE_MAC2) {
+        HW_WR_FIELD32(((((ICSS_EmacHwAttrs*)icssemacHandle->hwAttrs)->emacBaseAddrCfg)->prussIntcRegs + CSL_ICSSINTC_SECR0),
+                CSL_ICSSINTC_SECR0_ENA_STATUS_31_0, (1U) << 21);
+    } else {
+        HW_WR_FIELD32(((((ICSS_EmacHwAttrs*)icssemacHandle->hwAttrs)->emacBaseAddrCfg)->prussIntcRegs + CSL_ICSSINTC_SECR0),
+                CSL_ICSSINTC_SECR0_ENA_STATUS_31_0, (1U) << 20);
+    }
+}
+
+void ICSS_EmacEnableRxInterrupt(ICSS_EmacHandle icssemacHandle);   /* for misra warning*/
+void ICSS_EmacEnableRxInterrupt(ICSS_EmacHandle icssemacHandle)
+{
+    uint32_t intNum = ((ICSS_EmacObject*)icssemacHandle->object)->emacInitcfg->rxIntNum;
+    ICSS_EMAC_osalHardwareInterruptEnable((int32_t)intNum);
+}
+
+void ICSS_EmacDisableRxInterrupt(ICSS_EmacHandle icssemacHandle);  /* for misra warning*/
+void ICSS_EmacDisableRxInterrupt(ICSS_EmacHandle icssemacHandle)
+{
+    uint32_t intNum = ((ICSS_EmacObject*)icssemacHandle->object)->emacInitcfg->rxIntNum;
+    ICSS_EMAC_osalHardwareInterruptDisable((int32_t)intNum);
+
+}
+
+
+/**
+ *  \name ICSS_EmacClearTxIrq
+ *  @brief Clears Tx Packet Completion interrupt
+ *
+ *  @param none
+ *
+ *  @retval none
+ *
+ */
+inline void ICSS_EmacClearTxIrq(ICSS_EmacHandle icssemacHandle); /* for misra warnings*/
+inline void ICSS_EmacClearTxIrq(ICSS_EmacHandle icssemacHandle)
+{
+    if((((ICSS_EmacObject*)icssemacHandle->object)->emacInitcfg)->portMask == ICSS_EMAC_MODE_MAC2) {
+        HW_WR_FIELD32(((((ICSS_EmacHwAttrs*)icssemacHandle->hwAttrs)->emacBaseAddrCfg)->prussIntcRegs + CSL_ICSSINTC_SECR0),
+                CSL_ICSSINTC_SECR0_ENA_STATUS_31_0, (1U) << 23);
+    } else {
+        HW_WR_FIELD32(((((ICSS_EmacHwAttrs*)icssemacHandle->hwAttrs)->emacBaseAddrCfg)->prussIntcRegs + CSL_ICSSINTC_SECR0),
+                CSL_ICSSINTC_SECR0_ENA_STATUS_31_0, (1U) << 22);
+    }
+}
+
+void ICSS_EmacEnableTxInterrupt(ICSS_EmacHandle icssemacHandle); /* for misra warnings*/
+void ICSS_EmacEnableTxInterrupt(ICSS_EmacHandle icssemacHandle) {
+    uint32_t intNum = ((ICSS_EmacObject*)icssemacHandle->object)->emacInitcfg->txIntNum;
+    ICSS_EMAC_osalHardwareInterruptEnable((int32_t)intNum);
+}
+
+void ICSS_EmacDisableTxInterrupt(ICSS_EmacHandle icssemacHandle); /* for misra warnings*/
+void ICSS_EmacDisableTxInterrupt(ICSS_EmacHandle icssemacHandle) {
+    uint32_t intNum = ((ICSS_EmacObject*)icssemacHandle->object)->emacInitcfg->txIntNum;
+    ICSS_EMAC_osalHardwareInterruptDisable((int32_t)intNum);
+
+}
+/**
+ *  \name ICSS_EmacTxInterruptHandler
+ *  @brief Main Tx completion interrupt service routine
+ *
+ *  @param args arguments if any
+ *
+ *  @retval
+ *       void
+ *
+ */
+void ICSS_EmacTxInterruptHandler(void *args)
+{
+    ICSS_EmacHandle handle = (ICSS_EmacHandle)args;
+    ICSS_EMAC_osalPostLock(((ICSS_EmacObject*)handle->object)->txSemaphoreHandle);
+    ICSS_EmacClearTxIrq((ICSS_EmacHandle)args);
+}
+/**
+ *  \name ICSS_EmacRxInterruptHandler
+ *  @brief Main Rx interrupt service routine
+ *
+ *  @param args arguments if any
+ *
+ *  @retval
+ *       void
+ *
+ */
+void ICSS_EmacRxInterruptHandler(void *args)
+{
+    uint8_t pacingEnabled;
+#ifdef ENABLE_TIMER_SUPPORT
+    uint8_t pacingMode;
+#endif
+    ICSS_EmacHandle handle = (ICSS_EmacHandle)args;
+    ICSS_EmacClearRxIrq((ICSS_EmacHandle)args);
+
+    pacingEnabled = (((ICSS_EmacObject*)handle->object)->emacInitcfg)->enableIntrPacing;
+
+#ifdef ENABLE_TIMER_SUPPORT
+    pacingMode = (((ICSS_EmacObject*)handle->object)->emacInitcfg)->ICSS_EmacIntrPacingMode;
+#endif
+    /*disable Rx interrupt on ARM, PRU line stays high*/
+    if(pacingEnabled == ICSS_EMAC_ENABLE_PACING) {
+        ICSS_EmacDisableRxInterrupt(handle);
+
+#ifdef ENABLE_TIMER_SUPPORT
+        if(pacingMode == ICSS_EMAC_INTR_PACING_MODE2) {
+            ICSS_EMAC_osalTimerStart(pacingTimerHandle);
+        }
+#endif
+     }
+
+    ICSS_EMAC_osalPostLock(((ICSS_EmacObject*)handle->object)->rxSemaphoreHandle);
+}
+
+/**
+ *  \name ICSS_EMacOsRxTaskFnc
+ *  @brief
+ *      Function which pends on Rx semaphore.Gets the Rx packet info for processing
+ *
+ *  @param a0 arg 1
+ *  @param a1 arg 2
+ *
+ *  @retval none
+ *
+ */
+void ICSS_EMacOsRxTaskFnc(uint32_t a0, uint32_t a1)
+{
+    int32_t port_number;
+    int32_t queue_number;
+    int32_t pkt_proc;
+    int16_t pLength;
+    int32_t allQueuesEempty = 0;
+    int8_t  dest_address[ICSS_EMAC_MAXMTU];
+    uint16_t numPacketsInLoop = 0;
+    uint8_t pacingEnabled;
+    uint8_t pacingMode;
+    ICSS_EmacHandle icssEmacHandle;
+    icssEmacHandle = (ICSS_EmacHandle)a0;
+    ICSS_EmacRxArgument rxArg;
+
+    pacingEnabled = (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->enableIntrPacing;
+    pacingMode    = (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->ICSS_EmacIntrPacingMode;
+
+    while(1)
+    {
+        ICSS_EMAC_osalPendLock(((ICSS_EmacObject*)icssEmacHandle->object)->rxSemaphoreHandle, SemaphoreP_WAIT_FOREVER);
+
+        while((allQueuesEempty != 1) && (numPacketsInLoop <= ((((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->pacingThreshold)))
+        {
+            pLength = ((int16_t)(ICSS_EmacRxPktInfo(icssEmacHandle, &port_number, &queue_number, &pkt_proc)));
+            if(pLength > 0)
+            {
+                /*Ethernet packet will be put into ICSS_EMAC_QUEUEPRIO4 only
+                 * Give the packet to ndk stack*/
+                if(queue_number >= ((ICSS_EmacObject*)(icssEmacHandle->object))->emacInitcfg->ethPrioQueue)
+                {
+                      ((ICSS_EmacObject*)icssEmacHandle->object)->icssEmacHwIntRx(&queue_number,icssEmacHandle);
+                } 
+                else 
+                {
+                    if(((((ICSS_EmacObject*)icssEmacHandle->object)->callBackHandle)->rxRTCallBack)->callBack != NULL) {
+                        ((((ICSS_EmacObject*)icssEmacHandle->object)->callBackHandle)->rxRTCallBack)->callBack(&queue_number,
+                                ((((ICSS_EmacObject*)icssEmacHandle->object)->callBackHandle)->rxRTCallBack)->userArg);
+                    } else {
+                            rxArg.icssEmacHandle = icssEmacHandle;
+                            rxArg.destAddress = (uint32_t)dest_address;
+                            rxArg.more = 0;
+                            rxArg.queueNumber = queue_number;
+                            rxArg.port=port_number;
+
+                            ((((ICSS_EmacObject *)icssEmacHandle->object)->callBackHandle)->rxCallBack)->callBack(&rxArg,NULL);   /* just dump the packet here so we do no stall the queues */
+                    }
+
+                }
+                if(pacingEnabled == ICSS_EMAC_ENABLE_PACING) {
+                    numPacketsInLoop++;
+                }
+            } 
+            else 
+            {
+                allQueuesEempty =1;
+            }
+        }
+        allQueuesEempty =0;
+
+        if(pacingEnabled == ICSS_EMAC_ENABLE_PACING) {
+            numPacketsInLoop = 0;
+            /*Enable interrupts*/
+            if(pacingMode == ICSS_EMAC_INTR_PACING_MODE1) {
+                ICSS_EmacEnableRxInterrupt(icssEmacHandle);
+            }
+        }
+
+    }
+}
+/**
+ *  \name ICSS_EmacInterruptPacingISR
+ *  @brief ISR for Interrupt Pacing DM Timer
+ *
+ *  @param args arguments if any
+ *
+ *  @retval
+ *       void
+ *
+ */
+void ICSS_EmacInterruptPacingISR(void *args); /* for misra warning*/
+void ICSS_EmacInterruptPacingISR(void *args)
+{
+    ICSS_EmacHandle icssEmacHandle;
+    icssEmacHandle = (ICSS_EmacHandle)args;
+    ICSS_EmacEnableRxInterrupt(icssEmacHandle);
+}
+
+/**
+ *  @b Description
+ *  @n
+ *      API to queue a frame which has to be transmitted on the
+ *      specified port queue
+ *
+ *  @param[in]  txArg defined at @ref ICSS_EmacTxArgument
+ *  @param[in]  userArg custom Tx packet callback packet options only required for custom TxPacket implementations,
+                default to NULL when calling ICSS_EmacTxPacket which is default Tx Packet API
+ *  @retval     0 on scuess,  <0 on failure
+ */
+int32_t ICSS_EmacTxPacket(ICSS_EmacTxArgument *txArg, void* userArg)
+
+{
+    int32_t ret=-1;
+    const uint8_t*        macId;
+    uint8_t txPort, trigTx1, trigTx2;
+
+    ICSS_EmacHandle icssEmacHandle = txArg->icssEmacHandle;
+    uint8_t portNumber= txArg->portNumber;
+    uint8_t queuePriority = txArg->queuePriority;
+    uint16_t lengthOfPacket = txArg->lengthOfPacket;
+
+    
+    int32_t ret_val = 0;
+
+    macId = txArg->srcAddress;
+
+    if (portNumber == ICSS_EMAC_PORT_0)    /* special case to use MAC learning */
+    {
+        /* get the Port number from MAC tables.. */
+        txPort = findMAC(macId, ((ICSS_EmacObject*)(icssEmacHandle)->object)->macTablePtr);
+
+        switch (txPort)
+        {
+            case 0U: /* need to send on both ports */
+                trigTx1 = 1U;
+                trigTx2 = 1U;
+                break;
+            case 1U: /* ICSS_EMAC_PORT_1 */
+                trigTx1 = 1U;
+                trigTx2 = 0U;
+                break;
+            case 2U: /* ICSS_EMAC_PORT_2 */
+                trigTx1 = 0U;
+                trigTx2 = 1U;
+                break;
+            default:    /* ICSS_EMAC_PORT_0 */
+                trigTx1 = 1U;
+                trigTx2 = 0U;
+                break;
+        }
+        if(trigTx1 == 1U)
+        {
+            ret = ICSS_EmacTxPacketEnqueue(icssEmacHandle,
+                                           txArg->srcAddress,
+                                           ICSS_EMAC_PORT_1, 
+                                           queuePriority,
+                                           lengthOfPacket);
+        }
+        if(trigTx2 == 1U)
+        {
+            if (ret == 0) {
+                ICSS_EmacTxPacketEnqueue( icssEmacHandle,
+                                          txArg->srcAddress,
+                                          ICSS_EMAC_PORT_2,
+                                          queuePriority,
+                                          lengthOfPacket);
+            } else {
+                ret = ICSS_EmacTxPacketEnqueue( icssEmacHandle,
+                                                txArg->srcAddress,
+                                                ICSS_EMAC_PORT_2,
+                                                queuePriority,
+                                                lengthOfPacket);
+            }
+        }
+
+    }
+    else
+    {
+        ret = ICSS_EmacTxPacketEnqueue(icssEmacHandle,
+                                       txArg->srcAddress,
+                                       portNumber,
+                                       queuePriority,
+                                       lengthOfPacket);
+    }
+
+    if(ret == 0)
+    {
+        ret_val = 0;
+    }
+    else
+    {
+        ret_val = -1;
+    }
+
+    return(ret_val);
+}
+
+/* Local Functions */
+/**
+ *  @brief  API to copy a packet from DDR to Tx Queue memory on L3 and synchronize with
+ *  firmware
+ *
+ *  @param[in]  icssEmacHandle handle to ICSS_EMAC Instance.
+ *  @param[in]  srcAddress    Base address of the buffer where the frame to be transmitted resides
+ *  @param[in]  portNumber   Port on which frame has to be transmitted.
+ *                            Valid values are:
+                              1 == PORT1, 2 == PORT2
+ *  @param[in]  queuePriority    Queue number in which frame will be
+ *                               queued for transmission
+ *  @param[in] lengthOfPacket   length of the frame in bytes
+ *  @retval     0 on scuess,  <0 on failure
+ */
+int32_t ICSS_EmacTxPacketEnqueue (ICSS_EmacHandle icssEmacHandle,
+                                  const uint8_t* srcAddress,
+                                  uint8_t portNumber,
+                                  uint8_t queuePriority,
+                                  uint16_t lengthOfPacket)
+{
+    uint16_t buffer_offset_computed =0;
+    uint32_t buffer_des = 0;
+    uint16_t queue_wr_ptr =0;
+    uint16_t wrk_queue_wr_ptr =0;
+    uint16_t size = 0;
+    uint16_t queue_rd_ptr =0;
+    uint16_t num_of_bytes =0;
+    uint16_t new_packet_length =0;
+    uint32_t temp =0;
+    uint16_t i =0;
+    uint32_t collision_queue_selected =0;
+    uint16_t collision_status =0;
+    uint16_t col_queue_already_occupied =0;
+    uint16_t original_length_of_packet =0;
+    uint16_t packet_min_size_padding = 0;
+    uint16_t remaining_valid_frame_data_length =0;
+    uint8_t *macAddr;
+    uint32_t pruSharedMem = 0;
+    ICSS_EmacQueueParams *txQueue;
+    ICSS_EmacHostStatistics_t* hostStatPtr;
+    uint8_t linkStatus=0;
+
+    uint8_t emacMode=0;
+
+    uint32_t temp_addr = 0U;
+    if((((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->portMask == ICSS_EMAC_MODE_SWITCH)
+    {
+        emacMode =0;
+    }
+    else
+    {
+        emacMode =1U;
+    }
+
+    if(emacMode) { /*MAC Mode*/
+
+        if(ICSS_EMAC_PORT_1 == portNumber) {
+            pruSharedMem = (((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam0BaseAddr;
+        }
+        if(ICSS_EMAC_PORT_2 == portNumber) {
+            pruSharedMem = (((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr;
+        }
+        linkStatus = ((ICSS_EmacObject*)icssEmacHandle->object)->linkStatus[0];
+        hostStatPtr = (ICSS_EmacHostStatistics_t*)((((ICSS_EmacObject*)icssEmacHandle->object)->hostStat));
+    }
+    else
+    {
+        linkStatus = ((ICSS_EmacObject*)icssEmacHandle->object)->linkStatus[portNumber-1];
+        hostStatPtr = (ICSS_EmacHostStatistics_t*)((((ICSS_EmacObject*)icssEmacHandle->object)->hostStat));
+        hostStatPtr += (portNumber - 1);/*Switch mode. Points to correct structure depending on port*/
+    }
+
+    if((portNumber != ICSS_EMAC_PORT_1) && (portNumber != ICSS_EMAC_PORT_2))
+    {
+        hostStatPtr->txDroppedPackets++;
+        return ((int32_t)ICSS_EMAC_SWITCH_INVALID_PORT);
+    }
+    if((queuePriority < ICSS_EMAC_QUEUE1) || (queuePriority > ICSS_EMAC_QUEUE4))
+    {
+        hostStatPtr->txDroppedPackets++;
+        return ((int32_t)ICSS_EMAC_ERR_SWITCH_INVALID_PARAM);
+    }
+    if(lengthOfPacket > (int32_t)ICSS_EMAC_MAXMTU)
+    {    
+        hostStatPtr->txDroppedPackets++;
+        return ((int32_t)ICSS_EMAC_ERR_BADPACKET);
+    }
+    if(lengthOfPacket < ICSS_EMAC_MINMTU)
+    {    
+        hostStatPtr->txDroppedPackets++;
+        return ((int32_t)ICSS_EMAC_ERR_BADPACKET);
+    }
+
+    if(lengthOfPacket < ETHERNET_FRAME_SIZE_60)
+    {
+        original_length_of_packet = (uint16_t)lengthOfPacket;
+        packet_min_size_padding =1U;
+        lengthOfPacket = ETHERNET_FRAME_SIZE_60;
+    }
+    else
+    {
+        packet_min_size_padding = 0;
+    }
+
+    macAddr = (uint8_t*)srcAddress;
+
+    if(linkStatus == 0U)
+    {
+        hostStatPtr->txDroppedPackets++;
+        return ((int32_t)ICSS_EMAC_ERR_TX_NO_LINK);
+    }
+
+    ICSS_EmacPortParams *sPort;
+    sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[portNumber]);
+    if(emacMode == 0U) { /*Switch Mode*/
+
+         txQueue = &(sPort->queue[queuePriority]);
+        /* Check whether Queue is busy.If yes then put the packet in the collision Queue. Set the busy_s bit because Host is always a Slave. */
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + txQueue->queue_desc_offset + 4U);
+        temp =  HWREG(temp_addr);
+        collision_queue_selected =  (temp & 0x00000100U);  /* Check the "busy_m" bit */
+        if(collision_queue_selected != 0U)
+        {
+           num_of_collision_occured = num_of_collision_occured +1;
+           /* Queue is busy  .. put the packet in the collision Queue */
+           txQueue = &(sPort->queue[ICSS_EMAC_COLQUEUE]);
+            if(portNumber == ICSS_EMAC_PORT_1)
+            {
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + COLLISION_STATUS_ADDR + 1U);
+                col_queue_already_occupied = HWREGB(temp_addr);
+            }
+            else
+            {
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + COLLISION_STATUS_ADDR + 2U);
+                col_queue_already_occupied = HWREGB(temp_addr);
+            }
+            if(col_queue_already_occupied != 0)
+            {
+              hostStatPtr->txDroppedPackets++;
+              collision_pkt_dropped ++;
+              return ((int32_t)ICSS_EMAC_ERR_COLLISION_FAIL);   /*No space in collision queue */
+            }
+        }
+        else
+        {
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + txQueue->queue_desc_offset + 4U);
+            /* Queue is Not Busy .. Acquire the Queue by setting "busy_s" bit */
+            HWREGB(temp_addr) = 1; /* Set the "busy_s" bit */
+            /*Again check if host acquired the queue successfully by checking the busy_m bit */
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + txQueue->queue_desc_offset + 4U);
+            temp =  HWREG(temp_addr);
+            collision_queue_selected =  (temp & 0x00000100U);  /* Check the "busy_m" bit */
+            if(collision_queue_selected != 0U)
+            {
+                num_of_collision_occured = num_of_collision_occured +1;
+                temp_addr = ( (((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr+ txQueue->queue_desc_offset + 4U);
+                HWREGB(temp_addr) = 0; /* Clear the busy_s bit */
+                /* Queue is busy  .. put the packet in the collision Queue */
+                txQueue = &(sPort->queue[ICSS_EMAC_COLQUEUE]);
+            }
+        }
+    } else { /*MAC Mode*/
+        txQueue = &(sPort->queue[queuePriority]);
+        /* Queue is Not Busy .. Acquire the Queue by setting "busy_s" bit */
+        temp_addr = (pruSharedMem + txQueue->queue_desc_offset + 4U);
+        HWREGB(temp_addr) = 1U; /* Set the "busy_s" bit */
+
+    }
+    /*  Compute the buffer descriptor ..length is from bit 18 to 28 */
+    buffer_des = (((uint32_t)(lengthOfPacket)) << 18U);
+
+    if(emacMode == 0U) { /*Switch Mode*/
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + txQueue->queue_desc_offset);
+        /*  Read the write pointer from Queue descriptor */
+        temp =  HWREG(temp_addr);
+    } else {
+        temp_addr = (pruSharedMem + txQueue->queue_desc_offset);
+        temp =  HWREG(temp_addr);
+    }
+
+    queue_wr_ptr = ((uint16_t)(temp >> 16));
+    queue_rd_ptr = ((uint16_t)(temp & 0x0000ffffU));
+
+    wrk_queue_wr_ptr = (((uint16_t)(lengthOfPacket)) >> 5U);  /* Divide by 32 */
+    wrk_queue_wr_ptr = (wrk_queue_wr_ptr << 2);  /* Multiply by 4 ..as one descriptor represents 32 bytes and BD takes 4 bytes */
+    if((((uint32_t)(lengthOfPacket)) & 0x0000001fU) != 0U)
+    {
+         wrk_queue_wr_ptr = wrk_queue_wr_ptr + 4U;
+    }
+
+    /* Add to get the value of new queue write pointer */
+    wrk_queue_wr_ptr = wrk_queue_wr_ptr + queue_wr_ptr;
+    size = txQueue->queue_size;
+    /*Check if queue is full and there is an wrap around */
+    if(((queue_wr_ptr + 4U) % size) == 0U)
+    {
+        if(queue_rd_ptr == txQueue->buffer_desc_offset) /* Since queue is not starting from 0. */
+        {
+            txQueue->qStat.errCount++;
+            if(emacMode == 0U) { /*Switch Mode*/
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + txQueue->queue_desc_offset + 4U);
+                HWREGB(temp_addr) = 0;
+            } else {
+                temp_addr = (pruSharedMem + txQueue->queue_desc_offset + 4U);
+                HWREGB(temp_addr) = 0U;
+            }
+            hostStatPtr->txDroppedPackets++;
+            return ((int32_t)ICSS_EMAC_ERR_TX_OUT_OF_BD);   /* No space in queue */
+        }
+    }
+    /* Check if the Queue is already full */
+    if((queue_wr_ptr + 4U) == queue_rd_ptr)
+    {
+        txQueue->qStat.errCount++;
+        if(emacMode == 0U) { /*Switch Mode*/
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr+ txQueue->queue_desc_offset + 4U);
+            HWREGB(temp_addr) = 0;
+        } else {
+            temp_addr = (pruSharedMem + txQueue->queue_desc_offset + 4U);
+            HWREGB(temp_addr) = 0U;
+        }
+        hostStatPtr->txDroppedPackets++;
+        return ((int32_t)ICSS_EMAC_ERR_TX_OUT_OF_BD);       /* No space in queue */
+    }
+    /* Three cases arise between wr_ptr and rd_ptr */
+    if(queue_wr_ptr == queue_rd_ptr)
+    {
+        /*Check for wrap around */
+        if(wrk_queue_wr_ptr >=  size)
+        {
+            wrk_queue_wr_ptr = (wrk_queue_wr_ptr % size);
+            /*Add offset as queue doesn't start from 0. */
+            wrk_queue_wr_ptr = wrk_queue_wr_ptr + txQueue->buffer_desc_offset;
+        }
+    }
+    else if(queue_wr_ptr > queue_rd_ptr)
+    {
+        /*Check for wrap around */
+        if(wrk_queue_wr_ptr >=  size)
+        {
+            wrk_queue_wr_ptr = (wrk_queue_wr_ptr % size);
+            wrk_queue_wr_ptr = wrk_queue_wr_ptr + txQueue->buffer_desc_offset;
+            if(wrk_queue_wr_ptr >= queue_rd_ptr)
+            {
+                txQueue->qStat.errCount++;
+                if(emacMode == 0U) { /*Switch Mode*/
+                    temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + txQueue->queue_desc_offset + 4U);
+                    HWREGB(temp_addr) = 0;
+                } else {
+                    temp_addr = (pruSharedMem + txQueue->queue_desc_offset + 4U);
+                    HWREGB(temp_addr) = 0U;
+                }
+                hostStatPtr->txDroppedPackets++;
+                return ((int32_t)ICSS_EMAC_ERR_TX_OUT_OF_BD);      /* No space in queue */
+            }
+        }
+    }
+    else
+    {
+        if(wrk_queue_wr_ptr >= queue_rd_ptr)
+        {
+            txQueue->qStat.errCount++;
+            if(emacMode == 0U) { /*Switch Mode*/
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + txQueue->queue_desc_offset + 4U);
+                HWREGB(temp_addr) = 0;
+            } else {
+                temp_addr = (pruSharedMem + txQueue->queue_desc_offset + 4U);
+                HWREGB(temp_addr) = 0U;
+            }
+            hostStatPtr->txDroppedPackets++;
+            return ((int32_t)ICSS_EMAC_ERR_TX_OUT_OF_BD);                          /* No space in queue */
+        }
+    }
+    /* Compute the offset of buffer descriptor in ICSS shared RAM */
+    buffer_offset_computed = txQueue->buffer_offset + ((queue_wr_ptr - txQueue->buffer_desc_offset)*8U);    /* queue_wr_ptr points to currently available free buffer */
+
+    /* Check if queue wrap around has happened. If yes then data can't be stored sequentially. */
+    if( (wrk_queue_wr_ptr < queue_wr_ptr) &&  (wrk_queue_wr_ptr != txQueue->buffer_desc_offset))
+    {
+        num_of_bytes = (size - queue_wr_ptr);
+        num_of_bytes *= 8U;                    /* divide by 4 * 32! */
+        /* check if Padding has to be done. If yes then Pad with Zero's to reach the minimum size for the ethernet frame. */
+        if(packet_min_size_padding == 1U)
+        {
+            if( num_of_bytes <= original_length_of_packet)
+            {
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed));
+                memcpy((int32_t*)(temp_addr), (int32_t*) srcAddress, num_of_bytes);
+            }
+            else
+            {
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed));
+                /* Copy the valid packet data first and then Pad with zero's.  */
+                memcpy((int32_t*)(temp_addr), (int32_t*) srcAddress, original_length_of_packet);
+                /* Padd the remaining bytes with Zero's */
+                for(i=0; i< (num_of_bytes - original_length_of_packet); i++)
+                {
+                    temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr+ ((uint32_t)buffer_offset_computed) + original_length_of_packet + i);
+                    HWREGB(temp_addr) = 0;
+                }
+            }
+        }
+        else
+        {
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed));
+            memcpy((int32_t*)(temp_addr), (int32_t*) srcAddress, num_of_bytes);
+        }
+        new_packet_length = ((uint16_t)lengthOfPacket) - num_of_bytes;
+        srcAddress = srcAddress + num_of_bytes;
+
+        if(emacMode == 0U) { /*Switch Mode*/
+            if(collision_queue_selected != 0) {
+                buffer_offset_computed = buffer_offset_computed + num_of_bytes;
+            } else {
+                buffer_offset_computed = txQueue->buffer_offset;
+            }
+        } else { /*MAC Mode*/
+            buffer_offset_computed = txQueue->buffer_offset;
+        }
+
+        if( packet_min_size_padding == 1u)
+        {
+            if(    original_length_of_packet <= num_of_bytes)
+            {
+                /* Pad all the remaining bytes with Zero's */
+                for(i=0; i< new_packet_length; i++)
+                {
+                    temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed) + i);
+                    HWREGB(temp_addr) = 0;
+                }
+            }
+            else
+            {
+                /* Fill the frame data  */
+                remaining_valid_frame_data_length = (original_length_of_packet- num_of_bytes);
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed));
+                memcpy((int32_t*)(temp_addr),(int32_t*) srcAddress, remaining_valid_frame_data_length);
+                /*Pad the remaining bytes with Zero's */
+                for(i=0; i< (new_packet_length - remaining_valid_frame_data_length); i++)
+                {
+                    temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed) + remaining_valid_frame_data_length+ i);
+                    HWREGB(temp_addr) = 0;
+                }
+            }
+        }    
+        else
+        {
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed));
+            memcpy((int32_t*)(temp_addr),(int32_t*) srcAddress, new_packet_length);
+        }
+    }
+    else
+    {
+        if( packet_min_size_padding  == 1u)
+        {
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed));
+            memcpy((int32_t*)(temp_addr), (int32_t*)srcAddress, original_length_of_packet);
+            /* Padd the remaining bytes with Zero's */
+            for(i=0; i< (((uint16_t)lengthOfPacket) - original_length_of_packet); i++)
+            {
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed) + original_length_of_packet + i);
+                HWREGB(temp_addr) = 0;
+            }
+        }
+        else
+        {
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + ((uint32_t)buffer_offset_computed));
+            memcpy((int32_t*)(temp_addr), (int32_t*)srcAddress, (uint32_t)lengthOfPacket);
+        }
+    }
+    if(emacMode == 0U) { /*Switch Mode*/
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->sharedDataRamBaseAddr + ((uint32_t)queue_wr_ptr) );
+        HWREG(temp_addr) = buffer_des;
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + txQueue->queue_desc_offset +2U);
+        /* Write new wr_ptr in the queue descriptor */
+        HWREGH(temp_addr) = wrk_queue_wr_ptr;
+    } else {
+        temp_addr = (pruSharedMem + queue_wr_ptr );
+        HWREG(temp_addr) = buffer_des;
+        temp_addr = (pruSharedMem + txQueue->queue_desc_offset +2U);
+        HWREGH(temp_addr) = wrk_queue_wr_ptr;
+    }
+
+    txQueue->qStat.rawCount++;
+
+    if(emacMode == 0U) { /*Switch Mode*/
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + txQueue->queue_desc_offset + 4U);
+        /* Release the Queue. Clear the "busy_s" bit .. even if collision queue was selected then below line won't have any impact. */
+        HWREGB(temp_addr) = 0;
+    } else {
+        temp_addr = (pruSharedMem + txQueue->queue_desc_offset + 4U);
+        HWREGB(temp_addr) = 0U;
+    }
+
+    if(emacMode == 0U) { /*Switch Mode*/
+        /* If packet was put in collision queue then indiciate it to collision task */
+        if(collision_queue_selected != 0)
+        {
+            if(portNumber ==ICSS_EMAC_PORT_1)
+            {
+                collision_status = ((uint16_t)queuePriority);
+                collision_status = (collision_status << 1);
+                collision_status = (collision_status | 0x0001U);
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + COLLISION_STATUS_ADDR +1U);
+                HWREGB(temp_addr) = collision_status;
+            }
+            else
+            {
+                collision_status = ((uint16_t)queuePriority);
+                collision_status = (collision_status << 1);
+                collision_status = (collision_status | 0x0001U);
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + COLLISION_STATUS_ADDR + 2U);
+                HWREGB(temp_addr) = collision_status;
+            }
+        }
+    }
+
+    
+    if(emacMode == 0U) /*In Switch Mode both the statistics structures are in single handle.Depending on port update the corresponding structure*/
+    hostStatPtr += (portNumber - 1);
+    ICSS_EmacUpdateTxStats(macAddr,(uint32_t)lengthOfPacket, hostStatPtr);
+    return 0;
+}
+
+/**
+ *  @b Description
+ *  @n
+ *       API to retrieve the information about the received frame which
+ *       is then used to dequeue the frame from the host queues
+ *
+ *  @param[in]  icssEmacHandle handle to ICSS_EMAC Instance.
+ *  @param[out]  portNumber    Return pointer of port number where frame was received
+ *  @param[out]  queueNumber   Return pointer of host queue where the received frame is queued
+ *  @param[out]  pktProc       Return pointer of packet type
+
+ *  @retval     none
+ */
+int32_t ICSS_EmacRxPktInfo(ICSS_EmacHandle icssEmacHandle,
+                           int32_t* portNumber,
+                           int32_t* queueNumber,
+                                  int32_t* pktProc)
+
+{
+    uint16_t queue_rd_ptr;
+    uint16_t queue_wr_ptr;
+    uint32_t rd_buf_desc=0;
+    uint16_t rd_packet_length;
+    int32_t packet_found =0;
+    Queue *qDesc;
+    uint16_t shadow=0;
+    uint32_t rd_buffer_l3_addr;
+    uint16_t rd_buf_desc_num;
+    ICSS_EmacQueueParams *rxQueue;
+
+    uint8_t initPrioQueue = ICSS_EMAC_QUEUE1;
+    uint8_t finalPrioQueue = (uint8_t)ICSS_EMAC_QUEUE4;
+    uint8_t i= ICSS_EMAC_QUEUE1;
+
+    uint8_t emacMode=0;
+    uint32_t temp_addr = 0U;
+    uint32_t temp_var1 = 0U;
+    uint32_t temp_var2 = 0U;
+
+    ICSS_EmacPortParams *sPort;
+
+    switch((((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->portMask)
+    {
+        case ICSS_EMAC_MODE_SWITCH:
+            emacMode =0;
+            initPrioQueue = ICSS_EMAC_QUEUE1;
+            finalPrioQueue = (uint8_t)ICSS_EMAC_QUEUE4;
+            break;
+        case ICSS_EMAC_MODE_MAC1:
+            emacMode =1u;
+            initPrioQueue = ICSS_EMAC_QUEUE1;
+            finalPrioQueue= (uint8_t)ICSS_EMAC_QUEUE2;
+            break;
+        case ICSS_EMAC_MODE_MAC2:
+            emacMode =1u;
+            initPrioQueue = (uint8_t)ICSS_EMAC_QUEUE3;
+            finalPrioQueue= (uint8_t)ICSS_EMAC_QUEUE4;
+            break;
+        default:
+            break;
+    }
+
+    i=initPrioQueue;
+
+    while((packet_found == 0) && (i <= finalPrioQueue))
+    {
+
+        if(emacMode == 0U) { /*Switch Mode*/
+            temp_var1 = ((uint32_t)(i))*8U;
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + P0_QUEUE_DESC_OFFSET + temp_var1);
+            qDesc = (Queue *)(temp_addr);
+        } else {
+            temp_var1 = ((uint32_t)(i))*8U;
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->sharedDataRamBaseAddr + HOST_QUEUE_DESC_OFFSET + temp_var1);
+            qDesc = (Queue *)(temp_addr);
+        }
+        queue_wr_ptr = qDesc->wr_ptr;
+        queue_rd_ptr = qDesc->rd_ptr;
+
+        sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_0]);
+
+        if(qDesc->overflow_cnt > 0)
+        {
+            sPort->queue[i].qStat.errCount += qDesc->overflow_cnt;  /* increment missed packets to error counter */
+            qDesc->overflow_cnt = 0;    /* reset to zero as limited to 256 anyway */
+        }
+        if(queue_rd_ptr != queue_wr_ptr)
+        {
+            (*queueNumber) = i;
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->sharedDataRamBaseAddr + ((uint32_t)queue_rd_ptr));
+            rd_buf_desc = HWREG(temp_addr);
+            /* Take out the port number */
+            (*portNumber) = (0x00030000U & rd_buf_desc) >> 16U;
+            /* Get the length */
+            rd_packet_length = ((uint16_t)((0x1ffc0000U & rd_buf_desc) >> 18U));
+            packet_found = 1;
+
+           rxQueue = &(sPort->queue[i]);
+
+           if(emacMode == 0U) { /*Switch Mode*/
+               /* Determine the address of the first buffer descriptor from the rd_ptr */
+               /*Check if Packet was received in collision queue or not */
+               shadow = ((uint16_t)((rd_buf_desc & 0x00004000U) >> 14U));
+               if(shadow != 0)
+               {
+                 /* Pick the data from collision buffer's */
+                   rd_buffer_l3_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr+ P0_COL_BUFFER_OFFSET);
+               } else  {
+                   rd_buf_desc_num = (queue_rd_ptr - rxQueue->buffer_desc_offset) >> 2;
+                   temp_var1 = (((uint32_t)(rd_buf_desc_num)) * 32U);
+                   temp_var2 = (rxQueue->buffer_offset);
+                   rd_buffer_l3_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + temp_var1 + temp_var2);
+               }
+           } else {
+               rd_buf_desc_num = (queue_rd_ptr - rxQueue->buffer_desc_offset) >> 2;
+               temp_var1 = ((uint32_t)(rd_buf_desc_num)) * 32U;
+               temp_var2 = (rxQueue->buffer_offset);
+               rd_buffer_l3_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + temp_var1 + temp_var2);
+           }
+           *pktProc = PruSwitch((char *)rd_buffer_l3_addr);
+        }
+        i++;
+    }
+    /* Received IRQ but can't find the packet in any queue */
+    if(packet_found == 0)
+    {
+        rd_packet_length = 0;
+    }
+    return (int32_t)rd_packet_length;
+}
+
+/**
+ *  @b Description
+ *  @n
+ *      Retrieves a frame from a host queue and copies it
+ *           in the allocated stack buffer
+ *
+ *  @param[in]  rxArg defined at @ref ICSS_EmacRxArgument
+ *  @param[in]  userArg custom Rx packet callback packet options only required for custom RxPacket implementations,
+                default to NULL when calling ICSS_EmacRxPktGet which is default Tx Packet API
+ *  @retval     Length of the frame received in number of bytes or -1 on Failure
+ */
+int32_t ICSS_EmacRxPktGet(ICSS_EmacRxArgument *rxArg, void* userArg)
+
+{
+    uint16_t queue_rd_ptr;
+    uint16_t queue_wr_ptr;
+    uint16_t rd_buf_desc_num;
+    uint32_t rd_buf_desc=0;
+    uint16_t rd_packet_length;
+    uint32_t rd_buffer_l3_addr;
+    uint16_t size =0;
+    uint16_t update_rd_ptr=0;
+    uint16_t rx_num_of_bytes=0;
+    uint16_t new_size =0;
+    ICSS_EmacQueueParams *rxQueue;
+    Queue *qDesc;
+    uint16_t    shadow=0;
+
+    uint8_t* srcMacId;
+    uint8_t* destMacId;
+
+    uint16_t *typeProt;
+    uint16_t  typeProt1;
+    uint16_t  typeProt2;
+
+    uint8_t emacMode=0;
+
+    uint32_t temp_addr = 0U;
+    uint32_t temp_var1 = 0U;
+    uint32_t temp_var2 = 0U;
+
+    uint8_t ret_flag = 0U;
+    int32_t ret_val = 0;
+
+    ICSS_EmacHandle icssEmacHandle = rxArg->icssEmacHandle;
+    uint32_t  destAddress = rxArg->destAddress;
+    uint8_t queueNumber= rxArg->queueNumber;
+
+    
+    ICSS_EmacPortParams *sPort;
+    if((((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->portMask == ICSS_EMAC_MODE_SWITCH)
+    {
+        emacMode =0;
+    }
+    else
+    {
+        emacMode =1U;
+    }
+
+    HashTable_t *macTablePtr;
+    ICSS_EmacHostStatistics_t* hostStatPtr;
+
+    ICSS_EmacCallBackConfig* learningExcCallback;
+
+#ifdef SWITCH_DEBUG
+        genSeqOfEvents(RX_PACKET_GET);
+#endif
+
+    if(emacMode == 0U) { /*Switch Mode*/
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr+ P0_QUEUE_DESC_OFFSET + (((uint32_t)(queueNumber))*8U));
+        qDesc = (Queue *)(temp_addr);
+    } else {
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->sharedDataRamBaseAddr + HOST_QUEUE_DESC_OFFSET + (((uint32_t)(queueNumber))*8U));
+        qDesc = (Queue *)(temp_addr);
+    }
+    queue_wr_ptr = qDesc->wr_ptr;
+    queue_rd_ptr = qDesc->rd_ptr;
+    sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_0]);
+    if(qDesc->overflow_cnt > 0)
+    {
+        sPort->queue[queueNumber].qStat.errCount += qDesc->overflow_cnt;        /* increment missed packets to error counter */
+        qDesc->overflow_cnt = 0;
+        /* reset to zero as limited to 256 anyway */
+    }
+    temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->sharedDataRamBaseAddr + ((uint32_t)queue_rd_ptr));
+    rd_buf_desc = HWREG(temp_addr);
+    rxQueue = &(sPort->queue[queueNumber]);
+
+    if(emacMode == 0U) { /*Switch Mode*/
+        /* Determine the address of the first buffer descriptor from the rd_ptr */
+        /*Check if Packet was received in collision queue or not */
+        shadow = ((uint16_t)((rd_buf_desc & 0x00004000U) >> 14U));
+        if(shadow != 0)
+        {
+          /* Pick the data from collision buffer's */
+            rd_buffer_l3_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr+ P0_COL_BUFFER_OFFSET);
+        } else  {
+            rd_buf_desc_num = (queue_rd_ptr - rxQueue->buffer_desc_offset) >> 2;
+            temp_var1 = (((uint32_t)(rd_buf_desc_num)) * 32U);
+            temp_var2 = (rxQueue->buffer_offset);
+            rd_buffer_l3_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + temp_var1 + temp_var2);
+        }
+    } else {
+        rd_buf_desc_num = (queue_rd_ptr - rxQueue->buffer_desc_offset) >> 2;
+        temp_var1 = ((uint32_t)(rd_buf_desc_num)) * 32U;
+        temp_var2 = (rxQueue->buffer_offset);
+        rd_buffer_l3_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + temp_var1 + temp_var2);
+    }
+    /* Take out the port number - it may have changed */
+    rxArg->port = (0x00030000U & rd_buf_desc)>>16;
+
+    temp_addr = (rd_buffer_l3_addr + 6U);
+    srcMacId = (uint8_t*)(temp_addr);
+
+    destMacId = (uint8_t*)rd_buffer_l3_addr;
+
+
+    rd_packet_length = ((uint16_t)((0x1ffc0000U & rd_buf_desc) >> 18));
+
+    size = (rd_packet_length >>2);
+    if( (rd_packet_length & 0x00000003U) != 0U )
+    {
+        size = size + 1u;
+    }
+
+    /*Compute number of buffer desc required & update rd_ptr in queue */
+    update_rd_ptr = ((rd_packet_length >> 5U)*4U) + queue_rd_ptr;
+    if( (rd_packet_length & 0x0000001fU) != 0U) /* checks multiple of 32 else need to increment by 4 */
+    {
+        update_rd_ptr += 4U;
+    }
+    /*Check for wrap around */
+    if(update_rd_ptr >= rxQueue->queue_size)
+    {
+        update_rd_ptr = update_rd_ptr - (rxQueue->queue_size - rxQueue->buffer_desc_offset);
+    }
+    if(rd_packet_length <= ICSS_EMAC_MAXMTU)        /* make sure we do not have too big packets */
+    {
+
+        if((((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->learningEn) { /*Switch Mode*/
+
+            learningExcCallback = (((ICSS_EmacObject*)icssEmacHandle->object)->callBackHandle)->learningExCallBack;
+            macTablePtr = (HashTable_t*)(((ICSS_EmacObject*)icssEmacHandle->object)->macTablePtr);
+            updateHashTable(srcMacId, rxArg->port, macTablePtr,learningExcCallback);
+
+        }
+
+        /* Copy the data from switch buffers to DDR */
+        if( (update_rd_ptr < queue_rd_ptr) && (update_rd_ptr != rxQueue->buffer_desc_offset))
+        {
+            typeProt = (uint16_t*)rd_buffer_l3_addr + 6;
+            typeProt1 = ((uint16_t)((*typeProt) << 8U));
+            typeProt2 = ((uint16_t)((*typeProt) >> 8U));
+            typeProt1 = typeProt1 | typeProt2;
+            rx_num_of_bytes = (rxQueue->queue_size - queue_rd_ptr);
+            rx_num_of_bytes = (rx_num_of_bytes >> 2);
+            rx_num_of_bytes = (rx_num_of_bytes << 5);
+
+            memcpy((int32_t*)destAddress, (int32_t*)rd_buffer_l3_addr, rx_num_of_bytes);
+              destAddress = destAddress + rx_num_of_bytes;
+              new_size = rd_packet_length - rx_num_of_bytes;
+
+              if(emacMode == 0U) { /*Switch Mode*/
+                  if(shadow != 0) {
+                      rd_buffer_l3_addr = rd_buffer_l3_addr + rx_num_of_bytes;
+                  } else {
+                      rd_buffer_l3_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + rxQueue->buffer_offset);
+                  }
+              } else {
+                  rd_buffer_l3_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->l3OcmcBaseAddr + rxQueue->buffer_offset);
+              }
+
+              memcpy((int32_t*)destAddress, (int32_t*)rd_buffer_l3_addr, new_size);
+        }
+        else
+        {
+
+            memcpy((int32_t*)destAddress, (int32_t*)rd_buffer_l3_addr, rd_packet_length);
+            typeProt = (uint16_t*)destAddress + 6;
+            typeProt1 = ((uint16_t)((*typeProt) << 8U));
+            typeProt2 = ((uint16_t)((*typeProt) >> 8U));
+            typeProt1 = typeProt1 | typeProt2;
+        }
+    }
+    else  /* wrong packet size (exceeds ICSS_EMAC_MAXMTU)*/
+    {
+        rxQueue->qStat.errCount++;
+        ret_flag = 1U;
+        ret_val = -1;
+    }
+
+    if(ret_flag == 0U)
+    {
+        if(emacMode == 0U) { /*Switch Mode*/
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + P0_QUEUE_DESC_OFFSET + (((uint32_t)(queueNumber))*8U));
+            /* Write back to queue */
+            HWREGH(temp_addr) = update_rd_ptr;
+             /* Check if Host needs to change the wr_ptr for collision queue as well */
+            if(shadow != 0)
+            {
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + P0_COL_QUEUE_DESC_OFFSET);
+                Queue *qDescCol = (Queue *)(temp_addr);
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + P0_COL_QUEUE_DESC_OFFSET +2U);
+                /*Write back to collision queue desc */
+                HWREGH(temp_addr) = qDescCol->rd_ptr;
+                
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + COLLISION_STATUS_ADDR +3U);
+                HWREGH(temp_addr) = 0;
+
+            }
+        } else {
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->sharedDataRamBaseAddr + HOST_QUEUE_DESC_OFFSET + (((uint32_t)(queueNumber))*8U));
+            HWREGH(temp_addr) = update_rd_ptr;
+        }
+        rxQueue->qStat.rawCount++;
+
+        rxArg->more = 0;
+        if(emacMode == 0U) { /*Switch Mode*/
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + P0_QUEUE_DESC_OFFSET + (((uint32_t)(queueNumber))*8U));
+            /* get new pointer data in case new packets received in meantime - experimental.. */
+            qDesc = (Queue *)(temp_addr);
+        } else {
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->sharedDataRamBaseAddr + HOST_QUEUE_DESC_OFFSET + (((uint32_t)(queueNumber))*8U));
+            qDesc = (Queue *)(temp_addr);
+        }
+        queue_wr_ptr = qDesc->wr_ptr;
+
+        if(update_rd_ptr != queue_wr_ptr)
+        {
+            rxArg->more = 1;
+        }
+
+        hostStatPtr = (ICSS_EmacHostStatistics_t*)((((ICSS_EmacObject*)icssEmacHandle->object)->hostStat));
+        if(emacMode == 0U) /*In Switch Mode both the statistics structures are in single handle.Depending on port update the corresponding structure*/
+            hostStatPtr += (rxArg->port - 1);
+        ICSS_EmacUpdateRxStats(destMacId,rd_packet_length, typeProt1, hostStatPtr);
+
+        ret_val = (int32_t)rd_packet_length;
+    }
+    return (ret_val);
+}
+
+/**
+ *  @b Description
+ *  @n
+ *      Finds the maximum fill level of the queue in terms of 32 byte blocks.
+        For example, if there was only one 64 byte packet received when this
+        API is called then it would return value of 2.
+        It also returns number of times queue has overflown.
+ *
+ *  @param[in]  icssEmacHandle handle to ICSS_EMAC Instance.
+ *  @param[in]  portNumber    Port on which queue resides. Valid values are:
+                              0 == PORT0, 1 == PORT1, 2 == PORT2
+ *  @param[in]  queuePriority   Priority of the queue or queue number whose fill level has to be found
+ *  @param[in]  queueType   Rx/Tx Queue
+ *  @param[out]  queueOverflowCount    Number of times queue has overflown
+
+ *  @retval     The maximum fill level of the queue in terms of 32 byte blocks or
+ *              <0 if there was an error in the input parameters
+ */
+int32_t ICSS_EmacGetMaxQueueFillLevel(ICSS_EmacHandle icssEmacHandle,
+                                      int32_t portNumber, 
+                                      int32_t queuePriority, 
+                                      uint8_t queueType,
+                                      int32_t* queueOverflowCount)
+{
+    int32_t queueMaxFillLevel =0;
+    uint32_t temp_addr = 0U;
+    ICSS_EmacPortParams *sPort;
+
+    int32_t ret_val = 0;
+
+    if((portNumber != ICSS_EMAC_PORT_0) && 
+       (portNumber != ICSS_EMAC_PORT_1) &&
+       (portNumber != ICSS_EMAC_PORT_2))
+    {    
+        ret_val = ((int32_t)ICSS_EMAC_SWITCH_INVALID_PORT);
+    }
+    else
+    {
+       sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[portNumber]);
+        if((queuePriority < ICSS_EMAC_QUEUE1) || (queuePriority > ICSS_EMAC_QUEUE4))
+        {
+            ret_val = ((int32_t)ICSS_EMAC_ERR_SWITCH_INVALID_PARAM);
+        }
+        else
+        {
+            ICSS_EmacQueueParams *queue_local = &(sPort->queue[queuePriority]);
+
+            /*Read the max fill level for the queue */
+            if(ICSS_EMAC_MODE_SWITCH == (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->portMask) { /*Switch Mode*/
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + queue_local->queue_desc_offset + Q_MAX_FILL_LEVEL_OFFSET);
+                queueMaxFillLevel =  HWREGB(temp_addr);
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + queue_local->queue_desc_offset + Q_OVERFLOW_CNT_OFFSET);
+                *queueOverflowCount = HWREGB(temp_addr);
+            } else {
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->sharedDataRamBaseAddr + queue_local->queue_desc_offset + Q_MAX_FILL_LEVEL_OFFSET);
+                queueMaxFillLevel =  HWREGB(temp_addr);
+                temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->sharedDataRamBaseAddr+ queue_local->queue_desc_offset + Q_OVERFLOW_CNT_OFFSET);
+                *queueOverflowCount = HWREGB(temp_addr);
+            }
+            ret_val = queueMaxFillLevel;
+        }
+    }
+    return ret_val;
+}
+/**
+ *  \name ClearStatistics
+ *  @brief  Function to clear queue statistics
+ *
+ *  @param none
+ *  @retval none
+ */
+void ClearStatistics(ICSS_EmacHandle icssEmacHandle); /* for misra warning*/
+void ClearStatistics(ICSS_EmacHandle icssEmacHandle)
+{
+    ICSS_EmacPortParams *sPort;
+
+    int32_t i, j;
+    for (j=0; j<3; j++)
+    {
+        sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[j]);
+        sPort->errCount = 0;
+        sPort->rawCount = 0;
+        for (i=0; i<ICSS_EMAC_NUMQUEUES; i++)
+        {
+            sPort->queue[i].qStat.errCount = 0;
+            sPort->queue[i].qStat.rawCount = 0;
+        }
+    }
+}
+
+void ICSS_EmacHostInit(ICSS_EmacHandle icssEmacHandle)
+{
+    ICSS_EmacPortParams *sPort;
+
+    /* Initialize port 0*/
+    sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_0]);
+    sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset       = P0_Q1_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P0_Q1_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = HOST_QUEUE_DESC_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (HOST_QUEUE_1_SIZE << 2) + P0_Q1_BD_OFFSET;        /* really the end of Queue */
+
+    sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset       = P0_Q2_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P0_Q2_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = HOST_QUEUE_DESC_OFFSET + 8U;
+    sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (HOST_QUEUE_2_SIZE << 2) + P0_Q2_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset       = P0_Q3_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P0_Q3_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = HOST_QUEUE_DESC_OFFSET + 16U;
+    sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (HOST_QUEUE_3_SIZE << 2) + P0_Q3_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset       = P0_Q4_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P0_Q4_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = HOST_QUEUE_DESC_OFFSET + 24U;
+    sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (HOST_QUEUE_4_SIZE << 2) + P0_Q4_BD_OFFSET;
+
+}
+
+void ICSS_EmacMACInit(ICSS_EmacHandle icssEmacHandle, uint8_t portNum)
+{
+    ICSS_EmacPortParams *sPort;
+
+    if(((uint8_t)(ICSS_EMAC_PORT_1)) == portNum) {
+        sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_1]);
+       /* Initialize port 1*/
+        sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset       = P1_Q1_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P1_Q1_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (QUEUE_1_SIZE << 2) + P1_Q1_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset       = P1_Q2_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P1_Q2_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET + 8U;
+        sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (QUEUE_2_SIZE << 2) + P1_Q2_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset       = P1_Q3_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P1_Q3_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET + 16U;
+        sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (QUEUE_3_SIZE << 2) + P1_Q3_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset       = P1_Q4_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P1_Q4_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET + 24U;
+        sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (QUEUE_4_SIZE << 2) + P1_Q4_BD_OFFSET;
+    }
+
+    if(((uint8_t)(ICSS_EMAC_PORT_2)) == portNum) {
+        /* Initialize port 2*/
+        sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_2]);
+       sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset       = P2_Q1_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P2_Q1_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (QUEUE_1_SIZE << 2) + P2_Q1_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset       = P2_Q2_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P2_Q2_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET + 8U;
+        sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (QUEUE_2_SIZE << 2) + P2_Q2_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset       = P2_Q3_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P2_Q3_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET + 16U;
+        sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (QUEUE_3_SIZE << 2) + P2_Q3_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset       = P2_Q4_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P2_Q4_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET + 24U;
+        sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (QUEUE_4_SIZE << 2) + P2_Q4_BD_OFFSET;
+    }
+
+}
+
+int32_t ICSS_EmacPortInit(ICSS_EmacHandle icssEmacHandle); /* for misra warning*/
+int32_t ICSS_EmacPortInit(ICSS_EmacHandle icssEmacHandle)
+{
+    ICSS_EmacPortParams *sPort;
+    /* Clear counters */
+    ClearStatistics(icssEmacHandle);
+    /* Initialize port 0*/
+    sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_0]);
+    sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset       = P0_Q1_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P0_Q1_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = P0_QUEUE_DESC_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (HOST_QUEUE_1_SIZE << 2) + P0_Q1_BD_OFFSET;        /* really the end of Queue */
+
+    sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset       = P0_Q2_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P0_Q2_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = P0_QUEUE_DESC_OFFSET + 8U;
+    sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (HOST_QUEUE_2_SIZE << 2) + P0_Q2_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset       = P0_Q3_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P0_Q3_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = P0_QUEUE_DESC_OFFSET + 16U;
+    sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (HOST_QUEUE_3_SIZE << 2) + P0_Q3_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset       = P0_Q4_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P0_Q4_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = P0_QUEUE_DESC_OFFSET + 24U;
+    sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (HOST_QUEUE_4_SIZE << 2) + P0_Q4_BD_OFFSET;
+
+    /* Initialize port 1*/
+    sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_1]);
+   sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset       = P1_Q1_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P1_Q1_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = P1_QUEUE_DESC_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (QUEUE_1_SIZE << 2) + P1_Q1_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset       = P1_Q2_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P1_Q2_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = P1_QUEUE_DESC_OFFSET + 8U;
+    sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (QUEUE_2_SIZE << 2) + P1_Q2_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset       = P1_Q3_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P1_Q3_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = P1_QUEUE_DESC_OFFSET +16U;
+    sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (QUEUE_3_SIZE << 2) + P1_Q3_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset       = P1_Q4_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P1_Q4_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = P1_QUEUE_DESC_OFFSET +24U;
+    sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (QUEUE_4_SIZE << 2) + P1_Q4_BD_OFFSET;
+    
+    /*Collision Queue */
+    sPort->queue[ICSS_EMAC_COLQUEUE].buffer_offset           = P1_COL_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_COLQUEUE].buffer_desc_offset = P1_COL_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_COLQUEUE].queue_desc_offset  = P1_COL_QUEUE_DESC_OFFSET;
+    sPort->queue[ICSS_EMAC_COLQUEUE].queue_size         = (COLLISION_QUEUE_SIZE << 2) + P1_COL_BD_OFFSET;
+
+    /* Initialize port 2*/
+    sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_2]);
+    sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset       = P2_Q1_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P2_Q1_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = P2_QUEUE_DESC_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (QUEUE_1_SIZE << 2) + P2_Q1_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset       = P2_Q2_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P2_Q2_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = P2_QUEUE_DESC_OFFSET + 8U;
+    sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (QUEUE_2_SIZE << 2) + P2_Q2_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset       = P2_Q3_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P2_Q3_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = P2_QUEUE_DESC_OFFSET +16U;
+    sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (QUEUE_3_SIZE << 2) + P2_Q3_BD_OFFSET;
+
+    sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset       = P2_Q4_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P2_Q4_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = P2_QUEUE_DESC_OFFSET +24U;
+    sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (QUEUE_4_SIZE << 2) + P2_Q4_BD_OFFSET;
+    
+    /*Collision Queue */
+    sPort->queue[ICSS_EMAC_COLQUEUE].buffer_offset           = P2_COL_BUFFER_OFFSET;
+    sPort->queue[ICSS_EMAC_COLQUEUE].buffer_desc_offset = P2_COL_BD_OFFSET;
+    sPort->queue[ICSS_EMAC_COLQUEUE].queue_desc_offset  = P2_COL_QUEUE_DESC_OFFSET;
+    sPort->queue[ICSS_EMAC_COLQUEUE].queue_size         = (COLLISION_QUEUE_SIZE << 2) + P2_COL_BD_OFFSET;
+
+    return 0;
+}
+
+
+/**
+*  @internal
+*  @brief Function to re-initialize all Port Queue params
+*
+*  @param portNumber number of the port to flush
+*  @retval None
+*/
+void macFlush(ICSS_EmacHandle icssEmacHandle, Int32 portNumber); /* for misra warning*/
+void macFlush(ICSS_EmacHandle icssEmacHandle, Int32 portNumber)
+{
+    ICSS_EmacPortParams *sPort;
+
+    switch(portNumber) {
+        case ICSS_EMAC_PORT_1:
+        sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_1]);
+        /* Initialize port 1*/
+        sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset       = P1_Q1_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P1_Q1_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (QUEUE_1_SIZE << 2) + P1_Q1_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset       = P1_Q2_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P1_Q2_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET + 8U;
+        sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (QUEUE_2_SIZE << 2) + P1_Q2_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset       = P1_Q3_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P1_Q3_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET +16U;
+        sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (QUEUE_3_SIZE << 2) + P1_Q3_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset       = P1_Q4_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P1_Q4_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET +24U;
+        sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (QUEUE_4_SIZE << 2) + P1_Q4_BD_OFFSET;
+        break;
+
+    case ICSS_EMAC_PORT_2:
+        /* Initialize port 2*/
+        sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_2]);
+        sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset       = P2_Q1_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P2_Q1_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (QUEUE_1_SIZE << 2) + P2_Q1_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset       = P2_Q2_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P2_Q2_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET + 8U;
+        sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (QUEUE_2_SIZE << 2) + P2_Q2_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset       = P2_Q3_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P2_Q3_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET +16U;
+        sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (QUEUE_3_SIZE << 2) + P2_Q3_BD_OFFSET;
+
+        sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset       = P2_Q4_BUFFER_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P2_Q4_BD_OFFSET;
+        sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = PORT_QUEUE_DESC_OFFSET +24U;
+        sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (QUEUE_4_SIZE << 2) + P2_Q4_BD_OFFSET;
+        break;
+
+    default:
+        break;
+    }
+
+}
+
+/**
+ *  @b Description
+ *  @n
+ *      API Function to re-initialize all Port Queue params
+ * 
+ *  @param[in]  icssEmacHandle handle to ICSS_EMAC Instance
+ *  @param[in]  portNumber number of the port to flush
+ *  @retval None
+ */
+void ICSS_EmacPortFlush(ICSS_EmacHandle icssEmacHandle, int32_t portNumber)
+{
+  ICSS_EmacPortParams *sPort;
+
+  switch ( portNumber )
+  {
+    case ICSS_EMAC_PORT_1:
+      sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_1]);
+
+      sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset      = P1_Q1_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P1_Q1_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = P1_QUEUE_DESC_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (QUEUE_1_SIZE << 2) + P1_Q1_BD_OFFSET;
+
+      sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset      = P1_Q2_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P1_Q2_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = P1_QUEUE_DESC_OFFSET + 8U;
+      sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (QUEUE_2_SIZE << 2) + P1_Q2_BD_OFFSET;
+
+      sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset      = P1_Q3_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P1_Q3_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = P1_QUEUE_DESC_OFFSET +16U;
+      sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (QUEUE_3_SIZE << 2) + P1_Q3_BD_OFFSET;
+
+      sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset      = P1_Q4_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P1_Q4_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = P1_QUEUE_DESC_OFFSET +24U;
+      sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (QUEUE_4_SIZE << 2) + P1_Q4_BD_OFFSET;
+
+      sPort->queue[ICSS_EMAC_COLQUEUE].buffer_offset      = P1_COL_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_COLQUEUE].buffer_desc_offset = P1_COL_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_COLQUEUE].queue_desc_offset  = P1_COL_QUEUE_DESC_OFFSET;
+      sPort->queue[ICSS_EMAC_COLQUEUE].queue_size         = (COLLISION_QUEUE_SIZE << 2) + P1_COL_BD_OFFSET;
+
+      break;
+
+    case ICSS_EMAC_PORT_2:
+      sPort = &(((ICSS_EmacObject*)icssEmacHandle->object)->switchPort[ICSS_EMAC_PORT_2]);
+
+      sPort->queue[ICSS_EMAC_QUEUE1].buffer_offset      = P2_Q1_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE1].buffer_desc_offset = P2_Q1_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE1].queue_desc_offset  = P2_QUEUE_DESC_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE1].queue_size         = (QUEUE_1_SIZE << 2) + P2_Q1_BD_OFFSET;
+
+      sPort->queue[ICSS_EMAC_QUEUE2].buffer_offset      = P2_Q2_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE2].buffer_desc_offset = P2_Q2_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE2].queue_desc_offset  = P2_QUEUE_DESC_OFFSET + 8U;
+      sPort->queue[ICSS_EMAC_QUEUE2].queue_size         = (QUEUE_2_SIZE << 2) + P2_Q2_BD_OFFSET;
+
+      sPort->queue[ICSS_EMAC_QUEUE3].buffer_offset      = P2_Q3_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE3].buffer_desc_offset = P2_Q3_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE3].queue_desc_offset  = P2_QUEUE_DESC_OFFSET +16U;
+      sPort->queue[ICSS_EMAC_QUEUE3].queue_size         = (QUEUE_3_SIZE << 2) + P2_Q3_BD_OFFSET;
+
+      sPort->queue[ICSS_EMAC_QUEUE4].buffer_offset      = P2_Q4_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE4].buffer_desc_offset = P2_Q4_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_QUEUE4].queue_desc_offset  = P2_QUEUE_DESC_OFFSET +24U;
+      sPort->queue[ICSS_EMAC_QUEUE4].queue_size         = (QUEUE_4_SIZE << 2) + P2_Q4_BD_OFFSET;
+
+      sPort->queue[ICSS_EMAC_COLQUEUE].buffer_offset      = P2_COL_BUFFER_OFFSET;
+      sPort->queue[ICSS_EMAC_COLQUEUE].buffer_desc_offset = P2_COL_BD_OFFSET;
+      sPort->queue[ICSS_EMAC_COLQUEUE].queue_desc_offset  = P2_COL_QUEUE_DESC_OFFSET;
+      sPort->queue[ICSS_EMAC_COLQUEUE].queue_size         = (COLLISION_QUEUE_SIZE << 2) + P2_COL_BD_OFFSET;
+
+      break;
+
+    default:
+      break;
+  }
+}
+/**
+ *  @b Description
+ *  @n
+ *      API to register the hardware interrupt receive packet callback function
+ *
+ *  @param[in]  hwIntRx    hardware interrupt receive packet callback function
+ *  @retval     none
+ */
+void ICSS_EmacRegisterHwIntRx (ICSS_EmacHandle icssEmacHandle, ICSS_EmacCallBack hwIntRx)
+{
+    ((ICSS_EmacObject*)icssEmacHandle->object)->icssEmacHwIntRx = hwIntRx;
+}
+
+/**
+ *  @b Description
+ *  @n
+ *      API to register the hardware interrupt for Transmit packet complete by PRU-ICSS firmware
+ *
+ *  @param[in]  hwIntRx    hardware interrupt transmit packet complete callback function
+ *  @retval     none
+ */
+void ICSS_EmacRegisterHwIntTx(ICSS_EmacHandle icssEmacHandle, ICSS_EmacCallBack hwIntTx)
+{
+    ((ICSS_EmacObject*)icssEmacHandle->object)->icssEmacHwIntTx = hwIntTx;
+}
+int8_t ICSS_EmacOSInit(ICSS_EmacHandle icssEmacHandle)
+{
+    int8_t ret_val = 0;
+
+#ifdef ENABLE_TIMER_SUPPORT
+    uint8_t pacingMode;
+    TimerP_Params timerParams;
+#endif
+    SemaphoreP_Params semParams;
+
+    ICSS_EMAC_osalSemParamsInit(&semParams);
+    semParams.mode = SemaphoreP_Mode_BINARY;
+    semParams.name= "rxSemaphore";
+
+    ((ICSS_EmacObject*)icssEmacHandle->object)->rxSemaphoreHandle =  ICSS_EMAC_osalCreateBlockingLock(0,&semParams);
+    if(((ICSS_EmacObject*)icssEmacHandle->object)->rxSemaphoreHandle==NULL)
+    {
+        ret_val = -1;
+    }
+    else
+    {
+        ICSS_EMAC_osalSemParamsInit(&semParams);
+        semParams.mode = SemaphoreP_Mode_BINARY;
+        semParams.name= "txSemaphore";
+        ((ICSS_EmacObject*)icssEmacHandle->object)->txSemaphoreHandle =  ICSS_EMAC_osalCreateBlockingLock(0,&semParams);
+        if(((ICSS_EmacObject*)icssEmacHandle->object)->txSemaphoreHandle==NULL)
+        {
+            ret_val = -1;
+        }
+#ifdef ENABLE_TIMER_SUPPORT
+        else
+        {
+            pacingMode = (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->ICSS_EmacIntrPacingMode;
+            if(pacingMode == ICSS_EMAC_INTR_PACING_MODE2)
+            {
+                ICSS_EMAC_osalTimerParamsInit(&timerParams);
+
+                timerParams.period = DEFAULT_PACING_TIMER_VAL;
+                timerParams.arg = (void*)icssEmacHandle;
+                timerParams.freqHi = 0;
+                timerParams.freqLo = DMTIMER_SRC_CLK_FREQ;
+
+                /*Create Interrupt Pacing Timer*/
+                ICSS_EMAC_osalTimerCreate(DMTIMER4_ID, (TimerP_Fxn)ICSS_EmacInterruptPacingISR, &timerParams);
+
+                if (pacingTimerHandle == NULL) {
+                    ret_val = -1;
+                }
+            }
+        }
+#endif
+    }
+    return ret_val;
+}
+/**
+* @internal
+* @brief Function to delete Rx task (to receive packet)
+*
+* @param none
+*
+* @retval Success -   0
+*         Error   -   <0
+*/
+int8_t ICSS_EmacOSDeInit(ICSS_EmacHandle icssEmacHandle)
+{
+    ICSS_EMAC_osalDeleteBlockingLock(((ICSS_EmacObject*)icssEmacHandle->object)->rxSemaphoreHandle);
+    return 0;
+}
+
+void ICSS_EmacAddProtocolToList(uint16_t protocolType);   /* for misra warning*/
+void ICSS_EmacAddProtocolToList(uint16_t protocolType)
+{
+    if(MAX_NUM_PROTOCOL_IMPLEMENTED > numImplementedProtocols) {
+        protocol_impl[numImplementedProtocols] =  protocolType;
+        numImplementedProtocols++;
+    }
+}
+
+void ICSS_EmacUpdatePhyStatus(uint8_t portNum,ICSS_EmacHandle icssEmacHandle);  /* for misra warning*/
+void ICSS_EmacUpdatePhyStatus(uint8_t portNum,ICSS_EmacHandle icssEmacHandle) 
+{
+
+    volatile uint8_t *portStatusPtr=NULL;
+    volatile uint8_t portStatus = 0;
+    uint8_t linkStatus=0;
+    volatile uint32_t *phySpeedStatusPtr=NULL;
+    uint8_t index=0;
+    uint16_t phyStat=0;
+    uint8_t duplexity=1U;
+    uint16_t regStatus=0;
+
+    uint32_t temp_addr = 0U;
+
+    if(ICSS_EMAC_MODE_SWITCH == (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->portMask)
+    {
+        index= portNum-1U;
+    }
+    else
+    {
+        index= 0;
+    }
+
+    linkStatus = ((ICSS_EmacObject*)icssEmacHandle->object)->linkStatus[index];
+
+    if(portNum == ((uint8_t)(ICSS_EMAC_PORT_1))) {
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam0BaseAddr + PHY_SPEED_OFFSET);
+        phySpeedStatusPtr = (uint32_t*)(temp_addr);
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam0BaseAddr + PORT_STATUS_OFFSET);
+        portStatusPtr = (uint8_t*)(temp_addr);
+    }
+
+    if(portNum == ((uint8_t)(ICSS_EMAC_PORT_2))) {
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + PHY_SPEED_OFFSET);
+        phySpeedStatusPtr = (uint32_t*)(temp_addr);
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->dataRam1BaseAddr + PORT_STATUS_OFFSET);
+        portStatusPtr = (uint8_t*)(temp_addr);
+    }
+
+    if(linkStatus)
+    {
+            CSL_MDIO_phyRegRead((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs,
+                                               (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->phyAddr[index], TLKPHY_PHYSTS_REG, &regStatus);
+            if (regStatus & TLK_SPEED_STATUS) /*Speed is 10*/
+            {
+                if (regStatus & TLK_DUPLEX_STATUS)
+                {
+                    phyStat = PHY_CONFIG_10FD;
+                }
+                else
+                {
+                    phyStat =  PHY_CONFIG_10HD;
+                }
+            }
+            else/*Speed is 100*/
+            {
+                if (regStatus & TLK_DUPLEX_STATUS)
+                {
+                    phyStat =  PHY_CONFIG_100FD;
+                }
+                else
+                {
+                    phyStat = PHY_CONFIG_100HD;
+                }
+        }
+
+        if(phySpeedStatusPtr != NULL)
+        {
+            switch(phyStat)
+            {
+                case PHY_CONFIG_100FD:
+                    *(phySpeedStatusPtr) = Hundread_Mbps;
+                    duplexity=1u;
+                    break;
+                case PHY_CONFIG_100HD:
+                    *(phySpeedStatusPtr) = Hundread_Mbps;
+                    duplexity=0;
+                    break;
+                case PHY_CONFIG_10FD:
+                    *(phySpeedStatusPtr) = Ten_Mbps;
+                    duplexity=1u;
+                    break;
+                case PHY_CONFIG_10HD:
+                    *(phySpeedStatusPtr) = Ten_Mbps;
+                    duplexity=0;
+                    break;
+                default:
+                    *(phySpeedStatusPtr) = Hundread_Mbps;
+                    duplexity=1u;    
+                    break;
+            }
+        }
+        if((((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->halfDuplexEnable)
+        {
+            /*set flags for HD*/
+            if(duplexity == 0U) {
+                portStatus |= PORT_IS_HD_MASK;
+            } else
+            {
+                portStatus &= ~(PORT_IS_HD_MASK);
+            }
+        }
+        /*Set Link Up Flag*/
+        portStatus |= PORT_LINK_MASK;
+
+} 
+    else
+    {
+        /*Clear Link Up Flag*/
+        portStatus &= ~(PORT_LINK_MASK);
+    }
+
+    if(portStatusPtr != NULL)
+    {
+        /*write back*/
+        *(portStatusPtr) = portStatus;
+    }
+}
+/**
+* @brief Link change status interrupt for Port 0 and Port 1
+*         calls a user callback if defined to provide link info to stack
+*
+* @param arg
+*
+* @retval none
+*/
+void ICSS_EmacLinkISR(void* arg) {
+
+    volatile uint32_t linkStatus;
+    volatile uint32_t *intStatusPtr;
+    ICSSEMAC_IoctlCmd ioctlParams;
+    uint8_t ioctlvalue = 0;
+    ICSS_EmacHandle icssEmacHandle = (ICSS_EmacHandle)arg;
+
+    uint32_t temp_addr = 0U;
+
+    temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->prussIntcRegs + CSL_ICSSINTC_SECR1);
+    /*Find out which port it is*/
+    intStatusPtr = (uint32_t*)(temp_addr);
+
+    if(LINK0_PRU_EVT_MASK & *intStatusPtr) { /**Link 0 Port event*/
+        linkStatus = ICSS_EmacPhyLinkStatusGet((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs, 
+                                                                 (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->phyAddr[0],
+                                                                 100U);
+        ((ICSS_EmacObject*)icssEmacHandle->object)->linkStatus[0]=(uint8_t)linkStatus;
+
+        /*Update flags in memory*/
+        ICSS_EmacUpdatePhyStatus((uint8_t)ICSS_EMAC_PORT_1, icssEmacHandle);
+
+        if(linkStatus) {
+            ioctlvalue = ICSS_EMAC_IOCTL_PORT_CTRL_ENABLE;
+            ioctlParams.ioctlVal = &ioctlvalue;
+            ICSS_EmacIoctl(icssEmacHandle, ICSS_EMAC_IOCTL_PORT_CTRL, (uint8_t)ICSS_EMAC_PORT_1, (void*)&ioctlParams);
+        } else {
+            ioctlvalue = ICSS_EMAC_IOCTL_PORT_CTRL_DISABLE;
+            ioctlParams.ioctlVal = &ioctlvalue;
+            ICSS_EmacIoctl(icssEmacHandle, ICSS_EMAC_IOCTL_PORT_CTRL, (uint8_t)ICSS_EMAC_PORT_1, (void*)&ioctlParams);
+        }
+
+        /*Protocol specific processing*/
+        if(((ICSS_EmacObject*)icssEmacHandle->object)->port0ISRCall != NULL) {
+           ((ICSS_EmacObject*)icssEmacHandle->object)->port0ISRCall((void *)linkStatus,((ICSS_EmacObject*)icssEmacHandle->object)->port0ISRUser);
+        }
+        
+        temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs + ICSS_MDIO_LINKINT_RAW_MASK_OFFSET);
+        /*clear interrupt in MDIO*/
+        HWREG(temp_addr) = 0x01;
+
+        /*clear PRU-ICSS INTC interrupt*/
+        *intStatusPtr = LINK0_PRU_EVT_MASK;
+    } else {
+        if(LINK1_PRU_EVT_MASK & *intStatusPtr) { /**Link 1 Port event*/
+            if(ICSS_EMAC_MODE_SWITCH != ((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg->portMask) {
+                linkStatus = ICSS_EmacPhyLinkStatusGet((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs,
+                                                                    (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->phyAddr[0],
+                                                                     100U);
+                ((ICSS_EmacObject*)icssEmacHandle->object)->linkStatus[0]=(uint8_t)linkStatus;
+            } else {
+                linkStatus = ICSS_EmacPhyLinkStatusGet((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs,
+                                                                   (((ICSS_EmacObject*)icssEmacHandle->object)->emacInitcfg)->phyAddr[1],
+                                                                                100U);
+                ((ICSS_EmacObject*)icssEmacHandle->object)->linkStatus[ICSS_EMAC_PORT_2-1]=(uint8_t)linkStatus;
+            }
+
+
+            /*Update flags in memory*/
+            ICSS_EmacUpdatePhyStatus((uint8_t)ICSS_EMAC_PORT_2, icssEmacHandle);
+
+            if(linkStatus) {
+                ioctlvalue = ICSS_EMAC_IOCTL_PORT_CTRL_ENABLE;
+                ioctlParams.ioctlVal = &ioctlvalue;
+                ICSS_EmacIoctl(icssEmacHandle, ICSS_EMAC_IOCTL_PORT_CTRL, (uint8_t)ICSS_EMAC_PORT_2, (void*)&ioctlParams);
+            } else {
+                ioctlvalue = ICSS_EMAC_IOCTL_PORT_CTRL_DISABLE;
+                ioctlParams.ioctlVal = &ioctlvalue;
+                ICSS_EmacIoctl(icssEmacHandle, ICSS_EMAC_IOCTL_PORT_CTRL, (uint8_t)ICSS_EMAC_PORT_2, (void*)&ioctlParams);
+            }
+
+            if(((ICSS_EmacObject*)icssEmacHandle->object)->port1ISRCall != NULL) {
+               ((ICSS_EmacObject*)icssEmacHandle->object)->port1ISRCall((void *)linkStatus,((ICSS_EmacObject*)icssEmacHandle->object)->port1ISRUser);
+            }
+
+            temp_addr = ((((ICSS_EmacHwAttrs*)icssEmacHandle->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs + ICSS_MDIO_LINKINT_RAW_MASK_OFFSET);
+            /*clear interrupt in MDIO*/
+            HWREG(temp_addr) = 0x02;
+
+            /*clear PRU-ICSS INTC interrupt*/
+            *intStatusPtr = LINK1_PRU_EVT_MASK;
+        }
+    }
+}
+
+/**
+* @brief Callback function to process protocol specific handler for link status ISR for Port 0
+*
+* @param callBack    Callback function pointer
+* @param userArg    user specific parameter
+*
+* @retval none
+*/
+void ICSS_EmacRegisterPort0ISRCallback(ICSS_EmacHandle icssEmacHandle, ICSS_EmacCallBack callBack, void *userArg)
+{
+   ((ICSS_EmacObject*)icssEmacHandle->object)->port0ISRCall = callBack;
+   ((ICSS_EmacObject*)icssEmacHandle->object)->port0ISRUser = userArg;
+}
+
+/**
+* @brief Callback function to process protocol specific handler for link status ISR for Port 1
+*
+* @param callBack    Callback function pointer
+* @param userArg    user specific parameter
+*
+* @retval none
+*/
+void ICSS_EmacRegisterPort1ISRCallback(ICSS_EmacHandle icssEmacHandle, ICSS_EmacCallBack callBack, void *userArg)
+{
+   ((ICSS_EmacObject*)icssEmacHandle->object)->port1ISRCall = callBack;
+   ((ICSS_EmacObject*)icssEmacHandle->object)->port1ISRUser = userArg;
+}
+
+
+
+/**
+* @brief Function to status of Phy Link
+*
+* @param mdioBaseAddr       mdio subsystem base address
+* @param phyAddr            physical address
+* @param retries            retry count
+*
+* @retval 1 if phy link up, 0 phy link down
+*/
+uint32_t ICSS_EmacPhyLinkStatusGet(uint32_t mdioBaseAddr,
+                              uint32_t phyAddr,
+                              volatile uint32_t retries)
+{
+    volatile uint16_t linkStatus;
+    uint32_t ret_val = FALSE_VAL;
+    retries++;
+    while (retries)
+    {
+        /* First read the BSR of the PHY */
+        CSL_MDIO_phyRegRead(mdioBaseAddr, phyAddr, PHY_BSR, (uint16_t*)&linkStatus);
+
+        if(linkStatus & PHY_LINK_STATUS)
+        {
+            ret_val = TRUE_VAL;
+            break;
+        }
+
+        retries--;
+    }
+
+    return ret_val;
+}
+/**
+ *  \name ICSS_EMacOsTxTaskFnc
+ *  @brief
+ *      Function which pends on Tx semaphore.Invokes registered Tx Callback function
+ *
+ *  @param a0 arg 1
+ *  @param a1 arg 2
+ *
+ *  @retval none
+ *
+ */
+void ICSS_EMacOsTxTaskFnc(uint32_t a0, uint32_t a1)
+{
+    ICSS_EmacHandle icssEmacHandle;
+    icssEmacHandle = (ICSS_EmacHandle)a0;
+
+    while(1)
+    {
+        ICSS_EMAC_osalPendLock(((ICSS_EmacObject*)icssEmacHandle->object)->txSemaphoreHandle, SemaphoreP_WAIT_FOREVER);
+        ((ICSS_EmacObject*)icssEmacHandle->object)->icssEmacHwIntTx(icssEmacHandle,NULL);
+    }
+}
diff --git a/ipu1/icss_emacDrv.h b/ipu1/icss_emacDrv.h
new file mode 100644 (file)
index 0000000..a2bac7d
--- /dev/null
@@ -0,0 +1,689 @@
+/**
+ *   @file  icss_emacDrv.h
+ *   @brief
+ *      Include file for ICSS_EMAC RX/TX functions and queue structures
+ */
+
+/* Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 
+*
+*   Redistribution and use in source and binary forms, with or without 
+*   modification, are permitted provided that the following conditions 
+*   are met:
+*
+*     Redistributions of source code must retain the above copyright 
+*     notice, this list of conditions and the following disclaimer.
+*
+*     Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in the 
+*     documentation and/or other materials provided with the   
+*     distribution.
+*
+*     Neither the name of Texas Instruments Incorporated nor the names of
+*     its contributors may be used to endorse or promote products derived
+*     from this software without specific prior written permission.
+*
+*   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+*   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+*   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+*   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+*   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+*   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+*   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+*   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+*   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+*   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+*   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+
+
+#ifndef ICSS_EMACDRV__H
+#define ICSS_EMACDRV__H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <ti/csl/hw_types.h>
+
+
+#include <ti/drv/pruss/pruicss.h>
+#include <ti/drv/icss_emac/icss_emacDrv_Def.h>
+
+#include <ti/drv/icss_emac/icss_emacCommon.h>
+#include <ti/drv/icss_emac/icss_emacLearning.h>
+#include <ti/drv/icss_emac/icss_emacFwInit.h>
+#include <ti/drv/icss_emac/icss_emacStatistics.h>
+#include <ti/drv/icss_emac/icss_emacStormControl.h>
+#include <ti/drv/icss_emac/icss_emac_osal.h>
+
+#include <ti/drv/icss_emac/src/phy.h>
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+#define PKT_PROC_NONE           0
+#define PKT_PROC_GOOSE          1
+
+#define PKT_PROC_PTP            3
+#define PKT_PROC_SV             4
+#define PKT_PROC_MPU            5
+
+/**
+ *  \defgroup   ErrCodes    STANDARD ERROR CODES
+ *  @{
+ */
+/** Internal functions return error codes */
+#define ICSS_EMAC_SWITCH_INSTANCE_CODE                        (0u)
+/**< Switch Instance Code                                              */
+#define ICSS_EMAC_SWITCH_ERROR_BASE                           (0x200001Fu)
+/**< Switch Error Base                                              */
+#define ICSS_EMAC_SWITCH_ERROR_CODE                           ((ICSS_EMAC_SWITCH_ERROR_BASE | ((ICSS_EMAC_SWITCH_INSTANCE_CODE) << 16)))
+/**< Switch Error Code                                              */
+#define ICSS_EMAC_SWITCH_ERROR_INFO                           (ICSS_EMAC_SWITCH_ERROR_CODE)
+/**< Switch Error/Informational                                              */
+#define ICSS_EMAC_SWITCH_ERROR_WARNING                        (ICSS_EMAC_SWITCH_ERROR_CODE | 0x10000000u)
+/**< Switch Error/Warning                                              */
+#define ICSS_EMAC_SWITCH_ERROR_MINOR                          (ICSS_EMAC_SWITCH_ERROR_CODE | 0x20000000u)
+/**< Switch Error Minor                                              */
+#define ICSS_EMAC_SWITCH_ERROR_MAJOR                          (ICSS_EMAC_SWITCH_ERROR_CODE | 0x30000000u)
+/**< Switch Error Major                                              */
+#define ICSS_EMAC_SWITCH_ERROR_CRITICAL                       (ICSS_EMAC_SWITCH_ERROR_CODE | 0x40000000u)
+/**< Switch Error Critical                                              */
+
+/**  Success code */
+#define ICSS_EMAC_SWITCH_SUCCESS                              0u
+
+/**  Error codes */
+#define ICSS_EMAC_ERR_DEV_ALREADY_INSTANTIATED(instID)  (0x30000000u + ICSS_EMAC_SWITCH_ERROR_BASE + ((instId) << 16) )
+/**< Device with same instance ID already created. */
+#define ICSS_EMAC_ERR_DEV_NOT_INSTANTIATED              (ICSS_EMAC_SWITCH_ERROR_MAJOR + 1u)
+/**< Device is not instantiated yet.                                        */
+#define ICSS_EMAC_ERR_SWITCH_INVALID_PARAM                            (ICSS_EMAC_SWITCH_ERROR_MAJOR + 2u)
+/**< Function or calling parameter is invalid                               */
+#define ICSS_EMAC_ERR_CH_INVALID                        (ICSS_EMAC_SWITCH_ERROR_CRITICAL + 3u)
+/**< Channel number invalid                                                 */
+#define ICSS_EMAC_ERR_CH_ALREADY_INIT                   (ICSS_EMAC_SWITCH_ERROR_MAJOR + 4u)
+/**< Channel already initialized and setup                                  */
+#define ICSS_EMAC_ERR_TX_CH_ALREADY_CLOSED              (ICSS_EMAC_SWITCH_ERROR_MAJOR + 5u)
+/**< Tx Channel already  closed. Channel close failed                       */
+#define ICSS_EMAC_ERR_TX_CH_NOT_OPEN                   (ICSS_EMAC_SWITCH_ERROR_MAJOR + 6u)
+/**< Tx Channel not open.                                                   */
+#define ICSS_EMAC_ERR_TX_NO_LINK                       (ICSS_EMAC_SWITCH_ERROR_MAJOR + 7u)
+/**< Tx Link not up.                                                        */
+#define ICSS_EMAC_ERR_TX_OUT_OF_BD                     (ICSS_EMAC_SWITCH_ERROR_MAJOR + 8u)
+/**< Tx ran out of Buffer descriptors to use.                               */
+#define ICSS_EMAC_ERR_RX_CH_INVALID                    (ICSS_EMAC_SWITCH_ERROR_CRITICAL + 9u)
+/**< Rx Channel invalid number.                                             */
+#define ICSS_EMAC_ERR_RX_CH_ALREADY_INIT               (ICSS_EMAC_SWITCH_ERROR_MAJOR + 10u)
+/**< Rx Channel already setup.                                              */
+#define ICSS_EMAC_ERR_RX_CH_ALREADY_CLOSED             (ICSS_EMAC_SWITCH_ERROR_MAJOR + 11u)
+/**< Rx Channel already closed. Channel close failed.                       */
+#define ICSS_EMAC_ERR_RX_CH_NOT_OPEN                   (ICSS_EMAC_SWITCH_ERROR_MAJOR + 12u)
+/**< Rx Channel not open yet.                                               */
+#define ICSS_EMAC_ERR_DEV_ALREADY_CREATED              (ICSS_EMAC_SWITCH_ERROR_MAJOR + 13u)
+/**< EMAC device already created.                                           */
+#define ICSS_EMAC_ERR_DEV_NOT_OPEN                     (ICSS_EMAC_SWITCH_ERROR_MAJOR + 14u)
+/**< Device is not open or not ready                                        */
+#define ICSS_EMAC_ERR_DEV_ALREADY_CLOSED               (ICSS_EMAC_SWITCH_ERROR_MAJOR + 15u)
+/**< Device close failed. Device already closed.                            */
+#define ICSS_EMAC_ERR_DEV_ALREADY_OPEN                 (ICSS_EMAC_SWITCH_ERROR_MAJOR + 16u)
+/**< Device open failed. Device already open.                               */
+#define ICSS_EMAC_ERR_RX_BUFFER_ALLOC_FAIL             (ICSS_EMAC_SWITCH_ERROR_CRITICAL +17u)
+/**< Rx Buffer Descriptor allocation failed.                                */
+#define ICSS_EMAC_SWITCH_INTERNAL_FAILURE                     (ICSS_EMAC_SWITCH_ERROR_MAJOR + 18u)
+/**< EMAC Internal failure.                                                 */
+#define ICSS_EMAC_SWITCH_VLAN_UNAWARE_MODE          (ICSS_EMAC_SWITCH_ERROR_MAJOR + 19u)
+/**< VLAN support not enabled in EMAC                                       */
+#define ICSS_EMAC_SWITCH_ALE_TABLE_FULL             (ICSS_EMAC_SWITCH_ERROR_MAJOR + 20u)
+/**< ALE Table full.                                               */
+#define ICSS_EMAC_SWITCH_ADDR_NOTFOUND              (ICSS_EMAC_SWITCH_ERROR_MAJOR + 21u)
+/**< Multicast/Unicast/OUI Address not found in ALE.                        */
+#define ICSS_EMAC_SWITCH_INVALID_VLANID             (ICSS_EMAC_SWITCH_ERROR_MAJOR + 22u)
+/**< Invalid VLAN Id.                                                       */
+#define ICSS_EMAC_SWITCH_INVALID_PORT               (ICSS_EMAC_SWITCH_ERROR_MAJOR + 23u)
+/**< Invalid Port Specified.                                                */
+#define ICSS_EMAC_SWITCH_BD_ALLOC_FAIL              (ICSS_EMAC_SWITCH_ERROR_MAJOR + 24u)
+/**< Buffer Descriptor Allocation failure. OOM                              */
+#define ICSS_EMAC_ERR_BADPACKET                        (ICSS_EMAC_SWITCH_ERROR_MAJOR + 25u)
+/**< Supplied packet was invalid  */
+#define ICSS_EMAC_ERR_COLLISION_FAIL                   (ICSS_EMAC_SWITCH_ERROR_MAJOR + 26u)
+/**< Collision queue was full                             */
+#define ICSS_EMAC_ERR_MACFATAL                         (ICSS_EMAC_SWITCH_ERROR_CRITICAL + 26u)
+/**< Fatal Error - EMACClose() required                                    */
+/* @} */
+
+/**Dual MAC Mode. Both Ports Enabled  */
+#define ICSS_EMAC_MODE_DUALMAC   (4U)
+/**witch Mode  */
+#define ICSS_EMAC_MODE_SWITCH    (3U)
+/**Single EMAC Mode. Port 1 Enabled  */
+#define ICSS_EMAC_MODE_MAC1      (1U)
+/**Single EMAC Mode. Port 2 Enabled  */
+#define ICSS_EMAC_MODE_MAC2      (2U)
+
+/** Number of Ports in a single ICSS  */
+#define MAX_PORT_NUMBER     2
+
+/**Total Queues available*/
+#define ICSS_EMAC_NUMQUEUES (5)
+/**Priority Queue 1*/
+#define ICSS_EMAC_QUEUE1 (0)
+/**Priority Queue 2*/
+#define ICSS_EMAC_QUEUE2 (1)
+/**Priority Queue 3*/
+#define ICSS_EMAC_QUEUE3 (2)
+/**Priority Queue 4*/
+#define ICSS_EMAC_QUEUE4 (3)
+/**Collision Queue*/
+#define ICSS_EMAC_COLQUEUE (4)
+
+
+/*
+*  @brief     ICSS EMAC Init Configuration Structure
+*/
+typedef struct {
+    /** Phy address of the ports.For mac each handle will have single port only
+    *   And Two for Switch handle
+    */
+    uint32_t phyAddr[MAX_PORT_NUMBER];
+    /** Flag to enable Half duplex capability. Firmware support also is required to
+    *  enable the functionality
+    */
+    uint8_t halfDuplexEnable;
+    /** Flag to enable Interrupt pacing */
+    uint8_t enableIntrPacing;
+    /** Number of packets threshold for Pacing Mode1 */
+    uint16_t pacingThreshold;
+    /** Queue Priority separation for RT and NRT packets
+    *  If packets are in Queue <=ethPrioQueue, they will be forwarded to NRT callback
+    *  and others to RT callback
+    */
+    uint8_t ethPrioQueue;
+    /** Flag to enable learning. Not applicable for Mac mode */
+    uint8_t learningEn;
+    /**Port Mask. Indication to LLD which ports to be used
+    * Valid values:ICSS_EMAC_MODE_SWITCH,ICSS_EMAC_MODE_MAC1,ICSS_EMAC_MODE_MAC1
+    */
+    uint8_t portMask;
+    /**Rx interrupt number*/
+    uint8_t rxIntNum;
+    /**Link interrupt number*/
+    uint8_t linkIntNum;
+    /**Tx completion interrupt number*/
+    uint8_t txIntNum;
+    /**Macid to be used for the interface*/
+    uint8_t* macId;
+    /**Pacing mode to be used(MODE1/MODE2)*/
+    uint8_t ICSS_EmacIntrPacingMode;
+} ICSS_EmacInitConfig;
+
+#define ICSSEMAC_InitConfig ICSS_EmacInitConfig
+
+
+/**
+ * @brief Queue Statistics
+ */
+typedef struct {
+    /**queue raw count*/
+    uint32_t rawCount;
+    /**queue error count*/
+    uint32_t errCount;
+} ICSS_EmacQueueStats;
+
+
+/**
+ * @brief Queue Parameters
+ */
+typedef struct queParams {
+    /**Queue statistics*/
+    ICSS_EmacQueueStats  qStat;
+    /**buffer  offset*/
+    uint16_t    buffer_offset;
+    /**buffer descriptor offset*/
+    uint16_t    buffer_desc_offset;
+    /**queue descriptor offset*/
+    uint16_t    queue_desc_offset;
+    /**queue size*/
+    uint16_t    queue_size;
+} ICSS_EmacQueueParams;
+
+/**
+ * @brief Port parameters
+ */
+typedef struct {
+    /**pointer to PTCP packet mem*/
+    uint8_t*            ptcpPktBuff;
+    /**statistics   - raw*/
+    uint32_t            rawCount;
+    /**Error count*/
+    uint32_t            errCount;
+    /**Queues per port*/
+    ICSS_EmacQueueParams        queue[ICSS_EMAC_NUMQUEUES];
+} ICSS_EmacPortParams;
+
+/*
+*  @brief     ICSSEMAC_Object
+*             Handle containing pointers to all modules as well as Initialization Config
+*/
+typedef struct ICSS_EmacObject_s {
+    /*! PRUICSS Handle details where the EMAC driver will be based on       */
+    PRUICSS_Handle            pruIcssHandle;
+    /*! Pointer to initial configuration structure                          */
+    ICSS_EmacInitConfig       *emacInitcfg;
+    /*! Mac Table Pointer for Learning module. Not applicable for Emac mode */
+    HashTable_t               *macTablePtr;
+    /*! Pointer All Driver specific Callback  structure                     */
+    ICSS_EmacCallBackObject   *callBackHandle;
+    /*! Pointer to  Emac driver Firmware statistics structure               */
+    void                      *pruStat;
+    /*! Pointer to Emac Driver host statistics structure                    */
+    void                      *hostStat;
+    /*! Pointer to Storm Prevention structure */
+    void                      *stormPrevPtr;
+    /*! Rx Task Handle for the emac instance.Required for receiving packets */
+    void                      *rxTaskHandle;
+    /*! Tx Task Handle for the emac instance.Required for notification of Trasnmit Complete indication from  PRUICSS firmware */
+    void                      *txTaskHandle;
+    /*! Rx Semaphore Handle for the emac instance.Required for receiving packets */
+    void                      *rxSemaphoreHandle;
+    /*! Tx Complete Semaphore Handle for the emac instance.Required for notification of Trasnmit Complete indication from  PRUICSS firmware */
+    void                      *txSemaphoreHandle;
+    /*! Rx interrupt handler */
+    void                      *rxintHandle;
+    /*! Link interrupt handler */
+    void                      *linkintHandle;
+
+    /*! Tx Complete interrupt handler */
+    void                      *txintHandle;
+    
+    /*! Pointer to store any data from High Level Driver  */
+    void                      *pvtInfo;
+    /*! Link status for the ports */
+    uint8_t                   linkStatus[MAX_PORT_NUMBER];
+
+    ICSS_EmacCallBack port0ISRCall;
+    ICSS_EmacCallBack port1ISRCall;
+
+    ICSS_EmacCallBack icssEmacHwIntRx;
+    ICSS_EmacCallBack icssEmacHwIntTx;
+    void *port0ISRUser;
+    void *port1ISRUser;
+    ICSS_EmacPortParams switchPort[3];
+} ICSS_EmacObject;
+
+/* For backward compatibility */
+#define ICSSEMAC_Object ICSS_EmacObject
+/**
+ * @brief Handle containing base addresses for all memories and modules
+ */
+typedef struct ICSS_EmacHwAttrs_s {
+    ICSS_EmacBaseAddressHandle_T emacBaseAddrCfg;
+}ICSS_EmacHwAttrs;
+/* For backward compatibility */
+#define ICSSEMAC_HwAttrs ICSS_EmacHwAttrs
+
+/**
+ * @brief Base EMAC handle containing pointers to all modules required for driver to work
+ */
+typedef struct ICSS_EmacConfig_s {
+    /*! Pointer to a driver specific data object */
+    void                   *object;
+
+    /*! Pointer to a driver specific hardware attributes structure */
+    void          const    *hwAttrs;
+
+} ICSS_EmacConfig;
+
+/**
+ * @brief Rx packet processing information block that needs to passed into  call to ICSS_EmacRxPktGet
+ */
+typedef struct
+{
+    ICSS_EmacHandle icssEmacHandle; /*! handle to ICSS_EMAC Instance*/
+    uint32_t destAddress; /*! Base address of data buffer where received frame has to be stored */
+    uint8_t queueNumber;    /*!Receive queue from which frame has to be copied */
+    uint8_t port;   /*!Returns port number on which frame was received */
+    uint32_t more;  /*!Returns more which is set to 1 if there are more frames in the queue */
+} ICSS_EmacRxArgument;
+
+/**
+ * @brief Tx packet processing information block that needs to passed into  call to ICSS_EmacTxPacket
+ */
+typedef struct
+{
+    ICSS_EmacHandle icssEmacHandle; /*! handle to ICSS_EMAC Instance*/
+    const uint8_t *srcAddress;  /*! Base address of the buffer where the frame to be transmitted resides */
+    uint8_t portNumber; /*!  Port on which frame has to be transmitted */
+    uint8_t queuePriority;  /*! Queue number in which frame will be  queued for transmission */
+    uint16_t lengthOfPacket;    /*! length of the frame in bytes */
+} ICSS_EmacTxArgument;
+
+/* For backward compatibility */
+#define ICSSEMAC_Config ICSS_EmacConfig
+
+/**
+* @brief Enum for enableIntrPacing
+*/
+typedef enum {
+       ICSS_EMAC_ENABLE_PACING = 0,            /**< Interrupt pacing enabled*/
+       ICSS_EMAC_DISABLE_PACING                        /**< Interrupt pacing disabled*/
+} intrPacing;
+
+/**
+* @brief Enum for ICSS_EmacIntrPacingMode
+*/
+typedef enum {
+       ICSS_EMAC_INTR_PACING_MODE1 = 0,    /**< Frame Count based Interrupt pacing*/
+       ICSS_EMAC_INTR_PACING_MODE2         /**< Timer based Interrupt pacing*/
+} ICSS_EmacIntrPacingMode_e;
+
+
+
+
+/**Maximum Valid size (incl header + VLAN TAG..., no CRC)*/
+#define ICSS_EMAC_MAXMTU  (1518U)
+/**Minimum Valid size ( DA + SA + Ethertype)*/
+#define ICSS_EMAC_MINMTU  (14)
+
+/**
+ *  @def  ICSS_EMAC_PORT_0
+ *        Used to specify host side port
+ */
+#define ICSS_EMAC_PORT_0 (0)
+
+/**
+ *  @def  ICSS_EMAC_PORT_1
+ *        Used to specify physical port 1 MII 0 (tx)
+ */
+#define ICSS_EMAC_PORT_1 (1)
+
+/**
+ *  @def  ICSS_EMAC_PORT_2
+ *        Used to specify physical port 2 MII 1 (tx)
+ */
+#define ICSS_EMAC_PORT_2 (2)
+
+
+/**
+* @def MAX_NUM_PROTOCOL_IMPLEMENTED
+*       Max Number of protocols
+*/
+#define MAX_NUM_PROTOCOL_IMPLEMENTED   (50U)
+/**
+* @def NUM_PROTOCOLS_IMPLEMENTED
+*      Number of protocols supported
+*/
+#define NUM_PROTOCOLS_IMPLEMENTED  (2U)
+/**
+* @def IP4_PROT_TYPE
+*      IP4 Protcol type
+*/
+#define IP4_PROT_TYPE  (0x800)
+/**
+* @def ARP_PROT_TYPE
+*      ARP protocol type
+*/
+#define ARP_PROT_TYPE  (0x806)
+
+
+/**
+ *  @b Description
+ *  @n
+ *      Receive frame interrupt service routine
+ *
+ *  @param[in]  args parameter list to interrupt service routine
+ *  @retval     none
+ */
+void ICSS_EmacRxInterruptHandler(void *args);
+
+
+
+/**
+ *  @b Description
+ *  @n
+ *      Transmit complete frame interrupt service routine
+ *
+ *  @param[in]  args parameter list to interrupt service routine
+ *  @retval     none
+ */
+void ICSS_EmacTxInterruptHandler(void *args);
+
+
+
+/**
+* @brief Link change status interrupt for Port 0 and Port 1
+*         calls a user callback if defined to provide link info to stack
+*
+* @param arg
+*
+* @retval none
+*/
+void ICSS_EmacLinkISR(void* arg);
+
+/**
+ *  @b Description
+ *  @n
+ *      Retrieves a frame from a host queue and copies it
+ *           in the allocated stack buffer
+ *
+ *  @param[in]  rxArg defined at @ref ICSS_EmacRxArgument
+ *  @param[in]  userArg custom Rx packet callback packet options only required for custom RxPacket implementations,
+                default to NULL when calling ICSS_EmacRxPktGet which is default Tx Packet API
+ *  @retval     Length of the frame received in number of bytes or -1 on Failure
+ */
+int32_t ICSS_EmacRxPktGet(ICSS_EmacRxArgument *rxArg, void* userArg);
+
+
+/**
+ *  @b Description
+ *  @n
+ *      Finds the maximum fill level of the queue in terms of 32 byte blocks.
+        For example, if there was only one 64 byte packet received when this
+        API is called then it would return value of 2.
+        It also returns number of times queue has overflown.
+ *
+ *  @param[in]  icssEmacHandle handle to ICSS_EMAC Instance.
+ *  @param[in]  portNumber    Port on which queue resides. Valid values are:
+                              0 == PORT0, 1 == PORT1, 2 == PORT2
+ *  @param[in]  queuePriority   Priority of the queue or queue number whose fill level has to be found
+ *  @param[in]  queueType   Rx/Tx Queue
+ *  @param[out]  queueOverflowCount    Number of times queue has overflown
+
+ *  @retval     The maximum fill level of the queue in terms of 32 byte blocks or
+ *              <0 if there was an error in the input parameters
+ */
+int32_t ICSS_EmacGetMaxQueueFillLevel(ICSS_EmacHandle icssEmacHandle,int32_t portNumber, int32_t queuePriority,uint8_t queueType, int32_t* queueOverflowCount);
+
+/**
+ *  @b Description
+ *  @n
+ *      API to register the hardware interrupt receive packet callback function
+ *
+ *  @param[in]  hwIntRx    hardware interrupt receive packet callback function
+ *  @retval     none
+ */
+void ICSS_EmacRegisterHwIntRx (ICSS_EmacHandle icssEmacHandle, ICSS_EmacCallBack hwIntRx);
+
+/**
+ *  @b Description
+ *  @n
+ *       API to retrieve the information about the received frame which
+ *       is then used to dequeue the frame from the host queues
+ *
+ *  @param[in]  icssEmacHandle handle to ICSS_EMAC Instance.
+ *  @param[out]  portNumber    Return pointer of port number where frame was received
+ *  @param[out]  queueNumber   Return pointer of host queue where the received frame is queued
+ *  @param[ou]   pktProc       Return pointer of packet type
+ *  @retval     none
+ */
+int32_t ICSS_EmacRxPktInfo(ICSS_EmacHandle icssEmacHandle,
+                           int32_t* portNumber,
+                           int32_t* queueNumber,
+                           int32_t* pktProc);
+/**
+ *  @b Description
+ *  @n
+ *      API to queue a frame which has to be transmitted on the
+ *      specified port queue
+ *
+ *  @param[in]  txArg defined at @ref ICSS_EmacTxArgument
+ *  @param[in]  userArg custom Tx packet callback packet options only required for custom TxPacket implementations,
+                default to NULL when calling ICSS_EmacTxPacket which is default Tx Packet API
+ *  @retval     0 on scuess,  <0 on failure
+ */
+int32_t ICSS_EmacTxPacket(ICSS_EmacTxArgument *txArg, void* userArg);
+
+
+
+
+/* Local Functions */
+/** @brief  API to copy a packet from DDR to Tx Queue memory on L3 and synchronize with
+ *  firmware
+ *  @internal
+ *  @param[in]  icssEmacHandle handle to ICSS_EMAC Instance.
+ *  @param[in]  srcAddress    Base address of the buffer where the frame to be transmitted resides
+ *  @param[in]  portNumber   Port on which frame has to be transmitted.
+ *                            Valid values are:
+                              1 == PORT1, 2 == PORT2
+ *  @param[in]  queuePriority    Queue number in which frame will be
+ *                               queued for transmission
+ *  @param[in] lengthOfPacket   length of the frame in bytes
+ *  @retval     0 on scuess,  <0 on failure
+ */
+int32_t ICSS_EmacTxPacketEnqueue (ICSS_EmacHandle icssEmacHandle,
+                                  const uint8_t* srcAddress,
+                                  uint8_t portNumber,
+                                  uint8_t queuePriority,
+                                  uint16_t lengthOfPacket);
+/**
+ *  @brief  Task to enable copying of Rx data from queues to DDR. This is a function that calls
+ *  another function to empty the queues
+ *  @internal
+ *  @param[in]  a0 Generic argument
+ *  @param[in]  a1    Generic argument
+ *  @retval     none
+ */
+void ICSS_EMacOsRxTaskFnc(uint32_t a0, uint32_t a1);
+
+
+/**
+ *  @brief  Task to enable receiving Indication of transmit packet complete by PRU-ICSS firmware. 
+ *  @internal
+ *  @param[in]  a0 Generic argument
+ *  @param[in]  a1    Generic argument
+ *  @retval     none
+ */
+void ICSS_EMacOsTxTaskFnc(uint32_t a0, uint32_t a1);
+
+
+/**
+ *  @brief Function to initialize all Port Queue params
+ *  @internal
+ *  @retval 0 on success
+ */
+int32_t ICSS_EmacPortInit(ICSS_EmacHandle icssEmacHandle);
+
+/**
+ *  @brief Function to initialize Host Port Queue params
+ *  @internal
+ *  @param icssEmacHandle pointer to ICSS EMAC handle
+ *  @retval 0 on success
+ */
+void ICSS_EmacHostInit(ICSS_EmacHandle icssEmacHandle);
+
+/**
+ *  @brief Function to initialize MAC Port Queue params
+ *  @internal
+ *  @param portNum Port number
+ *  @retval 0 on success
+ */
+void ICSS_EmacMACInit(ICSS_EmacHandle icssEmacHandle, uint8_t portNum);
+/**
+ *  @brief Function to add Ether Type to approved list of protocols
+ *  @internal
+ *  @param icssEmacHandle pointer to ICSS EMAC handle
+ *  @param protocolType 16 bit value indicating protocol type. IEEE format
+ *  @retval 0 on success
+ */
+void addProtocolToList(uint16_t protocolType);
+/**
+ *  @brief Function to delete Rx semaphore and Task
+ *  @internal
+ *  @param icssEmacHandle pointer to ICSS EMAC handle
+ *  @retval 0 on success
+ */
+int8_t ICSS_EmacOSDeInit(ICSS_EmacHandle icssEmacHandle);
+/**
+
+ *  @brief Function to initialize Rx semaphore and Task
+ *  @internal
+ *  @param icssEmacHandle pointer to ICSS EMAC handle
+ *  @retval 0 on success
+ */
+int8_t ICSS_EmacOSInit(ICSS_EmacHandle icssEmacHandle);
+
+/**
+* @brief Callback function to process protocol specific handler for link status ISR
+* @param icssEmacHandle pointer to ICSS EMAC handle
+* @param callBack      Callback function pointer
+* @param userArg       user specific parameter
+*
+* @retval none
+*/
+void ICSS_EmacRegisterPort0ISRCallback(ICSS_EmacHandle icssEmacHandle, ICSS_EmacCallBack callBack, void *userArg);
+/**
+* @brief Callback function to process protocol specific handler for link status ISR
+*
+* @param icssEmacHandle pointer to ICSS EMAC handle
+* @param callBack      Callback function pointer
+* @param userArg       user specific parameter
+*
+* @retval none
+*/
+void ICSS_EmacRegisterPort1ISRCallback(ICSS_EmacHandle icssEmacHandle, ICSS_EmacCallBack callBack, void *userArg);
+
+
+/**
+* @brief Function to status of Phy Link
+*
+* @param mdioBaseAddr       mdio subsystem base address
+* @param phyAddr            physical address
+* @param retries            retry count
+*
+* @retval 1 if phy link up, 0 phy link down
+*/
+uint32_t ICSS_EmacPhyLinkStatusGet(uint32_t mdioBaseAddr,
+                                     uint32_t phyAddr,
+                                     volatile uint32_t retries);
+
+
+/**
+ *  @b Description
+ *  @n
+ *      API to register the hardware interrupt for Transmit packet complete by PRU-ICSS firmware
+ *
+ *  @param[in]  hwIntRx    hardware interrupt transmit packet complete callback function
+ *  @retval     none
+ */
+void ICSS_EmacRegisterHwIntTx( ICSS_EmacHandle icssEmacHandle, ICSS_EmacCallBack hwIntTx);
+
+
+/**
+ *  @b Description
+ *  @n
+ *      API Function to re-initialize all Port Queue params
+ * 
+ *  @param[in]  icssEmacHandle handle to ICSS_EMAC Instance
+ *  @param[in]  portNumber number of the port to flush
+ *  @retval None
+ */
+void ICSS_EmacPortFlush(ICSS_EmacHandle icssEmacHandle, int32_t portNumber);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ICSS_EMACDRV_H_ */
diff --git a/ipu1/makefile b/ipu1/makefile
new file mode 100644 (file)
index 0000000..9f578fb
--- /dev/null
@@ -0,0 +1,151 @@
+#
+#  Copyright (c) 2012-2016 Texas Instruments Incorporated - http://www.ti.com
+#  All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#
+#  *  Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#
+#  *  Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  *  Neither the name of Texas Instruments Incorporated nor the names of
+#     its contributors may be used to endorse or promote products derived
+#     from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+#  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+#  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+#  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+#  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+#  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+#  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+#  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+#  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+#  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+#  ======== makefile ========
+#
+
+EXBASE = ..
+include $(EXBASE)/products.mak
+
+srcs = MainIpu1.c Server.c PktProcEng.c icss_emacDrv.c PktSwitch.c
+objs = $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.oem4,$(srcs)))
+CONFIG = bin/$(PROFILE)/configuro
+
+PKGPATH := $(BIOS_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(IPC_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(XDC_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(PDK_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(CSL_INSTALL_DIR)/
+
+-include $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.oem4.dep,$(srcs)))
+
+.PRECIOUS: %/compiler.opt %/linker.cmd
+
+all: debug release
+
+debug:
+       $(MAKE) PROFILE=debug PROCLIST="$(PROCLIST)" server_ipu1.x
+
+release:
+       $(MAKE) PROFILE=release PROCLIST="$(PROCLIST)" server_ipu1.x
+
+server_ipu1.x: bin/$(PROFILE)/server_ipu1.xem4
+bin/$(PROFILE)/server_ipu1.xem4: $(objs) $(libs) $(CONFIG)/linker.cmd
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(LD) $(LDFLAGS) -o $@ $(objs) \
+            $(addprefix -l ,$(libs)) $(CONFIG)/linker.cmd $(LDLIBS)
+
+bin/$(PROFILE)/obj/%.oem4: %.c $(CONFIG)/compiler.opt
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(CC) $(CPPFLAGS) $(CFLAGS) --output_file=$@ -fc $<
+
+%/linker.cmd %/compiler.opt: $(CONFIG)/.config ;
+$(CONFIG)/.config: Ipu1.cfg ../shared/config.bld
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(XDC_INSTALL_DIR)/xs --xdcpath="$(subst +,;,$(PKGPATH))" \
+            xdc.tools.configuro -o $(CONFIG) \
+            -t ti.targets.arm.elf.M4 \
+            -c $(ti.targets.arm.elf.M4) \
+            -p ti.platforms.evmDRA7XX:ipu1 \
+            -b ../shared/config.bld -r $(PROFILE) \
+            --cfgArgs "{ configBld: \"../shared/config.bld\" }" \
+            Ipu1.cfg
+       @$(ECHO) "" > $@
+
+install:
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       @$(MKDIR) $(EXEC_DIR)/debug
+       $(CP) bin/debug/server_ipu1.xem4 $(EXEC_DIR)/debug
+       @$(MKDIR) $(EXEC_DIR)/release
+       $(CP) bin/release/server_ipu1.xem4 $(EXEC_DIR)/release
+
+help:
+       @$(ECHO) "make                   # build executable"
+       @$(ECHO) "make clean             # clean everything"
+
+clean::
+       $(RMDIR) bin
+
+#  ======== install validation ========
+ifeq (install,$(MAKECMDGOALS))
+ifeq (,$(EXEC_DIR))
+$(error must specify EXEC_DIR)
+endif
+endif
+
+#  ======== toolchain macros ========
+CGTOOLS = $(ti.targets.arm.elf.M4)
+
+CC = $(CGTOOLS)/bin/armcl -c
+LD = $(CGTOOLS)/bin/armcl -z
+
+CPPFLAGS =
+CFLAGS = -DSOC_AM572x -qq -pdsw225 -ppd=$@.dep -ppa $(CCPROFILE_$(PROFILE)) -@$(CONFIG)/compiler.opt -I.
+
+# entry point is set to an aligned address so that IPC can load the slave
+LDFLAGS = -w -q -u _c_int00 -c -m $(@D)/obj/$(@F).map
+LDLIBS = -l $(CGTOOLS)/lib/libc.a
+
+CCPROFILE_debug = -D_DEBUG_=1 --symdebug:dwarf
+CCPROFILE_release = -O2
+#CCPROFILE_release = -o4 -mv7m4 --abi=eabi --float_support=vfplib
+
+#  ======== standard macros ========
+ifneq (,$(wildcard $(XDC_INSTALL_DIR)/xdc.exe))
+    # use these on Windows
+    CP      = $(XDC_INSTALL_DIR)/bin/cp
+    ECHO    = $(XDC_INSTALL_DIR)/bin/echo
+    MKDIR   = $(XDC_INSTALL_DIR)/bin/mkdir -p
+    RM      = $(XDC_INSTALL_DIR)/bin/rm -f
+    RMDIR   = $(XDC_INSTALL_DIR)/bin/rm -rf
+else
+    # use these on Linux
+    CP      = cp
+    ECHO    = echo
+    MKDIR   = mkdir -p
+    RM      = rm -f
+    RMDIR   = rm -rf
+endif
+
+#  ======== create output directories ========
+ifneq (clean,$(MAKECMDGOALS))
+ifneq (,$(PROFILE))
+ifeq (,$(wildcard bin/$(PROFILE)/obj))
+    $(shell $(MKDIR) -p bin/$(PROFILE)/obj)
+endif
+endif
+endif
diff --git a/ipu1/rsc_table_vayu_ipu.h b/ipu1/rsc_table_vayu_ipu.h
new file mode 100644 (file)
index 0000000..91c9c63
--- /dev/null
@@ -0,0 +1,381 @@
+/*
+ * Copyright (c) 2012-2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== rsc_table_vayu_ipu.h ========
+ *
+ *  Define the resource table entries for all IPU cores. This will be
+ *  incorporated into corresponding base images, and used by the remoteproc
+ *  on the host-side to allocated/reserve resources.
+ *
+ */
+
+#ifndef _RSC_TABLE_VAYU_IPU_H_
+#define _RSC_TABLE_VAYU_IPU_H_
+
+#define VAYU_IPU_1
+#include "rsc_types.h"
+
+/* IPU Memory Map */
+#define L4_DRA7XX_BASE          0x4A000000
+
+/* L4_CFG & L4_WKUP */
+#define L4_PERIPHERAL_L4CFG     (L4_DRA7XX_BASE)
+#define IPU_PERIPHERAL_L4CFG    0x6A000000
+
+#define L4_PERIPHERAL_L4PER1    0x48000000
+#define IPU_PERIPHERAL_L4PER1   0x68000000
+
+#define L4_PERIPHERAL_L4PER2    0x48400000
+#define IPU_PERIPHERAL_L4PER2   0x68400000
+
+#define L4_PERIPHERAL_L4PER3    0x48800000
+#define IPU_PERIPHERAL_L4PER3   0x68800000
+
+#define L4_PERIPHERAL_L4EMU     0x54000000
+#define IPU_PERIPHERAL_L4EMU    0x74000000
+
+#define L3_PERIPHERAL_PRUSS     0x4B200000
+#define IPU_PERIPHERAL_PRUSS    0x6B200000
+
+#define L3_PERIPHERAL_DMM       0x4E000000
+#define IPU_PERIPHERAL_DMM      0x6E000000
+
+#define L3_IVAHD_CONFIG         0x5A000000
+#define IPU_IVAHD_CONFIG        0x7A000000
+
+#define L3_IVAHD_SL2            0x5B000000
+#define IPU_IVAHD_SL2           0x7B000000
+
+#define L3_TILER_MODE_0_1       0x60000000
+#define IPU_TILER_MODE_0_1      0xA0000000
+
+#define L3_TILER_MODE_2         0x70000000
+#define IPU_TILER_MODE_2        0xB0000000
+
+#define L3_TILER_MODE_3         0x78000000
+#define IPU_TILER_MODE_3        0xB8000000
+
+#define L3_OCMC_RAM            0x40300000
+#define IPU_OCMC_RAM           0x60300000
+
+#define L3_EMIF_SDRAM          0xA0000000
+#define IPU_EMIF_SDRAM         0x10000000
+
+#define IPU_MEM_TEXT            0x0
+#define IPU_MEM_DATA            0x80000000
+
+#define IPU_MEM_IOBUFS          0x90000000
+
+#define IPU_MEM_IPC_DATA        0x9F000000
+#define IPU_MEM_IPC_VRING       0x60000000
+#define IPU_MEM_RPMSG_VRING0    0x60000000
+#define IPU_MEM_RPMSG_VRING1    0x60004000
+#define IPU_MEM_VRING_BUFS0     0x60040000
+#define IPU_MEM_VRING_BUFS1     0x60080000
+
+#define IPU_MEM_IPC_VRING_SIZE  SZ_1M
+#define IPU_MEM_IPC_DATA_SIZE   SZ_1M
+
+#if defined(VAYU_IPU_1)
+#define IPU_MEM_TEXT_SIZE       (SZ_1M)
+#elif defined(VAYU_IPU_2)
+#define IPU_MEM_TEXT_SIZE       (SZ_1M * 6)
+#endif
+
+#if defined(VAYU_IPU_1)
+#define IPU_MEM_DATA_SIZE       (SZ_1M * 5)
+#elif defined(VAYU_IPU_2)
+#define IPU_MEM_DATA_SIZE       (SZ_1M * 48)
+#endif
+
+#define IPU_MEM_IOBUFS_SIZE     (SZ_1M * 90)
+
+/*
+ * Assign fixed RAM addresses to facilitate a fixed MMU table.
+ * PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together.
+ */
+/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
+#if defined(VAYU_IPU_1)
+#define PHYS_MEM_IPC_VRING      0x9D000000
+#elif defined (VAYU_IPU_2)
+#define PHYS_MEM_IPC_VRING      0x95800000
+#endif
+
+#define PHYS_MEM_IOBUFS         0xBA300000
+
+/*
+ * Sizes of the virtqueues (expressed in number of buffers supported,
+ * and must be power of 2)
+ */
+#define IPU_RPMSG_VQ0_SIZE      256
+#define IPU_RPMSG_VQ1_SIZE      256
+
+/* flip up bits whose indices represent features we support */
+#define RPMSG_IPU_C0_FEATURES   1
+
+struct my_resource_table {
+    struct resource_table base;
+
+    UInt32 offset[21];  /* Should match 'num' in actual definition */
+
+    /* rpmsg vdev entry */
+    struct fw_rsc_vdev rpmsg_vdev;
+    struct fw_rsc_vdev_vring rpmsg_vring0;
+    struct fw_rsc_vdev_vring rpmsg_vring1;
+
+    /* text carveout entry */
+    struct fw_rsc_carveout text_cout;
+
+    /* data carveout entry */
+    struct fw_rsc_carveout data_cout;
+
+    /* ipcdata carveout entry */
+    struct fw_rsc_carveout ipcdata_cout;
+
+    /* trace entry */
+    struct fw_rsc_trace trace;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem0;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem1;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem2;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem3;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem4;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem5;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem6;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem7;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem8;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem9;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem10;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem11;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem12;
+
+    /* devmem entry */
+    struct fw_rsc_devmem devmem13; 
+    
+    /* devmem entry */
+    struct fw_rsc_devmem devmem14; 
+    
+    /* devmem entry */
+    struct fw_rsc_devmem devmem15; 
+};
+extern char ti_trace_SysMin_Module_State_0_outbuf__A;
+#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
+
+#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
+#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
+
+struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
+    1,      /* we're the first version that implements this */
+    21,     /* number of entries in the table */
+    0, 0,   /* reserved, must be zero */
+    /* offsets to entries */
+    {
+        offsetof(struct my_resource_table, rpmsg_vdev),
+        offsetof(struct my_resource_table, text_cout),
+        offsetof(struct my_resource_table, data_cout),
+        offsetof(struct my_resource_table, ipcdata_cout),
+        offsetof(struct my_resource_table, trace),
+        offsetof(struct my_resource_table, devmem0),
+        offsetof(struct my_resource_table, devmem1),
+        offsetof(struct my_resource_table, devmem2),
+        offsetof(struct my_resource_table, devmem3),
+        offsetof(struct my_resource_table, devmem4),
+        offsetof(struct my_resource_table, devmem5),
+        offsetof(struct my_resource_table, devmem6),
+        offsetof(struct my_resource_table, devmem7),
+        offsetof(struct my_resource_table, devmem8),
+        offsetof(struct my_resource_table, devmem9),
+        offsetof(struct my_resource_table, devmem10),
+        offsetof(struct my_resource_table, devmem11),
+        offsetof(struct my_resource_table, devmem12),
+        offsetof(struct my_resource_table, devmem13),
+        offsetof(struct my_resource_table, devmem14),
+        offsetof(struct my_resource_table, devmem15),
+    },
+
+    /* rpmsg vdev entry */
+    {
+        TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
+        RPMSG_IPU_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
+        /* no config data */
+    },
+    /* the two vrings */
+    { IPU_MEM_RPMSG_VRING0, 4096, IPU_RPMSG_VQ0_SIZE, 1, 0 },
+    { IPU_MEM_RPMSG_VRING1, 4096, IPU_RPMSG_VQ1_SIZE, 2, 0 },
+
+    {
+        TYPE_CARVEOUT,
+        IPU_MEM_TEXT, 0,
+        IPU_MEM_TEXT_SIZE, 0, 0, "IPU_MEM_TEXT",
+    },
+
+    {
+        TYPE_CARVEOUT,
+        IPU_MEM_DATA, 0,
+        IPU_MEM_DATA_SIZE, 0, 0, "IPU_MEM_DATA",
+    },
+
+    {
+        TYPE_CARVEOUT,
+        IPU_MEM_IPC_DATA, 0,
+        IPU_MEM_IPC_DATA_SIZE, 0, 0, "IPU_MEM_IPC_DATA",
+    },
+
+    {
+        TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:sysm3",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
+        IPU_MEM_IPC_VRING_SIZE, 0, 0, "IPU_MEM_IPC_VRING",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_MEM_IOBUFS, PHYS_MEM_IOBUFS,
+        IPU_MEM_IOBUFS_SIZE, 0, 0, "IPU_MEM_IOBUFS",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_TILER_MODE_0_1, L3_TILER_MODE_0_1,
+        SZ_256M, 0, 0, "IPU_TILER_MODE_0_1",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_TILER_MODE_2, L3_TILER_MODE_2,
+        SZ_128M, 0, 0, "IPU_TILER_MODE_2",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_TILER_MODE_3, L3_TILER_MODE_3,
+        SZ_128M, 0, 0, "IPU_TILER_MODE_3",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
+        SZ_16M, 0, 0, "IPU_PERIPHERAL_L4CFG",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
+        SZ_2M, 0, 0, "IPU_PERIPHERAL_L4PER1",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
+        SZ_4M, 0, 0, "IPU_PERIPHERAL_L4PER2",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
+        SZ_8M, 0, 0, "IPU_PERIPHERAL_L4PER3",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
+        SZ_16M, 0, 0, "IPU_PERIPHERAL_L4EMU",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_PERIPHERAL_PRUSS, L3_PERIPHERAL_PRUSS,
+        SZ_1M, 0, 0, "IPU_PERIPHERAL_PRUSS",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_IVAHD_CONFIG, L3_IVAHD_CONFIG,
+        SZ_16M, 0, 0, "IPU_IVAHD_CONFIG",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_IVAHD_SL2, L3_IVAHD_SL2,
+        SZ_16M, 0, 0, "IPU_IVAHD_SL2",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
+        SZ_1M, 0, 0, "IPU_PERIPHERAL_DMM",
+    },
+
+    {
+        TYPE_DEVMEM,
+        IPU_OCMC_RAM, L3_OCMC_RAM,
+        SZ_4M, 0, 0, "IPU_OCMC_RAM",
+    },    
+
+    {
+        TYPE_DEVMEM,
+        IPU_EMIF_SDRAM, L3_EMIF_SDRAM,
+        SZ_256M, 0, 0, "IPU_EMIF_SDRAM",
+    },    
+
+};
+
+#endif /* _RSC_TABLE_VAYU_IPU_H_ */
diff --git a/ipu1/rsc_types.h b/ipu1/rsc_types.h
new file mode 100644 (file)
index 0000000..1bf5a27
--- /dev/null
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2011-2016, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  ======== rsc_types.h ========
+ *
+ *  Include common definitions for sizes and type of resources
+ *  used by the the resource table in each base image, which is
+ *  read from remoteproc on host side.
+ *
+ */
+
+#ifndef _RSC_TYPES_H_
+#define _RSC_TYPES_H_
+
+#include <xdc/std.h>
+
+/* Size constants must match those used on host: include/asm-generic/sizes.h */
+#define SZ_64K                          0x00010000
+#define SZ_128K                         0x00020000
+#define SZ_256K                         0x00040000
+#define SZ_512K                         0x00080000
+#define SZ_1M                           0x00100000
+#define SZ_2M                           0x00200000
+#define SZ_4M                           0x00400000
+#define SZ_8M                           0x00800000
+#define SZ_16M                          0x01000000
+#define SZ_32M                          0x02000000
+#define SZ_64M                          0x04000000
+#define SZ_128M                         0x08000000
+#define SZ_256M                         0x10000000
+#define SZ_512M                         0x20000000
+
+/* Virtio Ids: keep in sync with the linux "include/linux/virtio_ids.h" */
+#define VIRTIO_ID_CONSOLE       3 /* virtio console */
+#define VIRTIO_ID_RPMSG         7 /* virtio remote processor messaging */
+
+/* Indices of rpmsg virtio features we support */
+#define VIRTIO_RPMSG_F_NS       0  /* RP supports name service notifications */
+#define VIRTIO_RING_F_SYMMETRIC 30 /* We support symmetric vring */
+
+/* Resource info: Must match include/linux/remoteproc.h: */
+#define TYPE_CARVEOUT    0
+#define TYPE_DEVMEM      1
+#define TYPE_TRACE       2
+#define TYPE_VDEV        3
+#define TYPE_INTMEM      4
+
+/* Common Resource Structure Types */
+struct resource_table {
+    UInt32 ver;
+    UInt32 num;
+    UInt32 reserved[2];
+};
+
+struct fw_rsc_carveout {
+    UInt32  type;
+    UInt32  da;
+    UInt32  pa;
+    UInt32  len;
+    UInt32  flags;
+    UInt32  reserved;
+    Char    name[32];
+};
+
+struct fw_rsc_intmem {
+    UInt32  type;
+    UInt32  version;
+    UInt32  da;
+    UInt32  pa;
+    UInt32  len;
+    UInt32  reserved;
+    Char    name[32];
+};
+
+struct fw_rsc_devmem {
+    UInt32  type;
+    UInt32  da;
+    UInt32  pa;
+    UInt32  len;
+    UInt32  flags;
+    UInt32  reserved;
+    Char    name[32];
+};
+
+struct fw_rsc_trace {
+    UInt32  type;
+    UInt32  da;
+    UInt32  len;
+    UInt32  reserved;
+    Char    name[32];
+};
+
+struct fw_rsc_vdev_vring {
+    UInt32  da; /* device address */
+    UInt32  align;
+    UInt32  num;
+    UInt32  notifyid;
+    UInt32  reserved;
+};
+
+struct fw_rsc_vdev {
+    UInt32  type;
+    UInt32  id;
+    UInt32  notifyid;
+    UInt32  dfeatures;
+    UInt32  gfeatures;
+    UInt32  config_len;
+    Char    status;
+    Char    num_of_vrings;
+    Char    reserved[2];
+};
+
+#endif /* _RSC_TYPES_H_ */
diff --git a/ipu2/Ipu2.cfg b/ipu2/Ipu2.cfg
new file mode 100644 (file)
index 0000000..2123169
--- /dev/null
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2013-2015 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Ipu2.cfg ========
+ *  Platform: DRA7XX_linux_elf
+ *  Target: ti.targets.arm.elf.M4
+ */
+
+/* root of the configuration object model */
+var Program = xdc.useModule('xdc.cfg.Program');
+
+/* build arguments for this executable */
+var cfgArgs = Program.build.cfgArgs;
+var configBld = xdc.loadCapsule(cfgArgs.configBld);
+
+/* application uses the following modules and packages */
+xdc.useModule('xdc.runtime.Assert');
+xdc.useModule('xdc.runtime.Diags');
+xdc.useModule('xdc.runtime.Error');
+xdc.useModule('xdc.runtime.Log');
+xdc.useModule('xdc.runtime.Registry');
+
+xdc.useModule('ti.sysbios.gates.GateHwi');
+xdc.useModule('ti.sysbios.knl.Semaphore');
+xdc.useModule('ti.sysbios.knl.Task');
+
+/*
+ *  ======== IPC Configuration ========
+ */
+xdc.useModule('ti.ipc.ipcmgr.IpcMgr');
+
+Program.global.procName = "IPU2";
+var ipc_cfg = xdc.loadCapsule("../shared/ipc.cfg.xs");
+
+var BIOS        = xdc.useModule('ti.sysbios.BIOS');
+BIOS.addUserStartupFunction('&IpcMgr_ipcStartup');
+
+/*
+ *  ======== SYS/BIOS Configuration ========
+ */
+if (Program.build.profile == "debug") {
+    BIOS.libType = BIOS.LibType_Debug;
+} else {
+    BIOS.libType = BIOS.LibType_Custom;
+}
+BIOS.smpEnabled = true; /* only support SMP mode on IPU */
+
+var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core');
+Core.ipuId = 2;
+
+/* no rts heap */
+Program.argSize = 100;  /* minimum size */
+Program.stack = 0x1000;
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.common$.namedInstance = true;
+
+/* Remap the interrupt xbar mmr base address to match AMMU settings */
+var IntXbar = xdc.useModule('ti.sysbios.family.shared.vayu.IntXbar');
+IntXbar.mmrBaseAddr = 0x6A002000;
+
+/* default memory heap */
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var heapMemParams = new HeapMem.Params();
+heapMemParams.size = 0x8000;
+Memory.defaultHeapInstance = HeapMem.create(heapMemParams);
+
+/* create a heap for MessageQ messages */
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var params = new HeapBuf.Params;
+params.align = 8;
+params.blockSize = 512;
+params.numBlocks = 256;
+var msgHeap = HeapBuf.create(params);
+
+var MessageQ  = xdc.useModule('ti.sdo.ipc.MessageQ');
+MessageQ.registerHeapMeta(msgHeap, 0);
+
+/* Setup MessageQ transport */
+var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
+MessageQ.SetupTransportProxy = VirtioSetup;
+
+/* Setup NameServer remote proxy */
+var NameServer = xdc.useModule("ti.sdo.utils.NameServer");
+var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
+NameServer.SetupProxy = NsRemote;
+
+/* Enable Memory Translation module that operates on the BIOS Resource Table */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+
+/*  Use SysMin because trace buffer address is required for Linux/QNX
+ *  trace debug driver, plus provides better performance.
+ */
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('ti.trace.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize  = 0x8000;
+
+Program.sectMap[".tracebuf"] = "TRACE_BUF";
+Program.sectMap[".errorbuf"] = "EXC_DATA";
+
+/*  Configure external timer base address to match resource table mapping.
+ */
+var dmTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+/* dmTimer 0 mapped to GPT1 */
+dmTimer.timerSettings[0].baseAddr = 0x6AE18000;
+/* dmTimer 1 mapped to GPT2 */
+dmTimer.timerSettings[1].baseAddr = 0x68032000;
+/* dmTimer 2 mapped to GPT3 */
+dmTimer.timerSettings[2].baseAddr = 0x68034000;
+/* dmTimer 3 mapped to GPT4 */
+dmTimer.timerSettings[3].baseAddr = 0x68036000;
+/* dmTimer 4 mapped to GPT5 */
+dmTimer.timerSettings[4].baseAddr = 0x68820000;
+/* dmTimer 5 mapped to GPT6 */
+dmTimer.timerSettings[5].baseAddr = 0x68822000;
+/* dmTimer 6 mapped to GPT7 */
+dmTimer.timerSettings[6].baseAddr = 0x68034000;
+/* dmTimer 7 mapped to GPT8 */
+dmTimer.timerSettings[7].baseAddr = 0x68036000;
+/* dmTimer 8 mapped to GPT9 */
+dmTimer.timerSettings[8].baseAddr = 0x6803E000;
+/* dmTimer 9 mapped to GPT10 */
+dmTimer.timerSettings[9].baseAddr = 0x68086000;
+/* dmTimer 10 mapped to GPT11 */
+dmTimer.timerSettings[10].baseAddr = 0x68088000;
+/* dmTimer 11 mapped to GPT12 */
+dmTimer.timerSettings[11].baseAddr = 0x6AE20000;
+/* dmTimer 12 mapped to GPT13 */
+dmTimer.timerSettings[12].baseAddr = 0x68828000;
+/* dmTimer 13 mapped to GPT14 */
+dmTimer.timerSettings[13].baseAddr = 0x6882A000;
+/* dmTimer 14 mapped to GPT15 */
+dmTimer.timerSettings[14].baseAddr = 0x6882C000;
+/* dmTimer 15 mapped to GPT16 */
+dmTimer.timerSettings[15].baseAddr = 0x6882E000;
+
+/* use external timers because they keep running when IPU is not */
+var halTimer = xdc.useModule('ti.sysbios.hal.Timer');
+halTimer.TimerProxy = dmTimer;
+
+/* ----------------------------- TICK ---------------------------------------*/
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+Clock.tickSource = Clock.TickSource_USER;
+/* Configure GPTimer3 as BIOS clock source */
+Clock.timerId = 2;
+
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+var timerParams = new Timer.Params();
+timerParams.period = Clock.tickPeriod;
+timerParams.periodType = Timer.PeriodType_MICROSECS;
+/* Smart-idle wake-up-capable mode */
+timerParams.tiocpCfg.idlemode = 0x3;
+/* Wake-up generation for Overflow */
+timerParams.twer.ovf_wup_ena = 0x1;
+Timer.create(Clock.timerId, Clock.doTick, timerParams);
+
+/* configure the IPU AMMU */
+xdc.loadCapsule("IpuAmmu.cfg");
+
+
+/* idle functions */
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+
+/* function to flush unicache on each core */
+Idle.addCoreFunc('&VirtQueue_cacheWb', 0);
+Idle.addCoreFunc('&VirtQueue_cacheWb', 1);
+
+var Deh = xdc.useModule('ti.deh.Deh');
+
+/* Watchdog detection functions in each core */
+/* Must be placed before pwr mgmt */
+Idle.addCoreFunc('&ti_deh_Deh_idleBegin', 0);
+Idle.addCoreFunc('&ti_deh_Deh_idleBegin', 1);
+
+/*
+ *  ======== Instrumentation Configuration ========
+ */
+
+/* system logger */
+var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
+var LoggerSysParams = new LoggerSys.Params();
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
+
+/* enable runtime Diags_setMask() for non-XDC spec'd modules */
+var Diags = xdc.useModule('xdc.runtime.Diags');
+Diags.setMaskEnabled = true;
+
+/* override diags mask for selected modules */
+xdc.useModule('xdc.runtime.Main');
+Diags.setMaskMeta("xdc.runtime.Main",
+    Diags.ENTRY | Diags.EXIT | Diags.INFO, Diags.RUNTIME_ON);
+
+var Registry = xdc.useModule('xdc.runtime.Registry');
+Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF;
+Registry.common$.diags_EXIT  = Diags.RUNTIME_OFF;
+Registry.common$.diags_INFO  = Diags.RUNTIME_OFF;
+Registry.common$.diags_USER1 = Diags.RUNTIME_OFF;
+Registry.common$.diags_LIFECYCLE = Diags.RUNTIME_OFF;
+Registry.common$.diags_STATUS = Diags.RUNTIME_OFF;
+
+var Main = xdc.useModule('xdc.runtime.Main');
+Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
+Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
+
+var Hwi = xdc.useModule('ti.sysbios.family.arm.m3.Hwi');
+Hwi.nvicCCR.DIV_0_TRP = 1;
diff --git a/ipu2/IpuAmmu.cfg b/ipu2/IpuAmmu.cfg
new file mode 100644 (file)
index 0000000..fa8439e
--- /dev/null
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2012-2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* -------------------------------- Cache ----------------------------------*/
+var Cache = xdc.useModule('ti.sysbios.hal.unicache.Cache');
+Cache.enableCache = true;
+
+/* -------------------------------- AMMU -----------------------------------*/
+var AMMU = xdc.useModule('ti.sysbios.hal.ammu.AMMU');
+/*********************** Small Pages *************************/
+/* smallPages[0] & smallPages[1] are auto-programmed by h/w */
+
+/* Overwrite smallPage[1] so that 16K is covered. H/w reset value configures
+ * only 4K */
+AMMU.smallPages[1].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[1].logicalAddress = 0x40000000;
+AMMU.smallPages[1].translatedAddress = 0x55080000;
+AMMU.smallPages[1].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[1].size = AMMU.Small_16K;
+
+/* L2RAM: 64K mapped using 4 smallPages(16K); cacheable; translated */
+/* config small page[2] to map 16K VA 0x20000000 to PA 0x55020000  */
+AMMU.smallPages[2].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[2].logicalAddress = 0x20000000;
+AMMU.smallPages[2].translatedAddress = 0x55020000;
+AMMU.smallPages[2].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[2].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+AMMU.smallPages[2].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+AMMU.smallPages[2].L1_posted = AMMU.PostedPolicy_POSTED;
+AMMU.smallPages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.smallPages[2].size = AMMU.Small_16K;
+
+/* config small page[3] to map 16K VA 0x20004000 to PA 0x55024000 */
+AMMU.smallPages[3].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[3].logicalAddress = 0x20004000;
+AMMU.smallPages[3].translatedAddress = 0x55024000;
+AMMU.smallPages[3].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[3].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+AMMU.smallPages[3].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+AMMU.smallPages[3].L1_posted = AMMU.PostedPolicy_POSTED;
+AMMU.smallPages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.smallPages[3].size = AMMU.Small_16K;
+
+/* config small page[4] to map 16K VA 0x20008000 to PA 0x55028000 */
+AMMU.smallPages[4].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[4].logicalAddress = 0x20008000;
+AMMU.smallPages[4].translatedAddress = 0x55028000;
+AMMU.smallPages[4].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[4].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+AMMU.smallPages[4].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+AMMU.smallPages[4].L1_posted = AMMU.PostedPolicy_POSTED;
+AMMU.smallPages[4].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.smallPages[4].size = AMMU.Small_16K;
+
+/* config small page[5] to map 16K VA 0x2000C000 to PA 0x5502C000 */
+AMMU.smallPages[5].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[5].logicalAddress = 0x2000C000;
+AMMU.smallPages[5].translatedAddress = 0x5502C000;
+AMMU.smallPages[5].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[5].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
+AMMU.smallPages[5].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
+AMMU.smallPages[5].L1_posted = AMMU.PostedPolicy_POSTED;
+AMMU.smallPages[5].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.smallPages[5].size = AMMU.Small_16K;
+
+/* ISS: Use 3 small pages(1 4K and 2 16K) for various ISP registers; non-cacheable; translated */
+/* config small page[6] to map 16K VA 0x50000000 to PA 0x55040000 */
+/* non cacheable by default */
+AMMU.smallPages[6].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[6].logicalAddress = 0x50000000;
+AMMU.smallPages[6].translatedAddress = 0x55040000;
+AMMU.smallPages[6].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[6].size = AMMU.Small_16K;
+
+/* config small page[7] to map 16K VA 0x50010000 to PA 0x55050000 */
+/* non cacheable by default */
+AMMU.smallPages[7].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[7].logicalAddress = 0x50010000;
+AMMU.smallPages[7].translatedAddress = 0x55050000;
+AMMU.smallPages[7].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[7].size = AMMU.Small_16K;
+
+/* config small page[8] to map 4K VA 0x50020000 to PA 0x55060000 */
+/* non cacheable by default */
+AMMU.smallPages[8].pageEnabled = AMMU.Enable_YES;
+AMMU.smallPages[8].logicalAddress = 0x50020000;
+AMMU.smallPages[8].translatedAddress = 0x55060000;
+AMMU.smallPages[8].translationEnabled = AMMU.Enable_YES;
+AMMU.smallPages[8].size = AMMU.Small_4K;
+
+/*********************** Medium Pages *************************/
+/* ISS: The entire ISS register space using a medium page (256K); cacheable; translated */
+/* config medium page[0] to map 256K VA 0x50000000 to PA 0x55040000 */
+/* Make it L1 cacheable */
+AMMU.mediumPages[0].pageEnabled = AMMU.Enable_YES;
+AMMU.mediumPages[0].logicalAddress = 0x50000000;
+AMMU.mediumPages[0].translatedAddress = 0x55040000;
+AMMU.mediumPages[0].translationEnabled = AMMU.Enable_YES;
+AMMU.mediumPages[0].size = AMMU.Medium_256K;
+AMMU.mediumPages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.mediumPages[0].L1_posted = AMMU.PostedPolicy_POSTED;
+
+
+/*********************** Large Pages *************************/
+/* Instruction Code: Large page  (512M); cacheable */
+/* config large page[0] to map 512MB VA 0x0 to L3 0x0 */
+AMMU.largePages[0].pageEnabled = AMMU.Enable_YES;
+AMMU.largePages[0].logicalAddress = 0x0;
+AMMU.largePages[0].translationEnabled = AMMU.Enable_NO;
+AMMU.largePages[0].size = AMMU.Large_512M;
+AMMU.largePages[0].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.largePages[0].L1_posted = AMMU.PostedPolicy_POSTED;
+
+/* Peripheral regions: Large Page (512M); non-cacheable */
+/* config large page[1] to map 512MB VA 0x60000000 to L3 0x60000000 */
+AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
+AMMU.largePages[1].logicalAddress = 0x60000000;
+AMMU.largePages[1].translationEnabled = AMMU.Enable_NO;
+AMMU.largePages[1].size = AMMU.Large_512M;
+AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
+AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED;
+
+/* Private, Shared and IPC Data regions: Large page (512M); cacheable */
+/* config large page[2] to map 512MB VA 0x80000000 to L3 0x80000000 */
+AMMU.largePages[2].pageEnabled = AMMU.Enable_YES;
+AMMU.largePages[2].logicalAddress = 0x80000000;
+AMMU.largePages[2].translationEnabled = AMMU.Enable_NO;
+AMMU.largePages[2].size = AMMU.Large_512M;
+AMMU.largePages[2].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.largePages[2].L1_posted = AMMU.PostedPolicy_POSTED;
+
+/* TILER & DMM regions: Large page (512M); cacheable */
+/* config large page[3] to map 512MB VA 0xA0000000 to L3 0xA0000000 */
+AMMU.largePages[3].pageEnabled = AMMU.Enable_YES;
+AMMU.largePages[3].logicalAddress = 0xA0000000;
+AMMU.largePages[3].translationEnabled = AMMU.Enable_NO;
+AMMU.largePages[3].size = AMMU.Large_512M;
+AMMU.largePages[3].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
+AMMU.largePages[3].L1_posted = AMMU.PostedPolicy_POSTED;
diff --git a/ipu2/MainIpu2.c b/ipu2/MainIpu2.c
new file mode 100644 (file)
index 0000000..0047f94
--- /dev/null
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== main_Ipu2.c ========
+ *
+ */
+
+/* xdctools header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/Log.h>
+#include <xdc/runtime/System.h>
+
+/* package header files */
+#include <ti/ipc/Ipc.h>
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+
+/* local header files */
+#include "Server.h"
+
+/* private functions */
+static Void smain(UArg arg0, UArg arg1);
+
+
+/*
+ *  ======== main ========
+ */
+Int main(Int argc, Char* argv[])
+{
+    Error_Block     eb;
+    Task_Params     taskParams;
+
+    Log_print0(Diags_ENTRY, "--> main:");
+
+    /* must initialize the error block before using it */
+    Error_init(&eb);
+
+    /* create main thread (interrupts not enabled in main on BIOS) */
+    Task_Params_init(&taskParams);
+    taskParams.instance->name = "smain";
+    taskParams.arg0 = (UArg)argc;
+    taskParams.arg1 = (UArg)argv;
+    taskParams.stackSize = 0x1000;
+    Task_create(smain, &taskParams, &eb);
+
+    if (Error_check(&eb)) {
+        System_abort("main: failed to create application startup thread");
+    }
+
+    /* start scheduler, this never returns */
+    BIOS_start();
+
+    /* should never get here */
+    Log_print0(Diags_EXIT, "<-- main:");
+    return (0);
+}
+
+
+/*
+ *  ======== smain ========
+ */
+Void smain(UArg arg0, UArg arg1)
+{
+    Int                 status = 0;
+    Error_Block         eb;
+    Bool                running = TRUE;
+
+    Log_print0(Diags_ENTRY | Diags_INFO, "--> smain:");
+
+    Error_init(&eb);
+
+    /* initialize modules */
+    Server_init();
+
+    /* turn on Diags_INFO trace */
+    Diags_setMask("Server+F");
+
+    /* loop forever */
+    while (running) {
+
+        /* BEGIN server phase */
+
+        /* server setup phase */
+        status = Server_create();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* server execute phase */
+        status = Server_exec();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* server shutdown phase */
+        status = Server_delete();
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        /* END server phase */
+
+    } /* while (running) */
+
+    /* finalize modules */
+    Server_exit();
+
+leave:
+    Log_print1(Diags_EXIT, "<-- smain: %d", (IArg)status);
+    return;
+}
diff --git a/ipu2/Server.c b/ipu2/Server.c
new file mode 100644 (file)
index 0000000..3d83084
--- /dev/null
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2013-2014, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Server.c ========
+ *
+ */
+
+/* this define must precede inclusion of any xdc header file */
+#define Registry_CURDESC Test__Desc
+#define MODULE_NAME "Server"
+
+/* xdctools header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Assert.h>
+#include <xdc/runtime/Diags.h>
+#include <xdc/runtime/Log.h>
+#include <xdc/runtime/Registry.h>
+
+#include <stdio.h>
+
+/* package header files */
+#include <ti/ipc/MessageQ.h>
+#include <ti/ipc/MultiProc.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+
+/* local header files */
+#include "../shared/AppCommon.h"
+
+/* module header file */
+#include "Server.h"
+
+/* module structure */
+typedef struct {
+    UInt16              hostProcId;         // host processor id
+    MessageQ_Handle     slaveQue;           // created locally
+} Server_Module;
+
+/* private data */
+Registry_Desc               Registry_CURDESC;
+static Server_Module        Module;
+
+
+/*
+ *  ======== Server_init ========
+ */
+Void Server_init(Void)
+{
+    Registry_Result result;
+
+    /* register with xdc.runtime to get a diags mask */
+    result = Registry_addModule(&Registry_CURDESC, MODULE_NAME);
+    Assert_isTrue(result == Registry_SUCCESS, (Assert_Id)NULL);
+
+    /* initialize module object state */
+    Module.hostProcId = MultiProc_getId("HOST");
+}
+
+
+/*
+ *  ======== Server_create ========
+ */
+Int Server_create()
+{
+    Int                 status = 0;
+    MessageQ_Params     msgqParams;
+    char                msgqName[32];
+
+    /* enable some log events */
+    Diags_setMask(MODULE_NAME"+EXF");
+
+    /* create local message queue (inbound messages) */
+    MessageQ_Params_init(&msgqParams);
+    sprintf(msgqName, App_SlaveMsgQueName, MultiProc_getName(MultiProc_self()));
+    Module.slaveQue = MessageQ_create(msgqName, &msgqParams);
+
+    if (Module.slaveQue == NULL) {
+        status = -1;
+        goto leave;
+    }
+
+    Log_print0(Diags_INFO,"Server_create: server is ready");
+
+leave:
+    Log_print1(Diags_EXIT, "<-- Server_create: %d", (IArg)status);
+    return (status);
+}
+
+
+
+
+/*
+ *  ======== Server_exec ========
+ */
+Int Server_exec()
+{
+    Int                 status;
+    Bool                running = TRUE;
+    App_Msg *           msg;
+    MessageQ_QueueId    queId;
+
+    Log_print0(Diags_ENTRY | Diags_INFO, "--> Server_exec:");
+
+    while (running) {
+
+        /* wait for inbound message */
+        status = MessageQ_get(Module.slaveQue, (MessageQ_Msg *)&msg,
+            MessageQ_FOREVER);
+
+        if (status < 0) {
+            goto leave;
+        }
+
+        if (msg->cmd == App_CMD_SHUTDOWN) {
+            running = FALSE;
+        }
+
+        /* process the message */
+        Log_print1(Diags_INFO, "Server_exec: processed cmd=0x%x", msg->cmd);
+
+        /* send message back */
+        queId = MessageQ_getReplyQueue(msg); /* type-cast not needed */
+        MessageQ_put(queId, (MessageQ_Msg)msg);
+    } /* while (running) */
+
+leave:
+    Log_print1(Diags_EXIT, "<-- Server_exec: %d", (IArg)status);
+    return(status);
+}
+
+/*
+ *  ======== Server_delete ========
+ */
+
+Int Server_delete()
+{
+    Int         status;
+
+    Log_print0(Diags_ENTRY, "--> Server_delete:");
+
+    /* delete the video message queue */
+    status = MessageQ_delete(&Module.slaveQue);
+
+    if (status < 0) {
+        goto leave;
+    }
+
+leave:
+    if (status < 0) {
+        Log_error1("Server_finish: error=0x%x", (IArg)status);
+    }
+
+    /* disable log events */
+    Log_print1(Diags_EXIT, "<-- Server_delete: %d", (IArg)status);
+    Diags_setMask(MODULE_NAME"-EXF");
+
+    return(status);
+}
+
+/*
+ *  ======== Server_exit ========
+ */
+
+Void Server_exit(Void)
+{
+    /*
+     * Note that there isn't a Registry_removeModule() yet:
+     *     https://bugs.eclipse.org/bugs/show_bug.cgi?id=315448
+     *
+     * ... but this is where we'd call it.
+     */
+}
diff --git a/ipu2/Server.h b/ipu2/Server.h
new file mode 100644 (file)
index 0000000..5278f23
--- /dev/null
@@ -0,0 +1,56 @@
+/*
+#  Copyright (c) 2012-2014 Texas Instruments Incorporated - http://www.ti.com
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *  ======== Server.h ========
+ */
+
+#ifndef Server__include
+#define Server__include
+
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+
+Void Server_init(Void);
+Void Server_exit(Void);
+
+Int Server_create(Void);
+Int Server_exec(Void);
+Int Server_delete(Void);
+
+
+#if defined (__cplusplus)
+}
+#endif /* defined (__cplusplus) */
+#endif /* Server__include */
diff --git a/ipu2/makefile b/ipu2/makefile
new file mode 100644 (file)
index 0000000..fa1ee23
--- /dev/null
@@ -0,0 +1,148 @@
+#
+#  Copyright (c) 2012-2015 Texas Instruments Incorporated - http://www.ti.com
+#  All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#
+#  *  Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#
+#  *  Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  *  Neither the name of Texas Instruments Incorporated nor the names of
+#     its contributors may be used to endorse or promote products derived
+#     from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+#  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+#  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+#  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+#  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+#  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+#  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+#  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+#  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+#  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+#  ======== makefile ========
+#
+
+EXBASE = ..
+include $(EXBASE)/products.mak
+
+srcs = MainIpu2.c Server.c
+objs = $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.oem4,$(srcs)))
+CONFIG = bin/$(PROFILE)/configuro
+
+PKGPATH := $(BIOS_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(IPC_INSTALL_DIR)/packages
+PKGPATH := $(PKGPATH)+$(XDC_INSTALL_DIR)/packages
+
+-include $(addprefix bin/$(PROFILE)/obj/,$(patsubst %.c,%.oem4.dep,$(srcs)))
+
+.PRECIOUS: %/compiler.opt %/linker.cmd
+
+all: debug release
+
+debug:
+       $(MAKE) PROFILE=debug PROCLIST="$(PROCLIST)" server_ipu2.x
+
+release:
+       $(MAKE) PROFILE=release PROCLIST="$(PROCLIST)" server_ipu2.x
+
+server_ipu2.x: bin/$(PROFILE)/server_ipu2.xem4
+bin/$(PROFILE)/server_ipu2.xem4: $(objs) $(libs) $(CONFIG)/linker.cmd
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(LD) $(LDFLAGS) -o $@ $(objs) \
+            $(addprefix -l ,$(libs)) $(CONFIG)/linker.cmd $(LDLIBS)
+
+bin/$(PROFILE)/obj/%.oem4: %.c $(CONFIG)/compiler.opt
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(CC) $(CPPFLAGS) $(CFLAGS) --output_file=$@ -fc $<
+
+%/linker.cmd %/compiler.opt: $(CONFIG)/.config ;
+$(CONFIG)/.config: Ipu2.cfg ../shared/config.bld
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(XDC_INSTALL_DIR)/xs --xdcpath="$(subst +,;,$(PKGPATH))" \
+            xdc.tools.configuro -o $(CONFIG) \
+            -t ti.targets.arm.elf.M4 \
+            -c $(ti.targets.arm.elf.M4) \
+            -p ti.platforms.evmDRA7XX:ipu2 \
+            -b ../shared/config.bld -r $(PROFILE) \
+            --cfgArgs "{ configBld: \"../shared/config.bld\" }" \
+            Ipu2.cfg
+       @$(ECHO) "" > $@
+
+install:
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       @$(MKDIR) $(EXEC_DIR)/debug
+       $(CP) bin/debug/server_ipu2.xem4 $(EXEC_DIR)/debug
+       @$(MKDIR) $(EXEC_DIR)/release
+       $(CP) bin/release/server_ipu2.xem4 $(EXEC_DIR)/release
+
+help:
+       @$(ECHO) "make                   # build executable"
+       @$(ECHO) "make clean             # clean everything"
+
+clean::
+       $(RMDIR) bin
+
+#  ======== install validation ========
+ifeq (install,$(MAKECMDGOALS))
+ifeq (,$(EXEC_DIR))
+$(error must specify EXEC_DIR)
+endif
+endif
+
+#  ======== toolchain macros ========
+CGTOOLS = $(ti.targets.arm.elf.M4)
+
+CC = $(CGTOOLS)/bin/armcl -c
+LD = $(CGTOOLS)/bin/armcl -z
+
+CPPFLAGS =
+CFLAGS = -qq -pdsw225 -ppd=$@.dep -ppa $(CCPROFILE_$(PROFILE)) -@$(CONFIG)/compiler.opt -I.
+
+# entry point is set to an aligned address so that IPC can load the slave
+LDFLAGS = -w -q -u _c_int00 -c -m $(@D)/obj/$(@F).map
+LDLIBS = -l $(CGTOOLS)/lib/libc.a
+
+CCPROFILE_debug = -D_DEBUG_=1 --symdebug:dwarf
+CCPROFILE_release = -O2
+
+#  ======== standard macros ========
+ifneq (,$(wildcard $(XDC_INSTALL_DIR)/xdc.exe))
+    # use these on Windows
+    CP      = $(XDC_INSTALL_DIR)/bin/cp
+    ECHO    = $(XDC_INSTALL_DIR)/bin/echo
+    MKDIR   = $(XDC_INSTALL_DIR)/bin/mkdir -p
+    RM      = $(XDC_INSTALL_DIR)/bin/rm -f
+    RMDIR   = $(XDC_INSTALL_DIR)/bin/rm -rf
+else
+    # use these on Linux
+    CP      = cp
+    ECHO    = echo
+    MKDIR   = mkdir -p
+    RM      = rm -f
+    RMDIR   = rm -rf
+endif
+
+#  ======== create output directories ========
+ifneq (clean,$(MAKECMDGOALS))
+ifneq (,$(PROFILE))
+ifeq (,$(wildcard bin/$(PROFILE)/obj))
+    $(shell $(MKDIR) -p bin/$(PROFILE)/obj)
+endif
+endif
+endif
diff --git a/makefile b/makefile
new file mode 100644 (file)
index 0000000..4702ff6
--- /dev/null
+++ b/makefile
@@ -0,0 +1,98 @@
+#
+#  Copyright (c) 2012-2015 Texas Instruments Incorporated - http://www.ti.com
+#  All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#
+#  *  Redistributions of source code must retain the above copyright
+#     notice, this list of conditions and the following disclaimer.
+#
+#  *  Redistributions in binary form must reproduce the above copyright
+#     notice, this list of conditions and the following disclaimer in the
+#     documentation and/or other materials provided with the distribution.
+#
+#  *  Neither the name of Texas Instruments Incorporated nor the names of
+#     its contributors may be used to endorse or promote products derived
+#     from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+#  THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+#  PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+#  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+#  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+#  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+#  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+#  WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+#  OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+#  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+#  ======== makefile ========
+#
+
+# edit PROCLIST list to control how many executables to build
+PROCLIST = dsp1 dsp2 ipu1 ipu2 host
+
+EXBASE = .
+include $(EXBASE)/products.mak
+.PHONY: $(PROCLIST)
+
+.PHONY: install
+
+all: $(PROCLIST)
+
+$(PROCLIST):
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       $(MAKE) -C $@ PROCLIST="$(PROCLIST)"
+
+help:
+       @$(ECHO) "make                                  # build executables"
+       @$(ECHO) "make clean                            # clean everything"
+       @$(ECHO) "make install EXEC_DIR=/.../testbench  # install folder"
+
+# setup install goal
+ifeq (install,$(MAKECMDGOALS))
+ifeq (,$(EXEC_DIR))
+EXEC_DIR=$(CURDIR)/install
+endif
+override EXEC_DIR:=$(EXEC_DIR)/ex02_messageq
+endif
+
+install: $(PROCLIST) $(addsuffix _install,$(PROCLIST))
+$(addsuffix _install,$(PROCLIST)):
+       @$(ECHO) "#"
+       @$(ECHO) "# Making $@ ..."
+       @$(MKDIR) $(EXEC_DIR)/debug
+       @$(MKDIR) $(EXEC_DIR)/release
+       $(MAKE) -C $(subst _install,,$@) EXEC_DIR=$(EXEC_DIR) install
+
+clean: $(addsuffix _clean,$(PROCLIST))
+       $(RMDIR) install
+
+$(addsuffix _clean,$(PROCLIST)):
+       $(MAKE) -C $(subst _clean,,$@) clean
+
+
+#  ======== standard macros ========
+ifneq (,$(wildcard $(XDC_INSTALL_DIR)/xdc.exe))
+    # use these on Windows
+    CP      = $(XDC_INSTALL_DIR)/bin/cp
+    ECHO    = $(XDC_INSTALL_DIR)/bin/echo
+    INSTALL = $(XDC_INSTALL_DIR)/bin/cp
+    MKDIR   = $(XDC_INSTALL_DIR)/bin/mkdir -p
+    RM      = $(XDC_INSTALL_DIR)/bin/rm -f
+    RMDIR   = $(XDC_INSTALL_DIR)/bin/rm -rf
+else
+    # use these on Linux
+    CP      = cp
+    ECHO    = echo
+    INSTALL = install
+    MKDIR   = mkdir -p
+    RM      = rm -f
+    RMDIR   = rm -rf
+endif
diff --git a/manifest.htm b/manifest.htm
new file mode 100755 (executable)
index 0000000..66091b5
--- /dev/null
@@ -0,0 +1,328 @@
+<!--\r\r
+Texas Instruments Manifest Format 2.0\r\r
+-->\r\r
+\r\r
+<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r\r
+<html>\r\r
+\r\r
+<head>\r\r
+<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />\r\r
+<!-- @Start Style -->\r\r
+<!-- Default style in case someone doesnt have Internet Access -->\r\r
+<style type="text/css" id="internalStyle">\r\r
+       body, div, p {\r\r
+               font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\r\r
+               font-size: 13px;\r\r
+               line-height: 1.3;\r\r
+       }\r\r
+       body {\r\r
+               margin: 20px;   \r\r
+       }\r\r
+       h1 {\r\r
+               font-size: 150%;\r\r
+       }\r\r
+       h2 {\r\r
+               font-size: 120%;\r\r
+       }\r\r
+       h3 {\r\r
+               font-size: 100%;\r\r
+       }\r\r
+       img {\r\r
+               border: 0px;\r\r
+               vertical-align: middle;\r\r
+       }\r\r
+       table, th, td, tr {\r\r
+               border: 1px solid black;        \r\r
+               font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\r\r
+               font-size: 13px;\r\r
+               line-height: 1.3;\r\r
+               empty-cells: show;  \r\r
+               padding: 5px;\r\r
+       }\r\r
+       table {\r\r
+               border-collapse: collapse; \r\r
+               width: 100%;\r\r
+       }\r\r
+       tr {\r\r
+               page-break-inside: avoid;\r\r
+       }\r\r
+       #TIlogoLeft {\r\r
+               background-color: black; \r\r
+               padding: 0;\r\r
+               width: 20%;\r\r
+       }\r\r
+       #TIlogoRight {\r\r
+               background-color: red; \r\r
+               padding: 0;\r\r
+       }\r\r
+       #ProductName {\r\r
+               text-align: center;\r\r
+       }\r\r
+       #ReleaseDate {\r\r
+               text-align: center;\r\r
+       }\r\r
+       .LogoSection {\r\r
+               margin: 0;\r\r
+               padding: 0;\r\r
+       }\r\r
+       .HeaderSection {\r\r
+               margin: 25px 0 25px 0;\r\r
+               padding: 0;\r\r
+       }\r\r
+       .LegendSection {\r\r
+               margin: 25px 0 25px 0;\r\r
+       }\r\r
+       .ExportSection {\r\r
+               margin: 25px 0 25px 0;\r\r
+       }\r\r
+       .DisclaimerSection {\r\r
+               margin: 25px 0 25px 0;  \r\r
+       }\r\r
+       .CreditSection {\r\r
+               margin: 25px 0 25px 0;  \r\r
+       }\r\r
+       .LicenseSection {\r\r
+               margin: 25px 0 25px 0;  \r\r
+       }\r\r
+       .ManifestTable {\r\r
+               margin: 25px 0 25px 0;  \r\r
+       }\r\r
+</style> \r\r
+<!-- Override style from TI if they have Internet Access -->\r\r
+<link type="text/css" rel="stylesheet" href="timanifeststyle.css">\r\r
+<!-- @End Style -->\r\r
+<title>Texas Instruments Manifest</title>\r\r
+</head>\r\r
+\r\r
+<body><!-- Logo display, will need to fix up the URLs, this is just for testing.. Image alternate display not wporking well yet -->\r\r
+<div class="LogoSection">\r\r
+<table>\r\r
+  <tbody>\r\r
+    <tr>\r\r
+      <td id="TIlogoLeft">\r\r
+        <a href="http://www.ti.com/">\r\r
+          <!-- img src="tilogo.gif" alt="Texas Instruments Incorporated" -->\r\r
+                 <img alt="" src="data:image/gif;base64,R0lGODlh3gA2AKIAAAAAAP///7u7u29vbz8/PwYGBujo6BgYGCH5BAAAAAAALAAAAADeADYAAAP/CLrc/jDKSau9OOvNu/9gKI5kaZ5oqq5s675wLM90bd94ru987//AoHBILBqPyKRyyWw6n9CodHorDALYLIHKJVqz2q44eAUHtoDB4DBu48rgLQErcNtnX7NhMDcICIB3gix5ZmtqAAZZew8EAo+QkQIDNVZqiIM1cHGKZ4YPAmaiAWw0c1gFmZqjB3SbZ6kNe6WhsAeOlDV0qjSFAXUAp7lwuREFtVsFgMvLB7fNAM+BCs+lDLd8BNYOuxfV22PL0RiWlwO1u3kDqejAEsjR6GB86FsHoYwA6gxWnVgGEegUuIelWJk6jswAGlXQ36J1xBSoQwfulIEDr/6l+VeK/+AehrAGOHRnAWRBbbWegckXAV6wk4AeRQtDQBEaBYsYlMl2hUCsBt0iKgilT9EfAlfO7SmzdKkrkQUT/fqZSECqLCSlntH375IAA1tqGUilLIBSNVnU+NmJNBRVChlF1QwAdlRWBy5P3QymwCLBYhs73cTHYBq3X33nDQ2wcWuBgef0FRD4GK3jU3VCZZUJAIw1OGg0P+4bFiubOWoOsEP1+KvZn3wurDbZ6lfcuw3yYkFjRSeYzRe7ARAbW0K3PmGIMi0OFDG1Mmha+RnufAHn3xL9ha6uTZ/rXagZ1GKAtTsHeWb+FEQvHILuX4+mLzj2j2r4TrFesTwMbE5Cuv8JzbTSGuRV1xgfUJFC3WbA0JWFalcItpgf8YU2yT/qATaedent5cBb8zk0DzIitgfKbonRFV9Wp2xl3UXq5Ccibp05598BnRigiAIJmrZAexkJQIuBwzX4CB3SQbeYQkPVAUco63DI2HzsAdYAiAvEZdYlaVQ5wXs3+bQAjovEUoBRR9LVAFLaPXCcY/KMqVRasQB5kiJgLcYgTkJiuCWKC2ZpIY/z/LRhYefkBAGW1HTyRy2UjObLHxSAOZ948EUVGCSC3SLZbB7iZKOLc2GRRgMH/VhdHnJwFCgD8iEGx0VKvpqbO+hoaCppEg3UiTES1CTkhNaQ+Qs4LQGql07/lET4mIQ6SvTSVGZ9Bmhz/bkYzK+PFKtpje6wumRm1wrLZzSdQASoZvyswdmSuk7p616HfkjBTxZBQucFgqXCFKdn1NpiUlQJhs8kteBWG0AbATbXS2tBlaeoVkmJRova4KkGPmhMFdiSYmq8cbTRYhrlkiHaNufJ9mIgVqEXnAOJM5JE4sgjudQ8bF82x+cKBP4Iiedecyjgx2/WtMNjjhcL9h+S4xq9RYJgsbeeUbmdrPTSQbPccsyijEXOfI8xyuinVJH1wdkS/MQ2Bc5Iq08DyHYwGglvPyCilbz0fa8GLV7r9+Btb7CJ14Qnzg8HpdKoOOF5Py752JNXvrblNphzEHnmnF/a+ecTbA465qKPXnnppkuOeuqKr8465K+z7nrsfc9Ouyq23z5I7rrfwXvvbhSQAAA7" />\r\r
+        </a>\r\r
+      </td>\r\r
+      <td id="TILogoRight">\r\r
+        <!-- img src="titagline.gif" alt="Technology for Innovators(tm)"-->\r\r
+               <img alt="" src="data:image/gif;base64,R0lGODlhOgEaALMAAP8AAP////92dv+3t/+Njf/W1v/t7f8hIf/19f+jo//Hx/8/P/9cXP/j4//6+v/+/iH5BAAAAAAALAAAAAA6ARoAAAT/EMhJq7046827/2AojmRpnmiqrmzrvnAsz3Rt33iu73zv/8CgcEgsGo/IpHLJbDqft0NDMCBQodis1jcADBKE7nYcCpjPgU5AQBKkVYOHAeRudqtXsh60/vRHdSoBBCGBNAkLe4o4f2psgG8pjR6GM5OLmDB/DA0GBoQADAgICRIBBQUOYgwGCg2kEgudBgUHAIGcBg0MsZ0NCnMGYgsBtqEGAbCynrW3AQONgcIFBgiErK6wAAfUtLbCscWiowoAyLDczLZu0AIJCAYOoJn0G38ObAwPEvLEts/O1vUhsA8AAjGonEmA9W6hGAVpEjiQoKBAhT8HJSRkVyEQQAAJ//a5YeMPQIFyACqCnJjSIgFCB4oB+HOSokWOAB6wIWCxnk8MfYh5QsYg5sVHfQLVMSqhztJIxWIaC6QzJy8KfZgqrNT0zR+nUNl8fSMvZ6IDwJCJRfoI7IR4Cub9nDsha6RwR02xUZpGq1utUWUq9FKgYV6/abgOHjt45tquEgY0SDDHoJg+fxhXolKNrmfH/EoR5EdAKmjQfB1qvPmGIQIJ3g4gC2egVF7LqxtP8Ng2cViTKFUCIGbNFKEEmB/VbDlYdqLRn+du8oTg6jjbmfe+CbTM2+BcuySgbQVtQoOCt7s3U8wbsqGs3ZppZLnylwFe8Uql825ogANPckUnYDoOCogxQGXADajggjcw4AA8DSSyTQASMmjhhTQscBWGHHbo4YcghijiiCSWaOKJKKao4oostugiFBEAADs=" />\r\r
+      </td>\r\r
+    </tr>\r\r
+  </tbody>\r\r
+</table>\r\r
+</div><div class="HeaderSection">\r\r
+<h1 id="ProductName">\r\r
+<!-- @Start Product -->\r\r
+IPC Demo on AM572x Manifest\r\r
+<!-- @End Product -->\r\r
+</h1>\r\r
+\r\r
+<h2 id="ReleaseDate">\r\r
+<!-- @Start Date -->\r\r
+04-21-2016\r\r
+<!-- @End Date -->\r\r
+</h2>\r\r
+\r\r
+\r\r
+<h2 id="SRASID">\r\r
+<!-- @Start Date -->\r\r
+Manifest ID - SRAS00002679\r\r
+<!-- @End Date -->\r\r
+</h2>\r\r
+</div><div class="LegendSection">\r\r
+<h2>Legend</h2>\r\r
+<p>(explanation of the fields in the Manifest Table below)</p>\r\r
+<table>\r\r
+<tbody>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Software Name </b>\r\r
+</td>\r\r
+<td>\r\r
+The name of the application or file\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Version</b>\r\r
+</td>\r\r
+<td>\r\r
+Version of the application or file\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>License Type</b>\r\r
+</td>\r\r
+<td>\r\r
+Type of license(s) under which TI will be providing\r\r
+software to the licensee (e.g. BSD-3-Clause, GPL-2.0, TI TSPA License, TI\r\r
+Commercial License). The license could be under Commercial terms or Open Source. See Open Source Reference License Disclaimer in\r\r
+the Disclaimers Section. Whenever possible, TI will use an <a href="http://spdx.org/licenses/"> SPDX Short Identifier </a> for an Open Source\r\r
+License. TI Commercial license terms are not usually included in the manifest and are conveyed through a variety \r\r
+of means such as a clickwrap license upon install, \r\r
+a signed license agreement and so forth.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Location</b>\r\r
+</td>\r\r
+<td>\r\r
+The directory name and path on the media or a specific file where the Software is located. Typically fully qualified path names \r\r
+are not used and instead the relevant top level directory of the application is given. \r\r
+A notation often used in the manifests is [as installed]/directory/*. Note that the asterisk implies that all\r\r
+files under that directory are licensed as the License Type field denotes. Any exceptions to this will \r\r
+generally be denoted as [as installed]/directory/* except as noted below which means as shown in subsequent rows of \r\r
+the manifest.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Delivered As</b>\r\r
+</td>\r\r
+<td>\r\r
+This field will either be &#8220;Source&#8221;, &#8220;Binary&#8221; or &#8220;Source\r\r
+and Binary&#8221; and is the primary form the content of the Software is delivered\r\r
+in. If the Software is delivered in an archive format, this field\r\r
+applies to the contents of the archive. If the word Limited is used\r\r
+with Source, as in &#8220;Limited Source&#8221; or &#8220;Limited Source and Binary&#8221; then\r\r
+only portions of the Source for the application are provided.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Modified by TI</b>\r\r
+</td>\r\r
+<td>\r\r
+This field will either be &#8220;Yes&#8221; or &#8220;No&#8221;. A &#8220;Yes&#8221; means\r\r
+TI has made changes to the Software. A &#8220;No&#8221; means TI has not made any\r\r
+changes. Note: This field is not applicable for Software &#8220;Obtained\r\r
+from&#8221; TI.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Obtained from</b>\r\r
+</td>\r\r
+<td>\r\r
+This field specifies from where or from whom TI obtained\r\r
+the Software. It may be a URL to an Open Source site, a 3<sup>rd</sup>\r\r
+party licensor, or TI. See Links Disclaimer in the Disclaimers\r\r
+Section.\r\r
+</td>\r\r
+</tr>\r\r
+</tbody>\r\r
+</table>\r\r
+</div><div class="DisclaimerSection">\r\r
+<h2>Disclaimers</h2>\r\r
+<h3>Export Control Classification Number (ECCN)</h3>\r\r
+<p>Any use of ECCNs listed in the Manifest is at the user&#8217;s risk\r\r
+and without recourse to TI. Your\r\r
+company, as the exporter of record, is responsible for determining the\r\r
+correct classification of any item at\r\r
+the time of export. Any export classification by TI of Software is for\r\r
+TI&#8217;s internal use only and shall not be construed as a representation\r\r
+or warranty\r\r
+regarding the proper export classification for such Software or whether\r\r
+an export\r\r
+license or other documentation is required for exporting such Software</p>\r\r
+<h3>Links in the Manifest</h3>\r\r
+<p>Any\r\r
+links appearing on this Manifest\r\r
+(for example in the &#8220;Obtained from&#8221; field) were verified at the time\r\r
+the Manifest was created. TI makes no guarantee that any listed links\r\r
+will\r\r
+remain active in the future.</p>\r\r
+<h3>Open Source License References</h3>\r\r
+<p>Your company is responsible for confirming the\r\r
+applicable license terms for any open source Software\r\r
+listed in this Manifest that was not &#8220;Obtained from&#8221; TI. Any open\r\r
+source license\r\r
+specified in this Manifest for Software that was\r\r
+not &#8220;Obtained from&#8221; TI is for TI&#8217;s internal use only and shall not be\r\r
+construed as a representation or warranty regarding the proper open\r\r
+source license terms\r\r
+for such Software.</p>\r\r
+</div><div class="ExportSection">\r\r
+<h2>Export Information</h2>\r\r
+<p>ECCN for Software included in this release:</p>\r\r
+Publicly Available  - Open Source or TI TSPA License\r\r
+</div><div class="ManifestTable">\r\r
+<!-- h2>Manifest Table</h2 -->\r\r
\r
+ <table> \r
+ <tbody> \r
\r
+ <h2> \r
+  IPC Demo on AM572x Manifest Table \r
+ </h2> \r
\r
+  \r
+ <p> \r
\r
+ See the Legend above for a description of these columns. \r
\r
+ </p> \r
+  \r
+ <table id="targetpackages" name="targetpackages"> \r
+ <thead>  \r
+       <tr> \r
+               <td><b>Software Name</b></td> \r
+               <td><b>Version</b></td> \r
+               <td><b>License Type</b></td> \r
+               <td><b>Delivered As</b></td> \r
+               <td><b>Modified by TI</b></td> \r
+               <td></td> \r
+               <td></td> \r
+       </tr> \r
+ </thead>  \r
\r
\r
+ <tbody> \r
+       <tr> \r
+               <td id="name" name="name" rowspan="2"> \r
+ IPC demo on AM572x \r
+ </td> \r
+               <td id="version" name="version" rowspan="2"> \r
+ 1.0 \r
+ </td> \r
+               <td id="license" name="license" rowspan="2"> \r
+ BSD-3-Clause \r
+ </td> \r
+               <td id="delivered" name="delivered" rowspan="2"> \r
+ Source \r
+ </td> \r
+               <td id="modified" name="modified" rowspan="2"> \r
+  \r
+ </td> \r
+               <td><b>Location</b></td> \r
+               <td id="location" name="location"> \r
+ C:/home/user/ \r
+ </td> \r
+       </tr> \r
+       <tr> \r
+               <td><b>Obtained from</b></td>