1 /*-----------------------------------------------------------------------------
2 * EcEscReg.h file
3 * Copyright acontis technologies GmbH, Weingarten, Germany
4 * Response Willig, Andreas
5 * Description ESC Controller Registers
6 * Date 2009/7/15::10:40
7 *---------------------------------------------------------------------------*/
9 #ifndef INC_ECESCREG
10 #define INC_ECESCREG
12 /*-INCLUDES------------------------------------------------------------------*/
14 /*-DEFINES-------------------------------------------------------------------*/
15 #define ESC_PORT_A ((EC_T_WORD)0)
16 #define ESC_PORT_B ((EC_T_WORD)1)
17 #define ESC_PORT_C ((EC_T_WORD)2)
18 #define ESC_PORT_D ((EC_T_WORD)3)
19 #define ESC_PORT_COUNT ((EC_T_WORD)4)
20 #define ESC_PORT_INVALID ((EC_T_WORD)0xFF)
22 /*-TYPEDEFS------------------------------------------------------------------*/
24 /*-CLASS---------------------------------------------------------------------*/
26 /*-FUNCTION DECLARATION------------------------------------------------------*/
28 /*-LOCAL VARIABLES-----------------------------------------------------------*/
30 /*-REGISTERS-----------------------------------------------------------------*/
32 /* EtherCAT configuration register offsets */
33 #define ECREG_SC_TYPE ((EC_T_WORD)0x0000)
34 #define ECREG_PORT_DESCRIPTOR ((EC_T_WORD)0x0007)
35 #define ECREG_FEATURES_SUPPORTED ((EC_T_WORD)0x0008)
36 #define ECREG_STATION_ADDRESS ((EC_T_WORD)0x0010)
37 #define ECREG_STATION_ADDRESS_ALIAS ((EC_T_WORD)0x0012)
38 #define ECREG_RESET_ECAT ((EC_T_WORD)0x0040)
39 #define ECREG_RESET_PDI ((EC_T_WORD)0x0041)
40 #define ECREG_DL_CONTROL ((EC_T_WORD)0x0100)
41 #define ECREG_DL_CONTROL1 ((EC_T_WORD)0x0101)
42 #define ECREG_DL_CONTROL2 ((EC_T_WORD)0x0102)
43 #define ECREG_DL_CONTROL3 ((EC_T_WORD)0x0103)
44 #define ECREG_DL_STATUS ((EC_T_WORD)0x0110)
45 #define ECREG_AL_CONTROL ((EC_T_WORD)0x0120)
46 #define ECREG_AL_STATUS ((EC_T_WORD)0x0130)
47 #define ECREG_AL_STATUS_LO ((EC_T_WORD)0x0130)
48 #define ECREG_AL_STATUSCODE ((EC_T_WORD)0x0134)
49 #define ECREG_AL_STATUSCODE_LO ((EC_T_WORD)0x0134)
50 #define ECREG_PDI_CONTROL ((EC_T_WORD)0x0140)
52 #define ECREG_SLV_ECATEVENTMASK ((EC_T_WORD)0x0200)
53 #define ECREG_SLV_ALEVENTMASK ((EC_T_WORD)0x0204)
54 #define ECREG_SLV_ECATEVENTREQUEST ((EC_T_WORD)0x0210)
55 #define ECREG_SLV_ALEVENTREQUEST ((EC_T_WORD)0x0220)
57 #define ECREG_SLV_RXERRCOUNTER ((EC_T_WORD)0x0300)
59 #define ECREG_WATCHDOG_DIVIDER ((EC_T_WORD)0x0400)
60 #define ECREG_WATCHDOG_TIME_PDI ((EC_T_WORD)0x0410)
61 #define ECREG_WATCHDOG_TIME_PROCESS_DATA ((EC_T_WORD)0x0420)
62 #define ECREG_WATCHDOG_COUNTER_PROCESS_DATA ((EC_T_WORD)0x0442)
64 #define ECM_SB_EEP_SLV_PDIACCSTATE ((EC_T_WORD)0x0500)
65 #define ECM_SB_EEP_SLV_CTRLSTATUS ((EC_T_WORD)0x0502)
66 #define ECM_SB_EEP_SLV_EEPDATA ((EC_T_WORD)0x0508)
68 /* FMMU configuration */
69 #define ECREG_FMMU_CONFIG ((EC_T_WORD)0x0600)
70 #define ECREG_FMMU_MAX_NUMOF ((EC_T_WORD)16)
72 /* Sync Manager configuration */
73 #define ECREG_SYNCMANAGER_CONFIG ((EC_T_WORD)0x0800)
74 #define ECREG_SYNCMANAGER_MBX_OUT ((EC_T_WORD)0x0800)
75 #define ECREG_SYNCMANAGER_MBX_IN ((EC_T_WORD)0x0808)
76 #define ECREG_SYNCMANAGER0 ((EC_T_WORD)0x0800)
77 #define ECREG_SYNCMANAGER1 ((EC_T_WORD)0x0808)
78 #define ECREG_SYNCMANAGER2 ((EC_T_WORD)0x0810)
79 #define ECREG_SYNCMANAGER3 ((EC_T_WORD)0x0818)
80 #define ECREG_SYNCMANAGER4 ((EC_T_WORD)0x0820)
81 #define ECREG_SYNCMANAGER5 ((EC_T_WORD)0x0828)
82 #define ECREG_SYNCMANAGER6 ((EC_T_WORD)0x0830)
83 #define ECREG_SYNCMANAGER7 ((EC_T_WORD)0x0838)
84 #define ECREG_SYNCMANAGER8 ((EC_T_WORD)0x0840)
85 #define ECREG_SYNCMANAGER9 ((EC_T_WORD)0x0848)
86 #define ECREG_SYNCMANAGER10 ((EC_T_WORD)0x0850)
87 #define ECREG_SYNCMANAGER11 ((EC_T_WORD)0x0858)
88 #define ECREG_SYNCMANAGER12 ((EC_T_WORD)0x0860)
89 #define ECREG_SYNCMANAGER13 ((EC_T_WORD)0x0868)
90 #define ECREG_SYNCMANAGER14 ((EC_T_WORD)0x0870)
91 #define ECREG_SYNCMANAGER15 ((EC_T_WORD)0x0878)
92 #define ECREG_SYNCMANAGER_MAX_NUMOF ((EC_T_WORD)16)
94 /* DC */
95 #define ECM_DCS_REC_TIMEPORT0 ((EC_T_WORD)0x0900)
96 #define ECM_DCS_REC_TIMEPORT1 ((EC_T_WORD)0x0904)
97 #define ECM_DCS_REC_TIMEPORT2 ((EC_T_WORD)0x0908)
98 #define ECM_DCS_REC_TIMEPORT3 ((EC_T_WORD)0x090C)
99 #define ECM_DCS_SYSTEMTIME ((EC_T_WORD)0x0910)
100 #define ECM_DCS_REC_TIMEPORTL0 ((EC_T_WORD)0x0918)
102 #define ECM_DCS_SYSTIME_OFFSET ((EC_T_WORD)0x0920)
103 #define ECM_DCS_SYSTIME_DELAY ((EC_T_WORD)0x0928)
105 #define ECM_DCS_SPEEDCOUNT_START ((EC_T_WORD)0x0930)
106 #define ECM_DCS_SPEEDCOUNT_DIFF ((EC_T_WORD)0x0932)
107 #define ECM_DCS_SYSTIMEDIFF_FILTERDEPTH ((EC_T_WORD)0x0934)
108 #define ECM_DCS_SPEEDCOUNT_FILTERDEPTH ((EC_T_WORD)0x0935)
110 /*#define ECM_DCS_DC_USER_P1 ((EC_T_WORD)0x0981)*/
112 #define ECM_DCS_DC_UNIT_CONTROL ((EC_T_WORD)0x0980)
113 #define ECM_DCS_DC_ACTIVATION_REGISTER ((EC_T_WORD)0x0981)
114 #define ECM_DCS_DC_SYNCPULSEWIDTH ((EC_T_WORD)0x0982)
116 #define ECM_DCS_DC_WR_STARTCYCOP ((EC_T_WORD)0x0990)
117 #define ECM_DCS_DC_RD_TIMNEXTSYNC0 ((EC_T_WORD)0x0990)
119 #define ECM_DCS_DC_CYCLETIME0 ((EC_T_WORD)0x09A0)
120 #define ECM_DCS_DC_CYCLETIME1 ((EC_T_WORD)0x09A4)
122 /*DC Latching*/
123 #define ECM_DCL_SYNCLATCH_CONFIGURATION ((EC_T_WORD)0x0151)
124 #define ECM_DCL_LATCHSTATUS_REGISTER ((EC_T_WORD)0x09AE)
126 #define ECREG_SYSTEMTIME ((EC_T_WORD)0x0910)
127 #define ECREG_SYSTIME_DIFF ((EC_T_WORD)0x092C)
129 /* DCL */
130 #define ECREG_DCL_CTRL_LATCH ((EC_T_WORD)0x09a8)
131 #define ECREG_DCL_CTRL_LATCH1 ((EC_T_WORD)0x09a9)
133 #define ECM_DCL_LTIME0_POSITIVE ((EC_T_WORD)0x09b0)
134 #define ECM_DCL_LTIME0_NEGATIVE ((EC_T_WORD)0x09b8)
135 #define ECM_DCL_LTIME1_POSITIVE ((EC_T_WORD)0x09c0)
136 #define ECM_DCL_LTIME1_NEGATIVE ((EC_T_WORD)0x09c8)
138 /*-/REGISTERS----------------------------------------------------------------*/
140 /*-REGISTER BITDEFINITIONS---------------------------------------------------*/
142 /*****************************************************************************
143 * 0x0000: SC_TYPE (ECREG_SC_TYPE)
144 *****************************************************************************/
145 #define ESCTYPE_BKHF_ELOLD ((EC_T_BYTE)0x01)
146 #define ESCTYPE_ESC10 ((EC_T_BYTE)0x02)
147 #define ESCTYPE_ESC20 ((EC_T_BYTE)0x02)
148 #define ESCTYPE_ESC10_20 ((EC_T_BYTE)0x02)
149 #define ESCTYPE_BKHF_EKOLD ((EC_T_BYTE)0x03)
150 #define ESCTYPE_IPCORE ((EC_T_BYTE)0x04)
151 #define ESCTYPE_IPCOREBKHF ((EC_T_BYTE)0x05)
152 #define ESCTYPE_ET1100 ((EC_T_BYTE)0x11)
153 #define ESCTYPE_ET1200 ((EC_T_BYTE)0x12)
154 #define ESCTYPE_NETX100_500 ((EC_T_BYTE)0x80)
155 #define ESCTYPE_NETX50 ((EC_T_BYTE)0x81)
156 #define ESCTYPE_NETX5 ((EC_T_BYTE)0x82)
157 #define ESCTYPE_NETX51_52 ((EC_T_BYTE)0x83)
158 #define ESCTYPE_HILSCHER_RES1 ((EC_T_BYTE)0x84)
159 #define ESCTYPE_HILSCHER_RES2 ((EC_T_BYTE)0x85)
160 #define ESCTYPE_HILSCHER_RES3 ((EC_T_BYTE)0x86)
161 #define ESCTYPE_HILSCHER_RES4 ((EC_T_BYTE)0x87)
162 #define ESCTYPE_HILSCHER_RES5 ((EC_T_BYTE)0x88)
163 #define ESCTYPE_TI ((EC_T_BYTE)0x90)
164 #define ESCTYPE_INFINEON ((EC_T_BYTE)0x98)
165 #define ESCTYPE_RENESAS ((EC_T_BYTE)0xA0)
166 #define ESCTYPE_INNOVASIC ((EC_T_BYTE)0xA8)
167 #define ESCTYPE_HMS ((EC_T_BYTE)0xB0)
168 #define ESCTYPE_PROFICHIP ((EC_T_BYTE)0xB8)
169 #define ESCTYPE_MICROCHIP ((EC_T_BYTE)0xC0)
170 #define ESCTYPE_TRINAMIC ((EC_T_BYTE)0xD0)
172 /*****************************************************************************
173 * 0x0007: Port descriptor (ECREG_PORT_DESCRIPTOR)
174 *****************************************************************************/
175 #define ECM_PORT_NOTIMPLEMENTED ((EC_T_BYTE)(0x00))
176 #define ECM_PORT_NOTCONFIGURED ((EC_T_BYTE)(0x01))
177 #define ECM_PORT_EBUS ((EC_T_BYTE)(0x02))
178 #define ECM_PORT_MII ((EC_T_BYTE)(0x03))
180 /*****************************************************************************
181 * 0x0008: ESC Features Supported (ECREG_FEATURES_SUPPOR TED)
182 *****************************************************************************/
183 #define ECM_DLI_FMMUBITSUPPORT ((EC_T_BYTE)(0x01))
184 #define ECM_DLI_DCSUPPORT ((EC_T_BYTE)(0x04))
185 #define ECM_DLI_DC64SUPPORT ((EC_T_BYTE)(0x08))
188 /*****************************************************************************
189 * 0x0100: DL CONTROL (ECREG_DL_CONTROL)
190 *****************************************************************************/
191 #define ECM_DLCTRL_NONEC_FORWARDING ((EC_T_DWORD)0x00000001)
192 #define ECM_DLCTRL_TEMPORARY_USE ((EC_T_DWORD)0x00000002)
193 #define ECM_DLCTRL_LOOP_PORT0_SHIFT ((EC_T_DWORD)0x08)
194 #define ECM_DLCTRL_LOOP_PORT1_SHIFT ((EC_T_DWORD)0x0A)
195 #define ECM_DLCTRL_LOOP_PORT2_SHIFT ((EC_T_DWORD)0x0C)
196 #define ECM_DLCTRL_LOOP_PORT3_SHIFT ((EC_T_DWORD)0x0E)
197 #define ECM_DLCTRL_LOOP_PORTS_MASK ((EC_T_DWORD)0x00000003)
199 #define ECM_DLCTRL_LOOP_PORTX_SHIFT(x) ((EC_T_DWORD)(ECM_DLCTRL_LOOP_PORT0_SHIFT+(2*((x)%4))))
200 #define ECM_DLCTRL_LOOP_PORTX_MASK(x) ((EC_T_DWORD)(0x00000003<<ECM_DLCTRL_LOOP_PORTX_SHIFT((x))))
202 #define ECM_DLCTRL_RXFIFOSIZE_SHIFT ((EC_T_DWORD)0x10)
203 #define ECM_DLCTRL_RXFIFOSIZE_MASK ((EC_T_DWORD)0x00000007)
204 #define ECM_DLCTRL_EBUS_LOWJITTER ((EC_T_DWORD)0x00100000)
205 #define ECM_DLCTRL_USEALIAS ((EC_T_DWORD)0x01000000)
207 #define ECM_DLCTRL_LOOP_PORT_VAL_AUTO ((EC_T_DWORD)0x0)
208 #define ECM_DLCTRL_LOOP_PORT_VAL_AUTOCLOSE ((EC_T_DWORD)0x1)
209 #define ECM_DLCTRL_LOOP_PORT_VAL_ALWAYSOPEN ((EC_T_DWORD)0x2)
210 #define ECM_DLCTRL_LOOP_PORT_VAL_ALWAYSCLOSED ((EC_T_DWORD)0x3)
212 /*****************************************************************************
213 * 0x0110: DL STATUS (ECREG_DL_STATUS)
214 *****************************************************************************/
215 #define ECM_DLS_PDI_OPERATIONAL ((EC_T_WORD)0x0001)
216 #define ECM_DLS_PDI_WATCHDOG_STATUS ((EC_T_WORD)0x0002)
217 #define ECM_DLS_PDI_ENH_LINK_DETECTION ((EC_T_WORD)0x0004)
218 #define ECM_DLS_PDI_PHYSICAL_LINK_ON_PORT0 ((EC_T_WORD)0x0010)
219 #define ECM_DLS_PDI_PHYSICAL_LINK_ON_PORT(x) ((EC_T_WORD)(1<<(4+((x)%4))))
221 #define ECM_DLS_PDI_LOOP_PORT0 ((EC_T_WORD)0x0100)
222 #define ECM_DLS_PDI_COM_ON_PORT0 ((EC_T_WORD)0x0200)
224 #define ECM_DLS_PDI_LOOP_PORT(x) ((EC_T_WORD)(1<<(8+(2*((x)%4)))))
225 #define ECM_DLS_PDI_COM_ON_PORT(x) ((EC_T_WORD)(1<<(9+(2*((x)%4)))))
227 /*****************************************************************************
228 * 0x0120: AL CONTROL (ECREG_AL_CONTROL)
229 *****************************************************************************/
230 #define ECR_ALCTRL_ACK_ERROR_IND ((EC_T_BYTE)(0x10))
231 #define ECR_ALCTRL_DEVICE_ID_REQUEST ((EC_T_BYTE)(0x20))
233 /*****************************************************************************
234 * 0x0130: AL STATUS (ECREG_AL_STATUS, ECREG_AL_STATUS_LO, ECREG_AL_STATUS_HI)
235 *****************************************************************************/
236 #define DEVICE_STATE_UNKNOWN ((EC_T_WORD)(0xFFFF&(~DEVICE_STATE_ERROR)))
237 #define DEVICE_STATE_INIT ((EC_T_WORD)0x0001)
238 #define DEVICE_STATE_PREOP ((EC_T_WORD)0x0002)
239 #define DEVICE_STATE_BOOTSTRAP ((EC_T_WORD)0x0003)
240 #define DEVICE_STATE_SAFEOP ((EC_T_WORD)0x0004)
241 #define DEVICE_STATE_OP ((EC_T_WORD)0x0008)
242 #define DEVICE_STATE_MASK ((EC_T_WORD)0x000F)
243 #define DEVICE_STATE_ERROR ((EC_T_WORD)0x0010)
244 #define DEVICE_STATE_IDREQUEST ((EC_T_WORD)0x0020)
246 #define SlaveDevStateText(nState) \
247 ((nState)==DEVICE_STATE_UNKNOWN?"UNKNOWN": \
248 ((nState&DEVICE_STATE_MASK)==DEVICE_STATE_INIT?"INIT": \
249 ((nState&DEVICE_STATE_MASK)==DEVICE_STATE_PREOP?"PRE OPERATIONAL": \
250 ((nState&DEVICE_STATE_MASK)==DEVICE_STATE_BOOTSTRAP?"BOOTSTRAP": \
251 ((nState&DEVICE_STATE_MASK)==DEVICE_STATE_SAFEOP?"SAFE OPERATIONAL": \
252 ((nState&DEVICE_STATE_MASK)==DEVICE_STATE_OP?"OPERATIONAL": \
253 ((nState&DEVICE_STATE_ERROR)==DEVICE_STATE_ERROR?"ERROR": \
254 "INVALID STATE VALUE!!!" \
255 )))))))
257 /*****************************************************************************
258 * 0x0134: AL STATUS CODE (ECREG_AL_STATUSCODE, ECREG_AL_STATUSCODE_LO, ECREG_AL_STATUSCODE_HI)
259 * See ETG.1020, V1.2.0, Table 1: Description of AL Status Codes usage
260 * See also EC_TXT_STATUSCODE_..., EcStatusCodeToString, ALSTATUSCODE_ in SSC
261 *****************************************************************************/
262 #define DEVICE_STATUSCODE_NOERROR ((EC_T_WORD)0x0000)
263 #define DEVICE_STATUSCODE_ERROR ((EC_T_WORD)0x0001)
264 #define DEVICE_STATUSCODE_NO_MEMORY ((EC_T_WORD)0x0002)
265 #define DEVICE_STATUSCODE_INVALID_DEVICE_SETUP ((EC_T_WORD)0x0003)
266 #define DEVICE_STATUSCODE_SII_EEPROM_INFORMATION_MISMATCH ((EC_T_WORD)0x0006)
267 #define DEVICE_STATUSCODE_FIRMWARE_UPDATE_ERROR ((EC_T_WORD)0x0007)
268 #define DEVICE_STATUSCODE_LICENSE_ERROR ((EC_T_WORD)0x000E)
269 #define DEVICE_STATUSCODE_INVREQSTATECNG ((EC_T_WORD)0x0011)
270 #define DEVICE_STATUSCODE_UNKREQSTATE ((EC_T_WORD)0x0012)
271 #define DEVICE_STATUSCODE_BOOTSTRAPNSUPP ((EC_T_WORD)0x0013)
272 #define DEVICE_STATUSCODE_NOVALIDFW ((EC_T_WORD)0x0014)
273 #define DEVICE_STATUSCODE_INVALIDMBXCNF1 ((EC_T_WORD)0x0015)
274 #define DEVICE_STATUSCODE_INVALIDMBXCNF2 ((EC_T_WORD)0x0016)
275 #define DEVICE_STATUSCODE_INVALIDSMCNF ((EC_T_WORD)0x0017)
276 #define DEVICE_STATUSCODE_NOVALIDIN ((EC_T_WORD)0x0018)
277 #define DEVICE_STATUSCODE_NOVALIDOUT ((EC_T_WORD)0x0019)
278 #define DEVICE_STATUSCODE_SYNCERROR ((EC_T_WORD)0x001A)
279 #define DEVICE_STATUSCODE_SMWATCHDOG ((EC_T_WORD)0x001B)
280 #define DEVICE_STATUSCODE_INVSMTYPES ((EC_T_WORD)0x001C)
281 #define DEVICE_STATUSCODE_INVOUTCONFIG ((EC_T_WORD)0x001D)
282 #define DEVICE_STATUSCODE_INVINCONFIG ((EC_T_WORD)0x001E)
283 #define DEVICE_STATUSCODE_INVWDCONFIG ((EC_T_WORD)0x001F)
284 #define DEVICE_STATUSCODE_SLVNEEDCOLDRS ((EC_T_WORD)0x0020)
285 #define DEVICE_STATUSCODE_SLVNEEDINIT ((EC_T_WORD)0x0021)
286 #define DEVICE_STATUSCODE_SLVNEEDPREOP ((EC_T_WORD)0x0022)
287 #define DEVICE_STATUSCODE_SLVNEEDSAFEOP ((EC_T_WORD)0x0023)
288 #define DEVICE_STATUSCODE_INVALID_INPUT_MAPPING ((EC_T_WORD)0x0024)
289 #define DEVICE_STATUSCODE_INVALID_OUTPUT_MAPPING ((EC_T_WORD)0x0025)
290 #define DEVICE_STATUSCODE_INCONSISTENT_SETTINGS ((EC_T_WORD)0x0026)
291 #define DEVICE_STATUSCODE_FREERUN_NOT_SUPPORTED ((EC_T_WORD)0x0027)
292 #define DEVICE_STATUSCODE_SYNCMODE_NOT_SUPPORTED ((EC_T_WORD)0x0028)
293 #define DEVICE_STATUSCODE_FREERUN_NEEDS_THREEBUFFER_MODE ((EC_T_WORD)0x0029)
294 #define DEVICE_STATUSCODE_BACKGROUND_WATCHDOG ((EC_T_WORD)0x002A)
295 #define DEVICE_STATUSCODE_NO_VALID_INPUTS_AND_OUTPUTS ((EC_T_WORD)0x002B)
296 #define DEVICE_STATUSCODE_FATAL_SYNC_ERROR ((EC_T_WORD)0x002C)
297 #define DEVICE_STATUSCODE_NO_SYNC_ERROR ((EC_T_WORD)0x002D)
298 #define DEVICE_STATUSCODE_CYCLE_TIME_TOO_SMALL ((EC_T_WORD)0x002E)
300 #define DEVICE_STATUSCODE_INVDCSYNCCNFG ((EC_T_WORD)0x0030)
301 #define DEVICE_STATUSCODE_INVDCLATCHCNFG ((EC_T_WORD)0x0031)
302 #define DEVICE_STATUSCODE_PLLERROR ((EC_T_WORD)0x0032)
303 #define DEVICE_STATUSCODE_INVDCIOERROR ((EC_T_WORD)0x0033)
304 #define DEVICE_STATUSCODE_INVDCTOERROR ((EC_T_WORD)0x0034)
305 #define DEVICE_STATUSCODE_DC_INVALID_SYNC_CYCLE_TIME ((EC_T_WORD)0x0035)
306 #define DEVICE_STATUSCODE_DC_SYNC0_CYCLE_TIME ((EC_T_WORD)0x0036)
307 #define DEVICE_STATUSCODE_DC_SYNC1_CYCLE_TIME ((EC_T_WORD)0x0037)
309 #define DEVICE_STATUSCODE_MBX_AOE ((EC_T_WORD)0x0041)
310 #define DEVICE_STATUSCODE_MBX_EOE ((EC_T_WORD)0x0042)
311 #define DEVICE_STATUSCODE_MBX_COE ((EC_T_WORD)0x0043)
312 #define DEVICE_STATUSCODE_MBX_FOE ((EC_T_WORD)0x0044)
313 #define DEVICE_STATUSCODE_MBX_SOE ((EC_T_WORD)0x0045)
315 #define DEVICE_STATUSCODE_MBX_VOE ((EC_T_WORD)0x004F)
317 #define DEVICE_STATUSCODE_EEPROM_NO_ACCESS ((EC_T_WORD)0x0050)
318 #define DEVICE_STATUSCODE_EEPROM_ERROR ((EC_T_WORD)0x0051)
319 #define DEVICE_STATUSCODE_EXT_HARDWARE_NOT_READY ((EC_T_WORD)0x0052)
321 #define DEVICE_STATUSCODE_SLAVE_RESTARTED_LOCALLY ((EC_T_WORD)0x0060)
322 #define DEVICE_STATUSCODE_DEVICE_IDENTIFICATION_UPDATED ((EC_T_WORD)0x0061)
324 #define DEVICE_STATUSCODE_MODULE_ID_LIST_NOT_MATCH ((EC_T_WORD)0x0070)
326 #define DEVICE_STATUSCODE_APPLICATION_CONTROLLER_AVAILABLE ((EC_T_WORD)0x00F0)
328 #define SlaveDevStatusCodeText(nCode) \
329 ecatGetText(((EC_T_DWORD)(EC_ALSTATUSCODEBASE+(nCode))))
331 /*****************************************************************************
332 * 0x0140: PDI Control (ECREG_PDI_CONTROL)
333 *****************************************************************************/
334 #define ECM_PDICTRL_PDI_MASK ((EC_T_WORD)0x00ff)
335 #define ECM_PDICTRL_DEVICE_EMULATION ((EC_T_WORD)0x0100)
337 /*****************************************************************************
338 * 0x0200/0x210: ECAT Event Request (ECREG_SLV_ECATEVENTMASK, ECREG_SLV_ECATEVENTREQUEST)
339 *****************************************************************************/
340 #define ECM_ECATEVENT_LATCH ((EC_T_WORD)0x0001)
341 #define ECM_ECATEVENT_DLSTATUS ((EC_T_WORD)0x0004)
342 #define ECM_ECATEVENT_ALSTATUS ((EC_T_WORD)0x0008)
343 #define ECM_ECATEVENT_SMCHANNEL0 ((EC_T_WORD)0x0010)
344 #define ECM_ECATEVENT_SMCHANNEL1 ((EC_T_WORD)0x0020)
345 #define ECM_ECATEVENT_SMCHANNEL2 ((EC_T_WORD)0x0040)
346 #define ECM_ECATEVENT_SMCHANNEL3 ((EC_T_WORD)0x0080)
347 #define ECM_ECATEVENT_SMCHANNEL4 ((EC_T_WORD)0x0100)
348 #define ECM_ECATEVENT_SMCHANNEL5 ((EC_T_WORD)0x0200)
349 #define ECM_ECATEVENT_SMCHANNEL6 ((EC_T_WORD)0x0400)
350 #define ECM_ECATEVENT_SMCHANNEL7 ((EC_T_WORD)0x0800)
352 /*****************************************************************************
353 * 0x0500: SSI PDI ACC STATE (ECM_SB_EEP_SLV_PDIACCSTATE)
354 *****************************************************************************/
355 #define ECM_SB_EEP_PDIACCSTATE_PDI ((EC_T_WORD)0x0001)
356 #define ECM_SB_EEP_PDIACCSTATE_OVERRIDE ((EC_T_WORD)0x0002)
357 #define ECM_SB_EEP_PDIACCSTATE_PDIACTIVE ((EC_T_WORD)0x0100)
359 /*****************************************************************************
360 * 0x0502: SSI CONTROL STATUS (ECM_SB_EEP_SLV_CTRLSTATUS)
361 *****************************************************************************/
362 #define ECM_SB_EEP_CTRLSTATUS_WRITE_ENABLE ((EC_T_WORD)0x0001)
364 #define ECM_SB_EEP_CTRLSTATUS_WRITE_READACCESS ((EC_T_WORD)0x0100)
365 #define ECM_SB_EEP_CTRLSTATUS_READ_READINPROGRESS ((EC_T_WORD)0x0100)
366 #define ECM_SB_EEP_CTRLSTATUS_WRITE_WRITEACCESS ((EC_T_WORD)0x0200)
367 #define ECM_SB_EEP_CTRLSTATUS_READ_WRITEINPROGRESS ((EC_T_WORD)0x0200)
368 #define ECM_SB_EEP_CTRLSTATUS_WRITE_RELOADACCESS ((EC_T_WORD)0x0400)
369 #define ECM_SB_EEP_CTRLSTATUS_READ_RELOADINPROGRESS ((EC_T_WORD)0x0400)
371 /* busy flag is masked alone */
372 #define ECM_SB_EEP_CTRLSTATUS_ERRORMASK ((EC_T_WORD)0x7800)
373 #define ECM_SB_EEP_CTRLSTATUS_ERR_CHKSUM ((EC_T_WORD)0x0800)
374 #define ECM_SB_EEP_CTRLSTATUS_LOADING_STATUS ((EC_T_WORD)0x1000)
375 #define ECM_SB_EEP_CTRLSTATUS_ERR_ACK ((EC_T_WORD)0x2000)
376 #define ECM_SB_EEP_CTRLSTATUS_ERR_WRITE_ENA ((EC_T_WORD)0x4000)
377 #define ECM_SB_EEP_CTRLSTATUS_BUSY ((EC_T_WORD)0x8000)
380 /*****************************************************************************
381 * 0x0800: DC SPEED COUNTER START (ECREG_SYNCMAN_START)
382 *****************************************************************************/
383 #define ECREG_SYNCMANAGER_START ((EC_T_WORD)0x0000)
384 #define ECREG_SYNCMANAGER_LENGTH ((EC_T_WORD)0x0002)
385 #define ECREG_SYNCMANAGER_CTRL ((EC_T_WORD)0x0004)
386 #define ECREG_SYNCMANAGER_OPMODE_MASK ((EC_T_BYTE)0x03)
387 #define ECREG_SYNCMANAGER_OPMODE_BUF_MASK ((EC_T_BYTE)0x03)
388 #define ECREG_SYNCMANAGER_OPMODE_3BUF ((EC_T_BYTE)0x00)
389 #define ECREG_SYNCMANAGER_OPMODE_3BUF_M ((EC_T_BYTE)0x01)
390 #define ECREG_SYNCMANAGER_OPMODE_1BUF ((EC_T_BYTE)0x02)
391 #define ECREG_SYNCMANAGER_OPMODE_1BUF_F ((EC_T_BYTE)0x03)
392 #define ECREG_SYNCMANAGER_ACCESS_MASK ((EC_T_BYTE)0x0C)
393 #define ECREG_SYNCMANAGER_ACCESS_READ ((EC_T_BYTE)0x00)
394 #define ECREG_SYNCMANAGER_ACCESS_WRITE ((EC_T_BYTE)0x04)
395 #define ECREG_SYNCMANAGER_FLB_ENABLE ((EC_T_BYTE)0x10)
396 #define ECREG_SYNCMANAGER_PDI_ENABLE ((EC_T_BYTE)0x20)
397 #define ECREG_SYNCMANAGER_WD_TRIG_ENABLE ((EC_T_BYTE)0x40)
398 #define ECREG_SYNCMANAGER_1_R_P ((EC_T_BYTE)0x22)
399 #define ECREG_SYNCMANAGER_1_W_P ((EC_T_BYTE)0x26)
400 #define ECREG_SYNCMANAGER_1_W_T ((EC_T_BYTE)0x46)
401 #define ECREG_SYNCMANAGER_1_W_P_F ((EC_T_BYTE)0x27)
402 #define ECREG_SYNCMANAGER_3_R_P ((EC_T_BYTE)0x20)
403 #define ECREG_SYNCMANAGER_3_W_P ((EC_T_BYTE)0x24)
404 #define ECREG_SYNCMANAGER_3_W_T ((EC_T_BYTE)0x44)
405 #define ECREG_SYNCMANAGER_3_W_P_T ((EC_T_BYTE)0x64)
406 #define ECREG_SYNCMANAGER_3_R ((EC_T_BYTE)0x00)
407 #define ECREG_SYNCMANAGER_3_W ((EC_T_BYTE)0x04)
408 #define ECREG_SYNCMANAGER_1_R ((EC_T_BYTE)0x02)
409 #define ECREG_SYNCMANAGER_1_W ((EC_T_BYTE)0x06)
410 #define ECREG_SYNCMANAGER_1_W_F ((EC_T_BYTE)0x07)
411 #define ECREG_SYNCMANAGER_STATUS ((EC_T_WORD)0x0005)
412 #define ECREG_SYNCMANAGER_IRQ_WRITE ((EC_T_BYTE)0x01)
413 #define ECREG_SYNCMANAGER_IRQ_READ ((EC_T_BYTE)0x02)
414 #define ECREG_SYNCMANAGER_WATCHDOG ((EC_T_BYTE)0x04)
415 #define ECREG_SYNCMANAGER_1BUF_STATUS ((EC_T_BYTE)0x08)
416 #define ECREG_SYNCMANAGER_3BUF_MASK ((EC_T_BYTE)0x30)
417 #define ECREG_SYNCMANAGER_3BUF_1 ((EC_T_BYTE)0x00)
418 #define ECREG_SYNCMANAGER_3BUF_2 ((EC_T_BYTE)0x10)
419 #define ECREG_SYNCMANAGER_3BUF_3 ((EC_T_BYTE)0x20)
420 #define ECREG_SYNCMANAGER_ACTIVATE ((EC_T_WORD)0x0006)
421 #define ECREG_SYNCMANAGER_DISABLE ((EC_T_BYTE)0x00)
422 #define ECREG_SYNCMANAGER_ENABLE ((EC_T_BYTE)0x01)
423 #define ECREG_SYNCMANAGER_MBX_TOGGLE ((EC_T_BYTE)0x02)
424 #define ECREG_SYNCMANAGER_SM_LATCH_ECAT ((EC_T_BYTE)0x40)
425 #define ECREG_SYNCMANAGER_SM_LATCH_PDI ((EC_T_BYTE)0x80)
426 #define ECREG_SYNCMANAGER_UC_STATUS ((EC_T_WORD)0x0007)
429 /*****************************************************************************
430 * 0x0930: DC SPEED COUNTER START (ECM_DCS_SPEEDCOUNT_START)
431 *****************************************************************************/
432 #define ECM_DCS_SPEEDCOUNT_START_STD_VALUE ((EC_T_WORD)0x1000)
433 #define ECM_DCS_SPEEDCOUNT_START_BECK_VALUE ((EC_T_WORD)0x0800)
436 /*****************************************************************************
437 * 0x0980: DC CYCLIC UNIT CONTROL (ECM_DCS_DC_UNIT_CONTROL)
438 *****************************************************************************/
439 #define ECM_DCS_CTL_SYNCOUT ((EC_T_BYTE)0x01)
440 #define ECM_DCS_CTL_LATCHIN0 ((EC_T_BYTE)0x10)
441 #define ECM_DCS_CTL_LATCHIN1 ((EC_T_BYTE)0x20)
444 /*****************************************************************************
445 * 0x0981: DC ACTIVATION (ECM_DCS_DC_ACTIVATION_REGISTER)
446 *****************************************************************************/
447 #define ECM_DCS_ACT_SYNCOUTACTIVATION ((EC_T_BYTE)0x01)
448 #define ECM_DCS_ACT_SYNC0GENERATION ((EC_T_BYTE)0x02)
449 #define ECM_DCS_ACT_SYNC1GENERATION ((EC_T_BYTE)0x04)
450 #define ECM_DCS_ACT_AUTOACTIVATION ((EC_T_BYTE)0x08)
451 #define ECM_DCS_ACT_STARTTIME_EXTENSION ((EC_T_BYTE)0x10)
452 #define ECM_DCS_ACT_STARTTIME_PLAUSIBILITYCHECK ((EC_T_BYTE)0x20)
453 #define ECM_DCS_ACT_NEARFUTURE_CONFIGURATION ((EC_T_BYTE)0x40)
454 #define ECM_DCS_ACT_SYNCSIGNAL_DEBUGPULSE_VASILI ((EC_T_BYTE)0x80)
456 /*****************************************************************************
457 * 0x09a8: DC LATCHING (ECREG_DCL_CTRL_LATCH)
458 *****************************************************************************/
459 #define ECM_DCL_CTL_L0POS_SINGLE ((EC_T_BYTE)0)
460 #define ECM_DCL_CTL_L0NEG_SINGLE ((EC_T_BYTE)1)
461 #define ECM_DCL_CTL_L1POS_SINGLE ((EC_T_BYTE)8)
462 #define ECM_DCL_CTL_L1NEG_SINGLE ((EC_T_BYTE)9)
464 /*-/REGISTER BITDEFINITIONS--------------------------------------------------*/
466 /* SII (WORD) Offsets */
467 #define ESC_SII_REG_PDICONTROL ((EC_T_WORD)0x0000)
468 #define ESC_SII_REG_PDICONFIG ((EC_T_WORD)0x0001)
469 #define ESC_SII_REG_SYNCIMPULSELENGTH ((EC_T_WORD)0x0002)
470 #define ESC_SII_REG_EXTENDEDPDICONFIG ((EC_T_WORD)0x0003)
471 #define ESC_SII_REG_ALIASADDRESS ((EC_T_WORD)0x0004)
472 #define ESC_SII_REG_CHECKSUM ((EC_T_WORD)0x0007)
473 #define ESC_SII_REG_VENDORID ((EC_T_WORD)0x0008)
474 #define ESC_SII_REG_PRODUCTCODE ((EC_T_WORD)0x000A)
475 #define ESC_SII_REG_REVISIONNUMBER ((EC_T_WORD)0x000C)
476 #define ESC_SII_REG_REVISIONNUMBER_LO ((EC_T_WORD)0x000C)
477 #define ESC_SII_REG_REVISIONNUMBER_HI ((EC_T_WORD)0x000D)
478 #define ESC_SII_REG_SERIALNUMBER ((EC_T_WORD)0x000E)
479 #define ESC_SII_REG_BOOT_RECV_MBX ((EC_T_WORD)0x0014)
480 #define ESC_SII_REG_BOOT_RECV_MBX_OFFSET ((EC_T_WORD)0x0014)
481 #define ESC_SII_REG_BOOT_RECV_MBX_SIZE ((EC_T_WORD)0x0015)
482 #define ESC_SII_REG_BOOT_SEND_MBX ((EC_T_WORD)0x0016)
483 #define ESC_SII_REG_BOOT_SEND_MBX_OFFSET ((EC_T_WORD)0x0016)
484 #define ESC_SII_REG_BOOT_SEND_MBX_SIZE ((EC_T_WORD)0x0017)
485 #define ESC_SII_REG_STD_RECV_MBX ((EC_T_WORD)0x0018)
486 #define ESC_SII_REG_STD_RECV_MBX_OFFSET ((EC_T_WORD)0x0018)
487 #define ESC_SII_REG_STD_RECV_MBX_SIZE ((EC_T_WORD)0x0019)
488 #define ESC_SII_REG_STD_SEND_MBX ((EC_T_WORD)0x001A)
489 #define ESC_SII_REG_STD_SEND_MBX_OFFSET ((EC_T_WORD)0x001A)
490 #define ESC_SII_REG_STD_SEND_MBX_SIZE ((EC_T_WORD)0x001B)
491 #define ESC_SII_REG_MBX_PROTOCOL ((EC_T_WORD)0x001C)
492 #define ESC_SII_REG_FIRSTCATEGORYHDR ((EC_T_WORD)0x0040)
494 /*-SII category types--------------------------------------------------------*/
495 #define ESC_SII_CAT_HDRSIZE ((EC_T_WORD)2)
496 #define ESC_SII_CAT_NOP ((EC_T_WORD)0)
497 #define ESC_SII_CAT_FMMU ((EC_T_WORD)40)
498 #define ESC_SII_CAT_SYNCM ((EC_T_WORD)41)
499 #define ESC_SII_CAT_TXPDO ((EC_T_WORD)50)
500 #define ESC_SII_CAT_RXPDO ((EC_T_WORD)51)
501 #define ESC_SII_CAT_DC ((EC_T_WORD)60)
502 #define ESC_SII_CAT_END ((EC_T_WORD)0xFFFF)
504 /* SII category FMMU --------------------------------------------------------*/
505 #define ESC_SII_CAT_FMMU_OUTPUT ((EC_T_BYTE)0x01)
506 #define ESC_SII_CAT_FMMU_INPUT ((EC_T_BYTE)0x02)
507 #define ESC_SII_CAT_FMMU_MAILBOX ((EC_T_BYTE)0x03)
509 /* SII category SYNCM / (BYTE) offsets---------------------------------------*/
510 #define ESC_SII_CAT_SYNCM_ENTRYSIZE ((EC_T_BYTE)0x08)
511 #define ESC_SII_CAT_SYNCM_REG_STARTADDRESS ((EC_T_BYTE)0x00)
512 #define ESC_SII_CAT_SYNCM_REG_LENGTH ((EC_T_BYTE)0x02)
513 #define ESC_SII_CAT_SYNCM_REG_CONTROL ((EC_T_BYTE)0x04)
514 #define ESC_SII_CAT_SYNCM_REG_ENABLE ((EC_T_BYTE)0x06)
515 #define ESC_SII_CAT_SYNCM_REG_TYPE ((EC_T_BYTE)0x07)
517 #define ESC_SII_CAT_SYNCM_ENABLE_ENABLED ((EC_T_BYTE)0x01)
518 #define ESC_SII_CAT_SYNCM_ENABLE_FIXCONTENT ((EC_T_BYTE)0x02)
519 #define ESC_SII_CAT_SYNCM_ENABLE_VIRTUAL ((EC_T_BYTE)0x04)
520 #define ESC_SII_CAT_SYNCM_ENABLE_OP_ONLY ((EC_T_BYTE)0x08)
522 #define ESC_SII_CAT_SYNCM_TYPE_NOTUSED ((EC_T_BYTE)0x00)
523 #define ESC_SII_CAT_SYNCM_TYPE_MBXOUT ((EC_T_BYTE)0x01)
524 #define ESC_SII_CAT_SYNCM_TYPE_MBXIN ((EC_T_BYTE)0x02)
525 #define ESC_SII_CAT_SYNCM_TYPE_PDOUT ((EC_T_BYTE)0x03)
526 #define ESC_SII_CAT_SYNCM_TYPE_PDIN ((EC_T_BYTE)0x04)
528 /* SII category TX/RX PDO / (BYTE) offsets-----------------------------------*/
529 #define ESC_SII_CAT_PDOLIST_SIZE ((EC_T_BYTE)0x08)
530 #define ESC_SII_CAT_PDOLIST_INDEX ((EC_T_BYTE)0x00)
531 #define ESC_SII_CAT_PDOLIST_NUMOFENTRIES ((EC_T_BYTE)0x02)
532 #define ESC_SII_CAT_PDOLIST_SYNCM ((EC_T_BYTE)0x03)
534 #define ESC_SII_CAT_PDO_ENTRYSIZE ((EC_T_BYTE)0x08)
535 #define ESC_SII_CAT_PDO_INDEX ((EC_T_BYTE)0x00)
536 #define ESC_SII_CAT_PDO_SUBINDEX ((EC_T_BYTE)0x02)
537 #define ESC_SII_CAT_PDO_NAMEIDX ((EC_T_BYTE)0x03)
538 #define ESC_SII_CAT_PDO_TYPEIDX ((EC_T_BYTE)0x04)
539 #define ESC_SII_CAT_PDO_BITLEN ((EC_T_BYTE)0x05)
541 #define ESC_SII_CAT_DC_ENTRYSIZE ((EC_T_BYTE)0x18)
542 #define ESC_SII_CAT_DC_SYNC0_CYCLE_TIME ((EC_T_BYTE)0x00)
543 #define ESC_SII_CAT_DC_SYNC0_SHIFT_TIME ((EC_T_BYTE)0x04)
544 #define ESC_SII_CAT_DC_SYNC1_SHIFT_TIME ((EC_T_BYTE)0x08)
545 #define ESC_SII_CAT_DC_SYNC1_CYCLE_FACTOR ((EC_T_BYTE)0x0C)
546 #define ESC_SII_CAT_DC_REG_ACTIVATION ((EC_T_BYTE)0x0E)
547 #define ESC_SII_CAT_DC_SYNC0_CYCLE_FACTOR ((EC_T_BYTE)0x10)
548 #define ESC_SII_CAT_DC_NAMEIDX ((EC_T_BYTE)0x12)
549 #define ESC_SII_CAT_DC_DESCIDX ((EC_T_BYTE)0x13)
551 #endif /* INC_ECESCREG */
553 /*-END OF SOURCE FILE--------------------------------------------------------*/