author | Alexei Fedorov <Alexei.Fedorov@arm.com> | |
Wed, 25 Nov 2020 14:07:05 +0000 (14:07 +0000) | ||
committer | Alexei Fedorov <Alexei.Fedorov@arm.com> | |
Mon, 30 Nov 2020 15:24:52 +0000 (15:24 +0000) | ||
commit | a83103c8240b02c38688aaf18fed2222ffa467b7 | |
tree | 8e1048899d637558b56fe326e48d55ed75464be8 | tree | snapshot (tar.xz tar.gz zip) |
parent | 20c378920e4deea3430a5eb50e407eff2c339e37 | commit | diff |
Aarch64: Add support for FEAT_PANx extensions
This patch provides the changes listed below:
- Adds new bit fields definitions for SCTLR_EL1/2 registers
- Corrects the name of SCTLR_EL1/2.[20] bit field from
SCTLR_UWXN_BIT to SCTLR_TSCXT_BIT
- Adds FEAT_PANx bit field definitions and their possible
values for ID_AA64MMFR1_EL1 register.
- Adds setting of SCTLR_EL1.SPAN bit to preserve PSTATE.PAN
on taking an exception to EL1 in spm_sp_setup() function
(services\std_svc\spm_mm\spm_mm_setup.c)
Change-Id: If51f20e7995c649126a7728a4d0867041fdade19
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This patch provides the changes listed below:
- Adds new bit fields definitions for SCTLR_EL1/2 registers
- Corrects the name of SCTLR_EL1/2.[20] bit field from
SCTLR_UWXN_BIT to SCTLR_TSCXT_BIT
- Adds FEAT_PANx bit field definitions and their possible
values for ID_AA64MMFR1_EL1 register.
- Adds setting of SCTLR_EL1.SPAN bit to preserve PSTATE.PAN
on taking an exception to EL1 in spm_sp_setup() function
(services\std_svc\spm_mm\spm_mm_setup.c)
Change-Id: If51f20e7995c649126a7728a4d0867041fdade19
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
include/arch/aarch64/arch.h | diff | blob | history | |
services/std_svc/spm_mm/spm_mm_setup.c | diff | blob | history |