atf/arm-trusted-firmware.git
4 months agoMerge changes from topic "marvell-a3k-makefile" into integration master
Manish Pandey [Mon, 7 Dec 2020 11:29:46 +0000 (11:29 +0000)]
Merge changes from topic "marvell-a3k-makefile" into integration

* changes:
  plat: marvell: armada: a3k: Simplify check if WTP variable is defined
  plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
  plat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB
  plat: marvell: armada: Add missing FORCE, .PHONY and clean targets
  plat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT) code
  plat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
  plat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF-A repository
  plat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG)
  plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)

4 months agoplat: marvell: armada: a3k: Simplify check if WTP variable is defined
Pali Rohár [Thu, 3 Dec 2020 11:00:47 +0000 (12:00 +0100)]
plat: marvell: armada: a3k: Simplify check if WTP variable is defined

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ieb352f0765882efdcb64ef54e6b2a39768590a06

4 months agoplat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
Pali Rohár [Mon, 23 Nov 2020 18:49:23 +0000 (19:49 +0100)]
plat: marvell: armada: a3k: Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)

These two targets are build by make subprocesses and are independent.
So splitting them into own targets allow make to build them in parallel.
$(TIMBUILD) script depends on $(TIMDDRTOOL) so specify it in Makefile.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I139fc7fe64d8de275b01a853e15bfb88c4ff840d

4 months agoplat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB
Pali Rohár [Thu, 3 Dec 2020 10:59:53 +0000 (11:59 +0100)]
plat: marvell: armada: Maximal size of bl1 image in mrvl_bootimage is 128kB

Add check when building mrvl_bootimage that size of bl1 image is not bigger
than maximal size.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ib873debd3cfdba9acd4c168ee37edab3032e9f25

4 months agoplat: marvell: armada: Add missing FORCE, .PHONY and clean targets
Pali Rohár [Mon, 23 Nov 2020 18:45:28 +0000 (19:45 +0100)]
plat: marvell: armada: Add missing FORCE, .PHONY and clean targets

FORCE target is used as a dependency for other file targets which needs to
be always rebuilt. .PHONY target is standard Makefile target which specify
non-file targets and therefore needs to be always rebuilt.

Targets clean, realclean and distclean are .PHONY targets used to remove
built files. Correctly set that mrvl_clean target is prerequisite for these
clean targets to ensure that built files are removed.

Finally this change with usage of FORCE target allows to remove mrvl_clean
hack from the prerequisites of a8k ${DOIMAGETOOL} target which was used
just to ensure that ${DOIMAGETOOL} is always rebuilt via make subprocess.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2fa8971244b43f101d846fc433ef7b0b6f139c92

4 months agoplat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT...
Pali Rohár [Mon, 23 Nov 2020 18:37:28 +0000 (19:37 +0100)]
plat: marvell: armada: a3k: Use make ifeq/endif syntax for $(MARVELL_SECURE_BOOT) code

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Id766db4a900a56c795fe5ffdd8a2b80b1aaa2132

4 months agoplat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
Pali Rohár [Mon, 23 Nov 2020 18:34:43 +0000 (19:34 +0100)]
plat: marvell: armada: a3k: Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Iaecd6c24bf334a959ac2bf395c3ee49c810b01a7

4 months agoplat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF...
Pali Rohár [Mon, 23 Nov 2020 18:22:37 +0000 (19:22 +0100)]
plat: marvell: armada: a3k: Do not remove external WTMI image files outside of TF-A repository

Create copy of WTMI images instead of moving them into TF-A build directory.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2dc24c33b9ce540e4acde51fc1a5c946ae66a5d7

4 months agoplat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG)
Pali Rohár [Mon, 23 Nov 2020 18:19:04 +0000 (19:19 +0100)]
plat: marvell: armada: a3k: Do not modify $(WTMI_MULTI_IMG)

Rather create a temporary copy in $(BUILD_PLAT) and modify only copy.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I256c029106ea6f69faa086fc4e5bee9f68cd257f

4 months agoplat: marvell: armada: a3k: Do not modify $(WTMI_IMG)
Pali Rohár [Mon, 23 Nov 2020 18:14:40 +0000 (19:14 +0100)]
plat: marvell: armada: a3k: Do not modify $(WTMI_IMG)

$(WTMI_IMG) is used only by $(MAKE) subprocess in $(DOIMAGEPATH) directory.
So calling truncate on $(WTMI_IMG) after $(MAKE) in $(DOIMAGEPATH) has no
effect and can just damage input file for future usage. Therefore remove
this truncate call.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I9925c54c5d3d10eadc19825c5565ad4598a739a7

4 months agoMerge "qemu/qemu_sbsa: increase SHARED_RAM_SIZE" into integration
Madhukar Pappireddy [Mon, 7 Dec 2020 03:40:39 +0000 (03:40 +0000)]
Merge "qemu/qemu_sbsa: increase SHARED_RAM_SIZE" into integration

4 months agoMerge "plat: xilinx: zynqmp: Include GICv2 makefile" into integration
Madhukar Pappireddy [Sat, 5 Dec 2020 23:28:25 +0000 (23:28 +0000)]
Merge "plat: xilinx: zynqmp: Include GICv2 makefile" into integration

4 months agoplat: xilinx: zynqmp: Include GICv2 makefile
Venkatesh Yadav Abbarapu [Fri, 4 Dec 2020 03:27:18 +0000 (20:27 -0700)]
plat: xilinx: zynqmp: Include GICv2 makefile

Update the xilinx platform makefile to include GICv2 makefile
instead of adding the individual files. Updating this change
as per the latest changes done in the commit #1322dc94f7.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Change-Id: I79d8374c47a7f42761d121522b32ac7a5021ede8

4 months agoMerge "plat: xilinx: Use fno-jump-tables flag in CPPFLAGS" into integration
Madhukar Pappireddy [Thu, 3 Dec 2020 16:58:59 +0000 (16:58 +0000)]
Merge "plat: xilinx: Use fno-jump-tables flag in CPPFLAGS" into integration

4 months agoMerge ".editorconfig: set max line length to 100" into integration
Manish Pandey [Thu, 3 Dec 2020 16:14:40 +0000 (16:14 +0000)]
Merge ".editorconfig: set max line length to 100" into integration

4 months agoMerge "plat: marvell: Update SUBVERSION to match Marvell's forked version" into integ...
Madhukar Pappireddy [Thu, 3 Dec 2020 15:51:50 +0000 (15:51 +0000)]
Merge "plat: marvell: Update SUBVERSION to match Marvell's forked version" into integration

4 months ago.editorconfig: set max line length to 100
Yann Gautier [Wed, 19 Aug 2020 17:07:26 +0000 (19:07 +0200)]
.editorconfig: set max line length to 100

Relax the 80 character line length, as done in checkpatch,
since Linux 5.7.

Change-Id: I093a2e6a45336339193173f7ff6a461279cf411d
Signed-off-by: Yann Gautier <yann.gautier@st.com>
4 months agoMerge "Aarch64: Add support for FEAT_PANx extensions" into integration
Manish Pandey [Thu, 3 Dec 2020 13:08:02 +0000 (13:08 +0000)]
Merge "Aarch64: Add support for FEAT_PANx extensions" into integration

4 months agoMerge "Aarch64: Add support for FEAT_MTE3" into integration
Olivier Deprez [Thu, 3 Dec 2020 11:02:26 +0000 (11:02 +0000)]
Merge "Aarch64: Add support for FEAT_MTE3" into integration

4 months agoMerge "rockchip: Add support for the stack protector" into integration
Madhukar Pappireddy [Wed, 2 Dec 2020 18:26:47 +0000 (18:26 +0000)]
Merge "rockchip: Add support for the stack protector" into integration

4 months agoAarch64: Add support for FEAT_MTE3
Alexei Fedorov [Tue, 1 Dec 2020 13:22:25 +0000 (13:22 +0000)]
Aarch64: Add support for FEAT_MTE3

This patch provides the following changes:
- Adds definition for FEAT_MTE3 value in ID_AA64PFR1_EL1 register
- Enables Memory Tagging Extension for FEAT_MTE3.

Change-Id: I735988575466fdc083892ec12c1aee89b5faa472
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
4 months agoMerge "Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms...
Manish Pandey [Wed, 2 Dec 2020 12:18:02 +0000 (12:18 +0000)]
Merge "Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms" into integration

4 months agoMerge "Add support for Neoverse-N2 CPUs." into integration
Lauren Wehrmeister [Tue, 1 Dec 2020 17:06:46 +0000 (17:06 +0000)]
Merge "Add support for Neoverse-N2 CPUs." into integration

4 months agoqemu/qemu_sbsa: increase SHARED_RAM_SIZE
Masato Fukumori [Tue, 1 Dec 2020 13:17:27 +0000 (22:17 +0900)]
qemu/qemu_sbsa: increase SHARED_RAM_SIZE

Increase SHARED_RAM_SIZE in sbsa_qemu platform from 4KB to 8KB.

sbsa_qemu uses SHARED_RAM for mail box and hold state of each cpus. If
qemu is configured with 512 cpus, region size used by qemu is greater
than 4KB.

Signed-off-by: Masato Fukumori <masato.fukumori@linaro.org>
Change-Id: I639e44e89335249d385cdc339350f509e9bd5e36

4 months agorockchip: Add support for the stack protector
Christoph Müllner [Fri, 20 Nov 2020 21:06:16 +0000 (22:06 +0100)]
rockchip: Add support for the stack protector

It uses the system timer as "entropy" source in the same
way as QEMU, layerscape and others.

Change-Id: Icda17b78e85255bea96109ca2ee0e091187d62ac
Signed-off-by: Christoph Müllner <christophm30@gmail.com>
4 months agoAdd support for Neoverse-N2 CPUs.
Javier Almansa Sobrino [Fri, 23 Oct 2020 12:22:07 +0000 (13:22 +0100)]
Add support for Neoverse-N2 CPUs.

Enable basic support for Neoverse-N2 CPUs.

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad

4 months agoAarch64: Add support for FEAT_PANx extensions
Alexei Fedorov [Wed, 25 Nov 2020 14:07:05 +0000 (14:07 +0000)]
Aarch64: Add support for FEAT_PANx extensions

This patch provides the changes listed below:
- Adds new bit fields definitions for SCTLR_EL1/2 registers
- Corrects the name of SCTLR_EL1/2.[20] bit field from
SCTLR_UWXN_BIT to SCTLR_TSCXT_BIT
- Adds FEAT_PANx bit field definitions and their possible
values for ID_AA64MMFR1_EL1 register.
- Adds setting of SCTLR_EL1.SPAN bit to preserve PSTATE.PAN
on taking an exception to EL1 in spm_sp_setup() function
(services\std_svc\spm_mm\spm_mm_setup.c)

Change-Id: If51f20e7995c649126a7728a4d0867041fdade19
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
4 months agoMerge changes from topic "xilinx-pm-mainline-linux" into integration
Manish Pandey [Mon, 30 Nov 2020 12:05:11 +0000 (12:05 +0000)]
Merge changes from topic "xilinx-pm-mainline-linux" into integration

* changes:
  zynqmp: pm: update error codes to match Linux and PMU Firmware
  zynqmp: pm: Filter errors related to clock gate permissions

4 months agoMerge "mediatek: mt8183: add timer V20 compensation" into integration
Manish Pandey [Fri, 27 Nov 2020 11:11:39 +0000 (11:11 +0000)]
Merge "mediatek: mt8183: add timer V20 compensation" into integration

4 months agoMerge changes I5ad52909,Iea3214a2 into integration
Manish Pandey [Tue, 24 Nov 2020 12:04:42 +0000 (12:04 +0000)]
Merge changes I5ad52909,Iea3214a2 into integration

* changes:
  fdts: Add VirtIO network device to Morello FVP
  fdts: Remove "virtio-rng" from Morello FVP

4 months agoMerge "plat:qti Mandate SMC implementaion" into integration
Manish Pandey [Mon, 23 Nov 2020 10:29:48 +0000 (10:29 +0000)]
Merge "plat:qti Mandate SMC implementaion" into integration

4 months agofdts: Add VirtIO network device to Morello FVP
Jessica Clarke [Sun, 25 Oct 2020 18:18:47 +0000 (18:18 +0000)]
fdts: Add VirtIO network device to Morello FVP

Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: I5ad5290925f637b94168b507b3dcbdd5e1b82e5a

4 months agofdts: Remove "virtio-rng" from Morello FVP
Jessica Clarke [Sun, 25 Oct 2020 18:10:24 +0000 (18:10 +0000)]
fdts: Remove "virtio-rng" from Morello FVP

This is not a standard string that any kernel recognises, nor do any of
the FDTs embedded in kernels specify this, nor does QEMU's virt machine.
Whilst its presence does no harm, it's not a thing code should consult
as a result, and so drop it in order to not cause confusion and risk
incorrect code being written to search for it.

Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: Iea3214a23181c54e600cf8f4f12dfc822140c23d

4 months agoMerge "plat/nvidia: tegra: Rename SMC API" into integration
Madhukar Pappireddy [Fri, 20 Nov 2020 15:36:37 +0000 (15:36 +0000)]
Merge "plat/nvidia: tegra: Rename SMC API" into integration

4 months agoMerge "plat/qemu_sbsa: Include libraries for Cortex-A72" into integration
Manish Pandey [Fri, 20 Nov 2020 12:30:10 +0000 (12:30 +0000)]
Merge "plat/qemu_sbsa: Include libraries for Cortex-A72" into integration

4 months agoplat/qemu_sbsa: Include libraries for Cortex-A72
Tanmay Jagdale [Fri, 20 Nov 2020 11:06:50 +0000 (16:36 +0530)]
plat/qemu_sbsa: Include libraries for Cortex-A72

Include libraries needed to emulate Cortex-A72 on
sbsa-ref target of QEMU.

Signed-off-by: Tanmay Jagdale <tanmay.jagdale@linaro.org>
Change-Id: I98cf17b1662c70898977a841af07e07b5cfca8ba

4 months agoplat/nvidia: tegra: Rename SMC API
Manish V Badarkhe [Thu, 19 Nov 2020 19:52:41 +0000 (19:52 +0000)]
plat/nvidia: tegra: Rename SMC API

Renamed SMC API from "plat_smccc_feature_available" to
"plat_is_smccc_feature_available" as per the current implementation.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ib0fa400816fba61039c2029a9e127501a6a36811

4 months agoplat:qti Mandate SMC implementaion
Saurabh Gorecha [Thu, 19 Nov 2020 19:35:47 +0000 (01:05 +0530)]
plat:qti Mandate SMC implementaion

renamed smcc api with correct name  plat_is_smccc_feature_available

Change-Id: I277ece02bffc2caa065256576c1a047dfcde1c92
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
4 months agoMerge changes from topic "mrvl_bootimage" into integration
Manish Pandey [Thu, 19 Nov 2020 11:18:26 +0000 (11:18 +0000)]
Merge changes from topic "mrvl_bootimage" into integration

* changes:
  docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes
  plat: marvell: armada: Add new target mrvl_bootimage
  plat: marvell: armada: a3k: Add support for building $(DOIMAGETOOL)

4 months agoplat: marvell: Update SUBVERSION to match Marvell's forked version
Pali Rohár [Tue, 10 Nov 2020 15:34:48 +0000 (16:34 +0100)]
plat: marvell: Update SUBVERSION to match Marvell's forked version

Marvell's TF-A fork has SUBVERSION set to devel-18.12.2.

The only differences between Marvell's devel-18.12.0 and devel-18.12.2
versions are documentation updates and cherry-picked patches from TF-A
upstream repository.

So upstream TF-A has already all changes from Marvell's TF-A devel-18.12.2
fork and therefore update SUBVERSION to reflect this state.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ce946a5176a5cbf124acd8037392463d586b072

4 months agodocs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash...
Pali Rohár [Thu, 29 Oct 2020 16:44:27 +0000 (17:44 +0100)]
docs: marvell: Update build documentation to reflect mrvl_bootimage and mrvl_flash changes

Also add example how to build TF-A for A3720 Turris MOX board and also fix
style/indentation issues and information about default values.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I2dc957307b1b627b403a8d960e85f5ac9e15aee5

4 months agoplat: marvell: armada: Add new target mrvl_bootimage
Pali Rohár [Thu, 29 Oct 2020 15:50:19 +0000 (16:50 +0100)]
plat: marvell: armada: Add new target mrvl_bootimage

This new target builds boot-image.bin binary as described in documentation.
This image does not contain WTMI image and therefore WTP repository is not
required for building.

Having ability to build just this boot-image.bin binary without full
flash-image.bin is useful for A3720 Turris MOX board which does not use
Marvell's WTP and a3700_utils.

To reduce duplicity between a8k and a3k code, define this new target and
also definitions for $(BUILD_PLAT)/$(BOOT_IMAGE) in common include file
marvell_common.mk.

For this purpose it is needed to include plat/marvell/marvell.mk file from
a3700_common.mk unconditionally (and not only when WTP is defined). Now
when common file plat/marvell/marvell.mk does not contain definition for
building $(DOIMAGETOOL), it is possible to move its inclusion at the top of
the a3700_common.mk file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: Ic58303b37a1601be9a06ff83b7a279cb7cfc8280

4 months agoplat: marvell: armada: a3k: Add support for building $(DOIMAGETOOL)
Pali Rohár [Thu, 29 Oct 2020 15:44:45 +0000 (16:44 +0100)]
plat: marvell: armada: a3k: Add support for building $(DOIMAGETOOL)

Current binary wtptp/linux/tbb_linux which is specified in $(DOIMAGETOOL)
variable points to external pre-compiled Marvell x86_64 ELF linux binary
from A3700-utils-marvell WTP repository.

It means that currently it is not possible to compile TF-A for A3720 on
other host platform then linux x86_64.

Part of the A3700-utils-marvell WTP repository is also source code of
$(DOIMAGETOOL) TBB_Linux tool.

This change adds support for building $(DOIMAGETOOL) also for a3k platform.

After running $(MAKE) at appropriate subdirectory of A3700-utils-marvell
WTP repository, compiled TBB_linux tool will appear in WTP subdirectory
wtptp/src/TBB_Linux/release/. So update also $(DOIMAGETOOL) variable to
point to the correct location where TBB_linux was built.

To build TBB_linux it is required to compile external Crypto++ library
which is available at: https://github.com/weidai11/cryptopp.git

User needs to set CRYPTOPP_PATH option to specify path to that library.

After this change it is now possible to build whole firmware for A3720
platform without requirement to use pre-compiled/proprietary x86_64
executable binaries from Marvell.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I6f26bd4356778a2f8f730a223067a2e550e6c8e0

4 months agoMerge "Revert workaround for A77 erratum 1800714" into integration
Madhukar Pappireddy [Thu, 19 Nov 2020 01:30:49 +0000 (01:30 +0000)]
Merge "Revert workaround for A77 erratum 1800714" into integration

4 months agoMerge "Revert workaround for A76 erratum 1800710" into integration
Madhukar Pappireddy [Thu, 19 Nov 2020 01:30:42 +0000 (01:30 +0000)]
Merge "Revert workaround for A76 erratum 1800710" into integration

4 months agoMerge "Fix typos and misspellings" into integration
Madhukar Pappireddy [Thu, 19 Nov 2020 00:31:29 +0000 (00:31 +0000)]
Merge "Fix typos and misspellings" into integration

4 months agoMerge "TSP: Fix GCC 11.0.0 compilation error." into integration
Madhukar Pappireddy [Wed, 18 Nov 2020 18:14:14 +0000 (18:14 +0000)]
Merge "TSP: Fix GCC 11.0.0 compilation error." into integration

4 months agoMerge "Makefile: Update the minor version to indicate 2.4 release" into integration v2.4 v2.4-rc1 v2.4-rc2
Manish Pandey [Tue, 17 Nov 2020 16:43:51 +0000 (16:43 +0000)]
Merge "Makefile: Update the minor version to indicate 2.4 release" into integration

4 months agoMakefile: Update the minor version to indicate 2.4 release
Manish V Badarkhe [Thu, 8 Oct 2020 01:33:17 +0000 (02:33 +0100)]
Makefile: Update the minor version to indicate 2.4 release

Updated the minor version to '4' to indicate 2.4 release

Change-Id: Ib142fa15baeb43025fae371c7649199b8121c18f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
4 months agoMerge "docs: Update changelog for v2.4 release" into integration
Joanna Farley [Tue, 17 Nov 2020 14:32:01 +0000 (14:32 +0000)]
Merge "docs: Update changelog for v2.4 release" into integration

4 months agodocs: Update changelog for v2.4 release
Chris Kay [Thu, 29 Oct 2020 14:28:59 +0000 (14:28 +0000)]
docs: Update changelog for v2.4 release

Change-Id: I67c9db2fc6d4b83fec2d001745b9305102d4a2ae
Signed-off-by: Chris Kay <chris.kay@arm.com>
5 months agoTSP: Fix GCC 11.0.0 compilation error.
Alexei Fedorov [Fri, 13 Nov 2020 12:36:49 +0000 (12:36 +0000)]
TSP: Fix GCC 11.0.0 compilation error.

This patch fixes the following compilation error
reported by aarch64-none-elf-gcc 11.0.0:

bl32/tsp/tsp_main.c: In function 'tsp_smc_handler':
bl32/tsp/tsp_main.c:393:9: error: 'tsp_get_magic'
 accessing 32 bytes in a region of size 16
 [-Werror=stringop-overflow=]
  393 |         tsp_get_magic(service_args);
      |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~
bl32/tsp/tsp_main.c:393:9: note: referencing argument 1
 of type 'uint64_t *' {aka 'long long unsigned int *'}
In file included from bl32/tsp/tsp_main.c:19:
bl32/tsp/tsp_private.h:64:6: note: in a call to function 'tsp_get_magic'
   64 | void tsp_get_magic(uint64_t args[4]);
      |      ^~~~~~~~~~~~~

by changing declaration of tsp_get_magic function from
void tsp_get_magic(uint64_t args[4]);
to
uint128_t tsp_get_magic(void);
which returns arguments directly in x0 and x1 registers.

In bl32\tsp\tsp_main.c the current tsp_smc_handler()
implementation calls tsp_get_magic(service_args);
, where service_args array is declared as
uint64_t service_args[2];
and tsp_get_magic() in bl32\tsp\aarch64\tsp_request.S
copies only 2 registers in output buffer:
/* Store returned arguments to the array */
stp x0, x1, [x4, #0]

Change-Id: Ib34759fc5d7bb803e6c734540d91ea278270b330
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
5 months agoRevert workaround for A77 erratum 1800714
johpow01 [Thu, 12 Nov 2020 20:15:41 +0000 (14:15 -0600)]
Revert workaround for A77 erratum 1800714

This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe

5 months agoRevert workaround for A76 erratum 1800710
johpow01 [Thu, 12 Nov 2020 19:32:00 +0000 (13:32 -0600)]
Revert workaround for A76 erratum 1800710

This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0

5 months agoFix typos and misspellings
David Horstmann [Thu, 12 Nov 2020 15:19:04 +0000 (15:19 +0000)]
Fix typos and misspellings

Fix a number of typos and misspellings in TF-A
documentation and comments.

Signed-off-by: David Horstmann <david.horstmann@arm.com>
Change-Id: I34c5a28c3af15f28d1ccada4d9866aee6af136ee

5 months agoAdd myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms
Michal Simek [Thu, 12 Nov 2020 10:19:48 +0000 (11:19 +0100)]
Add myself and Venkatesh Yadav Abbarapu as code owners for Xilinx platforms

Jolly left the company and Siva (DP) has moved to different possition
that's why it is necessary to change code ownership.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I546d9a0f7a2abd0c7a65be807725bc609160f3b2

5 months agoplat: xilinx: Use fno-jump-tables flag in CPPFLAGS
Venkatesh Yadav Abbarapu [Tue, 14 Jul 2020 03:18:01 +0000 (21:18 -0600)]
plat: xilinx: Use fno-jump-tables flag in CPPFLAGS

From GCC-9 implementation of switch case was generated through jump tables,
because of which we are seeing 1MB increase in rodata section. To reduce
the size we are recommending to use fno-jump-tables.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I069733610809b8299fbf641f0ae35b359a8afd69

5 months agozynqmp: pm: update error codes to match Linux and PMU Firmware
Davorin Mista [Fri, 24 Aug 2018 15:09:06 +0000 (17:09 +0200)]
zynqmp: pm: update error codes to match Linux and PMU Firmware

All EEMI error codes start with value 2000.

Note: Legacy error codes ARGS (=1) and NOTSUPPORTED (=4) returned by
current ATF code have been left in place.

Signed-off-by: Davorin Mista <davorin.mista@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I939afa85957cac88025d82a80f9f6dd49be993b6

5 months agozynqmp: pm: Filter errors related to clock gate permissions
Mirela Simonovic [Fri, 24 Aug 2018 15:09:07 +0000 (17:09 +0200)]
zynqmp: pm: Filter errors related to clock gate permissions

Linux clock framework cannot properly deal with these errors. When the
error is related to the lack of permissions to control the clock we
filter the error and report the success to linux. Before recent changes
in clock framework across the stack, this was done in the PMU-FW as a
workaround. Since the PMU-FW now handles clocks and the permissions to
control them using general principles rather than workarounds, it can
no longer distinguish such exceptions and it has to return no-access
error.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>
Acked-by: Will Wong <WILLW@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change-Id: I1491a80e472f44e322a542b29a20eb1cb3319802

5 months agoMerge "make_helpers: tbbr: Fix FWU certificate generation" into integration
Manish Pandey [Mon, 9 Nov 2020 15:47:34 +0000 (15:47 +0000)]
Merge "make_helpers: tbbr: Fix FWU certificate generation" into integration

5 months agomake_helpers: tbbr: Fix FWU certificate generation
Manish V Badarkhe [Sun, 8 Nov 2020 17:38:57 +0000 (17:38 +0000)]
make_helpers: tbbr: Fix FWU certificate generation

Provide missed command line parameters such as KEY_ALG, HASH_ALG
and KEY_SIZE while generating the FWU certificate.

Signed-off-by: Gilad Ben Yossef <Gilad.BenYossef@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I017fa3fff844f4262ae2441cbc9fee909d357fb3

5 months agoMerge "Use constant stack size with RECLAIM_INIT_CODE" into integration v2.4-rc0
Alexei Fedorov [Thu, 29 Oct 2020 18:00:13 +0000 (18:00 +0000)]
Merge "Use constant stack size with RECLAIM_INIT_CODE" into integration

5 months agoMerge changes from topic "mbox-patches" into integration
Manish Pandey [Thu, 29 Oct 2020 11:17:01 +0000 (11:17 +0000)]
Merge changes from topic "mbox-patches" into integration

* changes:
  intel: common: Fix non-MISRA compliant code v2
  intel: mailbox: Fix non-MISRA compliant code
  intel: mailbox: Mailbox error recovery handling
  intel: mailbox: Enable sending large mailbox command
  intel: mailbox: Use retry count in mailbox poll
  intel: mailbox: Ensure time out duration is predictive
  intel: mailbox: Read mailbox response even there is an error
  intel: mailbox: Driver now handles larger response
  intel: common: Change how mailbox handles job id & buffer
  intel: common: Improve readability of mailbox read response
  intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
  intel: common: Remove urgent from mailbox async
  intel: common: Improve mailbox driver readability

5 months agoUse constant stack size with RECLAIM_INIT_CODE
David Horstmann [Wed, 14 Oct 2020 14:17:49 +0000 (15:17 +0100)]
Use constant stack size with RECLAIM_INIT_CODE

Currently, when RECLAIM_INIT_CODE is set, the
stacks are scaled to ensure that the entirety
of the init section can be reclaimed as stack.

This causes an issue in lib/psci/aarch64/psci_helpers.S,
where the stack size is used for cache operations in
psci_do_pwrdown_cache_maintenance(). If the stacks
are scaled, then the PSCI code may fail to invalidate
some of the stack memory before power down.

Resizing stacks is also not good for stability in general,
since code that works with a small number of cores may
overflow the stack when the number of cores is increased.

Change to make every stack be PLATFORM_STACK_SIZE big,
and allow the total stack to be smaller than the
init section.

Any pages of the init section not reclaimed as
stack will be set to read-only and execute-never,
for security.

Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8
Signed-off-by: David Horstmann <david.horstmann@arm.com>
5 months agoMerge "aarch64/arm: Add compiler barrier to barrier instructions" into integration
André Przywara [Wed, 28 Oct 2020 14:34:07 +0000 (14:34 +0000)]
Merge "aarch64/arm: Add compiler barrier to barrier instructions" into integration

5 months agoMerge changes from topic "mbox-patches" into integration
Manish Pandey [Wed, 28 Oct 2020 14:07:15 +0000 (14:07 +0000)]
Merge changes from topic "mbox-patches" into integration

* changes:
  intel: common: Clean up mailbox and sip header
  intel: clear 'PLAT_SEC_ENTRY' in early platform setup

5 months agoMerge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration
Manish Pandey [Wed, 28 Oct 2020 14:04:07 +0000 (14:04 +0000)]
Merge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration

* changes:
  mediatek: mt8192: add timer support
  mediatek: mt8192: Add reboot function for PSCI
  mediatek: mt8192: add sys_cirq driver
  mediatek: mt8192: add GPIO driver support

5 months agomediatek: mt8192: add timer support
Dehui Sun [Fri, 3 Jul 2020 01:19:06 +0000 (09:19 +0800)]
mediatek: mt8192: add timer support

add timer driver.

Signed-off-by: Dehui Sun <dehui.sun@mediatek.com>
Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7

5 months agomediatek: mt8192: Add reboot function for PSCI
Nina Wu [Thu, 2 Jul 2020 04:10:13 +0000 (12:10 +0800)]
mediatek: mt8192: Add reboot function for PSCI

Add system_reset function in psci ops

Change-Id: If85be70b8ae9d6487e02626356f0ff1e78b76de9
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
5 months agomediatek: mt8192: add sys_cirq driver
gtk_pangao [Thu, 19 Dec 2019 07:58:20 +0000 (15:58 +0800)]
mediatek: mt8192: add sys_cirq driver

1.add sys_cirq driver
2.add gic api for cirq

Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b
Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com>
5 months agoaarch64/arm: Add compiler barrier to barrier instructions
Andre Przywara [Fri, 16 Oct 2020 17:19:03 +0000 (18:19 +0100)]
aarch64/arm: Add compiler barrier to barrier instructions

When issuing barrier instructions like DSB or DMB, we must make sure
that the compiler does not undermine out efforts to fence off
instructions. Currently the compiler is free to move the barrier
instruction around, in respect to former or later memory access
statements, which is not what we want.

Add a compiler barrier to the inline assembly statement in our
DEFINE_SYSOP_TYPE_FUNC macro, to make sure memory accesses are not
reordered by the compiler.
This is in line with Linux' definition:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/include/asm/barrier.h

Since those instructions share a definition, apart from DSB and DMB this
now also covers some TLBI instructions. Having a compiler barrier there
also is useful, although we probably have stronger barriers in place
already.

Change-Id: If6fe97b13a562643a643efc507cb4aad29daa5b6
Reported-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
5 months agoMerge "plat: marvell: armada: Fix dependences for target fip" into integration
Manish Pandey [Tue, 27 Oct 2020 14:01:11 +0000 (14:01 +0000)]
Merge "plat: marvell: armada: Fix dependences for target fip" into integration

5 months agointel: common: Fix non-MISRA compliant code v2
Abdul Halim, Muhammad Hadi Asyrafi [Thu, 15 Oct 2020 07:27:18 +0000 (15:27 +0800)]
intel: common: Fix non-MISRA compliant code v2

This patch is used to fix remaining non compliant code for Intel
SoCFPGA's mailbox and sip driver. These changes include:
- Change non-interface required uint32_t into unsigned int
- Change non-negative variable to unsigned int
- Remove obsolete variable initialization to 0

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5

5 months agointel: mailbox: Fix non-MISRA compliant code
Abdul Halim, Muhammad Hadi Asyrafi [Tue, 1 Sep 2020 13:05:18 +0000 (21:05 +0800)]
intel: mailbox: Fix non-MISRA compliant code

This patch is used to fix remaining non compliant code for Intel
SocFPGA's mailbox driver. These changes include:
- adding integer literal for unsigned constant
- fix non-boolean controlling expression
- add braces even on conditional single statement bodies

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I0f8fd96a3540f35ee102fd2f2369b76fa73e39e1

5 months agointel: mailbox: Mailbox error recovery handling
Chee Hong Ang [Mon, 11 May 2020 03:23:21 +0000 (11:23 +0800)]
intel: mailbox: Mailbox error recovery handling

Attempt to restart the mailbox if the mailbox driver not able
to write any data into the mailbox command buffer.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: Ia45291c985844dec9da82839cac701347534d32b

5 months agointel: mailbox: Enable sending large mailbox command
Abdul Halim, Muhammad Hadi Asyrafi [Mon, 1 Jun 2020 17:06:33 +0000 (01:06 +0800)]
intel: mailbox: Enable sending large mailbox command

Allow mailbox command that is larger than mailbox command FIFO buffer
size to be sent to SDM in multiple chunks.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I683d5f1d04c4fdf57d11ecae6232b7ed3fc49e26

5 months agointel: mailbox: Use retry count in mailbox poll
Abdul Halim, Muhammad Hadi Asyrafi [Mon, 1 Jun 2020 17:05:24 +0000 (01:05 +0800)]
intel: mailbox: Use retry count in mailbox poll

Change the main loop inside mailbox poll function from while(1) to a
retry counter named sdm_loop. This is to limit the maximum possible
looping of the function and prevent unexpected behaviour.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I63afad958fe5f656f6333b60d5a8b4c0ada3b23d

5 months agointel: mailbox: Ensure time out duration is predictive
Chee Hong Ang [Sun, 10 May 2020 16:55:01 +0000 (00:55 +0800)]
intel: mailbox: Ensure time out duration is predictive

For each count down of time out counter, wait for number of
miliseconds to ensure the time out duration is predictive.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b

5 months agointel: mailbox: Read mailbox response even there is an error
Chee Hong Ang [Sun, 10 May 2020 16:40:18 +0000 (00:40 +0800)]
intel: mailbox: Read mailbox response even there is an error

Mailbox driver should read the response data if the response length
in the response header is non-zero even the response header indicates
error (non-zero).

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640

5 months agointel: mailbox: Driver now handles larger response
Abdul Halim, Muhammad Hadi Asyrafi [Wed, 29 Apr 2020 14:26:40 +0000 (22:26 +0800)]
intel: mailbox: Driver now handles larger response

This patch factorizes mailbox read response from SDM into a function.
Also fix the logic to support reading larger than 16 words response from
SDM.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5

5 months agointel: common: Change how mailbox handles job id & buffer
Abdul Halim, Muhammad Hadi Asyrafi [Mon, 18 May 2020 03:16:48 +0000 (11:16 +0800)]
intel: common: Change how mailbox handles job id & buffer

This patch modifies several basic mailbox driver features to prepare for
FCS enablement:
- Job id management for asynchronous response
- SDM command buffer full

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2

5 months agoMerge "SPMC: adjust device region for first secure partition" into integration
Olivier Deprez [Mon, 26 Oct 2020 09:51:32 +0000 (09:51 +0000)]
Merge "SPMC: adjust device region for first secure partition" into integration

5 months agomediatek: mt8192: add GPIO driver support
Po Xu [Fri, 18 Sep 2020 01:32:31 +0000 (09:32 +0800)]
mediatek: mt8192: add GPIO driver support

add GPIO driver

Change-Id: I67a9abef078e7a62b34dfbd366b45c03892800cd
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
5 months agointel: common: Clean up mailbox and sip header
Abdul Halim, Muhammad Hadi Asyrafi [Thu, 14 May 2020 06:53:29 +0000 (14:53 +0800)]
intel: common: Clean up mailbox and sip header

Sort and rearrange definitions in both mailbox and sip header to
increase readability and maintainability.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856

5 months agointel: common: Improve readability of mailbox read response
Abdul Halim, Muhammad Hadi Asyrafi [Wed, 12 Feb 2020 11:57:44 +0000 (19:57 +0800)]
intel: common: Improve readability of mailbox read response

Rename variables to improve readability of mailbox read response and
mailbox poll response flow.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Icd33ff1d2abb28eeead15e4eb9c7f9629f8cb402

5 months agointel: clear 'PLAT_SEC_ENTRY' in early platform setup
Chee Hong Ang [Fri, 24 Apr 2020 13:51:00 +0000 (21:51 +0800)]
intel: clear 'PLAT_SEC_ENTRY' in early platform setup

Ensure 'PLAT_SEC_ENTRY' is cleared during early platform
setup. This is to prevent the slave CPU cores jump to the stale
entry point after warm reset when using U-Boot SPL as first
stage boot loader.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a

5 months agointel: SIP: increase FPGA_CONFIG_SIZE to 32 MB
Richard Gong [Mon, 13 Apr 2020 14:40:43 +0000 (09:40 -0500)]
intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB

Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher
pre-reserved memory size between Intel service layer and secure monitor
software so we can handle JIC file authorization.

Signed-off-by: Richard Gong <richard.gong@intel.com>
Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c

5 months agointel: common: Remove urgent from mailbox async
Abdul Halim, Muhammad Hadi Asyrafi [Mon, 18 May 2020 02:32:15 +0000 (10:32 +0800)]
intel: common: Remove urgent from mailbox async

Remove urgent argument from asynchrounous mailbox command as any urgent
command should always be synchronous

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319

5 months agointel: common: Improve mailbox driver readability
Abdul Halim, Muhammad Hadi Asyrafi [Thu, 14 May 2020 07:32:43 +0000 (15:32 +0800)]
intel: common: Improve mailbox driver readability

Use pre-defined macros for return values and common mailbox arguments

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e

5 months agoMerge "docs: marvell: update ddr3 build instructions" into integration
Varun Wadekar [Sat, 24 Oct 2020 02:30:21 +0000 (02:30 +0000)]
Merge "docs: marvell: update ddr3 build instructions" into integration

5 months agoMerge changes I5ae9d08b,I5cbbd7eb,Idb389223 into integration
Varun Wadekar [Sat, 24 Oct 2020 02:29:31 +0000 (02:29 +0000)]
Merge changes I5ae9d08b,I5cbbd7eb,Idb389223 into integration

* changes:
  plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k
  plat: marvell: armada: Fix including plat/marvell/marvell.mk file
  plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it

5 months agoMerge "plat/qemu_sbsa: Remove cortex_a53 and aem_generic" into integration
Manish Pandey [Thu, 22 Oct 2020 08:49:30 +0000 (08:49 +0000)]
Merge "plat/qemu_sbsa: Remove cortex_a53 and aem_generic" into integration

5 months agoSPMC: adjust device region for first secure partition
Olivier Deprez [Thu, 8 Oct 2020 06:38:58 +0000 (08:38 +0200)]
SPMC: adjust device region for first secure partition

For the first partition, mark first 2GB as device memory excluding
the Trusted DRAM region reserved for the SPMC.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I3ff110b3facf5b6d41ac2519ff6ca5e30a0a502b

5 months agoMerge changes from topic "tc0_sel2_spmc" into integration
Manish Pandey [Wed, 21 Oct 2020 21:14:42 +0000 (21:14 +0000)]
Merge changes from topic "tc0_sel2_spmc" into integration

* changes:
  plat: tc0: Configure TZC with secure world regions
  plat: tc0: Enable SPMC execution at S-EL2
  plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS
  plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled
  plat: tc0: Disable SPE

5 months agoMerge changes from topic "tc0_sel2_spmc" into integration
Manish Pandey [Wed, 21 Oct 2020 21:03:14 +0000 (21:03 +0000)]
Merge changes from topic "tc0_sel2_spmc" into integration

* changes:
  lib: el3_runtime: Fix SPE system registers in el2_sysregs_context
  lib: el3_runtime: Conditionally save/restore EL2 NEVE registers
  lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_context

5 months agoplat/qemu_sbsa: Remove cortex_a53 and aem_generic
Tomas Pilar [Tue, 11 Aug 2020 14:06:16 +0000 (15:06 +0100)]
plat/qemu_sbsa: Remove cortex_a53 and aem_generic

The qemu_sbsa platform uses 42bit address size but
the cortex-a53 only supports 40bit addressing, the
cpu is incompatible with the platform.

The aem_generic is also not used with qemu_sbsa, in
fact, the platform currently only properly supports
the cortex-a57 cpu.

Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14
Signed-off-by: Tomas Pilar <tomas@nuviateam.com>
5 months agoplat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k
Pali Rohár [Wed, 21 Oct 2020 09:50:40 +0000 (11:50 +0200)]
plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k

Currently a3k target is misusing ${DOIMAGETOOL} target for building flash
and UART images. It is not used for building image tool.

So move ${DOIMAGETOOL} target from common marvell include file into a8k
include file and add correct invocation of ${MAKE} into a3k for building
flash and UART images.

Part of this change is also checks that MV_DDR_PATH for a3k was specified
by user as this option is required for building a3k flash and UART images.

Signed-off-by: Pali Rohár <pali@kernel.org>
Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6

5 months agomediatek: mt8183: add timer V20 compensation
Fengquan Chen [Mon, 12 Oct 2020 08:33:25 +0000 (16:33 +0800)]
mediatek: mt8183: add timer V20 compensation

add timer driver.

Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.com>
Change-Id: I60a7273f922233a618a6163b802c0858ed89f75f

5 months agoMerge "docs: code review guidelines" into integration
Manish Pandey [Tue, 20 Oct 2020 20:19:35 +0000 (20:19 +0000)]
Merge "docs: code review guidelines" into integration

5 months agoplat: tc0: Configure TZC with secure world regions
Usama Arif [Wed, 26 Aug 2020 13:04:31 +0000 (14:04 +0100)]
plat: tc0: Configure TZC with secure world regions

This includes configuration for SPMC and trusted OS.

Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3
Signed-off-by: Usama Arif <usama.arif@arm.com>
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>