1 /******************************************************************************
2 * (C) Copyright 2013, Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
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17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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31 *
32 */
33 #include <stdio.h>
34 #include <time.h>
35 #include <c6x.h>
37 /*---------------------------------------------------------------------------*/
38 /* This program will initialize the C6678 configuration registers to utilize */
39 /* the L1 Cache, L2 Cache, and fix the MAR (Memory Attribute Registers) to */
40 /* make all memory cacheable and pre-fetchable. Here is the layout of */
41 /* control registers, specific to the C6678. They are memory-mapped */
42 /* registers; write to the location and the internal register gets written. */
43 /* All are 32-bit registers. */
44 /* */
45 /* Address Function Value */
46 /* 0x01840000 Level 2 Cache Config 0x==== 0007 (all cache) */
47 /* 0x01845004 L2 Write-back invalidate 0x0000 0001 (flushes L2 cache) */
48 /* 0x01840040 Level 1 Cache Config 0x==== 0007 (all cache) */
49 /* 0x01845044 L1 Write-back invalidate 0x0000 0001 (flushes L1 cache) */
50 /* 0x01848000 16 reserved read-only MAR registers. */
51 /* 0x01848040 240 MAR regs. |= 0x0000 0009 (8=prefetch, 1=cacheable) */
52 /* 0x018483FC Last of the MAR regs. */
53 /* For MAR regs, bits 1-2 are reserved, so we leave them as-is. */
54 /* MAR reg 16 controls memory 1000 0000h to 10FF FFFFh, */
55 /* MAR reg 17 controls memory 1100 0000h to 11FF FFFFh, etc, */
56 /* MAR rg 255 controls memory FF00 0000h to FFFF FFFFh. */
57 /* Notice that MAR16 holds range of L1 SRAM, DO NOT cache that page! */
58 /* L1 config 0--7 == disabled, 4K,8K,16K,32K,32K,32K, max (=32K) */
59 /* L2 config 0--7 == disabled, 32K,64K,128K,256K,512K,1M,max (=1M). */
60 /* We set our L2 to '5' because the link file, C6678_unified.cmd, maps our */
61 /* L2 space to just 512K. */
62 /* */
63 /* Interrupt stuff: */
64 /* 0x01800040 4 Event Clear Registers, to 0x0180004C. */
65 /* 0x01800080 4 Event Mask Registers, to 0x0180008C. */
66 /* 0x01800104 3 Interrupt Mux registers, to 0x0180010C. */
67 /* ISTP is the Interrupt Service Table pointer. */
68 /* ISTP & 0xFFFFC000 is the base address, +0x01E0 is INT15 ISR (8 words). */
69 /* IER is an actual register (not to be confused with the EDMA channel */
70 /* control memory-mapped IER registers) that controls whether interrupts */
71 /* 4..15 are enabled. */
72 /* */
73 /* Modified Oct 18: Set L1 to just 4K, so 28K could be used as fast ram. */
74 /* Modified Mar 4: Set L2 to just 256K, so 256K could be used as fast ram. */
75 /* Nov 29: Added code to report on mapping of EDMA3CC (DMA, QDMA transfers). */
76 /*---------------------------------------------------------------------------*/
77 int main(int argc, char **args)
78 {
79 TSCL=0; /* Always start real-time clock, just in case timing. */
80 volatile unsigned int *L1PCFG = (unsigned int *) (0x01840020);
81 volatile unsigned int *L1CFG = (unsigned int *) (0x01840040);
82 volatile unsigned int *L2CFG = (unsigned int *) (0x01840000);
83 volatile unsigned int *MAR = (unsigned int *) (0x01848040);
84 volatile unsigned int *DEVSTAT= (unsigned int *) (0x02620020);
85 // volatile unsigned int *EDMA3CC0 = (unsigned int*) (0x02700000ul);
86 // volatile unsigned int *CC0_QEER = (unsigned int*) (0x02701084ul);
87 // volatile unsigned int *CC0_EER = (unsigned int*) (0x02701020ul);
88 // volatile unsigned int *EDMA3CC1 = (unsigned int*) (0x02720000ul);
89 // volatile unsigned int *EDMA3CC2 = (unsigned int*) (0x02740000ul);
90 // volatile unsigned int *EVTMASKR = (unsigned int*) (0x01800080ul);
91 // volatile unsigned int *INTMUXR = (unsigned int*) (0x01800104ul);
92 // volatile unsigned int *INTSVCT = NULL;
93 unsigned int i, v;
95 v = *L1PCFG; /* Get value. */
96 printf("L1PCFG on entry: %08X.\n", v); /* Report it. */
97 v &= 0xFFFFFFF8; /* Force final bits 000b. */
98 v |= 0x00000007; /* Force final bits 111b. */
99 *L1PCFG = v; /* Configure L1P Cache. */
101 v = *L1CFG; /* Get value. */
102 printf("L1CFG on entry: %08X.\n", v); /* Report it. */
103 v &= 0xFFFFFFF8; /* Force final bits 000b. */
104 v |= 0x00000001; /* Force final bits 001b. */
105 /* (28K work, 4K cache). */
106 *L1CFG = v; /* Configure L1 Cache. */
108 v = *L2CFG; /* Get value. */
109 printf("L2CFG on entry: %08X.\n", v); /* Report it. */
110 v &= 0xFFFFFFF8; /* Force final bits 000b. */
111 v |= 0x00000004; /* Force final bits 100b. */
112 *L2CFG = v; /* Configure L2 Cache. */
114 v = *MAR; /* Get typical MAR value. */
115 printf("MAR[16] on entry: %08X.\n", v); /* Report it. */
116 MAR[0] = 0; /* range of L1D SRAM! */
117 v = *MAR; /* Read again. */
118 printf("MAR[16] Modified: %08X.\n", v); /* Report it. */
119 v = 0x00000009; /* Value for MAR register. */
120 for (i=1; i<240; i++) /* For all other MAR regs, */
121 MAR[i] |= v; /* Configure address range.*/
123 printf("Cache Setup Complete: L1CFG=%08X, L2CFG=%08X.\n", *L1CFG, *L2CFG);
124 printf("DEVSTAT: %08X.\n", *DEVSTAT);
125 fflush(stdout);
127 /* Report on setup of interrupts. */
128 // for (i=0; i<4; i++)
129 // printf("EVTMASKR[%1i]=%08X.\n", i, EVTMASKR[i]);
131 // for (i=0; i<3; i++)
132 // printf("INTMUXR[%1i]=%08X.\n", i, INTMUXR[i]);
134 // v = IER; // get the interrupt Enable ptr.
135 // printf("IER=%08X.\n", v); // Report.
137 // v = ISTP; // get the interrupt service table ptr.
138 // printf("ISTP=%08X.\n", v); // Report.
140 // v &= 0xFFFFFC00; // Clear low part.
141 // v |= 0x000001E0; // Interrupt 15.
142 // INTSVCT = (unsigned int*) (v); // Recast.
143 // for (i=0; i<8; i++)
144 // printf("ISR_15[%1i]=%08X.\n", i, INTSVCT[i]);
146 /* Report on setup of CC0. */
147 // printf("CC0 EER=%08X; CC0 QEER=%08X. (Event Enabled Registers).\n",
148 // *CC0_EER, *CC0_QEER);
150 /* Report on the contents of QDMA 0-7 mapping, for each channel. */
151 /* Offset is 0x200 = 512, but in 4-byte ints, 128. */
152 // for (i=0; i<8; i++)
153 // printf("EDMA3CC0 QDMA(%1i)=0x%08X.\n", i,EDMA3CC0[128+i]);
154 // for (i=0; i<8; i++)
155 // printf("EDMA3CC1 QDMA(%1i)=0x%08X.\n", i,EDMA3CC1[128+i]);
156 // for (i=0; i<8; i++)
157 // printf("EDMA3CC2 QDMA(%1i)=0x%08X.\n", i,EDMA3CC2[128+i]);
159 return(0);
160 } /* END main */