Release use EdmaMgr and local L1 L2 start addresses BLAS.03.11.00.01
authorunknown <a0868762@LTA0868762B.am.dhcp.ti.com>
Thu, 16 Jan 2014 19:24:04 +0000 (13:24 -0600)
committerunknown <a0868762@LTA0868762B.am.dhcp.ti.com>
Thu, 16 Jan 2014 19:24:04 +0000 (13:24 -0600)
20 files changed:
blas-lib-3.11.0.pdf
blas/example/Makefile
blas/example/Setup_ECPY/alg/algEdma.h [moved from blas/example/Setup_ECPY/alg/ires/algIres.h with 76% similarity]
blas/example/Setup_ECPY/alg/algLoc.h
blas/example/Setup_ECPY/alg/ecpy/algEcpy.h [deleted file]
blas/example/Setup_ECPY/alg/ires/algIres.c [deleted file]
blas/example/Setup_ECPY/app/build/fcConfig.cfg
blas/example/Setup_ECPY/app/build/make/Makefile
blas/example/Setup_ECPY/app/build/make/algLoc.h
blas/example/Setup_ECPY/app/src/platform/c6678/appEdmaConfig.c
blas/example/Setup_ECPY/app/src/rman/appRman.c
blas/example/Setup_ECPY/app/src/rman/appRman.h
blas/example/Setup_ECPY/app/src/setup_ECPY.c
blas/example/Setup_ECPY/inc/alg.h
blas/example/sourceme.sh
blas/lib/libatlas.a
blas/lib/libcblas.a
blas/lib/liblapack.a
blas/lib/libtstatlas.a
blas/releasenote.txt

index d6490aaffb3eeea41215bfa0344604de340bde1f..0338db2f302771f60516659d11e0d0205d421351 100644 (file)
Binary files a/blas-lib-3.11.0.pdf and b/blas-lib-3.11.0.pdf differ
index 1a317f030a394b27dc36a1fe8a572bad29d542c4..86508df4e84d94bcd3de5212e16899e893c8a2b0 100644 (file)
@@ -1,6 +1,6 @@
 all: sgemm.out matrix_vector.out
 
-ECPY_OBJS = algIres.obj  appEdmaConfig.obj  appRman.obj  setup_ECPY.obj
+ECPY_OBJS = appEdmaConfig.obj  appRman.obj  setup_ECPY.obj
 ECPY_LINKER_CMDFILE = C6678_ECPY.cmd
 
 $(ECPY_OBJS) $(ECPY_LINKER_CMDFILE):
similarity index 76%
rename from blas/example/Setup_ECPY/alg/ires/algIres.h
rename to blas/example/Setup_ECPY/alg/algEdma.h
index e15e8eff3ed12f683aefff280bef797dcebeb268..b388d73fbc797d5f0a5a5911bf091b7aad78b1af 100644 (file)
@@ -1,7 +1,7 @@
 /******************************************************************************
  * FILE PURPOSE: Data structures for using DMA in Framework
  ******************************************************************************
- * FILE NAME:   algIres.h
+ * FILE NAME:   alg_ires.h
  *
  * (C) Copyright 2013, Texas Instruments Incorporated
  *
 #ifndef _ALG_IRES_H
 #define _ALG_IRES_H
 
-#define NUM_EDMA_CH 4
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <c6x.h>
+#include <ti/sdo/fc/edmamgr/edmamgr.h>
 
-#include <ti/sdo/fc/ecpy/ecpy.h>
-#include <ti/xdais/ires.h>
-#include <ti/sdo/fc/ires/edma3chan/ires_edma3Chan.h>
+#define ALG_NUM_EDMA_CH   4
+#define ALG_XFER_CHANNEL0 0
+#define ALG_XFER_CHANNEL1 1
+#define ALG_XFER_CHANNEL2 2
+#define ALG_XFER_CHANNEL3 3
 
-typedef struct alg_ecpy_channel_struct {
-   IRES_EDMA3CHAN_Handle       edmaHandle;
-   ECPY_Handle                 ecpyHandle;
-   IRES_EDMA3CHAN_ProtocolArgs edmaArgs;
-   Bool                        resActive;
-   Bool                        xferPending;
-} ALG_ECPY_Channel;
+#define ALG_MAX_EDMA_LINKS  1
 
 typedef struct alg_edma_struct
 {
     unsigned int num_channels;
     /* IRES stuff */
-    ALG_ECPY_Channel            ecpyChan[NUM_EDMA_CH];
-    IRES_YieldFxn               yieldFxn;
-    IRES_YieldArgs              yieldArgs;
-    IRES_YieldContext           yieldContext;
+    EdmaMgr_Handle      channel[ALG_NUM_EDMA_CH];
 } ALG_EDMA_Struct;
 
 #endif
+
 /* nothing after this point */
index 33d583bbb96779fea4743978afaf5dee5953ccdd..2e56a7817c3c64f904a2c0a5ece328c81a166549 100644 (file)
 #ifndef _ALG_LOC_H
 #define _ALG_LOC_H
 
-#include "algIres.h"
-#include "algEcpy.h"
+#include <algEdma.h>
 
 #define CHANNEL0       0
 #define CHANNEL1       1
 #define CHANNEL2       2
 #define CHANNEL3       3
 \r
+#define ALG_EDMA_STATE_INIT         0
+#define ALG_EDMA_STATE_ALLOCATED    1
+
 typedef struct algInst_s\r
 {\r
    ALG_EDMA_Struct alg_edma_state;\r
+   int alg_edma_status;
 } algInst_t;
 
 #endif
diff --git a/blas/example/Setup_ECPY/alg/ecpy/algEcpy.h b/blas/example/Setup_ECPY/alg/ecpy/algEcpy.h
deleted file mode 100644 (file)
index c13d0f3..0000000
+++ /dev/null
@@ -1,652 +0,0 @@
-/******************************************************************************
- * FILE PURPOSE: ECPY Wrapper for DMA transfer in Framework
- ******************************************************************************
- * FILE NAME:   algEcpy.h
- *
- * (C) Copyright 2013, Texas Instruments Incorporated
- *
- *  Redistribution and use in source and binary forms, with or without
- *  modification, are permitted provided that the following conditions
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#ifndef _EDMA_ECPY_H
-#define _EDMA_ECPY_H
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <c6x.h>
-
-#include <ti/sdo/fc/ecpy/ecpy.h>
-
-/*---------------------------------------------------------------*/
-/* This function convert single local address to global addresse */
-/*---------------------------------------------------------------*/
-extern cregister volatile unsigned int DNUM;
-static inline void *restrict EDMA_ADDR_LOC_TO_GLOB(void *restrict loc_addr)
-{
-   unsigned int tmp = (unsigned int)loc_addr;
-
-   if((tmp & 0xFF000000) == 0)
-   {
-      return (void *)((1 << 28) | (DNUM << 24) | tmp);
-   } else return loc_addr;
-}
-
-
-/*-----------------------------------------------------------*/
-/*  This function activates ECPY and then disables early     */
-/*  completion mode                                          */
-/*-----------------------------------------------------------*/
-static inline void ALG_EDMA_HW_assign (ALG_ECPY_Channel *ecpyChannel)
-{
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-
-    /* Activate ECPY */
-    ECPY_activate(dmaHandle);
-    /* Do not use early completion mode */
-    ECPY_setEarlyCompletionMode(dmaHandle, FALSE);
-}
-
-/*-----------------------------------------------------------*/
-/*  This function waits for all transfers on a specific      */
-/*  ECPY channel to complete. It is a blocking call          */
-/*  in the sense that CPU will wait until all transfers      */
-/*  are completed.                                           */
-/*-----------------------------------------------------------*/
-
-static inline void ALG_EDMA_wait(ALG_ECPY_Channel *ecpyChannel)
-{
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-
-    if (ecpyChannel->xferPending) {
-      ECPY_directWait(dmaHandle);
-      ecpyChannel->xferPending = FALSE;
-    }
-    return;
-}
-
-/*------------------------------------------------------------*/
-/* The following function performs a single 1D->1D transfer   */
-/* transferring "num_bytes" bytes from "src" which is the     */
-/* source address to "dst" which is the destination. This     */
-/* function uses the channel number "chan_num". It is assumed */
-/* by this function that there are no pending transfers on    */
-/* "chan_num".                                                */ 
-/*------------------------------------------------------------*/
-
-static inline int ALG_EDMA_copy1D1D
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src,
-    void     *restrict        dst,
-    int                       num_bytes
-)
-{
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-#if 1
-    unsigned int r, n = 0, a_cnt = num_bytes, i = 0;
-    char *c_src = (char *)src, *c_dst = (char *)dst;
-
-    /*
-     * This abstracts an effective 1D1D transfer which can transfer more than the 16-bit limit set by the HW.
-     *
-     * This is done by splitting the transfer into 2 transfers:
-     *   - One 2D1D transfer.
-     *   - One 1D1D transfer for the remainder.
-     */
-
-    while ( a_cnt > 0xFFFF )
-    {
-      a_cnt >>= 1;
-      n++;
-    }
-
-    r = num_bytes - (a_cnt << n);
-
-    if ( r > 0 )
-    {
-      src = (void *)c_src;
-      dst = (void *)c_dst;
-
-      memset(&p, 0, sizeof(ECPY_Params));
-      p.transferType = ECPY_1D1D;
-      p.dstAddr     = (void *)EDMA_ADDR_LOC_TO_GLOB(dst);
-      p.srcAddr     = (void *)EDMA_ADDR_LOC_TO_GLOB(src);
-      p.elementSize = r;
-      p.numElements = 1;
-      p.numFrames   = 1;
-
-      i++;
-      ECPY_directConfigure(dmaHandle, &p, i);
-
-      ECPY_directSetFinal(dmaHandle, i);
-      ECPY_directStartEdma(dmaHandle);
-
-      c_src += r;
-      c_dst += r;
-
-      src = (void *)c_src;
-      dst = (void *)c_dst;
-
-      ECPY_directWait(dmaHandle);
-      i = 0;
-    }
-
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_2D1D;
-    p.dstAddr     = (void *)EDMA_ADDR_LOC_TO_GLOB(dst);
-    p.srcAddr     = (void *)EDMA_ADDR_LOC_TO_GLOB(src);
-    p.elementSize = (1<<n);
-    p.numElements = a_cnt;
-    p.numFrames   = 1;
-    p.srcElementIndex = (1<<n);
-    p.dstElementIndex = (1<<n);
-
-    i++;
-    ECPY_directConfigure(dmaHandle, &p, i);
-
-    ECPY_directSetFinal(dmaHandle, i);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-#else
-    /* 
-     *  Single 1D1D transfer. 
-     *
-     *  NOTE: Max size of transfer is limited by 16-bit integer (65535 bytes)
-     */
-
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_1D1D;
-    p.dstAddr     = (void *)EDMA_ADDR_LOC_TO_GLOB(dst);
-    p.srcAddr     = (void *)EDMA_ADDR_LOC_TO_GLOB(src);
-    p.elementSize = num_bytes;
-    p.numElements = 1;
-    p.numFrames   = 1;
-
-    ECPY_directConfigure(dmaHandle, &p, 1);
-
-    ECPY_directSetFinal(dmaHandle, 1);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-#endif
-    return(chan_num);
-}
-
-/*----------------------------------------------------------*/
-/*  The following function performs a 1D->2D transfer       */
-/*  where the source is 1D one dimensional and destination  */
-/*  is 2D two dimensional. This function uses channel       */
-/*  number "chan_num" to transfer "num_lines" lines         */
-/*  each of "num_bytes" bytes. In this case after every     */
-/*  line of "num_bytes" is transferred, "src" source is     */
-/*  incremeneted by "num_bytes" and "dst" destination is    */
-/*  incremenetd by "pitch" bytes.                           */
-/*----------------------------------------------------------*/
-static inline int ALG_EDMA_copy1D2D
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src,
-    void     *restrict        dst,
-    int                       num_bytes,
-    int                       num_lines,
-    int                       pitch
-)
-{
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-    /* Setting up the parameters for the transfer */
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_1D2D;
-    p.numFrames    = 1;
-    p.elementSize = num_bytes;
-    p.numElements  = num_lines;
-    p.srcElementIndex = num_bytes;
-    p.dstElementIndex = pitch;
-    p.srcAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(src);
-    p.dstAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(dst);
-
-    ECPY_directConfigure(dmaHandle, &p, 1);
-
-    ECPY_directSetFinal(dmaHandle, 1);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-    return(chan_num);
-}
-
-/*----------------------------------------------------------*/
-/* This function performs a 2D->1D transfer by usinng the   */
-/* channel number "chan_num" by performing a transfer from  */
-/* source "src" to destination "dst", "num_lines" lines     */
-/* each of "num_bytes" bytes. At the end of transferring    */
-/* "num_bytes" bytes per line, the source is incremented    */
-/* by "pitch" bytes and the destination is incremented by   */
-/* "num_bytes" bytes as "src" is 2D and "dst" is 1D.        */
-/*----------------------------------------------------------*/
-static inline int ALG_EDMA_copy2D1D
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src,
-    void     *restrict        dst,
-    int                       num_bytes,
-    int                       num_lines,
-    int                       pitch
-)
-{
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-    /* Setting up the parameters for the first transfer (data grp 1) */
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_2D1D;
-    p.numFrames    = 1;
-    p.elementSize = num_bytes;
-    p.numElements  = num_lines;
-    p.srcElementIndex = pitch;
-    p.dstElementIndex = num_bytes;
-    p.srcAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(src);
-    p.dstAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(dst);
-
-    ECPY_directConfigure(dmaHandle, &p, 1);
-
-    ECPY_directSetFinal(dmaHandle, 1);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-    return(chan_num);
-}
-
-/*----------------------------------------------------------*/
-/* This function performs a 2D->2D transfer by using the    */
-/* channel number "chan_num" by performing a transfer from  */
-/* source "src" to destination "dst", "num_lines" lines     */
-/* each of "num_bytes" bytes. At the end of transferring    */
-/* "num_bytes" bytes per line, the source is incremented    */
-/* by "pitch" bytes and the destination is incremented by   */
-/* "pitch" bytes as well as "src" is 2D and "dst" is 2D.    */
-/*----------------------------------------------------------*/
-static inline int ALG_EDMA_copy2D2D
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src,
-    void     *restrict        dst,
-    int                       num_bytes,
-    int                       num_lines,
-    int                       pitch
-)
-{
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-    /* Setting up the parameters for the transfer */
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_2D2D;
-    p.numFrames    = 1;
-    p.elementSize = num_bytes;
-    p.numElements  = num_lines;
-    p.srcElementIndex = pitch;
-    p.dstElementIndex = pitch;
-    p.srcAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(src);
-    p.dstAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(dst);
-
-    ECPY_directConfigure(dmaHandle, &p, 1);
-
-    ECPY_directSetFinal(dmaHandle, 1);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-    return(chan_num);
-}
-
-/*----------------------------------------------------------*/
-/* This function performs a 2D->2D transfer by usinng the   */
-/* channel number "chan_num" by performing a transfer from  */
-/* source "src" to destination "dst", "num_lines" lines     */
-/* each of "num_bytes" bytes. At the end of transferring    */
-/* "num_bytes" bytes per line, the source is incremented    */
-/* by "dst_pitch" bytes and the destination is incremented  */
-/* by "src_pitch" bytes as well as "src" is 2D and "dst"    */
-/* is 2D. This function thus allows independent "src" and   */
-/* "dst" pitches.                                           */
-/*----------------------------------------------------------*/
-static inline int ALG_EDMA_copy2D2D_sep
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src,
-    void     *restrict        dst,
-    int                       num_bytes,
-    int                       num_lines,
-    int                       src_pitch,
-    int                       dst_pitch
-)
-{
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-    /* Setting up the parameters for the transfer */
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_2D2D;
-    p.numFrames    = 1;
-    p.elementSize = num_bytes;
-    p.numElements  = num_lines;
-    p.srcElementIndex = src_pitch;
-    p.dstElementIndex = dst_pitch;
-    p.srcAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(src);
-    p.dstAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(dst);
-
-    ECPY_directConfigure(dmaHandle, &p, 1);
-
-    ECPY_directSetFinal(dmaHandle, 1);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-    return(chan_num);
-}
-
-/*-----------------------------------------------------------*/
-/*  This function accepts an array of transfer parameters    */
-/*  and performs a group of 1D->1D linked transfers.         */ 
-/*                                                           */
-/*  ecpyChannel: pointer to ALG ECPY channel data structure. */
-/*  chan_num: Channel number on which transfer is issued.    */
-/*  src: Array of source addresses.                          */
-/*  dst: Array of destination addresses.                     */
-/*  num_bytes: Array of the number of bytes to transfer.     */
-/*  num_transfers: The number of transfers to perform.       */
-/*-----------------------------------------------------------*/
-static inline int ALG_EDMA_copy1D1D_linked
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src[],
-    void     *restrict        dst[],
-    int                       num_bytes[],
-    int                       num_transfers
-)
-{
-    int         i, j;
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-    /* Setting up the parameters for the transfer */
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_1D1D;
-    p.numFrames    = 1;
-    p.numElements  = 1;
-
-    for (i=0; i<num_transfers; i++) 
-    {
-        j = i+1;
-        p.elementSize = num_bytes[i];
-        p.srcAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(src[i]);
-        p.dstAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(dst[i]);
-        ECPY_directConfigure(dmaHandle, &p, j);
-    }
-    ECPY_directSetFinal(dmaHandle, num_transfers);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-    return(chan_num);
-}
-/*-----------------------------------------------------------*/
-/*  This function accepts an array of transfer parameters    */
-/*  and performs a group of src 1D-> dst 2D linked transfers */
-/*                                                           */
-/*  ecpyChannel: pointer to ALG ECPY channel data structure. */
-/*  chan_num:   Channel number to use for transfer.          */
-/*  src     :   Array of source addresses to use.            */
-/*  dst     :   Array of destination addresses to use.       */
-/*  num_bytes:  Number of bytes to transfer per line.        */
-/*  num_lines:  Number of such lines to transfer.            */
-/*  pitch:      Destination pitch to use between lines.      */
-/*  num_tfrs:   Number of transfers.                         */
-/*-----------------------------------------------------------*/
-
-
-static inline int ALG_EDMA_copy1D2D_linked
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src[],
-    void     *restrict        dst[],
-    int                       num_bytes[],
-    int                       num_lines[],
-    int                       pitch[],
-    int                       num_transfers
-)
-{
-    int         i, j;
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-    /* Setting up the parameters for the transfer */
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_1D2D;
-    p.numFrames    = 1;
-
-    for (i=0; i<num_transfers; i++) 
-    {
-        j = i+1;
-        p.elementSize = num_bytes[i];
-        p.numElements  = num_lines[i];
-        p.srcElementIndex = num_bytes[i];
-        p.dstElementIndex = pitch[i];
-        p.srcAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(src[i]);
-        p.dstAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(dst[i]);
-        ECPY_directConfigure(dmaHandle, &p, j);
-    }
-    ECPY_directSetFinal(dmaHandle, num_transfers);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-    return(chan_num);
-}
-
-
-/*-----------------------------------------------------------*/
-/*  This function accepts an array of transfer parameters    */
-/*  and performs a group of src 2D-> dst 1D linked transfers */
-/*                                                           */
-/*  ecpyChannel: pointer to ALG ECPY channel data structure. */
-/*  chan_num:   Channel number to use for transfer.          */
-/*  src     :   Array of source addresses to use.            */
-/*  dst     :   Array of destination addresses to use.       */
-/*  num_bytes:  Number of bytes to transfer per line.        */
-/*  num_lines:  Number of such lines to transfer.            */
-/*  pitch:      Source pitch to use between lines.           */
-/*  num_tfrs:   Number of transfers.                         */
-/*-----------------------------------------------------------*/
-static inline int ALG_EDMA_copy2D1D_linked
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src[],
-    void     *restrict        dst[],
-    int                       num_bytes[],
-    int                       num_lines[],
-    int                       pitch[],
-    int                       num_transfers
-)
-{
-    int         i, j;
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-    /* Setting up the parameters for the transfer */
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_2D1D;
-    p.numFrames    = 1;
-
-    for (i=0; i<num_transfers; i++) 
-    {
-        j = i+1;
-        p.elementSize = num_bytes[i];
-        p.numElements  = num_lines[i];
-        p.srcElementIndex = pitch[i];
-        p.dstElementIndex = num_bytes[i];
-        p.srcAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(src[i]);
-        p.dstAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(dst[i]);
-        ECPY_directConfigure(dmaHandle, &p, j);
-    }
-    ECPY_directSetFinal(dmaHandle, num_transfers);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-    return(chan_num);
-}
-/*-----------------------------------------------------------*/
-/*  This function accepts an array of transfer parameters    */
-/*  and performs a group of src 2D-> dst 2D linked transfers */
-/*                                                           */
-/*  ecpyChannel: pointer to ALG ECPY channel data structure. */
-/*  chan_num:   Channel number to use for transfer.          */
-/*  src     :   Array of source addresses to use.            */
-/*  dst     :   Array of destination addresses to use.       */
-/*  num_bytes:  Number of bytes to transfer per line.        */
-/*  num_lines:  Number of such lines to transfer.            */
-/*  pitch:      Source, Dest pitch to use between lines.     */
-/*  num_tfrs:   Number of transfers.                         */
-/*-----------------------------------------------------------*/
-static inline int ALG_EDMA_copy2D2D_linked
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src[],
-    void     *restrict        dst[],
-    int                       num_bytes[],
-    int                       num_lines[],
-    int                       pitch[],
-    int                       num_transfers
-)
-{
-    int         i, j;
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-    /* Setting up the parameters for the transfer */
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_2D2D;
-    p.numFrames    = 1;
-
-    for (i=0; i<num_transfers; i++) 
-    {
-        j = i+1;
-        p.elementSize = num_bytes[i];
-        p.numElements  = num_lines[i];
-        p.srcElementIndex = pitch[i];
-        p.dstElementIndex = pitch[i];
-        p.srcAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(src[i]);
-        p.dstAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(dst[i]);
-        ECPY_directConfigure(dmaHandle, &p, j);
-    }
-    ECPY_directSetFinal(dmaHandle, num_transfers);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-    return(chan_num);
-}
-
-/*-----------------------------------------------------------*/
-/*  This function accepts an array of transfer parameters    */
-/*  and performs a group of src 2D-> dst 2D linked transfers */
-/*                                                           */
-/*  ecpyChannel: pointer to ALG ECPY channel data structure. */
-/*  chan_num:   Channel number to use for transfer.          */
-/*  src     :   Array of source addresses to use.            */
-/*  dst     :   Array of destination addresses to use.       */
-/*  num_bytes:  Number of bytes to transfer per line.        */
-/*  num_lines:  Number of such lines to transfer.            */
-/*  pitchsrc:   Source pitch to use between lines.           */
-/*  pitchdst:   Destination pitch to use between lines.      */
-/*  num_tfrs:   Number of transfers.                         */
-/*-----------------------------------------------------------*/
-static inline int ALG_EDMA_copy2D2D_sep_linked
-(
-    ALG_ECPY_Channel          *ecpyChannel,
-    unsigned int              chan_num,
-    void     *restrict        src[],
-    void     *restrict        dst[],
-    int                       num_bytes[],
-    int                       num_lines[],
-    int                       pitchsrc[],
-    int                       pitchdst[],
-    int                       num_transfers
-)
-{
-    int         i, j;
-    ECPY_Handle dmaHandle = ecpyChannel->ecpyHandle;
-    ECPY_Params p;
-
-    /* Setting up the parameters for the transfer */
-    memset(&p, 0, sizeof(ECPY_Params));
-    p.transferType = ECPY_2D2D;
-    p.numFrames    = 1;
-
-    for (i=0; i<num_transfers; i++) 
-    {
-        j = i+1;
-        p.elementSize = num_bytes[i];
-        p.numElements  = num_lines[i];
-        p.srcElementIndex = pitchsrc[i];
-        p.dstElementIndex = pitchdst[i];
-        p.srcAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(src[i]);
-        p.dstAddr = (void *)EDMA_ADDR_LOC_TO_GLOB(dst[i]);
-        ECPY_directConfigure(dmaHandle, &p, j);
-    }
-    ECPY_directSetFinal(dmaHandle, num_transfers);
-    ECPY_directStartEdma(dmaHandle);
-
-    ecpyChannel->xferPending = TRUE;
-
-    return(chan_num);
-}
-
-#endif
-/* nothing after this point */
diff --git a/blas/example/Setup_ECPY/alg/ires/algIres.c b/blas/example/Setup_ECPY/alg/ires/algIres.c
deleted file mode 100644 (file)
index 09ddabf..0000000
+++ /dev/null
@@ -1,298 +0,0 @@
-/******************************************************************************
- * FILE PURPOSE: IRES functions for DMA transfer in Framework
- ******************************************************************************
- * FILE NAME:   algIres.c
- *
- * (C) Copyright 2013, Texas Instruments Incorporated
- * 
- *  Redistribution and use in source and binary forms, with or without 
- *  modification, are permitted provided that the following conditions 
- *  are met:
- *
- *    Redistributions of source code must retain the above copyright 
- *    notice, this list of conditions and the following disclaimer.
- *
- *    Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the 
- *    documentation and/or other materials provided with the   
- *    distribution.
- *
- *    Neither the name of Texas Instruments Incorporated nor the names of
- *    its contributors may be used to endorse or promote products derived
- *    from this software without specific prior written permission.
- *
- *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
- *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
- *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
- *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
- *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
- *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
- *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
-*/
-
-#include <xdc/std.h>
-#include <string.h>
-#include <ti/xdais/trace.h>
-#include <ti/xdais/dm/iuniversal.h>
-
-#include <ti/xdais/ialg.h>
-#include <ti/xdais/ires.h>
-
-/* Header file for the resources used in this example. */
-#include <ti/sdo/fc/ires/edma3chan/ires_edma3Chan.h>
-
-#include "algIres.h"
-
-/* IRES Function Declarations */
-static IRES_Status ALG_EDMA_activateRes(IALG_Handle handle, IRES_Handle res);
-static IRES_Status ALG_EDMA_activateAllRes(IALG_Handle handle);
-static IRES_Status ALG_EDMA_deactivateRes(IALG_Handle h, IRES_Handle res);
-static IRES_Status ALG_EDMA_deactivateAllRes(IALG_Handle handle);
-static Int32 ALG_EDMA_numResources(IALG_Handle handle);
-static IRES_Status ALG_EDMA_getResources(IALG_Handle handle, IRES_ResourceDescriptor *desc);
-static IRES_Status ALG_EDMA_initResources(IALG_Handle h, IRES_ResourceDescriptor * desc, IRES_YieldFxn  yieldFxn, IRES_YieldArgs yieldArgs);
-static IRES_Status ALG_EDMA_deInitResources(IALG_Handle h, IRES_ResourceDescriptor *desc);
-static IRES_Status ALG_EDMA_reInitResources(IALG_Handle handle, IRES_ResourceDescriptor *desc, IRES_YieldFxn yieldFxn, IRES_YieldArgs yieldArgs);
-
-/*
- *  ======== ALG_EDMA_IRES ========
- */
-IRES_Fxns ALG_EDMA_IRES = {
-    &ALG_EDMA_IRES,
-    ALG_EDMA_getResources,
-    ALG_EDMA_numResources,
-    ALG_EDMA_initResources,
-    ALG_EDMA_reInitResources,
-    ALG_EDMA_deInitResources,
-    ALG_EDMA_activateRes,
-    ALG_EDMA_activateAllRes,
-    ALG_EDMA_deactivateRes,
-    ALG_EDMA_deactivateAllRes
-};
-
-static IRES_ProtocolRevision _iresEDMA3ChanRevision = IRES_EDMA3CHAN_PROTOCOLREVISION_2_0_0;
-
-/*
- *  ======== ALG_EDMA_activateAllRes ========
- */
-static IRES_Status ALG_EDMA_activateAllRes(IALG_Handle handle)
-{
-    ALG_EDMA_Struct *algEdma  = (ALG_EDMA_Struct *)handle;
-    IRES_Status      status;
-    int i;
-    /* Activate all resources */
-    for (i = 0; i< NUM_EDMA_CH; i++) {
-       status = ALG_EDMA_activateRes(handle, (IRES_Handle)algEdma->ecpyChan[i].edmaHandle);
-       if (status != IRES_OK) {
-          return (status);
-       }
-    }
-
-    return (IRES_OK);
-}
-
-/*
- *  ======== ALG_EDMA_activateRes ========
- */
-static IRES_Status ALG_EDMA_activateRes(IALG_Handle handle, 
-        IRES_Handle res)
-{
-    ALG_EDMA_Struct *algEdma  = (ALG_EDMA_Struct *)handle;
-    int i;
-    
-    /* Check that res = alg->nullres */
-    for (i = 0; i< NUM_EDMA_CH; i++) {
-      if (res == (IRES_Handle)(algEdma->ecpyChan[i].edmaHandle)) {
-         if (TRUE == algEdma->ecpyChan[i].resActive) {
-            return (IRES_EFAIL);
-         }
-         algEdma->ecpyChan[i].resActive = TRUE;
-      }
-    }
-
-    return (IRES_OK);
-}
-
-/*
- *  ======== ALG_EDMA_deactivateAllRes ========
- */
-static IRES_Status ALG_EDMA_deactivateAllRes(IALG_Handle handle) 
-{
-    ALG_EDMA_Struct *algEdma  = (ALG_EDMA_Struct *)handle;
-    IRES_Status      status = IRES_OK;
-    int i;
-    
-    for (i = 0; i< NUM_EDMA_CH; i++) {
-       status = ALG_EDMA_deactivateRes(handle, (IRES_Handle)algEdma->ecpyChan[i].edmaHandle);
-       if (status != IRES_OK) {
-          return (status);
-       }
-    }
-    return (status);
-}
-
-/*
- *  ======== ALG_EDMA_deactivateRes ========
- */
-static IRES_Status ALG_EDMA_deactivateRes(IALG_Handle handle, IRES_Handle res)
-{
-    ALG_EDMA_Struct *algEdma  = (ALG_EDMA_Struct *)handle;
-    int i;
-    
-    /* Check that res = alg->nullres */
-    for (i = 0; i< NUM_EDMA_CH; i++) {
-      if (res == (IRES_Handle)(algEdma->ecpyChan[i].edmaHandle)) {
-         if (FALSE == algEdma->ecpyChan[0].resActive) {
-             return (IRES_EFAIL);
-         }
-         algEdma->ecpyChan[i].resActive = FALSE;
-      }
-    }
-
-    return (IRES_OK);
-}
-
-/*
- *  ======== ALG_EDMA_deInitResources ========
- */
-static IRES_Status ALG_EDMA_deInitResources(IALG_Handle handle,
-        IRES_ResourceDescriptor *desc)
-{
-    ALG_EDMA_Struct *algEdma  = (ALG_EDMA_Struct *)handle;
-    int i;
-    
-    for (i = 0; i< NUM_EDMA_CH; i++) {
-      if (desc[i].handle == (IRES_Handle)algEdma->ecpyChan[i].edmaHandle) {
-          algEdma->ecpyChan[i].edmaHandle = NULL;
-          algEdma->ecpyChan[i].resActive  = FALSE;
-                 algEdma->ecpyChan[i].xferPending = FALSE;
-                 ECPY_deleteHandle(algEdma->ecpyChan[i].ecpyHandle);
-      }
-      else {
-        return (IRES_ENOTFOUND);
-      }
-    }
-    return (IRES_OK);
-}
-
-/*
- *  ======== ALG_EDMA_getResources ========
- */
-static IRES_Status ALG_EDMA_getResources(IALG_Handle handle,
-        IRES_ResourceDescriptor *desc)
-{
-    ALG_EDMA_Struct *algEdma  = (ALG_EDMA_Struct *)handle;
-    int i;
-
-    TRACE_2print(h, TRACE_ENTER,"ALG_EDMA_getResources> Enter (alg=0x%x, "
-            "desc=0x%x)\n", h, desc);
-    /* 
-     * This API could be called to query for resource requirements and after
-     * having granted the resources, could also be queried for resource 
-     * holdings of the algorithm. The difference is that in the second case a 
-     * valid resource handle (that had been granted earlier) would be expected.
-     */
-    for (i=0; i<NUM_EDMA_CH; i++) {
-        desc[i].resourceName    = IRES_EDMA3CHAN_PROTOCOLNAME;
-        desc[i].revision        = &_iresEDMA3ChanRevision;
-        desc[i].protocolArgs    = (IRES_ProtocolArgs *)&(algEdma->ecpyChan[i].edmaArgs);
-        desc[i].handle          = (IRES_Handle)algEdma->ecpyChan[i].edmaHandle; 
-        (algEdma->ecpyChan[i].edmaArgs).size = sizeof(IRES_EDMA3CHAN_ProtocolArgs);
-        (algEdma->ecpyChan[i].edmaArgs).mode = IRES_SCRATCH;
-        (algEdma->ecpyChan[i].edmaArgs).numTccs   = 1;  
-        (algEdma->ecpyChan[i].edmaArgs).paRamIndex = IRES_EDMA3CHAN_PARAM_ANY; 
-        (algEdma->ecpyChan[i].edmaArgs).tccIndex   = IRES_EDMA3CHAN_TCC_ANY;
-        (algEdma->ecpyChan[i].edmaArgs).qdmaChan   = IRES_EDMA3CHAN_CHAN_NONE;
-        (algEdma->ecpyChan[i].edmaArgs).edmaChan   = IRES_EDMA3CHAN_EDMACHAN_ANY;
-        (algEdma->ecpyChan[i].edmaArgs).contiguousAllocation   = TRUE;
-        (algEdma->ecpyChan[i].edmaArgs).shadowPaRamsAllocation = FALSE;
-        (algEdma->ecpyChan[i].edmaArgs).numPaRams = 1;
-    }
-
-    TRACE_1print(h,TRACE_4CLASS, "ALG_EDMA_getResources> desc[0].handle = "
-            "0x%x\n", desc[0].handle);
-
-    TRACE_0print( h,TRACE_ENTER, "ALG_EDMA_getResources> Exit (status="
-            "IRES_OK)\n");
-    return (IRES_OK);
-}
-
-/*
- *  ======== ALG_EDMA_initResources ========
- */
-static IRES_Status ALG_EDMA_initResources(IALG_Handle handle,
-        IRES_ResourceDescriptor *desc, IRES_YieldFxn  yieldFxn,
-        IRES_YieldArgs yieldArgs)
-{
-    ALG_EDMA_Struct *algEdma  = (ALG_EDMA_Struct *)handle;
-    int i, j;
-    /* 
-     * Resource manager has returned a resource handle. Save it in the 
-     * algorithm's instance object 
-     */
-    for(i=0; i< NUM_EDMA_CH; i++)
-    {
-       algEdma->ecpyChan[i].edmaHandle = (IRES_EDMA3CHAN_Handle)desc[i].handle;
-       algEdma->ecpyChan[i].ecpyHandle = ECPY_createHandle((IRES_EDMA3CHAN2_Handle)desc[i].handle, handle);
-          if(algEdma->ecpyChan[i].ecpyHandle == NULL) {
-       for (j=0; j<i; j++) {
-                  ECPY_deleteHandle(algEdma->ecpyChan[j].ecpyHandle);  
-                }
-                return (IRES_ENOMEM);
-       }
-      algEdma->ecpyChan[i].xferPending = FALSE;
-    }
-
-    /* 
-     * Resource Manager also provides yield functions and yield Args alongwith  
-     * the resource handle.
-     */
-    algEdma->yieldFxn = yieldFxn;
-    algEdma->yieldArgs = yieldArgs;
-
-    return (IRES_OK);
-}
-
-/*
- *  ======== ALG_EDMA_numResources ========
- */
-/* ARGSUSED */
-static Int32 ALG_EDMA_numResources(IALG_Handle handle) 
-{
-    return (NUM_EDMA_CH);
-}
-
-/*
- *  ======== ALG_EDMA_reInitResources ========
- */
-static IRES_Status ALG_EDMA_reInitResources(IALG_Handle handle,
-        IRES_ResourceDescriptor *desc, IRES_YieldFxn  yieldFxn,
-        IRES_YieldArgs yieldArgs)
-{
-    ALG_EDMA_Struct *algEdma  = (ALG_EDMA_Struct *)handle;
-    int i;
-
-    algEdma->yieldFxn = yieldFxn;
-    algEdma->yieldArgs = yieldArgs;
-
-    /* 
-     * This function implies that the resource holdings of the algorithms have
-     * been changed.
-     * Update them in the algorithm instance object. 
-     */
-    for(i=0; i< NUM_EDMA_CH; i++)
-    {
-       algEdma->ecpyChan[i].edmaHandle = (IRES_EDMA3CHAN_Handle)desc[i].handle;
-       algEdma->ecpyChan[i].resActive  = FALSE;
-          algEdma->ecpyChan[i].xferPending = FALSE;
-    }
-
-    return (IRES_OK);
-}
-
-/* nothing after this point */
index 697bba1177cbe9bceb31f179b1606e035c809a89..4d0e7c8f403cb0ef1bd1d971a6d1191b6d7cfb38 100644 (file)
@@ -93,73 +93,18 @@ program.argSize = 512;
 /* being manipulated by the calling program. So if you need   */
 /* reduce this to make room for something else, don't chop it,*/
 /* just take the slice you need.                       Tony C.*/
-BIOS.heapSize = 0x1FFF0000;
+/* BIOS.heapSize = 0x1FFF0000; */
+BIOS.heapSize = 0x1FFE0000;
 
 /* disable Clock */
 BIOS.clockEnabled = false;
 
-/* Configure heap for FC use. This is not the heap that ATLAS */
-/* uses, we keep in L2SRAM for performance. 0x1500 is the     */
-/* value set by TI in their example code.              Tony C.*/
-var intHeapSize = 0x1500;   /* Size to make internal heap, the actual usage can be found from ROV */
-Program.sectMap[".INTMEM_HEAP"] = new Program.SectionSpec();
-Program.sectMap[".INTMEM_HEAP"].loadSegment = "L2SRAM";
-
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var heapMemParams = new HeapMem.Params();
-heapMemParams.size = intHeapSize;
-heapMemParams.sectionName = ".INTMEM_HEAP";
-Program.global.INTMEM_HEAP = HeapMem.create(heapMemParams);
-
-/* Configure DSKT2 heaps and scratch */
-var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');
-DSKT2.ALLOW_EXTERNAL_SCRATCH = false;
-
-DSKT2.DARAM0 = "INTMEM_HEAP";
-DSKT2.DARAM1 = "INTMEM_HEAP";
-DSKT2.DARAM2 = "INTMEM_HEAP";
-
-DSKT2.SARAM0 = "INTMEM_HEAP";
-DSKT2.SARAM1 = "INTMEM_HEAP";
-DSKT2.SARAM2 = "INTMEM_HEAP";
-
-DSKT2.ESDATA = "INTMEM_HEAP";
-DSKT2.IPROG  = "INTMEM_HEAP";
-DSKT2.EPROG  = "INTMEM_HEAP";
-
-DSKT2.DSKT2_HEAP = "INTMEM_HEAP";
-
-/* Configure RMAN and EDMA3 */
 var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');
-var EDMA3CHAN = xdc.useModule('ti.sdo.fc.ires.edma3chan.EDMA3CHAN');
-var EDMA3LLD = xdc.loadPackage('ti.sdo.edma3.rm');
-
-RMAN.useDSKT2 = true;
-RMAN.yieldSamePriority = true;
-RMAN.maxAlgs = 4;    /* Maximal number of alg instances which will use RMAN */
-
-/* Configure ECPY */
-var ECPY = xdc.useModule('ti.sdo.fc.ecpy.ECPY');
-ECPY.persistentAllocFxn = "DSKT2_allocPersistent";
-ECPY.persistentFreeFxn = "DSKT2_freePersistent"
-
-/* Configure META */
-var META = xdc.useModule('ti.sdo.fc.edma3.Settings');
-/* Use scratch group 0 and specify the maximum number of PaRAM sets,      */
-/* TCCs, EDMA channels, and QDMA channels for the group. In application   */
-/* C code, the same scratch ID of 0 is used in app_fc_assign_resources () */
-/* and app_fc_free_resources(). The allocation of PaRAM sets, TCCs,       */
-/* EDMA channels, and QDMA channels is defined in EDMA region config      */
-/* array C6678_config[] in app_c6678_config.c. For the 32-bit words in    */
-/* regionSample* there, each bit corresponds to a single                  */     
-/* PaRAMSet/EDMAChannel/QDMAChannel/TCC, and the value of 1 indicates     */
-/* the ownership or reservation. Change the maximum number of PaRAM sets, */ 
-/* TCCs, EDMA channels, and QDMA channels below if needed when the EDMA   */
-/* region config is modified.                                             */
-META.maxPaRams = [96, 0, 0, 0];
-META.maxTccs = [16, 0, 0, 0];
-META.maxEdmaChannels = [16, 0, 0, 0];
-META.maxQdmaChannels = [0, 0, 0, 0];
+RMAN.useDSKT2 = false;
+RMAN.persistentAllocFxn = "EdmaMgr_heap_alloc";
+RMAN.persistentFreeFxn = "EdmaMgr_heap_free";
+
+var EdmaMgr = xdc.useModule('ti.sdo.fc.edmamgr.EdmaMgr');
 
 /* Uncomment this to use debug mode for FC and EDMA3LLD */
 /* xdc.useModule('ti.sdo.fc.global.Settings').profile = "debug"; */ 
index f488a05ee9a629c7483b540bf482795fcf3167d5..4be053d0508685e48a7b4ad47b6b52dc22827ee5 100644 (file)
@@ -36,7 +36,7 @@
 
 default: all
 
-all: config_and_patch algIres.obj setup_ECPY.obj appRMAN.obj appEdmaConfig.obj
+all: config_and_patch setup_ECPY.obj appRMAN.obj appEdmaConfig.obj
 
 # Ensures CGEN_DIR is exported and available. 
 # Typically something like /opt/ti/TI_CGT_C6000_7.4.2
@@ -48,13 +48,11 @@ include Makefile_cfg
 
 # Include path
 INCLUDES=-I ../../../inc \
-         -I ../../../alg/ires \
-         -I ../../../alg/ecpy \
+         -I ../../../alg \
          -I ../../../app/src/rman  
 
 # Source files.
-SRC_FILES = ../../../alg/ires/algIres.c \
-            ../../../app/src/setup_ECPY.c \
+SRC_FILES = ../../../app/src/setup_ECPY.c \
             ../../../app/src/rman/appRman.c \
             ../../../app/src/platform/c6678/appEdmaConfig.c 
 
@@ -65,12 +63,13 @@ OBJDIR = ../../../..
 # Compiler defines
 CC        = $(CGEN_DIR)/bin/cl6x
 OPT_FILE  = $(CFGDIR)/compiler.opt
-CC_OPTS   = -@ $(OPT_FILE) -mv6600 $(INCLUDES)
+CC_OPTS   = -@ $(OPT_FILE) -mv6600 $(ENDIAN_FLAGS) $(INCLUDES)
 
 ifeq ($(BUILD_TYPE),debug)
     CC_OPTS += -g --optimize_with_debug=on
 else
-    CC_OPTS += -o3
+    CC_OPTS += -o2
+    CC_OPTS += --define="EDMAMGR_INLINE_ALL"
 endif
 
 # Linker defines
@@ -79,7 +78,8 @@ RTS_LIB   = $(CGEN_DIR)/lib/libc.a
 ifeq ($(BUILD_TYPE),debug)
     CC_OPTS += -g --optimize_with_debug=on
 else
-    CC_OPTS += -o3
+    CC_OPTS += -o2
+    CC_OPTS += --define="EDMAMGR_INLINE_ALL"
 endif
 
 
@@ -96,11 +96,9 @@ endif
 # precision peak (only 4 flops per cycle instead of 16) did not require 
 # the faster L2SRAM.                                           Tony C.
 config_and_patch: gen_config 
-       @echo "Patching L2SRAM size to 0x10000."; sed -i '/L2SRAM / s/len = 0x80000/len = 0x10000/' $(CMD_FILE)
+       @echo "Patching L2SRAM size to 0x20000."; sed -i '/L2SRAM / s/len = 0x80000/len = 0x20000/' $(CMD_FILE)
        @echo "Copying linker cmd file to $(OBJDIR)/C6678_ECPY.cmd."; cp -v $(CMD_FILE) $(OBJDIR)/C6678_ECPY.cmd
 
-algIres.obj: ../../../alg/ires/algIres.c
-       $(CC) $(CC_OPTS) $< -fr $(OBJDIR)  $(INCLUDES)
 setup_ECPY.obj: ../../../app/src/setup_ECPY.c
        $(CC) $(CC_OPTS) $< -fr $(OBJDIR)  $(INCLUDES)
 appRMAN.obj: ../../../app/src/rman/appRman.c
@@ -110,6 +108,6 @@ appEdmaConfig.obj: ../../../app/src/platform/c6678/appEdmaConfig.c
 
 # Clean
 clean: clean_config
-       rm -f $(OBJDIR)/algIres.obj $(OBJDIR)/setup_ECPY.obj $(OBJDIR)/appRman.obj $(OBJDIR)/appEdmaConfig.obj $(BASE_DIR)/C6678_ECPY.cmd
+       rm -f $(OBJDIR)/setup_ECPY.obj $(OBJDIR)/appRman.obj $(OBJDIR)/appEdmaConfig.obj $(BASE_DIR)/C6678_ECPY.cmd
        @echo Finished clean
 
index 33d583bbb96779fea4743978afaf5dee5953ccdd..2e56a7817c3c64f904a2c0a5ece328c81a166549 100644 (file)
 #ifndef _ALG_LOC_H
 #define _ALG_LOC_H
 
-#include "algIres.h"
-#include "algEcpy.h"
+#include <algEdma.h>
 
 #define CHANNEL0       0
 #define CHANNEL1       1
 #define CHANNEL2       2
 #define CHANNEL3       3
 \r
+#define ALG_EDMA_STATE_INIT         0
+#define ALG_EDMA_STATE_ALLOCATED    1
+
 typedef struct algInst_s\r
 {\r
    ALG_EDMA_Struct alg_edma_state;\r
+   int alg_edma_status;
 } algInst_t;
 
 #endif
index 20fec0c44fcacb0de58f2aea952e33964d3b516c..952c869d39ff50a026dbc62027c9006cd83adfa2 100644 (file)
 */\r
 \r
 #include <xdc/std.h>\r
+#include <ti/sdo/edma3/rm/edma3_rm.h>\r
 #include <ti/sdo/fc/edma3/edma3_config.h>\r
 \r
-/* Definition of EDMA3_InstanceInitConfig structure from                    */\r
-/* <ti/sdo/fc/edma3/edma3_config.h>. It is attached here and put under      */\r
-/* #if 0 for reference                                                      */\r
-\r
-/* EDMA3_InstanceInitConfig is init-time Region Specific Configuration      */\r
-/* structure for EDMA3 to provide region specific Information. It is used   */\r
-/* to specify which EDMA3 resources are owned and reserved by the EDMA3     */\r
-/* instance.                                                                */\r
-\r
-#if 0\r
-typedef struct\r
-{\r
-    unsigned int        ownPaRAMSets[EDMA3_MAX_PARAM_DWRDS];\r
-                            /**< PaRAM Sets owned by the EDMA3 RM Instance. */\r
-    unsigned int        ownDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];\r
-                            /**< DMA Channels owned by the EDMA3 RM Instance. */\r
-    unsigned int        ownQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];\r
-                            /**< QDMA Channels owned by the EDMA3 RM Instance.*/\r
-    unsigned int        ownTccs[EDMA3_MAX_TCC_DWRDS];\r
-                            /**< TCCs owned by the EDMA3 RM Instance. */\r
-    /**\r
-     * @brief       Reserved PaRAM Sets\r
-     */\r
-    unsigned int        resvdPaRAMSets[EDMA3_MAX_PARAM_DWRDS];\r
-    /**\r
-     * @brief       Reserved DMA channels\r
-     */\r
-    unsigned int        resvdDmaChannels[EDMA3_MAX_DMA_CHAN_DWRDS];\r
-    /**\r
-     * @brief       Reserved QDMA channels\r
-     */\r
-    unsigned int        resvdQdmaChannels[EDMA3_MAX_QDMA_CHAN_DWRDS];\r
-    /**\r
-     * @brief       Reserved TCCs\r
-     */\r
-    unsigned int        resvdTccs[EDMA3_MAX_TCC_DWRDS];\r
-} EDMA3_InstanceInitConfig;\r
-#endif\r
+#define EDMA_MGR_NUM_EDMA_INSTANCES 3\r
 \r
 /* In the arrays below, each bit of a 32-bit word corresponds to a single   */\r
 /* PaRAMSet/EDMAChannel/QDMAChannel/TCC owned by the corresponding region,  */\r
@@ -290,3 +254,580 @@ const EDMA3_InstanceInitConfig C6678_config[NUM_EDMA_INSTANCES][EDMA3_MAX_REGION
    regionSample1,  regionSample2,  regionSample3,  regionSample4\r
  }\r
 };\r
+\r
+const EDMA3_InstanceInitConfig edmaMgrInstanceInitConfig[EDMA_MGR_NUM_EDMA_INSTANCES][EDMA3_MAX_REGIONS] =\r
+{\r
+ /* EDMA3 INSTANCE# 0 */\r
+ { regionSample0,  regionSample0,  regionSample0,  regionSample0,\r
+   regionSample0,  regionSample0,  regionSample0,  regionSample0\r
+ },\r
+ /* EDMA3 INSTANCE# 1 */\r
+ { regionSample1,  regionSample2,  regionSample3,  regionSample4,\r
+   regionSample0,  regionSample0,  regionSample0,  regionSample0\r
+ },\r
+ /* EDMA3 INSTANCE# 2 */\r
+ { regionSample0,  regionSample0,  regionSample0,  regionSample0,\r
+   regionSample1,  regionSample2,  regionSample3,  regionSample4\r
+ }\r
+};\r
+\r
+int32_t edmaMgrRegion2Instance[EDMA3_MAX_REGIONS] = {1,1,1,1,2,2,2,2};\r
+\r
+/* Driver Object Initialization Configuration */\r
+EDMA3_GblConfigParams edmaMgrGblConfigParams [EDMA_MGR_NUM_EDMA_INSTANCES] =\r
+       {\r
+               {\r
+               /* EDMA3 INSTANCE# 0 */\r
+               /** Total number of DMA Channels supported by the EDMA3 Controller */\r
+               16u,\r
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
+               8u,\r
+               /** Total number of TCCs supported by the EDMA3 Controller */\r
+               16u,\r
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
+               128u,\r
+               /** Total number of Event Queues in the EDMA3 Controller */\r
+               2u,\r
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
+               2u,\r
+               /** Number of Regions on this EDMA3 controller */\r
+               8u,\r
+\r
+               /**\r
+                * \brief Channel mapping existence\r
+                * A value of 0 (No channel mapping) implies that there is fixed association\r
+                * for a channel number to a parameter entry number or, in other words,\r
+                * PaRAM entry n corresponds to channel n.\r
+                */\r
+               1u,\r
+\r
+               /** Existence of memory protection feature */\r
+               1u,\r
+\r
+               /** Global Register Region of CC Registers */\r
+               (void *)0x02700000u,\r
+               /** Transfer Controller (TC) Registers */\r
+               {\r
+               (void *)0x02760000u,\r
+               (void *)0x02768000u,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL\r
+               },\r
+               /** Interrupt no. for Transfer Completion */\r
+               38u,\r
+               /** Interrupt no. for CC Error */\r
+               32u,\r
+               /** Interrupt no. for TCs Error */\r
+               {\r
+               34u,\r
+               35u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               },\r
+\r
+               /**\r
+                * \brief EDMA3 TC priority setting\r
+                *\r
+                * User can program the priority of the Event Queues\r
+                * at a system-wide level.  This means that the user can set the\r
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+                * relative to IO initiated by the other bus masters on the\r
+                * device (ARM, DSP, USB, etc)\r
+                */\r
+               {\r
+               0u,\r
+               1u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+               /**\r
+                * \brief To Configure the Threshold level of number of events\r
+                * that can be queued up in the Event queues. EDMA3CC error register\r
+                * (CCERR) will indicate whether or not at any instant of time the\r
+                * number of events queued up in any of the event queues exceeds\r
+                * or equals the threshold/watermark value that is set\r
+                * in the queue watermark threshold register (QWMTHRA).\r
+                */\r
+               {\r
+               16u,\r
+               16u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+                * An optimally-sized command is defined by the transfer controller\r
+                * default burst size (DBS). Different TCs can have different\r
+                * DBS values. It is defined in Bytes.\r
+                */\r
+               {\r
+               128u,\r
+               128u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+                * if it exists, otherwise of no use.\r
+                */\r
+               {\r
+               EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP, \r
+               /* DMA channels 16-63 DOES NOT exist */\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,\r
+               EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS\r
+               },\r
+\r
+                /**\r
+                 * \brief Mapping from each DMA channel to a TCC. This specific\r
+                 * TCC code will be returned when the transfer is completed\r
+                 * on the mapped channel.\r
+                 */\r
+               {\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               /* DMA channels 16-63 DOES NOT exist */\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,\r
+               EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping of DMA channels to Hardware Events from\r
+                * various peripherals, which use EDMA for data transfer.\r
+                * All channels need not be mapped, some can be free also.\r
+                */\r
+               {\r
+               0x00000000u,\r
+               0x00000000u\r
+               }\r
+               },\r
+\r
+               {\r
+               /* EDMA3 INSTANCE# 1 */\r
+               /** Total number of DMA Channels supported by the EDMA3 Controller */\r
+               64u,\r
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
+               8u,\r
+               /** Total number of TCCs supported by the EDMA3 Controller */\r
+               64u,\r
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
+               512u,\r
+               /** Total number of Event Queues in the EDMA3 Controller */\r
+               4u,\r
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
+               4u,\r
+               /** Number of Regions on this EDMA3 controller */\r
+               8u,\r
+\r
+               /**\r
+                * \brief Channel mapping existence\r
+                * A value of 0 (No channel mapping) implies that there is fixed association\r
+                * for a channel number to a parameter entry number or, in other words,\r
+                * PaRAM entry n corresponds to channel n.\r
+                */\r
+               1u,\r
+\r
+               /** Existence of memory protection feature */\r
+               1u,\r
+\r
+               /** Global Register Region of CC Registers */\r
+               (void *)0x02720000u,\r
+               /** Transfer Controller (TC) Registers */\r
+               {\r
+               (void *)0x02770000u,\r
+               (void *)0x02778000u,\r
+               (void *)0x02780000u,\r
+               (void *)0x02788000u,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL\r
+               },\r
+               /** Interrupt no. for Transfer Completion */\r
+               8u,\r
+               /** Interrupt no. for CC Error */\r
+               0u,\r
+               /** Interrupt no. for TCs Error */\r
+               {\r
+               2u,\r
+               3u,\r
+               4u,\r
+               5u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               },\r
+\r
+               /**\r
+                * \brief EDMA3 TC priority setting\r
+                *\r
+                * User can program the priority of the Event Queues\r
+                * at a system-wide level.  This means that the user can set the\r
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+                * relative to IO initiated by the other bus masters on the\r
+                * device (ARM, DSP, USB, etc)\r
+                */\r
+               {\r
+               0u,\r
+               1u,\r
+               2u,\r
+               3u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+               /**\r
+                * \brief To Configure the Threshold level of number of events\r
+                * that can be queued up in the Event queues. EDMA3CC error register\r
+                * (CCERR) will indicate whether or not at any instant of time the\r
+                * number of events queued up in any of the event queues exceeds\r
+                * or equals the threshold/watermark value that is set\r
+                * in the queue watermark threshold register (QWMTHRA).\r
+                */\r
+               {\r
+               16u,\r
+               16u,\r
+               16u,\r
+               16u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+                * An optimally-sized command is defined by the transfer controller\r
+                * default burst size (DBS). Different TCs can have different\r
+                * DBS values. It is defined in Bytes.\r
+                */\r
+               {\r
+               128u,\r
+               64u,\r
+               128u,\r
+               64u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+                * if it exists, otherwise of no use.\r
+                */\r
+               {\r
+               EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
+               },\r
+\r
+                /**\r
+                 * \brief Mapping from each DMA channel to a TCC. This specific\r
+                 * TCC code will be returned when the transfer is completed\r
+                 * on the mapped channel.\r
+                 */\r
+               {\r
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
+               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping of DMA channels to Hardware Events from\r
+                * various peripherals, which use EDMA for data transfer.\r
+                * All channels need not be mapped, some can be free also.\r
+                */\r
+               {\r
+               0xFFFFFFFFu,\r
+               0xFF000000u\r
+               }\r
+               },\r
+\r
+               {\r
+               /* EDMA3 INSTANCE# 2 */\r
+               /** Total number of DMA Channels supported by the EDMA3 Controller */\r
+               64u,\r
+               /** Total number of QDMA Channels supported by the EDMA3 Controller */\r
+               8u,\r
+               /** Total number of TCCs supported by the EDMA3 Controller */\r
+               64u,\r
+               /** Total number of PaRAM Sets supported by the EDMA3 Controller */\r
+               512u,\r
+               /** Total number of Event Queues in the EDMA3 Controller */\r
+               4u,\r
+               /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */\r
+               4u,\r
+               /** Number of Regions on this EDMA3 controller */\r
+               8u,\r
+\r
+               /**\r
+                * \brief Channel mapping existence\r
+                * A value of 0 (No channel mapping) implies that there is fixed association\r
+                * for a channel number to a parameter entry number or, in other words,\r
+                * PaRAM entry n corresponds to channel n.\r
+                */\r
+               1u,\r
+\r
+               /** Existence of memory protection feature */\r
+               1u,\r
+\r
+               /** Global Register Region of CC Registers */\r
+               (void *)0x02740000u,\r
+               /** Transfer Controller (TC) Registers */\r
+               {\r
+               (void *)0x02790000u,\r
+               (void *)0x02798000u,\r
+               (void *)0x027A0000u,\r
+               (void *)0x027A8000u,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL,\r
+               (void *)NULL\r
+               },\r
+               /** Interrupt no. for Transfer Completion */\r
+               24u,\r
+               /** Interrupt no. for CC Error */\r
+               16u,\r
+               /** Interrupt no. for TCs Error */\r
+               {\r
+               18u,\r
+               19u,\r
+               20u,\r
+               21u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               },\r
+\r
+               /**\r
+                * \brief EDMA3 TC priority setting\r
+                *\r
+                * User can program the priority of the Event Queues\r
+                * at a system-wide level.  This means that the user can set the\r
+                * priority of an IO initiated by either of the TCs (Transfer Controllers)\r
+                * relative to IO initiated by the other bus masters on the\r
+                * device (ARM, DSP, USB, etc)\r
+                */\r
+               {\r
+               0u,\r
+               1u,\r
+               2u,\r
+               3u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+               /**\r
+                * \brief To Configure the Threshold level of number of events\r
+                * that can be queued up in the Event queues. EDMA3CC error register\r
+                * (CCERR) will indicate whether or not at any instant of time the\r
+                * number of events queued up in any of the event queues exceeds\r
+                * or equals the threshold/watermark value that is set\r
+                * in the queue watermark threshold register (QWMTHRA).\r
+                */\r
+               {\r
+               16u,\r
+               16u,\r
+               16u,\r
+               16u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief To Configure the Default Burst Size (DBS) of TCs.\r
+                * An optimally-sized command is defined by the transfer controller\r
+                * default burst size (DBS). Different TCs can have different\r
+                * DBS values. It is defined in Bytes.\r
+                */\r
+               {\r
+               128u,\r
+               64u,\r
+               64u,\r
+               128u,\r
+               0u,\r
+               0u,\r
+               0u,\r
+               0u\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping from each DMA channel to a Parameter RAM set,\r
+                * if it exists, otherwise of no use.\r
+                */\r
+               {\r
+               EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,\r
+        EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP\r
+               },\r
+\r
+                /**\r
+                 * \brief Mapping from each DMA channel to a TCC. This specific\r
+                 * TCC code will be returned when the transfer is completed\r
+                 * on the mapped channel.\r
+                 */\r
+               {\r
+               0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,\r
+               8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,\r
+               16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,\r
+               24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,\r
+               32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,\r
+               EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP\r
+               },\r
+\r
+               /**\r
+                * \brief Mapping of DMA channels to Hardware Events from\r
+                * various peripherals, which use EDMA for data transfer.\r
+                * All channels need not be mapped, some can be free also.\r
+                */\r
+               {\r
+               0xFFFFFFFFu,\r
+               0xFF000000u\r
+               }\r
+               },\r
+       };\r
+\r
+\r
+int32_t   *ti_sdo_fc_edmamgr_region2Instance = (int32_t*)&edmaMgrRegion2Instance[0];\r
+EDMA3_GblConfigParams    *ti_sdo_fc_edmamgr_edma3GblConfigParams = (EDMA3_GblConfigParams*)&edmaMgrGblConfigParams[0];\r
+EDMA3_InstanceInitConfig *ti_sdo_fc_edmamgr_edma3RegionConfig    = (EDMA3_InstanceInitConfig*)&edmaMgrInstanceInitConfig[0][0];\r
index f9d06d345a05fb799fe0d8a0fa8098695487d2b0..5a61616da32e6d4e11e4072a8f554fa3a20d9da6 100644 (file)
 #include <xdc/std.h>
 #include <ti/xdais/ires.h>
 
-#include <ti/sdo/fc/edma3/edma3_config.h>
-#include <ti/sdo/fc/rman/rman.h>
-
 /* Get globals from cfg header */
 #include <xdc/cfg/global.h>
 
+#include <algLoc.h>
+#include <algEdma.h>
+#include <appRman.h>
+
 //#define FC_TRACE
 #ifdef FC_TRACE
 #include <ti/sdo/fc/global/FCSettings.h>
 #include <xdc/runtime/Diags.h>
 #endif
-/*********************************************************************************
- * FUNCTION PURPOSE: Init RMAN resources
- *********************************************************************************
-  DESCRIPTION:      This function initializes RMAN resouces
-
-  Parameters :      Inputs: edmaInstanceId  : ID of EDMA instance to be used
-                            coreId          : core ID
-                    Output: TRUE if initialization successful; FALSE otherwise
- *********************************************************************************/
-extern const EDMA3_InstanceInitConfig C6678_config[][EDMA3_MAX_REGIONS];
-Bool app_rman_init(unsigned int edmaInstanceId, unsigned int coreId)
-{
-    EDMA3_PARAMS.regionConfig = (EDMA3_InstanceInitConfig *)&C6678_config[edmaInstanceId][coreId];
-    IRES_Status             ires_status;
-
-#ifdef FC_TRACE
-    /* Set default mask for FC modules */
-    FCSettings_init();
-    Diags_setMask(FCSETTINGS_MODNAME"+EX1234567");
-#endif
-
-    /* specify EDMA instance ID */
-    ti_sdo_fc_edma3_EDMA3_physicalId = edmaInstanceId;
-
-    /* RMAN init */
-    ires_status = RMAN_init();
-
-    if (IRES_OK != ires_status) {
-        return FALSE;
-    }
-    return TRUE;
-}
 
 /*********************************************************************************
- * FUNCTION PURPOSE: Assign and activate RMAN resources
+ * FUNCTION PURPOSE: Assign and activate EdmaMgr resources
  *********************************************************************************
   DESCRIPTION:      This function assigns and activates RMAN resouces
 
@@ -92,24 +61,34 @@ Bool app_rman_init(unsigned int edmaInstanceId, unsigned int coreId)
  *********************************************************************************/
 Bool app_rman_assign_resources(void* algHandle, void* resFxns)
 {
-    IRES_Status ires_status;
-    Int scratchId = 0; 
+  algInst_t *inst;
+  ALG_EDMA_Struct *algEdmaState;
+
+  inst = (algInst_t*)algHandle;
+  algEdmaState = &(inst->alg_edma_state); 
+  if ( inst->alg_edma_status != ALG_EDMA_STATE_ALLOCATED )
+  {
+    algEdmaState->num_channels = 0;
+
+    while ( algEdmaState->num_channels < ALG_NUM_EDMA_CH )
+    {
+      algEdmaState->channel[algEdmaState->num_channels] = EdmaMgr_alloc(ALG_MAX_EDMA_LINKS);
     
-    /* RMAN assign resource */
-    ires_status = RMAN_assignResources((IALG_Handle)algHandle, (IRES_Fxns*)resFxns, scratchId);
-    if (ires_status != IRES_OK) {
-        return FALSE;
+      if (algEdmaState->channel[algEdmaState->num_channels] == NULL)
+       return FALSE;
+
+      algEdmaState->num_channels++;
     }
+  }
+  inst->alg_edma_status = ALG_EDMA_STATE_ALLOCATED;
 
-    /* RMAN activate all resource */
-    RMAN_activateAllResources((IALG_Handle)algHandle, (IRES_Fxns*)resFxns, scratchId);
-    return TRUE;
+  return TRUE;
 }
 
 /*********************************************************************************
- * FUNCTION PURPOSE: Free RMAN resources
+ * FUNCTION PURPOSE: Free EdmaMgr resources
  *********************************************************************************
-  DESCRIPTION:      This function frees RMAN resouces
+  DESCRIPTION:      This function frees EdmaMgr resouces
 
   Parameters :      Inputs: algHandle   : alg handle
                             resFxns     : IRES function pointers
@@ -117,15 +96,27 @@ Bool app_rman_assign_resources(void* algHandle, void* resFxns)
  *********************************************************************************/
 Bool app_rman_free_resources(void* algHandle, void* resFxns)
 {
-    IRES_Status ires_status;
-    Int scratchId = 0; 
-
-    /* RMAN free resource */
-    ires_status = RMAN_freeResources((IALG_Handle)algHandle, (IRES_Fxns*)resFxns, scratchId);
-    if (ires_status != IRES_OK) {
-        return FALSE;
+  int      ret_val;
+  algInst_t *inst;
+  ALG_EDMA_Struct *algEdmaState;
+
+  inst = (algInst_t*)algHandle;
+  algEdmaState = &(inst->alg_edma_state); 
+
+  /* RMAN free resource */
+  if ( inst->alg_edma_status == ALG_EDMA_STATE_ALLOCATED )
+  {
+    while ( algEdmaState->num_channels > 0 )
+    {
+      ret_val = EdmaMgr_free(algEdmaState->channel[algEdmaState->num_channels-1]);
+      if (ret_val != EdmaMgr_SUCCESS)
+       return FALSE;
+    
+      algEdmaState->num_channels--;
     }
+  }
+  inst->alg_edma_status = ALG_EDMA_STATE_INIT;
 
-    return TRUE;
+  return TRUE;
 }
 
index e4eb3b48d8e4fb9deea793f48c8fa807c4a21e14..bfa8e1f05f7d91d6df42a43b56195054f8e2bc97 100644 (file)
@@ -37,7 +37,6 @@
  *\r
 */\r
 \r
-Bool app_rman_init(unsigned int edmaInstanceId, unsigned int coreId);\r
 Bool app_rman_assign_resources(void* algHandle, void* resFxns);\r
 Bool app_rman_free_resources(void* algHandle, void* resFxns);\r
 \r
index 5b432b6bb711c310e40a0030e697f8b5950019f6..ec3841681f9d692951ac03a83c1c5d143d170671 100644 (file)
 #include <ti/sysbios/family/c66/Cache.h>
 #include <ti/xdais/ires.h>
 
-#include "algLoc.h"
-#include "appRman.h"
-
-extern IRES_Fxns ALG_EDMA_IRES;
+#include "../../alg/algLoc.h"
+#include "../../alg/algEdma.h"
+#include "./rman/appRman.h"
 
 int main_C6678(int argc, char **args); /* Expect user main redefined to main_C6678. */
 
@@ -122,37 +121,25 @@ int main(int argc, char **args)
    int i;
    void *algHandle;
    algInst_t *inst;
-   ALG_EDMA_Struct *algEdmaState;
 
    /* Cache configuration */
    cache_config();
 
-   /* RMAN resource init */
-   ret_val = app_rman_init(edmaInstances[core_id], core_id);
-   app_assert( (ret_val == TRUE), core_id, "resource_init failed \n");
-
-   IRES_Fxns *resFxns = &ALG_EDMA_IRES;
-
    /* Create Alg */
    alg_create(&algHandle);
 
+   app_assert( (EdmaMgr_init(DNUM, NULL) == EdmaMgr_SUCCESS), DNUM, "EdmaMgr_init() return error!");
+   inst = (algInst_t*)algHandle;
+   inst->alg_edma_status = ALG_EDMA_STATE_INIT;
+
    /* RMAN assign resource to Alg*/
-   ret_val = app_rman_assign_resources(algHandle, resFxns);
+   ret_val = app_rman_assign_resources(algHandle, NULL);
    app_assert( (ret_val == TRUE), core_id, "assign_resources failed \n");
 
-   /* Activate ECPY */
-   inst = (algInst_t *)algHandle;               // Get algorithm handle.
-   algEdmaState = &(inst->alg_edma_state);      // Use it to get EDMA State.
-
-   for (i=0;i<NUM_EDMA_CH;i++)
-   {
-      ALG_EDMA_HW_assign(&(algEdmaState->ecpyChan[i]));
-   }
-
    i = main_C6678(argc, args);                  // Transfer to new main.
 
    /* RMAN free resource*/
-   ret_val = app_rman_free_resources(algHandle, resFxns);
+   ret_val = app_rman_free_resources(algHandle, NULL);
    app_assert( (ret_val == TRUE), core_id, "free_resources failed \n");
    return(i);                                   // Exit with main_C6678 ret value.
 }
index e57164c679576faa7db545dd84d3ffdb1313ac4b..8ff0b069d44ebdd83461554478e8e12f2e99b89c 100644 (file)
 #ifndef _ALG_H
 #define _ALG_H
 
-#include <ti/xdais/ires.h>
-\r
-extern IRES_Fxns ALG_EDMA_IRES;\r
-
 void alg_create(void **algHandle);
 void alg_process(void);             /* Modified by Tony C for ATLAS example. */
  
index 475d7fa4fe77397a28510bfdda50fb14eee9b4b9..0256b3271e5ab93167c43a2bf7ff62e0e25d8992 100644 (file)
@@ -1,13 +1,13 @@
 export COMPILER_BASE_DIR="/opt/ti/TI_CGT_C6000_7.4.2"
 export C6X_C_DIR="${COMPILER_BASE_DIR}/include;${COMPILER_BASE_DIR}/lib"
 export PATH="${COMPILER_BASE_DIR}/bin:$PATH"
-export XDCROOT="/opt/ti/xdctools_3_23_04_60/"
+export XDCROOT="/opt/ti/xdctools_3_25_02_70/"
 
 # Set up envs for the ECPY example
 TI_BASE_DIR="/opt/ti"
-export EDMA3LLD_DIR=$TI_BASE_DIR/edma3_lld_02_11_05_02/packages
-export BIOS_DIR=$TI_BASE_DIR/bios_6_33_06_50/packages
-export XDC_DIR=$TI_BASE_DIR/xdctools_3_23_04_60
+export EDMA3LLD_DIR=$TI_BASE_DIR/edma3_lld_02_11_10_09/packages
+export BIOS_DIR=$TI_BASE_DIR/bios_6_35_04_50/packages
+export XDC_DIR=$TI_BASE_DIR/xdctools_3_25_02_70
 export CGEN_DIR=$COMPILER_BASE_DIR
-export FC_DIR=$TI_BASE_DIR/framework_components_3_23_02_16/packages
+export FC_DIR=$TI_BASE_DIR/framework_components_3_30_00_04_eng/packages
 export XDAIS_DIR=$TI_BASE_DIR/xdais_7_23_00_06/packages
index 0ea66447e46db84c25efec1d8c64173153ae69a3..d488422198f327df59c26502c34f19aea6b70a5c 100644 (file)
Binary files a/blas/lib/libatlas.a and b/blas/lib/libatlas.a differ
index bacbbe6590d1666edb79af3a8753c8e5bf450b6b..8e0fc4a6dcf8f396c6541fec099f8c022756df62 100644 (file)
Binary files a/blas/lib/libcblas.a and b/blas/lib/libcblas.a differ
index 9283251c3c768c87d6041b3155060189dc676a08..0f3cc92fb0e9f21ec254981045c48460eadbd501 100644 (file)
Binary files a/blas/lib/liblapack.a and b/blas/lib/liblapack.a differ
index 73721a4cb0c9dc6bcfac2b3a4f4e1ff36fcafcbe..0e3314a460afc6b50eaacbd667962361cd50ae96 100644 (file)
Binary files a/blas/lib/libtstatlas.a and b/blas/lib/libtstatlas.a differ
index ea44fa628696a1fc6310cc0c46f0563765df8dc9..cf7b5fda60e0326643383eb230fbd7673f56f3bc 100644 (file)
@@ -6,6 +6,7 @@ Table of Contents
  01.00.00.00. Initial Release \r
  01.01.00.00. Optimized ECPY Release \r
  03.11.00.00. First Release Version \r
+ 03.11.00.01. Using EdmaMgr \r
 \r
 \r
 ================================================================================\r
@@ -26,6 +27,12 @@ Table of Contents
  - Change the version number to match the BLAS version number\r
 ================================================================================\r
 \r
+================================================================================\r
+ 03.11.00.01. Uisng EdmaMgr\r
+ - Using EdmaMgr to replace IRES, ECPY and RMAN\r
+ - Using local addresses to replace global address for L1/L2 working buffer start addresses\r
+================================================================================\r
+\r
 Dirctory Structure:\r
 \r
 - example (folder for the example code of ECPY version of ATLAS libraries)\r
@@ -41,16 +48,16 @@ Building and Testing Environment Setup
 - C6678EVM LE connected to PC via USB\r
 - CCS5.2 installed at /opt/ti/ccsv5\r
 - CGT7.4.2 installed at /opt/ti/TI_CGT_C6000_7.4.2\r
-- XDCTools3.23.04.60 installed at /opt/ti/xdctools_3_23_04_6\r
-- \93xdctools\94 is set up as the symbolic link pointing to /opt/ti/xdctools_3_23_04_6\r
-- bios_6_33_06_50 installed at /opt/ti/                  \r
-- mcsdk_2_01_02_06 installed at /opt/ti\r
-- omp_1_02_00_05 installed at /opt/ti\r
-- pdk_C6678_1_1_2_6 installed at /opt/ti\r
-- edma3_lld_02_11_05_02 installed at /opt/ti\r
+- XDCTools3.25.02.70 installed at /opt/ti/xdctools_3_25_02_7\r
+- \93xdctools\94 is set up as the symbolic link pointing to /opt/ti/xdctools_3_25_02_7\r
+- bios_6_35_04_50 installed at /opt/ti/                  \r
+- mcsdk_3_00_03_15 installed at /opt/ti\r
+- omp_2_01_09_00 installed at /opt/ti\r
+- pdk_C6678_2_1_3_7 installed at /opt/ti\r
+- edma3_lld_02_11_10_09 installed at /opt/ti\r
 - xdais_7_23_00_06 installed at /opt/ti\r
-- framework_components_3_23_02_16 installed at /opt/ti   \r
-- ipc_1_24_03_32 installed at /opt/ti\r
+- framework_components_3_30_00_06 installed at /opt/ti   \r
+- ipc_3_00_04_29 installed at /opt/ti\r
 \r
 \r
 How to Run Examples\r
@@ -60,3 +67,4 @@ How to Run Examples
 - make clean\r
 - make all\r
 - make run\r
+\r