1 /****************************************************************************\r
2 CToolsLib - ETB Library\r
3 \r
4 Copyright (c) 2009-2010 Texas Instruments Inc. (www.ti.com)\r
5 All rights reserved.\r
6 \r
7 Redistribution and use in source and binary forms, with or without\r
8 modification, are permitted provided that the following conditions\r
9 are met:\r
10 1. Redistributions of source code must retain the above copyright\r
11 notice, this list of conditions and the following disclaimer.\r
12 2. Redistributions in binary form must reproduce the above copyright\r
13 notice, this list of conditions and the following disclaimer in the\r
14 documentation and/or other materials provided with the distribution.\r
15 3. The name of the author may not be used to endorse or promote products\r
16 derived from this software without specific prior written permission.\r
17 \r
18 THIS SOFTWARE IS PROVIDED BY THE AUTHOR "AS IS" AND ANY EXPRESS OR\r
19 IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
20 OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
21 IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,\r
22 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT\r
23 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
24 DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
25 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
26 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF\r
27 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
28 ****************************************************************************/\r
29 \r
30 /*! \file TIETB.c\r
31 \version 1.7\r
32 */\r
33 //#include <stdio.h>\r
34 //#include <stdlib.h>\r
35 \r
36 #include "ETBInterface.h"\r
37 #include "ETBAddr.h"\r
38 \r
39 #ifdef DMA_SUPPORT\r
40 #include "edma_dev-c66xx.h"\r
41 \r
42 #if defined(C66AK2Hxx_CSSTM_ETB)\r
43 \r
44 #define GET_GLOBAL_ADDR(addr) (uint32_t)(addr)\r
45 \r
46 #else\r
47 \r
48 #define GET_GLOBAL_ADDR(addr) \\r
49 (uint32_t)( ((uint32_t)(addr)) < (uint32_t)0x00900000 ? \\r
50 ((uint32_t)(addr) | (uint32_t)((DNUM + 16) << 24)) : (uint32_t)(addr) )\r
51 #endif\r
52 #endif\r
53 \r
54 #if DTF_PRESENT\r
55 #include "c6x.h"\r
56 #endif\r
57 \r
58 ////////////////////////////////////////////////////////////////////////////////////////////////\r
59 //\r
60 // Private structs\r
61 //\r
62 ////////////////////////////////////////////////////////////////////////////////////////////////\r
63 \r
64 #if defined(C6657) || defined(C66AK2Hxx) || defined(C66AK2Exx) || defined(C66AK2Hxx_CSSTM_ETB) || defined(C66AK2Exx_CSSTM_ETB)\r
65 \r
66 /* DMA config structure used internally\r
67 for C6657 and keystone2 devices\r
68 */\r
69 typedef struct _DMAConfigInt\r
70 {\r
71 \r
72 uint32_t cc; /* EDMA3 channel controller number. */\r
73 \r
74 uint16_t etbhalfChannel; /* ETB half full channel for DMA draining (needs to\r
75 be able to access the ETB).\r
76 */\r
77 uint16_t etbfullChannel; /* ETB full channel for DMA draining (needs to\r
78 be able to access the ETB).\r
79 */\r
80 uint16_t linkparam[3]; /* 3 additional parameter RAM entry numbers.\r
81 */\r
82 uint32_t dbufAddress; /* DMA Drain buffer address */\r
83 uint32_t dbufWords; /* DMA Drain buffer size in 32-bit words */\r
84 eDMA_Mode mode; /* DMA Drain buffer mode (only eDMA_Circular and\r
85 eDMA_Stop_Buffer are valid values)\r
86 */\r
87 } DMAConfigInt;\r
88 \r
89 #endif\r
90 \r
91 struct _ETBHandle_t\r
92 {\r
93 uint32_t ulContext; /*!< ETB context handle*/\r
94 uint8_t id; /*!< ETB core user ID*/\r
95 uint8_t dnum; /*!< Detected CPU ID*/\r
96 ETB_errorCallback pCallBack; /*!< ETB error callback*/\r
97 \r
98 #if defined(C6657) || defined(C66AK2Hxx) || defined(C66AK2Exx) || defined(C66AK2Hxx_CSSTM_ETB) || defined(C66AK2Exx_CSSTM_ETB)\r
99 \r
100 DMAConfigInt *pDmaConfig; /*!< ETB DMA pointer, NULL when dma not used */\r
101 \r
102 #else\r
103 \r
104 DMAConfig *pDmaConfig; /*!< ETB DMA pointer, NULL when dma not used */\r
105 \r
106 #endif\r
107 \r
108 DMAStatus dmaStatus; /*!< Copy of ETB DMA status, populated when\r
109 ETB_flush_dma is called, used during ETB_read\r
110 calls.\r
111 */\r
112 };\r
113 \r
114 #ifdef __linux\r
115 static uint32_t virtural_ETB_BaseAddress[NUM_ETB_INSTANCES] = {0};\r
116 static uint32_t virtural_DTF_BaseAddress[NUM_ETB_INSTANCES] = {0};\r
117 static uint32_t virtural_PSC_BaseAddress = 0; \r
118 #endif\r
119 \r
120 // Max timeout for ETB DMA transfers to complete\r
121 #define ETB_DMA_TIMEOUT 100000\r
122 \r
123 /* ETB module access handle - virual for this library */\r
124 static ETBHandle stHandle[NUM_ETB_INSTANCES];\r
125 \r
126 /* Enumeration to define the options available to the internal flush function */\r
127 typedef enum _eETB_Options\r
128 {\r
129 eETB_OPT_NONE = 0, /*!< No options selected */\r
130 eETB_STOP_FORMATTER /*!< Stop the formatter once a flush has completed */\r
131 } eETB_OPTIONS;\r
132 \r
133 /* Enumeration for ETB and TBR types */\r
134 typedef enum _ETB_Type\r
135 {\r
136 TBR_TYPE = 0, /*!< TBR type */\r
137 ETB_TYPE /*!< ETB type */\r
138 }ETB_Type;\r
139 \r
140 /* Internal ETB flush function used by API function for common purposes */\r
141 static eETB_Error flush(ETBHandle *pHandle, eETB_OPTIONS options);\r
142 \r
143 /*! RETURN_ETB_CALLBACK\r
144 ImplementaMacro to return API error.\r
145 */\r
146 #define RETURN_ETB_CALLBACK(id,retValue) \\r
147 if ( 0 != stHandle[id].pCallBack ) stHandle[id].pCallBack(retValue); return retValue\r
148 \r
149 // ETBLib symbols for CCS ETB Receiver (Trace capture and decoding)\r
150 // ETBLib symbols need to be placed in external memory (MSMC or DDR3)\r
151 // for STM driver to read from these symbols\r
152 \r
153 #pragma DATA_SECTION(etbLib_buffer_start_addr,"ETBLib_ExtMem");\r
154 #pragma DATA_SECTION(etbLib_buffer_size,"ETBLib_ExtMem");\r
155 #pragma DATA_SECTION(etbLib_buffer_data_start,"ETBLib_ExtMem");\r
156 volatile uint32_t etbLib_buffer_start_addr[NUM_ETB_INSTANCES]; //start of ETB buffer\r
157 volatile uint32_t etbLib_buffer_size[NUM_ETB_INSTANCES]; //number of Bytes\r
158 volatile uint32_t etbLib_buffer_data_start[NUM_ETB_INSTANCES]; //address after circular buffer wrap point, where oldest data starts\r
159 \r
160 #if SYSETB_PRESENT\r
161 \r
162 #pragma DATA_SECTION(etbLib_sys_etb_index,"ETBLib_ExtMem");\r
163 volatile uint32_t etbLib_sys_etb_index = SYS_ETB_ID; //symbol for SYS_ETB index\r
164 \r
165 #endif\r
166 \r
167 /*****************************************************************\r
168 * Data that will be accessed by EDMA3 HW.\r
169 * Application should link this data into appropriate memory so\r
170 * that interference to the application is minimized\r
171 *****************************************************************/\r
172 /*\r
173 * If this data section is located in MSMC or DDR3 memory, it should\r
174 * be put in a non-cacheable region.\r
175 */\r
176 #ifdef DMA_SUPPORT\r
177 \r
178 #pragma DATA_SECTION(etbLib_bufferWrapped,"ETBLib_dmaData");\r
179 \r
180 #if defined(C6670)\r
181 \r
182 #pragma DATA_SECTION(etbLib_cpCicEventClearValue,"ETBLib_dmaData");\r
183 #pragma DATA_SECTION(etbLib_cpCicEventClearIndexReg,"ETBLib_dmaData");\r
184 \r
185 static uint32_t etbLib_cpCicEventClearValue[2][NUM_ETB_INSTANCES][2] = {\r
186 {\r
187 {CIC1_EVT_TETBHFULLINT0, CIC1_EVT_TETBFULLINT0},\r
188 {CIC1_EVT_TETBHFULLINT1, CIC1_EVT_TETBFULLINT1},\r
189 {CIC1_EVT_TETBHFULLINT2, CIC1_EVT_TETBFULLINT2},\r
190 {CIC1_EVT_TETBHFULLINT3, CIC1_EVT_TETBFULLINT3},\r
191 {0, 0},\r
192 {0, 0},\r
193 {0, 0},\r
194 {0, 0},\r
195 {CIC1_EVT_TETBHFULLINT, CIC1_EVT_TETBFULLINT}\r
196 },\r
197 {\r
198 {CIC2_EVT_TETBHFULLINT0, CIC2_EVT_TETBFULLINT0},\r
199 {CIC2_EVT_TETBHFULLINT1, CIC2_EVT_TETBFULLINT1},\r
200 {CIC2_EVT_TETBHFULLINT2, CIC2_EVT_TETBFULLINT2},\r
201 {CIC2_EVT_TETBHFULLINT3, CIC2_EVT_TETBFULLINT3},\r
202 {0, 0},\r
203 {0, 0},\r
204 {0, 0},\r
205 {0, 0},\r
206 {CIC2_EVT_TETBHFULLINT, CIC2_EVT_TETBFULLINT}\r
207 }\r
208 };\r
209 \r
210 static uint32_t etbLib_cpCicEventClearIndexReg[2] = {CIC1_STATUS_CLR_INDEX_REG, CIC2_STATUS_CLR_INDEX_REG};\r
211 \r
212 #elif defined(C6678)\r
213 \r
214 #pragma DATA_SECTION(etbLib_cpCicEventClearValue,"ETBLib_dmaData");\r
215 #pragma DATA_SECTION(etbLib_cpCicEventClearIndexReg,"ETBLib_dmaData");\r
216 \r
217 static uint32_t etbLib_cpCicEventClearValue[2][NUM_ETB_INSTANCES][2] =\r
218 {\r
219 {\r
220 {CIC2_EVT_TETBHFULLINT0, CIC2_EVT_TETBFULLINT0},\r
221 {CIC2_EVT_TETBHFULLINT1, CIC2_EVT_TETBFULLINT1},\r
222 {CIC2_EVT_TETBHFULLINT2, CIC2_EVT_TETBFULLINT2},\r
223 {CIC2_EVT_TETBHFULLINT3, CIC2_EVT_TETBFULLINT3},\r
224 {CIC2_EVT_TETBHFULLINT4, CIC2_EVT_TETBFULLINT4},\r
225 {CIC2_EVT_TETBHFULLINT5, CIC2_EVT_TETBFULLINT5},\r
226 {CIC2_EVT_TETBHFULLINT6, CIC2_EVT_TETBFULLINT6},\r
227 {CIC2_EVT_TETBHFULLINT7, CIC2_EVT_TETBFULLINT7},\r
228 {CIC2_EVT_TETBHFULLINT, CIC2_EVT_TETBFULLINT}\r
229 },\r
230 {\r
231 {CIC3_EVT_TETBHFULLINT0, CIC3_EVT_TETBFULLINT0},\r
232 {CIC3_EVT_TETBHFULLINT1, CIC3_EVT_TETBFULLINT1},\r
233 {CIC3_EVT_TETBHFULLINT2, CIC3_EVT_TETBFULLINT2},\r
234 {CIC3_EVT_TETBHFULLINT3, CIC3_EVT_TETBFULLINT3},\r
235 {CIC3_EVT_TETBHFULLINT4, CIC3_EVT_TETBFULLINT4},\r
236 {CIC3_EVT_TETBHFULLINT5, CIC3_EVT_TETBFULLINT5},\r
237 {CIC3_EVT_TETBHFULLINT6, CIC3_EVT_TETBFULLINT6},\r
238 {CIC3_EVT_TETBHFULLINT7, CIC3_EVT_TETBFULLINT7},\r
239 {CIC3_EVT_TETBHFULLINT, CIC3_EVT_TETBFULLINT}\r
240 }\r
241 };\r
242 \r
243 static uint32_t etbLib_cpCicEventClearIndexReg[2] = {CIC2_STATUS_CLR_INDEX_REG, CIC3_STATUS_CLR_INDEX_REG};\r
244 \r
245 #endif\r
246 \r
247 static uint32_t etbLib_bufferWrapped[NUM_ETB_INSTANCES][2];\r
248 \r
249 #pragma DATA_SECTION(etb_disable,"ETBLib_dmaData");\r
250 static uint32_t etb_disable = 0x0;\r
251 \r
252 #endif //#ifdef DMA_SUPPORT\r
253 \r
254 /**\r
255 * Normalize_ID(uint32_t id) - Normalize core/sys ETB ID\r
256 */\r
257 static uint32_t Normalize_ID(uint32_t id)\r
258 {\r
259 #if SYSETB_PRESENT\r
260 if(id == SYS_ETB || id == SYS_ETB_ID)\r
261 {\r
262 id = SYS_ETB_ID;\r
263 }\r
264 #endif\r
265 return id;\r
266 }\r
267 \r
268 /**\r
269 * Handle_index(uint32_t id) - Get handle id for the core/sys ETB\r
270 */\r
271 static uint32_t Handle_index(uint32_t id)\r
272 {\r
273 #if SYSETB_PRESENT\r
274 if(id == SYS_ETB || id == SYS_ETB_ID)\r
275 {\r
276 id = NUM_ETB_INSTANCES -1;\r
277 }\r
278 #endif\r
279 return id;\r
280 }\r
281 \r
282 /**\r
283 * Check whether the coreID passed is associated with a TI-ETB or TBR implementation\r
284 * returns TBR_TYPE = 0 - for TBR implementation and ETB_TYPE = 1 - for TI-ETB implementation\r
285 */\r
286 static ETB_Type check_etb_type(uint32_t id)\r
287 {\r
288 uint32_t dev_id;\r
289 // Read ETB device ID register\r
290 dev_id = *((volatile uint32_t*)ETB_DEVID(id));\r
291 \r
292 if(dev_id == ETB_DEVICE_ID)\r
293 {\r
294 // Return TI-ETB type\r
295 return(ETB_TYPE);\r
296 }\r
297 else if(dev_id == TBR_DEVICE_ID)\r
298 {\r
299 //Return TBR type\r
300 return(TBR_TYPE);\r
301 }\r
302 \r
303 //By default always return TI-ETB type\r
304 return(ETB_TYPE);\r
305 }\r
306 \r
307 #if !defined(C66AK2Hxx_CSSTM_ETB) && !defined(C66AK2Exx_CSSTM_ETB) && !defined(_OMAP54xx)\r
308 \r
309 /**\r
310 * Need_DTF(ETBHandle* pHandle) - Do we need to program DTF. Returns 1 (true) or 0 (false)\r
311 */\r
312 static uint32_t Need_DTF(ETBHandle* pHandle)\r
313 {\r
314 #if SYSETB_PRESENT\r
315 if(pHandle->id == SYS_ETB || pHandle->id == SYS_ETB_ID)\r
316 {\r
317 return 0;\r
318 }\r
319 #endif\r
320 \r
321 if (pHandle->id != pHandle->dnum)\r
322 {\r
323 return 0;\r
324 }\r
325 \r
326 #if DTF_PRESENT\r
327 return 1;\r
328 #else\r
329 return 0;\r
330 #endif\r
331 }\r
332 \r
333 /**\r
334 * Workaround_portownership() - Work around to setup correct debug port ownership\r
335 */\r
336 static void Workaround_portownership()\r
337 {\r
338 uint32_t status=0;\r
339 status = *(volatile uint32_t*)0x1bc013c;\r
340 status= status | 01;\r
341 *(volatile uint32_t*)0x1bc013c = status;\r
342 }\r
343 \r
344 \r
345 /**\r
346 * Program_Power_Sleep() - Work around to setup correct debug port ownership\r
347 */\r
348 eETB_Error Program_Power_Sleep(uint8_t coreID)\r
349 {\r
350 uint32_t status=0;\r
351 uint32_t ptcmdValue = 0;\r
352 uint32_t retry = 1000;\r
353 \r
354 /* Program Power and Sleep Controls */\r
355 #if defined(TCI6484)\r
356 /* Enable DEBUGSS */\r
357 *((volatile uint32_t*)PSC_MDCTL(6)) = 0x3;\r
358 \r
359 /* Power domain Go transition command */\r
360 ptcmdValue = 0x1;\r
361 \r
362 #elif defined(C66x)\r
363 /* If etb powered up and both etb and debugss enabled then exit */\r
364 {\r
365 uint32_t etb_power_state;\r
366 uint32_t debugss_cptracers_enable;\r
367 uint32_t etb_enable;\r
368 \r
369 etb_power_state = *((volatile uint32_t*)PSC_PDSTAT(1));\r
370 \r
371 debugss_cptracers_enable = *((volatile uint32_t*)PSC_MDSTAT(5));\r
372 \r
373 etb_enable = *((volatile uint32_t*)PSC_MDSTAT(6));\r
374 \r
375 if ((etb_power_state & 1) && (debugss_cptracers_enable & 3) && (etb_enable & 3))\r
376 {\r
377 return eETB_Success;\r
378 }\r
379 }\r
380 \r
381 /* Enable TETB power domain*/\r
382 \r
383 /* Power domain Go transition command for TETB power domain */\r
384 ptcmdValue = 0x2;\r
385 \r
386 /* Power up DebugSS */\r
387 *((volatile uint32_t*)PSC_PDCTL(1)) = 0x1;\r
388 \r
389 // Issue GO for the DebugSS power domain\r
390 *((volatile uint32_t*)PSC_PTCMD) = ptcmdValue;\r
391 \r
392 //Wait for the domain transition to complete\r
393 do\r
394 {\r
395 status = *(volatile uint32_t*)PSC_PTSTAT;\r
396 retry--;\r
397 } while( ( ( status & ptcmdValue ) != 0 ) && ( retry != 0 ) );\r
398 if ( retry == 0 ) return eETB_Error_Psc_Enabling;\r
399 \r
400 /* Enable DEBUGSS subsystem */\r
401 *((volatile uint32_t*)PSC_MDCTL(5)) = 0x3;\r
402 /* Enable Per-core TETB and system TETB subsystem */\r
403 *((volatile uint32_t*)PSC_MDCTL(6)) = 0x3;\r
404 \r
405 #endif\r
406 \r
407 /* Power domain Go transition command for enabled power domain */\r
408 *((volatile uint32_t*)PSC_PTCMD) = ptcmdValue;\r
409 \r
410 //Wait for the domain transition to complete\r
411 retry = 1000;\r
412 do\r
413 {\r
414 status = *(volatile uint32_t*)PSC_PTSTAT;\r
415 retry--;\r
416 } while( ( ( status & ptcmdValue ) != 0 ) && ( retry != 0 ) );\r
417 if ( retry == 0 ) return eETB_Error_Psc_Enabling;\r
418 \r
419 /* Check that the modules have been properly enabled */\r
420 #if defined(TCI6484)\r
421 if ((*((volatile uint32_t*)PSC_MDSTAT(6)) & 0x3F) != 0x3)\r
422 return eETB_Error_Psc_Enabling;\r
423 \r
424 Workaround_portownership();\r
425 \r
426 #elif defined(C66x)\r
427 if ((*((volatile uint32_t*)PSC_MDSTAT(5)) & 0x3F) != 0x3 ||\r
428 (*((volatile uint32_t*)PSC_MDSTAT(6)) & 0x3F) != 0x3)\r
429 return eETB_Error_Psc_Enabling;\r
430 Workaround_portownership();\r
431 \r
432 #endif\r
433 return eETB_Success;\r
434 }\r
435 //#endif //#ifndef _OMAP54xx\r
436 #endif\r
437 \r
438 #if defined(C6657) || defined(C66AK2Hxx) || defined(C66AK2Exx) || defined(C66AK2Hxx_CSSTM_ETB)\r
439 \r
440 static uint8_t get_edma_buffer_info (ETBHandle* pHandle, DMAStatus *pStatus, uint32_t paramAddress, uint16_t paramIdx, int32_t remWords)\r
441 {\r
442 int32_t remBytes;\r
443 \r
444 remBytes = (remWords * 4);\r
445 \r
446 /* Check for buffer wrap */\r
447 if(etbLib_bufferWrapped[pHandle->id][0])\r
448 {\r
449 pStatus->availableWords = pHandle->dmaStatus.dbufWords;\r
450 pStatus->startAddr = PARAM_DST_REG(paramAddress) + remBytes;\r
451 pStatus->isWrapped = 1;\r
452 }\r
453 else\r
454 {\r
455 pStatus->availableWords = (PARAM_DST_REG(paramAddress) -\r
456 pHandle->pDmaConfig->dbufAddress) / 4;\r
457 pStatus->availableWords += remWords;\r
458 pStatus->startAddr = pHandle->pDmaConfig->dbufAddress;\r
459 pStatus->isWrapped = 0;\r
460 }\r
461 \r
462 /* Copy the DMA status into the handle for later management. The status\r
463 * value for the number of words may be different than what was in the\r
464 * configuration structure. This value is set during configuration.\r
465 */\r
466 pStatus->dbufAddress = pHandle->pDmaConfig->dbufAddress;\r
467 pStatus->dbufWords = pHandle->dmaStatus.dbufWords;\r
468 pStatus->flushRequired = pHandle->dmaStatus.flushRequired;\r
469 pHandle->dmaStatus = *pStatus;\r
470 \r
471 /* If the mode has been set to non-circular and the buffer wrapped flag\r
472 * is set, then the memory buffer if full, otherwise continue the\r
473 * configuration for the final DMA.\r
474 */\r
475 if((pHandle->pDmaConfig->mode == eDMA_Stop_Buffer) &&\r
476 (etbLib_bufferWrapped[pHandle->id][0]))\r
477 {\r
478 /* If the buffer wrapped, the startAddr value is incorrect from\r
479 * above, set back to beginning of the buffer.\r
480 */\r
481 pStatus->startAddr = pHandle->pDmaConfig->dbufAddress;\r
482 pHandle->dmaStatus.startAddr = pHandle->pDmaConfig->dbufAddress;\r
483 return(1);\r
484 }\r
485 \r
486 // Update the 3 symbols which are required for CCS ETB receiver\r
487 etbLib_buffer_start_addr[pHandle->id] = pHandle->pDmaConfig->dbufAddress; //CCS ETB receiver will always get a linearized buffer for the non-EDMA ETB drain case\r
488 etbLib_buffer_size[pHandle->id] = pStatus->availableWords * 4; //Number of bytes available\r
489 etbLib_buffer_data_start[pHandle->id] = pStatus->startAddr; //circular buffer wrap point\r
490 \r
491 return(0);\r
492 }\r
493 \r
494 #endif\r
495 \r
496 /**\r
497 * ETB_open - open ETB programming module interface\r
498 */\r
499 \r
500 eETB_Error ETB_open(ETB_errorCallback pErrCallBack, eETB_Mode mode, uint8_t coreID, ETBHandle** ppHandle, uint32_t* pETBSizeInWords)\r
501 {\r
502 uint32_t dnum = 0;\r
503 uint32_t status, value;\r
504 \r
505 #if DTF_PRESENT\r
506 dnum = DNUM;\r
507 #endif\r
508 coreID = Normalize_ID(coreID);\r
509 \r
510 #if SYSETB_PRESENT \r
511 // populate SYS_ETB index symbol\r
512 if(coreID == SYS_ETB_ID)\r
513 {\r
514 etbLib_sys_etb_index = SYS_ETB_ID;\r
515 }\r
516 \r
517 #endif\r
518 \r
519 if(Handle_index(coreID) >= NUM_ETB_INSTANCES)\r
520 {\r
521 return eETB_Error_Bad_Param;\r
522 }\r
523 \r
524 if ((ppHandle == 0 ) || ( pETBSizeInWords == 0) )\r
525 {\r
526 return eETB_Error_Bad_Param;\r
527 }\r
528 \r
529 #ifdef __linux\r
530 virtural_ETB_BaseAddress[coreID] = cTools_memMap(ETB_BaseAddress(coreID), SIZEOF_ETB_SPACE);\r
531 virtural_DTF_BaseAddress[coreID] = cTools_memMap(DTF_BaseAddress(coreID), SIZEOF_DTF_SPACE);\r
532 if (virtural_PSC_BaseAddress == 0)\r
533 {\r
534 virtural_PSC_BaseAddress = cTools_memMap(PSC_BaseAddress, SIZEOF_PSC_SPACE);\r
535 }\r
536 #endif\r
537 \r
538 \r
539 #if !defined(C66AK2Hxx_CSSTM_ETB) && !defined(C66AK2Exx_CSSTM_ETB) && !defined(_OMAP54xx)\r
540 \r
541 eETB_Error retVal = eETB_Success;\r
542 \r
543 retVal = Program_Power_Sleep(coreID);\r
544 if (retVal != eETB_Success)\r
545 return retVal;\r
546 \r
547 #endif\r
548 \r
549 if(check_etb_type(coreID) == ETB_TYPE)\r
550 {\r
551 \r
552 // Reset the ETB\r
553 *((volatile uint32_t*)ETB_TI_CTL(coreID)) = *((volatile uint32_t*)ETB_TI_CTL(coreID)) | 0x4;\r
554 \r
555 /* Unlock ETB in order to enable accesses to any ETB registers below. */\r
556 *((volatile uint32_t*)ETB_LOCK(coreID)) = ETB_UNLOCK_VAL;\r
557 \r
558 /* Size of the ETB. ETB_RDP contains number of 32 bit wide words. */\r
559 *pETBSizeInWords = (*((volatile uint32_t*)ETB_RDP(coreID)));\r
560 \r
561 /* Setup ETB mode */\r
562 if ((eETB_TI_Mode == mode) || (eETB_TI_Mode_AND_Stop_Buffer == mode))\r
563 *((volatile uint32_t*)ETB_TI_CTL(coreID)) = TI_ETB_TI_MODE;\r
564 \r
565 status = *((volatile uint32_t*)ETB_TI_CTL(coreID));\r
566 if((eETB_Stop_Buffer != mode) && (eETB_TI_Mode_AND_Stop_Buffer != mode))\r
567 {\r
568 /* Set TI ETB for circular mode - clear the bit. */\r
569 *((volatile uint32_t*)ETB_TI_CTL(coreID)) = status & ~(TI_ETB_CIRCULARMODE_BIT);\r
570 }\r
571 else\r
572 {\r
573 /* Set TI ETB as stop buffer full mode - set the bit. */\r
574 *((volatile uint32_t*)ETB_TI_CTL(coreID)) = status | TI_ETB_CIRCULARMODE_BIT;\r
575 }\r
576 }\r
577 else //TBR implementation\r
578 {\r
579 // Reset the ETB\r
580 *((volatile uint32_t*)ETB_CTL(coreID)) = *((volatile uint32_t*)ETB_CTL(coreID)) | 0x4;\r
581 \r
582 //Read claim tag value and check if TBR is not already claimed\r
583 // Assumption here is that the debugger will set the claim bit to get ownership of the TBR\r
584 status = *((volatile uint32_t*)TBR_CLAIMCLR(coreID));\r
585 \r
586 if(status != 0)\r
587 {\r
588 return eETB_Error_Cannot_Own;\r
589 }\r
590 \r
591 /* Unlock to enable accesses */\r
592 status = (*((volatile uint32_t*)ETB_LOCK_STATUS(coreID)));\r
593 if (status & LOCK_STATUS_IMP_BIT)\r
594 {\r
595 /* If this bit is set, it device access is locked, we need to unlock the device*/\r
596 if (status & LOCK_STATUS_STAT_BIT)\r
597 {\r
598 /* Unlock ETB in order to enable accesses to any ETB registers below. */\r
599 *((volatile uint32_t*)ETB_LOCK(coreID)) = ETB_UNLOCK_VAL;\r
600 }\r
601 }\r
602 \r
603 /* Size of the ETB. ETB_RDP contains number of 32 bit wide words. */\r
604 value = (*((volatile uint32_t*)ETB_RDP(coreID)));\r
605 *pETBSizeInWords = (1 << (value-1)) << 10;\r
606 \r
607 /* Setup TBR mode */\r
608 value = (*((volatile uint32_t*)ETB_FFCR(coreID)));\r
609 \r
610 /* Setup TBR in buffer mode */\r
611 *((volatile uint32_t*)ETB_CTL(coreID)) &= TBR_BUFFER_MODE;\r
612 \r
613 if((eETB_Stop_Buffer == mode) || (eETB_TI_Mode_AND_Stop_Buffer == mode))\r
614 {\r
615 //Configure stop on Full mode\r
616 (*((volatile uint32_t*)ETB_FFCR(coreID))) = value | TBR_STP_FULL;\r
617 }\r
618 else if((eETB_Circular == mode) || (eETB_TI_Mode == mode))\r
619 {\r
620 //Configure circular mode\r
621 (*((volatile uint32_t*)ETB_FFCR(coreID))) = value & (~(uint32_t)TBR_STP_FULL);\r
622 }\r
623 }\r
624 \r
625 /* Set ETB context in the handle*/\r
626 stHandle[Handle_index(coreID)].ulContext = ETB_UNLOCK_VAL;\r
627 stHandle[Handle_index(coreID)].id = coreID;\r
628 stHandle[Handle_index(coreID)].dnum = dnum;\r
629 stHandle[Handle_index(coreID)].pCallBack = pErrCallBack;\r
630 stHandle[Handle_index(coreID)].pDmaConfig = 0;\r
631 stHandle[Handle_index(coreID)].dmaStatus.startAddr = 0;\r
632 stHandle[Handle_index(coreID)].dmaStatus.availableWords = 0;\r
633 stHandle[Handle_index(coreID)].dmaStatus.isWrapped = 0;\r
634 stHandle[Handle_index(coreID)].dmaStatus.dbufAddress = 0;\r
635 stHandle[Handle_index(coreID)].dmaStatus.dbufWords = 0;\r
636 stHandle[Handle_index(coreID)].dmaStatus.flushRequired = 1;\r
637 \r
638 *ppHandle = &stHandle[Handle_index(coreID)];\r
639 return eETB_Success;\r
640 }\r
641 \r
642 \r
643 #if defined(TCI6484)\r
644 /**\r
645 * TCI6484_discard_nops- TCI6484 ADTF defecrt work around to flush the the stuck packet.\r
646 *\r
647 */\r
648 eETB_Error TCI6484_nops(uint8_t coreID, uint8_t discard)\r
649 {\r
650 uint32_t value = 0;\r
651 \r
652 value = *(volatile uint32_t*)(DTF_CNTL(coreID));\r
653 \r
654 if (discard == 1)\r
655 {\r
656 value = value | (0x2);\r
657 }\r
658 else\r
659 {\r
660 value = value & (~0x2);\r
661 }\r
662 value = value | (0x1<<4);\r
663 \r
664 *(volatile uint32_t*)(DTF_CNTL(coreID)) = value;\r
665 \r
666 return eETB_Success;\r
667 }\r
668 #endif\r
669 \r
670 #if !defined(C66AK2Hxx_CSSTM_ETB) && !defined(C66AK2Exx_CSSTM_ETB) && !defined(_OMAP54xx)\r
671 \r
672 /**\r
673 * DTF_flush - Flush data from the ADTF\r
674 */\r
675 eETB_Error DTF_flush(uint8_t n)\r
676 {\r
677 /* Only ADTF v2 support software flush. Thus, the first step is to read\r
678 version ID to verify to version number */\r
679 \r
680 if ((*(volatile uint32_t*)(ID(n)) & DTF_ID_MAJOR_MASK) == DTF_ID_MAJOR_VER2)\r
681 {\r
682 /* The way the ADTFv2 flush work is to write 1 to the flush bit and then\r
683 clear it after that. That is because ADTF is looking for the rising edge of the signal. */\r
684 *(volatile uint32_t*)(DTF_CNTL(n)) = *(volatile uint32_t*)(DTF_CNTL(n)) | DTF_VER2_FLUSH_BIT;\r
685 }\r
686 \r
687 #if defined(TCI6484) /* ADTF bug work around in TCI6484 */\r
688 /* flush the ADTF */\r
689 TCI6484_nops(n, 0);\r
690 TCI6484_nops(n, 1);\r
691 #endif\r
692 return eETB_Success;\r
693 }\r
694 \r
695 #endif\r
696 \r
697 /**\r
698 * ETB_enable- Enable ETB to capture trace data\r
699 */\r
700 eETB_Error ETB_enable(ETBHandle* pHandle, uint32_t triggerCount)\r
701 {\r
702 uint32_t etbControl;\r
703 uint32_t waitCount = 1000;\r
704 \r
705 \r
706 if(!pHandle || pHandle->ulContext != ETB_UNLOCK_VAL)\r
707 {\r
708 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
709 }\r
710 \r
711 #if !defined(C66AK2Hxx_CSSTM_ETB) && !defined(C66AK2Exx_CSSTM_ETB) && !defined(_OMAP54xx)\r
712 \r
713 /* Setup DTF, if available */\r
714 if(Need_DTF(pHandle))\r
715 {\r
716 uint32_t value;\r
717 /* Unlock to enable accesses */\r
718 value = *(volatile uint32_t*)(DTF_LOCK_STATUS(pHandle->id));\r
719 if (value & LOCK_STATUS_IMP_BIT)\r
720 {\r
721 /* If this bit is set, it device access is locked, we need to unlock the device*/\r
722 if (value & LOCK_STATUS_STAT_BIT)\r
723 {\r
724 *(volatile uint32_t*)(DTF_LOCK(pHandle->id)) = ETB_UNLOCK_VAL;\r
725 }\r
726 }\r
727 /* Claim Tag Set */\r
728 *(volatile uint32_t*)(TAGSET(pHandle->id)) = 0x1;\r
729 \r
730 /* Enable ADTF */\r
731 *(volatile uint32_t*)(DTF_CNTL(pHandle->id)) = *(volatile uint32_t*)(DTF_CNTL(pHandle->id)) | 0x1;\r
732 }\r
733 \r
734 #endif\r
735 \r
736 /* Make sure that tracing is disabled or the write to the following\r
737 * registers will not actually get written.\r
738 */\r
739 *((volatile uint32_t*)ETB_CTL(pHandle->id)) = *((volatile uint32_t*)ETB_CTL(pHandle->id)) & (~ETB_ENABLE);/* DISABLE TraceCaptEn */\r
740 \r
741 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
742 {\r
743 /* ETB FIFO reset by writing 0 to ETB RAM Write Pointer Register. */\r
744 *((volatile uint32_t*)ETB_RWP(pHandle->id)) = 0;\r
745 \r
746 /* Initialize RDP. */\r
747 *((volatile uint32_t*)ETB_RRP(pHandle->id)) = 0;\r
748 \r
749 /* Clear all interrupts before enabling trace, just to make sure nothing pending*/\r
750 *((volatile uint32_t*)ETB_ICST(pHandle->id)) = (TI_ETB_IRST_FULL |\r
751 TI_ETB_IRST_HALF_FULL |\r
752 TI_ETB_IRST_OVERFLOW |\r
753 TI_ETB_IRST_UNDERFLOW);\r
754 }\r
755 else\r
756 {\r
757 /* Clear all interrupts before enabling trace, just to make sure nothing pending*/\r
758 *((volatile uint32_t*)TBR_IRQSTATUS(pHandle->id)) = (TBR_IRST_DAV |\r
759 TBR_IRST_AQCMP);\r
760 }\r
761 \r
762 /* Disable formatting and put ETB formatter into bypass mode. */\r
763 /* Clear all control bits except STP_FULL */\r
764 *((volatile uint32_t*)ETB_FFCR(pHandle->id)) &= TBR_STP_FULL; /* For TI-ETB: EnFCont=0, EnFTC=0 */\r
765 \r
766 if(check_etb_type(pHandle->id) == TBR_TYPE)\r
767 {\r
768 //Set ID period to 8. Artificial ID will be added, if there is no ID change for 8 TWP frames\r
769 *((volatile uint32_t*)TBR_IDPERIOD(pHandle->id)) = TBR_TWP_IDPERIOD;\r
770 \r
771 *((volatile uint32_t*)TBR_SEQCNTL(pHandle->id)) = TBR_TWP_SEQATBID | TBR_TWP_SEQPERIOD;\r
772 \r
773 //Always enable TBR TWP formatter\r
774 *((volatile uint32_t*)ETB_FFCR(pHandle->id)) = *((volatile uint32_t*)ETB_FFCR(pHandle->id)) | TBR_TWP_ENABLE;\r
775 //*((volatile uint32_t*)ETB_FFCR(pHandle->id)) = *((volatile uint32_t*)ETB_FFCR(pHandle->id)) & TBR_TWP_DISABLE;\r
776 }\r
777 \r
778 /* Setup Trigger counter. */\r
779 *((volatile uint32_t*)ETB_TRIG(pHandle->id)) = triggerCount;\r
780 \r
781 #ifdef DMA_SUPPORT\r
782 /* If the DMA has been enabled, indicated by dma pointer non-null, enable\r
783 * the ETB half-full and full interrupts.\r
784 */\r
785 if(pHandle->pDmaConfig != 0)\r
786 {\r
787 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
788 {\r
789 *((volatile uint32_t*)ETB_IER(pHandle->id)) = (TI_ETB_IRST_FULL |\r
790 TI_ETB_IRST_HALF_FULL);\r
791 }\r
792 }\r
793 #endif\r
794 \r
795 /* Enable ETB data capture by writing ETB Control Register. */\r
796 *((volatile uint32_t*)ETB_CTL(pHandle->id)) = *((volatile uint32_t*)ETB_CTL(pHandle->id)) | ETB_ENABLE; /* TraceCaptEn =1 */\r
797 \r
798 /* Put some delays in here - make sure we can read back. */\r
799 do\r
800 {\r
801 etbControl = *((volatile uint32_t*)ETB_CTL(pHandle->id));\r
802 waitCount--;\r
803 } while (((etbControl & 0x1) != ETB_ENABLE) && (waitCount > 0));\r
804 \r
805 if(waitCount ==0)\r
806 {\r
807 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
808 }\r
809 \r
810 return eETB_Success;\r
811 }\r
812 \r
813 /**\r
814 * ETB_disable - Disable ETB to stop capturing trace data\r
815 */\r
816 eETB_Error ETB_disable(ETBHandle* pHandle)\r
817 {\r
818 eETB_Error ret = eETB_Success;\r
819 \r
820 if(!pHandle || pHandle->ulContext != ETB_UNLOCK_VAL)\r
821 {\r
822 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
823 }\r
824 \r
825 /* Flush ETB, wait until after disabling data capture to check status.\r
826 * This function will not return until the flush has completed.\r
827 */\r
828 // Perform Flush + stop formatter only for non-EDMA examples. For EDMA examples \r
829 // the Flush + stop formatter is already done using the ETB_flush() API \r
830 if(pHandle->pDmaConfig == 0)\r
831 {\r
832 ret = flush(pHandle, eETB_STOP_FORMATTER);\r
833 }\r
834 \r
835 #if !defined(C66AK2Hxx_CSSTM_ETB) && !defined(C66AK2Exx_CSSTM_ETB) && !defined(_OMAP54xx)\r
836 \r
837 if(Need_DTF(pHandle))\r
838 {\r
839 /* Disable ADTF */\r
840 *(volatile uint32_t*)(DTF_CNTL(pHandle->id)) = *(volatile uint32_t*)(DTF_CNTL(pHandle->id)) | (~0x1);\r
841 }\r
842 \r
843 #endif\r
844 \r
845 /* Disable ETB data capture by writing ETB Control Register. */\r
846 *((volatile uint32_t*)ETB_CTL(pHandle->id)) = *((volatile uint32_t*)ETB_CTL(pHandle->id)) & (~ETB_ENABLE); /* TraceCaptEn =0 */\r
847 \r
848 if(ret != eETB_Success)\r
849 {\r
850 RETURN_ETB_CALLBACK(pHandle->id, ret);\r
851 }\r
852 \r
853 // Wait for ETB Acquisition Complete\r
854 /* ==> The code to check the ETB_STS register for ETB_STS_ACQCOMP bit\r
855 * is not necessary if a manual flush has occurred and\r
856 * completed. For the TBR case, the disable trace capture will\r
857 * cause a flush, polling this bit would serve a purpose.\r
858 */\r
859 \r
860 #ifdef DMA_SUPPORT\r
861 /* If the DMA has been enabled, indicated by dma pointer non-null, disable\r
862 * the ETB half-full and full interrupts.\r
863 */\r
864 if(pHandle->pDmaConfig != 0)\r
865 {\r
866 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
867 {\r
868 *((volatile uint32_t*)ETB_IECST(pHandle->id)) = (TI_ETB_IRST_FULL |\r
869 TI_ETB_IRST_HALF_FULL);\r
870 }\r
871 else\r
872 {\r
873 *((volatile uint32_t*)TBR_IRQENABLE_CLR(pHandle->id)) = TBR_IRST_DAV;\r
874 }\r
875 }\r
876 #endif\r
877 return ret;\r
878 }\r
879 \r
880 \r
881 /**\r
882 * ETB_status- Get ETB status\r
883 *\r
884 ETB status register .\r
885 STS:\r
886 RAMFull=1 [0], RAMEmpty=0 [0]\r
887 Triggered=1 [1], NotTriggered=0 [1]\r
888 AccqComp=1 [2], NotAccqComp=0 [2]\r
889 FtEmpty=1 [3], NotFtEmpty=0 [3]\r
890 x --> reserved\r
891 v --> read value\r
892 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00\r
893 ________________________________________________________________________________________________\r
894 |x | x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| x| v| v| v| v|\r
895 |__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|\r
896 \r
897 */\r
898 eETB_Error ETB_status(ETBHandle* pHandle, ETBStatus* status)\r
899 {\r
900 uint32_t etbStatus, etbControl=0, etb_size;\r
901 \r
902 if(!pHandle || pHandle->ulContext != ETB_UNLOCK_VAL)\r
903 {\r
904 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
905 }\r
906 \r
907 if(status == 0 )\r
908 {\r
909 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Bad_Param);\r
910 }\r
911 \r
912 //Get ETB Trace capture enable status\r
913 status->ETB_TraceCaptureEn = *((volatile uint32_t*)ETB_CTL(pHandle->id));\r
914 \r
915 #ifdef DMA_SUPPORT\r
916 \r
917 if(pHandle->pDmaConfig != 0)\r
918 {\r
919 uint32_t paramAddress;\r
920 uint16_t paramIdx;\r
921 \r
922 #if defined(C6657) || defined(C66AK2Hxx) || defined(C66AK2Exx)\r
923 \r
924 paramIdx = (EDMA3_DCHMAP_REG(pHandle->pDmaConfig->cc,\r
925 pHandle->pDmaConfig->etbhalfChannel) >> 5);\r
926 \r
927 #elif defined(C6670) || defined(C6678)\r
928 \r
929 paramIdx = (EDMA3_DCHMAP_REG(pHandle->pDmaConfig->cc,\r
930 pHandle->pDmaConfig->etbChannel) >> 5);\r
931 #endif\r
932 \r
933 paramAddress = EDMA_TPCC_PARAM_BASE_ADDR(pHandle->pDmaConfig->cc) +\r
934 (0x20 * paramIdx);\r
935 \r
936 /* Check for buffer wrap */\r
937 if(etbLib_bufferWrapped[pHandle->id][0])\r
938 {\r
939 status->availableWords = pHandle->dmaStatus.dbufWords;\r
940 status->isWrapped = 1;\r
941 status->canRead = 1;\r
942 }\r
943 else\r
944 {\r
945 status->availableWords = (PARAM_DST_REG(paramAddress) -\r
946 pHandle->pDmaConfig->dbufAddress) / 4;\r
947 status->isWrapped = 0;\r
948 status->canRead = 1;\r
949 }\r
950 }\r
951 else\r
952 #endif\r
953 {\r
954 status->canRead=0;\r
955 status->availableWords=0;\r
956 status->isWrapped=0;\r
957 status->overflow = 0;\r
958 etbStatus = *((volatile uint32_t*)ETB_STS(pHandle->id));\r
959 \r
960 if (etbStatus & TI_ETB_IRST_OVERFLOW) \r
961 {\r
962 status->overflow = 1;\r
963 }\r
964 \r
965 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
966 {\r
967 if ((TI_ETB_TI_MODE & *((volatile uint32_t*)ETB_TI_CTL(pHandle->id))) ==\r
968 TI_ETB_TI_MODE)\r
969 {\r
970 /* In this case we must take into account the number of words already read */\r
971 status->canRead = 1;\r
972 }\r
973 else\r
974 {\r
975 \r
976 etbControl = *((volatile uint32_t*)ETB_CTL(pHandle->id));\r
977 \r
978 if(etbControl == ETB_ENABLE)\r
979 {\r
980 return eETB_Success;\r
981 }\r
982 \r
983 if((etbStatus & ETB_STS_ACQCOMP) == ETB_STS_ACQCOMP)\r
984 {\r
985 status->canRead = 1;\r
986 }\r
987 }\r
988 \r
989 // get size of the ETB buffer in words\r
990 etb_size = (*((volatile uint32_t*)ETB_RDP(pHandle->id)));\r
991 }\r
992 else\r
993 {\r
994 etbControl = *((volatile uint32_t*)ETB_CTL(pHandle->id));\r
995 \r
996 if(etbControl == ETB_ENABLE)\r
997 {\r
998 return eETB_Success;\r
999 }\r
1000 \r
1001 if((etbStatus & ETB_STS_ACQCOMP) == ETB_STS_ACQCOMP)\r
1002 {\r
1003 status->canRead = 1;\r
1004 }\r
1005 \r
1006 // get size of the TBR buffer in words\r
1007 etb_size = (*((volatile uint32_t*)ETB_RDP(pHandle->id)));\r
1008 etb_size = (1 << (etb_size-1)) << 10;\r
1009 }\r
1010 \r
1011 if ((etbStatus & ETB_STS_FULL) == ETB_STS_FULL)\r
1012 {\r
1013 status->isWrapped = 1;\r
1014 status->availableWords = etb_size;\r
1015 }\r
1016 else\r
1017 status->availableWords = *((volatile uint32_t*)ETB_RWP(pHandle->id));\r
1018 }\r
1019 return eETB_Success;\r
1020 }\r
1021 \r
1022 \r
1023 /**\r
1024 * ETB_read- Read ETB data\r
1025 *\r
1026 * Reference Diagram for DMA drain buffer parameters:\r
1027 *\r
1028 * Wrapped buffer: Non-Wrapped buffer:\r
1029 * _______________ _______________\r
1030 * |_______________| -> dbufStartAddr |_______________| -> dbufStartAddr\r
1031 * | | | | && dataStartAddr\r
1032 * | | | |\r
1033 * // // // //\r
1034 * |_______________| // //\r
1035 * |_______________| -> dataEndAddr |_______________|\r
1036 * |_______________| -> dataStartAddr |_______________| -> dataEndAddr\r
1037 * | | | \\\\\\\\\\\\ |\r
1038 * | | | //////////// | No data\r
1039 * // // // \\\\\\\\\\\\ //\r
1040 * |_______________| | //////////// |\r
1041 * |_______________| -> dbufEndAddr |_______________| -> dbufEndAddr\r
1042 *\r
1043 */\r
1044 eETB_Error ETB_read(ETBHandle* pHandle, uint32_t *pBuffer,\r
1045 uint32_t bufferLength, uint32_t startWord,\r
1046 uint32_t readLength, uint32_t* pRetLength)\r
1047 {\r
1048 ETBStatus status;\r
1049 uint32_t idx, startAddr, depth, value;\r
1050 \r
1051 if(!pHandle || pHandle->ulContext != ETB_UNLOCK_VAL)\r
1052 {\r
1053 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1054 }\r
1055 /* Check if we have proper buffer pointer */\r
1056 if(pBuffer == 0)\r
1057 {\r
1058 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Bad_Param);\r
1059 }\r
1060 \r
1061 *pRetLength =0;\r
1062 \r
1063 #ifdef DMA_SUPPORT\r
1064 /* If the DMA has been configured to empty the ETB, then read from the memory\r
1065 * buffer instead of the ETB hardware registers.\r
1066 */\r
1067 if(pHandle->pDmaConfig != 0)\r
1068 {\r
1069 uint32_t *pDmaBuffer;\r
1070 uint32_t dataStartAddr; // Start of data address in case of wrap\r
1071 uint32_t dataEndAddr; // End of data address\r
1072 uint32_t wordCnt; // Number of words that will be copied\r
1073 int32_t remWords; // Remaining words to read from drain buffer\r
1074 uint32_t dbufEndAddr; // End of buffer address\r
1075 uint32_t dbufStartAddr = pHandle->dmaStatus.dbufAddress;\r
1076 \r
1077 /* Set/calculate address values */\r
1078 dataStartAddr = pHandle->dmaStatus.startAddr;\r
1079 dbufEndAddr = pHandle->dmaStatus.dbufAddress + (pHandle->dmaStatus.dbufWords*4) - 1;\r
1080 \r
1081 /* If the data starting address is not equal to the buffer starting address,\r
1082 * then the buffer has wrapped, the ending data address will be\r
1083 * the previous word's address. Otherwise, it will be the starting address\r
1084 * plus the number of words written into the drain buffer.\r
1085 */\r
1086 if(dataStartAddr > dbufStartAddr)\r
1087 {\r
1088 dataEndAddr = dataStartAddr - sizeof(uint32_t);\r
1089 }\r
1090 else\r
1091 {\r
1092 dataEndAddr = dataStartAddr + ((pHandle->dmaStatus.availableWords-1) * 4);\r
1093 }\r
1094 /* The startWord variable is passed into this function as an offset for\r
1095 * this read request. The value is translated into bytes from words to\r
1096 * get the correct address value to start reading words from the drain\r
1097 * buffer.\r
1098 */\r
1099 startAddr = dataStartAddr + (startWord * 4);\r
1100 \r
1101 /* Check to see if the starting address is past the end of the buffer */\r
1102 // if(startAddr > dbufEndAddr)\r
1103 // {\r
1104 // /* Subtract 1 from the difference to account for 0-based counting */\r
1105 // startAddr = ((startAddr - dbufEndAddr) + dbufStartAddr) - 1;\r
1106 // }\r
1107 \r
1108 /* Initially set the total word count to the specified buffer length,\r
1109 * then check if the requested read length is less, then finally if\r
1110 * the remaining words left in the drain buffer is less.\r
1111 */\r
1112 wordCnt = bufferLength;\r
1113 if(readLength < wordCnt)\r
1114 {\r
1115 wordCnt = readLength;\r
1116 }\r
1117 \r
1118 /* The following calculation is using the remaining words variable to calculate\r
1119 * byte address values. The conversion from bytes to words will occur after the\r
1120 * calculations have been completed.\r
1121 */\r
1122 remWords = dataEndAddr - startAddr;\r
1123 if(remWords < 0)\r
1124 {\r
1125 if(pHandle->dmaStatus.isWrapped)\r
1126 {\r
1127 /* 1 is added back to the end address to use the size vs. address */\r
1128 remWords = ((dbufEndAddr+1) - startAddr) + (dataEndAddr - dbufStartAddr);\r
1129 }\r
1130 else\r
1131 {\r
1132 remWords = 0;\r
1133 }\r
1134 }\r
1135 /* Convert from bytes to words */\r
1136 if(remWords != 0)\r
1137 {\r
1138 remWords /= 4;\r
1139 remWords += 1; /* 1 added for 0-based counting */\r
1140 }\r
1141 \r
1142 if(remWords < wordCnt)\r
1143 {\r
1144 wordCnt = remWords;\r
1145 }\r
1146 \r
1147 /* Loop through and copy the data from the ETB buffer into the provided\r
1148 * buffer.\r
1149 */\r
1150 pDmaBuffer = (uint32_t *)startAddr;\r
1151 for(idx = 0; idx < wordCnt; idx++)\r
1152 {\r
1153 /* Check for startAddr past the total words in the buffer and set\r
1154 * the pointer/address values to the buffer's starting address.\r
1155 */\r
1156 if(startAddr > dbufEndAddr)\r
1157 {\r
1158 pDmaBuffer = (uint32_t *)(pHandle->dmaStatus.dbufAddress + (startAddr - (dbufEndAddr+1)));\r
1159 startAddr = pHandle->dmaStatus.dbufAddress;\r
1160 }\r
1161 pBuffer[idx] = *pDmaBuffer++;\r
1162 \r
1163 (*pRetLength)++;\r
1164 \r
1165 startAddr += 4; /* Increment by full-word */\r
1166 }\r
1167 }\r
1168 else\r
1169 #endif\r
1170 {\r
1171 /* Get the status of the ETB before we can start reading. */\r
1172 if(eETB_Success == ETB_status(pHandle, &status))\r
1173 {\r
1174 if(status.canRead == 0)\r
1175 {\r
1176 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Cannot_Read);\r
1177 }\r
1178 \r
1179 // Update the 3 symbols which are required for CCS ETB receiver\r
1180 etbLib_buffer_start_addr[pHandle->id] = (uint32_t)pBuffer; //CCS ETB receiver will always get a linearized buffer for the non-EDMA ETB drain case\r
1181 etbLib_buffer_size[pHandle->id] = status.availableWords * 4; //Number of bytes available \r
1182 etbLib_buffer_data_start[pHandle->id] = etbLib_buffer_start_addr[pHandle->id]; //circular buffer wrap point, if equal to the start address, no unwrapping of the buffer is required \r
1183 \r
1184 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
1185 {\r
1186 /* ETB depth */\r
1187 depth = *((volatile uint32_t*)ETB_RDP(pHandle->id));\r
1188 }\r
1189 else\r
1190 {\r
1191 /* ETB depth */\r
1192 value = (*((volatile uint32_t*)ETB_RDP(pHandle->id)));\r
1193 depth = (1 << (value-1)) << 10;\r
1194 }\r
1195 \r
1196 /* Check if the buffer is wrapped or not; set read pointers\r
1197 * accordingly.\r
1198 */\r
1199 if(status.isWrapped == 1)\r
1200 {\r
1201 startAddr =\r
1202 *((volatile uint32_t*)ETB_RWP(pHandle->id)) + startWord;\r
1203 }\r
1204 else\r
1205 {\r
1206 startAddr = 0x0 + startWord;\r
1207 }\r
1208 \r
1209 /* Adjust the read size for the available user buffer and requested\r
1210 * data.\r
1211 */\r
1212 if(bufferLength < status.availableWords)\r
1213 status.availableWords = bufferLength;\r
1214 \r
1215 if(readLength < status.availableWords)\r
1216 status.availableWords = readLength;\r
1217 \r
1218 /* Adjust to accomodate the start word. */\r
1219 if(startWord < status.availableWords)\r
1220 status.availableWords = status.availableWords - startWord;\r
1221 else\r
1222 status.availableWords =0;\r
1223 \r
1224 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
1225 {\r
1226 // Not valid to write the RRP if TIETB has not wrapped\r
1227 if(status.isWrapped == 1)\r
1228 {\r
1229 /* Initialize the ETB RAM read pointer register with startAddr*/\r
1230 *((volatile uint32_t*)ETB_RRP(pHandle->id)) = startAddr;\r
1231 \r
1232 /* Clear the overflow flag*/\r
1233 *((volatile uint32_t*)ETB_ICST(pHandle->id)) = TI_ETB_IRST_OVERFLOW;\r
1234 }\r
1235 }\r
1236 else\r
1237 {\r
1238 /* Initialize the ETB RAM read pointer register with startAddr*/\r
1239 *((volatile uint32_t*)ETB_RRP(pHandle->id)) = startAddr;\r
1240 }\r
1241 \r
1242 /* Now read trace data out of ETB */\r
1243 for (idx = 0; idx < status.availableWords; idx++)\r
1244 {\r
1245 /* Read the ETB RAM read data register to retrieve trace data.\r
1246 * This would cause the read pointer register value to\r
1247 * auto-increment.\r
1248 */\r
1249 pBuffer[idx] = *((volatile uint32_t*)ETB_RRD(pHandle->id));\r
1250 \r
1251 (*pRetLength)++;\r
1252 \r
1253 startAddr++;\r
1254 \r
1255 if(startAddr == depth)\r
1256 {\r
1257 /*Now wrap from begining */\r
1258 startAddr = 0x0;\r
1259 *((volatile uint32_t*)ETB_RRP(pHandle->id)) = startAddr;\r
1260 }\r
1261 }\r
1262 }\r
1263 }\r
1264 \r
1265 return eETB_Success;\r
1266 }\r
1267 \r
1268 \r
1269 /**\r
1270 * ETB_close- Close ETB programming module interface\r
1271 */\r
1272 eETB_Error ETB_close(ETBHandle* pHandle)\r
1273 {\r
1274 if(!pHandle || pHandle->ulContext != ETB_UNLOCK_VAL)\r
1275 {\r
1276 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1277 }\r
1278 \r
1279 #if !defined(C66AK2Hxx_CSSTM_ETB) && !defined(C66AK2Exx_CSSTM_ETB) && !defined(_OMAP54xx)\r
1280 \r
1281 /* Disable DTF, if available */\r
1282 if(Need_DTF(pHandle))\r
1283 {\r
1284 // Claim Tag Clear\r
1285 *(volatile uint32_t*)(TAGCLR(pHandle->id)) = 0x1;\r
1286 \r
1287 /* Disable ADTF */\r
1288 *(volatile uint32_t*)(DTF_CNTL(pHandle->id)) = *(volatile uint32_t*)(DTF_CNTL(pHandle->id)) & (~0x1);\r
1289 }\r
1290 \r
1291 #endif\r
1292 \r
1293 if(pHandle->ulContext == ETB_UNLOCK_VAL)\r
1294 {\r
1295 pHandle->ulContext = 0;\r
1296 }\r
1297 \r
1298 #ifdef __linux\r
1299 {\r
1300 int i;\r
1301 cTools_memUnMap(virtural_ETB_BaseAddress[pHandle->id], SIZEOF_ETB_SPACE);\r
1302 cTools_memUnMap(virtural_DTF_BaseAddress[pHandle->id], SIZEOF_DTF_SPACE);\r
1303 virtural_ETB_BaseAddress[pHandle->id] = 0;\r
1304 virtural_DTF_BaseAddress[pHandle->id] = 0;\r
1305 \r
1306 /* Only close the PSC if no other instances of ETBs are open */\r
1307 for (i = 0; i < NUM_ETB_INSTANCES; i++) {\r
1308 if (virtural_ETB_BaseAddress[pHandle->id] != 0) break;\r
1309 }\r
1310 if ( i == NUM_ETB_INSTANCES) \r
1311 { \r
1312 cTools_memUnMap(virtural_PSC_BaseAddress, SIZEOF_PSC_SPACE);\r
1313 virtural_PSC_BaseAddress = 0;\r
1314 }\r
1315 }\r
1316 #endif\r
1317 \r
1318 return eETB_Success;\r
1319 }\r
1320 \r
1321 /**\r
1322 * ETB_flush - Flush the ETB and ADTF in c6484 case\r
1323 */\r
1324 eETB_Error ETB_flush(ETBHandle* pHandle)\r
1325 {\r
1326 eETB_Error ret;\r
1327 \r
1328 if(!pHandle || pHandle->ulContext != ETB_UNLOCK_VAL)\r
1329 {\r
1330 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1331 }\r
1332 \r
1333 #ifdef DMA_SUPPORT\r
1334 // Stop the formatter + Flush to the ETB, if EDMA mode is enabled or its a STM-ETB\r
1335 if((pHandle->pDmaConfig != 0) || (pHandle->id == SYS_ETB_ID))\r
1336 {\r
1337 ret = flush(pHandle, eETB_STOP_FORMATTER);\r
1338 }\r
1339 else // Only Flush to the ETB, if EDMA mode is disabled\r
1340 #endif\r
1341 {\r
1342 ret = flush(pHandle, eETB_OPT_NONE);\r
1343 }\r
1344 \r
1345 return ret;\r
1346 }\r
1347 \r
1348 /**\r
1349 * flush - internal function used to flush the ETB from both the ETB_Disable API\r
1350 * and the ETB_flush API.\r
1351 */\r
1352 static eETB_Error flush(ETBHandle *pHandle, eETB_OPTIONS options)\r
1353 {\r
1354 eETB_Error ret = eETB_Success;\r
1355 uint32_t etbControl;\r
1356 uint32_t status;\r
1357 uint32_t retry;\r
1358 #if defined(C6670) || defined(C6678)\r
1359 \r
1360 #ifdef DMA_SUPPORT\r
1361 \r
1362 uint32_t rrp;\r
1363 uint32_t cntr = 0;\r
1364 \r
1365 if(pHandle->pDmaConfig != 0)\r
1366 {\r
1367 // Check for both Stop On Full mode is enabled and ETBLib buffer is wrapped\r
1368 if((etbLib_bufferWrapped[pHandle->id][0] == 1) && (pHandle->pDmaConfig->mode == eDMA_Stop_Buffer))\r
1369 {\r
1370 // Re-enable the ETB trace as the ETB trace was disabled by EDMA on buffer full\r
1371 /* Enable ETB data capture by writing ETB Control Register. */\r
1372 *((volatile uint32_t*)ETB_CTL(pHandle->id)) |= ETB_ENABLE; /* TraceCaptEn =1 */\r
1373 }\r
1374 }\r
1375 \r
1376 /* If using DMA to drain the ETB, disable the event coming from the ETB\r
1377 * interrupts in case the flush causes the ETB to cross the half-full or\r
1378 * full threshold. If this were to occur and start a DMA transaction the\r
1379 * data or PaRAM could get corrupted when the ETB_flush_dma function is\r
1380 * called. After the flush occurs the read from the Event Register will\r
1381 * identify if an interrupt occurred from the ETB.\r
1382 *\r
1383 * This code will only get executed on the 1st call, it is expected this\r
1384 * function is called directly before calling the DMA flush function.\r
1385 * Afterwards the ETB read pointer will not be on an even half or full\r
1386 * boundary and the while loop below would timeout. The configuration\r
1387 * function will need to get called before another capture can occur.\r
1388 */\r
1389 if((pHandle->pDmaConfig != 0) && (pHandle->dmaStatus.flushRequired))\r
1390 {\r
1391 uint32_t etbHalfSize;\r
1392 \r
1393 /* By this point the ETB read register should be stable and at 0 or half\r
1394 * the ETB size, if not, then wait for the previous DMA to complete.\r
1395 */\r
1396 rrp = *((volatile uint32_t*)ETB_RRP(pHandle->id));\r
1397 etbHalfSize = *((volatile uint32_t*)ETB_RDP(pHandle->id));\r
1398 etbHalfSize /= 2;\r
1399 while((rrp != 0) && (rrp != etbHalfSize))\r
1400 {\r
1401 rrp = *((volatile uint32_t*)ETB_RRP(pHandle->id));\r
1402 if(cntr++ > ETB_DMA_TIMEOUT)\r
1403 break;\r
1404 }\r
1405 \r
1406 /* Disable Event Register */\r
1407 if(pHandle->pDmaConfig->clrChannel > 31)\r
1408 {\r
1409 EDMA3_EECRH_REG(pHandle->pDmaConfig->cc) =\r
1410 (1 << (pHandle->pDmaConfig->clrChannel-32));\r
1411 }\r
1412 else\r
1413 {\r
1414 EDMA3_EECR_REG(pHandle->pDmaConfig->cc) =\r
1415 (1 << pHandle->pDmaConfig->clrChannel);\r
1416 }\r
1417 \r
1418 /* Clear Interrupt Pending register for ETB channel */\r
1419 if(pHandle->pDmaConfig->etbChannel > 31)\r
1420 {\r
1421 EDMA3_ICRH_REG(pHandle->pDmaConfig->cc) =\r
1422 (1 << (pHandle->pDmaConfig->etbChannel - 32));\r
1423 }\r
1424 else\r
1425 {\r
1426 EDMA3_ICR_REG(pHandle->pDmaConfig->cc) =\r
1427 (1 << pHandle->pDmaConfig->etbChannel);\r
1428 }\r
1429 }\r
1430 \r
1431 #endif\r
1432 \r
1433 #elif defined(C6657) || defined(C66AK2Hxx) || defined(C66AK2Exx)\r
1434 \r
1435 #ifdef DMA_SUPPORT\r
1436 \r
1437 uint32_t rrp;\r
1438 uint32_t cntr = 0;\r
1439 \r
1440 if(pHandle->pDmaConfig != 0)\r
1441 {\r
1442 // Check for both Stop On Full mode is enabled and ETBLib buffer is wrapped\r
1443 if((etbLib_bufferWrapped[pHandle->id][0] == 1) && (pHandle->pDmaConfig->mode == eDMA_Stop_Buffer))\r
1444 {\r
1445 // Re-enable the ETB trace as the ETB trace was disabled by EDMA on buffer full\r
1446 /* Enable ETB data capture by writing ETB Control Register. */\r
1447 *((volatile uint32_t*)ETB_CTL(pHandle->id)) |= ETB_ENABLE; /* TraceCaptEn =1 */\r
1448 }\r
1449 }\r
1450 \r
1451 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
1452 {\r
1453 \r
1454 /* If using DMA to drain the ETB, disable the event coming from the ETB\r
1455 * interrupts in case the flush causes the ETB to cross the half-full or\r
1456 * full threshold. If this were to occur and start a DMA transaction the\r
1457 * data or PaRAM could get corrupted when the ETB_flush_dma function is\r
1458 * called. After the flush occurs the read from the Event Register will\r
1459 * identify if an interrupt occurred from the ETB.\r
1460 *\r
1461 * This code will only get executed on the 1st call, it is expected this\r
1462 * function is called directly before calling the DMA flush function.\r
1463 * Afterwards the ETB read pointer will not be on an even half or full\r
1464 * boundary and the while loop below would timeout. The configuration\r
1465 * function will need to get called before another capture can occur.\r
1466 */\r
1467 if((pHandle->pDmaConfig != 0) && (pHandle->dmaStatus.flushRequired))\r
1468 {\r
1469 uint32_t etbHalfSize;\r
1470 \r
1471 /* By this point the ETB read register should be stable and at 0 or half\r
1472 * the ETB size, if not, then wait for the previous DMA to complete.\r
1473 */\r
1474 rrp = *((volatile uint32_t*)ETB_RRP(pHandle->id));\r
1475 etbHalfSize = *((volatile uint32_t*)ETB_RDP(pHandle->id));\r
1476 etbHalfSize /= 2;\r
1477 while((rrp != 0) && (rrp != etbHalfSize))\r
1478 {\r
1479 rrp = *((volatile uint32_t*)ETB_RRP(pHandle->id));\r
1480 if(cntr++ > ETB_DMA_TIMEOUT)\r
1481 break;\r
1482 }\r
1483 \r
1484 /* Disable etbhalf Event Register */\r
1485 if(pHandle->pDmaConfig->etbhalfChannel > 31)\r
1486 {\r
1487 EDMA3_EECRH_REG(pHandle->pDmaConfig->cc) =\r
1488 (1 << (pHandle->pDmaConfig->etbhalfChannel-32));\r
1489 }\r
1490 else\r
1491 {\r
1492 EDMA3_EECR_REG(pHandle->pDmaConfig->cc) =\r
1493 (1 << pHandle->pDmaConfig->etbhalfChannel);\r
1494 }\r
1495 \r
1496 /* Disable etbfull Event Register */\r
1497 if(pHandle->pDmaConfig->etbfullChannel > 31)\r
1498 {\r
1499 EDMA3_EECRH_REG(pHandle->pDmaConfig->cc) =\r
1500 (1 << (pHandle->pDmaConfig->etbfullChannel-32));\r
1501 }\r
1502 else\r
1503 {\r
1504 EDMA3_EECR_REG(pHandle->pDmaConfig->cc) =\r
1505 (1 << pHandle->pDmaConfig->etbfullChannel);\r
1506 }\r
1507 \r
1508 /* Clear Interrupt Pending register for ETB half channel */\r
1509 if(pHandle->pDmaConfig->etbhalfChannel > 31)\r
1510 {\r
1511 EDMA3_ICRH_REG(pHandle->pDmaConfig->cc) =\r
1512 (1 << (pHandle->pDmaConfig->etbhalfChannel - 32));\r
1513 }\r
1514 else\r
1515 {\r
1516 EDMA3_ICR_REG(pHandle->pDmaConfig->cc) =\r
1517 (1 << pHandle->pDmaConfig->etbhalfChannel);\r
1518 }\r
1519 }\r
1520 }\r
1521 \r
1522 #endif\r
1523 #endif\r
1524 \r
1525 #ifdef TCI6484\r
1526 /* In the TCI6484 case the DTF flush is not integrated so we must do a manual flush */\r
1527 if(Need_DTF(pHandle))\r
1528 {\r
1529 ret = DTF_flush(pHandle->id);\r
1530 if ( eETB_Success != ret )\r
1531 {\r
1532 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1533 }\r
1534 }\r
1535 #endif\r
1536 /* Flush ETB and DTF*/\r
1537 etbControl = *((volatile uint32_t*)ETB_FFCR(pHandle->id));\r
1538 \r
1539 if(options == eETB_STOP_FORMATTER)\r
1540 {\r
1541 etbControl |= (1 << 12); /* Stop Formatter bit */\r
1542 }\r
1543 *((volatile uint32_t*)ETB_FFCR(pHandle->id)) = etbControl;\r
1544 \r
1545 etbControl |= (1<<6); /* Manual flush */\r
1546 *((volatile uint32_t*)ETB_FFCR(pHandle->id)) = etbControl;\r
1547 \r
1548 // Wait for the flush to complete\r
1549 retry = 1000;\r
1550 do\r
1551 {\r
1552 status = *(volatile uint32_t*)ETB_FFSR(pHandle->id);\r
1553 retry--;\r
1554 } while( ( ( status & ETB_FLUSH_INPROGRESS ) != 0 ) && ( retry != 0 ) );\r
1555 \r
1556 #if defined(C6670) || defined(C6678)\r
1557 \r
1558 #ifdef DMA_SUPPORT\r
1559 \r
1560 /* If using the DMA to drain the ETB, will need to check if the flush caused\r
1561 * a threshold interrupt from the ETB.\r
1562 */\r
1563 if((pHandle->pDmaConfig != 0) && (pHandle->dmaStatus.flushRequired))\r
1564 {\r
1565 uint32_t regValue;\r
1566 \r
1567 /* Read the event register, check for an event, then start and wait for\r
1568 * the DMA to complete before continuing.\r
1569 */\r
1570 if(pHandle->pDmaConfig->clrChannel > 31)\r
1571 {\r
1572 regValue = EDMA3_ERH_REG(pHandle->pDmaConfig->cc) &\r
1573 (1 << (pHandle->pDmaConfig->clrChannel-32));\r
1574 EDMA3_EESRH_REG(pHandle->pDmaConfig->cc) =\r
1575 (1 << (pHandle->pDmaConfig->clrChannel-32));\r
1576 }\r
1577 else\r
1578 {\r
1579 regValue = EDMA3_ER_REG(pHandle->pDmaConfig->cc) &\r
1580 (1 << pHandle->pDmaConfig->clrChannel);\r
1581 EDMA3_EESR_REG(pHandle->pDmaConfig->cc) =\r
1582 (1 << pHandle->pDmaConfig->clrChannel);\r
1583 }\r
1584 \r
1585 if(regValue)\r
1586 {\r
1587 cntr = 0;\r
1588 if(pHandle->pDmaConfig->etbChannel > 31)\r
1589 {\r
1590 while((EDMA3_IPRH_REG(pHandle->pDmaConfig->cc) &\r
1591 (1 << (pHandle->pDmaConfig->etbChannel - 32))) == 0)\r
1592 {\r
1593 if(cntr++ > ETB_DMA_TIMEOUT)\r
1594 break;\r
1595 }\r
1596 EDMA3_ICRH_REG(pHandle->pDmaConfig->cc) =\r
1597 (1 << (pHandle->pDmaConfig->etbChannel - 32));\r
1598 }\r
1599 else\r
1600 {\r
1601 while((EDMA3_IPR_REG(pHandle->pDmaConfig->cc) &\r
1602 (1 << pHandle->pDmaConfig->etbChannel)) == 0)\r
1603 {\r
1604 if(cntr++ > ETB_DMA_TIMEOUT)\r
1605 break;\r
1606 }\r
1607 EDMA3_ICR_REG(pHandle->pDmaConfig->cc) =\r
1608 (1 << pHandle->pDmaConfig->etbChannel);\r
1609 }\r
1610 }\r
1611 \r
1612 /* Clear flag indicating not to excercise DMA code for any consecutive calls\r
1613 to this function.\r
1614 */\r
1615 pHandle->dmaStatus.flushRequired = 0;\r
1616 }\r
1617 \r
1618 #endif\r
1619 \r
1620 #elif defined(C6657) || defined(C66AK2Hxx) || defined(C66AK2Exx)\r
1621 \r
1622 #ifdef DMA_SUPPORT\r
1623 \r
1624 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
1625 {\r
1626 /* If using the DMA to drain the ETB, will need to check if the flush caused\r
1627 * a threshold interrupt from the ETB.\r
1628 */\r
1629 if((pHandle->pDmaConfig != 0) && (pHandle->dmaStatus.flushRequired))\r
1630 {\r
1631 uint32_t regValue1, regValue2;\r
1632 \r
1633 /* Read the event register, check for a etbhalf or etbfull event, then start and wait for\r
1634 * the DMA to complete before continuing.\r
1635 */\r
1636 if(pHandle->pDmaConfig->etbhalfChannel > 31)\r
1637 {\r
1638 regValue1 = EDMA3_ERH_REG(pHandle->pDmaConfig->cc) &\r
1639 (1 << (pHandle->pDmaConfig->etbhalfChannel-32));\r
1640 EDMA3_EESRH_REG(pHandle->pDmaConfig->cc) =\r
1641 (1 << (pHandle->pDmaConfig->etbhalfChannel-32));\r
1642 }\r
1643 else\r
1644 {\r
1645 regValue1 = EDMA3_ER_REG(pHandle->pDmaConfig->cc) &\r
1646 (1 << pHandle->pDmaConfig->etbhalfChannel);\r
1647 EDMA3_EESR_REG(pHandle->pDmaConfig->cc) =\r
1648 (1 << pHandle->pDmaConfig->etbhalfChannel);\r
1649 }\r
1650 \r
1651 if(pHandle->pDmaConfig->etbfullChannel > 31)\r
1652 {\r
1653 regValue2 = EDMA3_ERH_REG(pHandle->pDmaConfig->cc) &\r
1654 (1 << (pHandle->pDmaConfig->etbfullChannel-32));\r
1655 EDMA3_EESRH_REG(pHandle->pDmaConfig->cc) =\r
1656 (1 << (pHandle->pDmaConfig->etbfullChannel-32));\r
1657 }\r
1658 else\r
1659 {\r
1660 regValue2 = EDMA3_ER_REG(pHandle->pDmaConfig->cc) &\r
1661 (1 << pHandle->pDmaConfig->etbfullChannel);\r
1662 EDMA3_EESR_REG(pHandle->pDmaConfig->cc) =\r
1663 (1 << pHandle->pDmaConfig->etbfullChannel);\r
1664 }\r
1665 \r
1666 if((regValue1 != 0) || (regValue2 != 0))\r
1667 {\r
1668 cntr = 0;\r
1669 if(pHandle->pDmaConfig->etbhalfChannel > 31)\r
1670 {\r
1671 while((EDMA3_IPRH_REG(pHandle->pDmaConfig->cc) &\r
1672 (1 << (pHandle->pDmaConfig->etbhalfChannel - 32))) == 0)\r
1673 {\r
1674 if(cntr++ > ETB_DMA_TIMEOUT)\r
1675 break;\r
1676 }\r
1677 EDMA3_ICRH_REG(pHandle->pDmaConfig->cc) =\r
1678 (1 << (pHandle->pDmaConfig->etbhalfChannel - 32));\r
1679 }\r
1680 else\r
1681 {\r
1682 while((EDMA3_IPR_REG(pHandle->pDmaConfig->cc) &\r
1683 (1 << pHandle->pDmaConfig->etbhalfChannel)) == 0)\r
1684 {\r
1685 if(cntr++ > ETB_DMA_TIMEOUT)\r
1686 break;\r
1687 }\r
1688 EDMA3_ICR_REG(pHandle->pDmaConfig->cc) =\r
1689 (1 << pHandle->pDmaConfig->etbhalfChannel);\r
1690 }\r
1691 }\r
1692 \r
1693 /* Clear flag indicating not to excercise DMA code for any consecutive calls\r
1694 to this function.\r
1695 */\r
1696 pHandle->dmaStatus.flushRequired = 0;\r
1697 }\r
1698 \r
1699 *((volatile uint32_t*)ETB_FFCR(pHandle->id)) = 0;\r
1700 }\r
1701 \r
1702 #endif\r
1703 #endif\r
1704 \r
1705 if ( retry == 0 )\r
1706 {\r
1707 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1708 }\r
1709 \r
1710 return ret;\r
1711 }\r
1712 \r
1713 #ifdef DMA_SUPPORT\r
1714 /******************************************************************************/\r
1715 /*! \copydoc ETB_config_dma\r
1716 */\r
1717 eETB_Error ETB_config_dma(ETBHandle* pHandle, const DMAConfig *pConfig)\r
1718 {\r
1719 #if defined(C6670) || defined(C6678)\r
1720 \r
1721 uint32_t paramBase;\r
1722 uint16_t paramIdx;\r
1723 uint32_t etbSize;\r
1724 uint32_t etbHalfSize;\r
1725 uint32_t clr1param;\r
1726 uint32_t clr2param;\r
1727 uint32_t etb1param;\r
1728 uint32_t etb2param;\r
1729 uint32_t etb3param;\r
1730 struct edma3_param param;\r
1731 /* Fixed location to store DMA configuration parameters */\r
1732 static DMAConfig dmaConfig[NUM_ETB_INSTANCES];\r
1733 \r
1734 // For C6678, Index = 0 (CIC2), Index = 1 (CIC3)\r
1735 // For C6670, Index = 0 (CIC1), Index = 1 (CIC2)\r
1736 uint8_t cic_index = 0;\r
1737 \r
1738 if(!pHandle || (pHandle->ulContext != ETB_UNLOCK_VAL) || !pConfig)\r
1739 {\r
1740 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1741 }\r
1742 \r
1743 if ((TI_ETB_TI_MODE & *((volatile uint32_t*)ETB_TI_CTL(pHandle->id))) != TI_ETB_TI_MODE )\r
1744 {\r
1745 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1746 }\r
1747 \r
1748 #if defined(C6670)\r
1749 if(!(pConfig->cic == eCIC_1 || pConfig->cic == eCIC_2))\r
1750 {\r
1751 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1752 }\r
1753 \r
1754 #elif defined(C6678)\r
1755 if(!(pConfig->cic == eCIC_2 || pConfig->cic == eCIC_3))\r
1756 {\r
1757 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1758 }\r
1759 \r
1760 #endif\r
1761 \r
1762 /* Validate the Channel Controller value and set the Parameter RAM base\r
1763 * address value\r
1764 */\r
1765 switch(pConfig->cc)\r
1766 {\r
1767 case 0:\r
1768 paramBase = EDMA_TPCC_PARAM_BASE_ADDR(0);\r
1769 break;\r
1770 case 1:\r
1771 paramBase = EDMA_TPCC_PARAM_BASE_ADDR(1);\r
1772 break;\r
1773 case 2:\r
1774 paramBase = EDMA_TPCC_PARAM_BASE_ADDR(2);\r
1775 break;\r
1776 default:\r
1777 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1778 }\r
1779 \r
1780 /* Calculate the address values for the specific PaRAM's. The PaRAM numbers\r
1781 * for the DMA channels provided are determined by reading the DMA to\r
1782 * PaRAM mapping registers.\r
1783 */\r
1784 paramIdx = (EDMA3_DCHMAP_REG(pConfig->cc,pConfig->clrChannel) >> 5);\r
1785 clr1param = paramBase + (0x20 * paramIdx);\r
1786 clr2param = paramBase + (0x20 * pConfig->linkparam[0]);\r
1787 paramIdx = (EDMA3_DCHMAP_REG(pConfig->cc,pConfig->etbChannel) >> 5);\r
1788 etb1param = paramBase + (0x20 * paramIdx);\r
1789 etb2param = paramBase + (0x20 * pConfig->linkparam[1]);\r
1790 etb3param = paramBase + (0x20 * pConfig->linkparam[2]);\r
1791 \r
1792 etbLib_bufferWrapped[pHandle->id][0] = 0;\r
1793 etbLib_bufferWrapped[pHandle->id][1] = 1;\r
1794 \r
1795 /* Store configuration information */\r
1796 dmaConfig[Handle_index(pHandle->id)].cc = pConfig->cc;\r
1797 dmaConfig[Handle_index(pHandle->id)].clrChannel = pConfig->clrChannel;\r
1798 dmaConfig[Handle_index(pHandle->id)].etbChannel = pConfig->etbChannel;\r
1799 dmaConfig[Handle_index(pHandle->id)].linkparam[0] = pConfig->linkparam[0];\r
1800 dmaConfig[Handle_index(pHandle->id)].linkparam[1] = pConfig->linkparam[1];\r
1801 dmaConfig[Handle_index(pHandle->id)].linkparam[2] = pConfig->linkparam[2];\r
1802 dmaConfig[Handle_index(pHandle->id)].dbufAddress = pConfig->dbufAddress;\r
1803 dmaConfig[Handle_index(pHandle->id)].dbufWords = pConfig->dbufWords;\r
1804 dmaConfig[Handle_index(pHandle->id)].mode = pConfig->mode;\r
1805 dmaConfig[Handle_index(pHandle->id)].cic = pConfig->cic;\r
1806 pHandle->pDmaConfig = &dmaConfig[Handle_index(pHandle->id)];\r
1807 \r
1808 /* Get the size of the ETB for this instance to determine the count values\r
1809 * required for the EDMA parameter ram (PaRAM) configuration. The size if\r
1810 * provided in words, convert to bytes for calculations. The count values\r
1811 * for the EDMA are in bytes.\r
1812 */\r
1813 etbSize = *((volatile uint32_t*)ETB_RDP(pHandle->id));\r
1814 etbSize *= 4;\r
1815 etbHalfSize = etbSize / 2;\r
1816 \r
1817 #if defined(C6670)\r
1818 \r
1819 cic_index = pHandle->pDmaConfig->cic - 1;\r
1820 \r
1821 #elif defined(C6678)\r
1822 \r
1823 cic_index = pHandle->pDmaConfig->cic - 2;\r
1824 \r
1825 #endif\r
1826 \r
1827 /* The following 2 PaRAM's are used to clear the INTC1 event register. When\r
1828 * the bit for the specific event in the register is set, no other incoming\r
1829 * events will get forwarded to its corresponding output until the event\r
1830 * has been cleared.\r
1831 * The early completion is used to chain to the start of the ETB transfer\r
1832 * PaRAM.\r
1833 */\r
1834 param.options = (PARAM_OPT_TCCHEN |\r
1835 PARAM_OPT_TCC(pConfig->etbChannel) |\r
1836 PARAM_OPT_TCC_EARLY|\r
1837 PARAM_OPT_AB_SYNC);\r
1838 param.src_addr = GET_GLOBAL_ADDR(&etbLib_cpCicEventClearValue[cic_index][pHandle->id][0]);\r
1839 param.ab_cnt = (PARAM_BCNT(2) | PARAM_ACNT(4));\r
1840 param.dst_addr = etbLib_cpCicEventClearIndexReg[cic_index];\r
1841 param.srcdst_bidx = 4;\r
1842 param.link_bcnt = PARAM_LINK(clr2param);\r
1843 param.srcdst_cidx = 0;\r
1844 param.ccnt = 1;\r
1845 \r
1846 /* Copy local structure to actual PaRAM memory locations */\r
1847 *(struct edma3_param *)clr1param = param;\r
1848 *(struct edma3_param *)clr2param = param;\r
1849 \r
1850 /* Create the PaRAM entries that will be used to transfer data from ETB RAM\r
1851 * Burst Data Read Register locations to a drain buffer in memory. The\r
1852 * second PaRAM is used once to transfer a buffer wrapped flag that is used\r
1853 * to indicate the drain buffer has wrapped. It is linked to the 3rd PaRAM\r
1854 * that is used to reload with initial values to tranfer data from ETB.\r
1855 */\r
1856 param.options = (PARAM_OPT_ITCINTEN | PARAM_OPT_TCINTEN |\r
1857 PARAM_OPT_TCCHEN |\r
1858 PARAM_OPT_TCC(pConfig->etbChannel) |\r
1859 PARAM_OPT_AB_SYNC);\r
1860 param.src_addr = ETB_RBD(pHandle->id);\r
1861 param.ab_cnt = PARAM_BCNT(etbHalfSize / ETB_BURST_SIZE) | PARAM_ACNT(ETB_BURST_SIZE);\r
1862 param.dst_addr = pConfig->dbufAddress;\r
1863 param.srcdst_bidx = PARAM_DST_BIDX(ETB_BURST_SIZE);\r
1864 param.link_bcnt = PARAM_LINK(etb2param);\r
1865 param.srcdst_cidx = PARAM_DST_CIDX(etbHalfSize);\r
1866 param.ccnt = (pConfig->dbufWords*4) / etbHalfSize;\r
1867 \r
1868 /* Set the DMA status to the actual number of words used in the provided\r
1869 * buffer, also reset any previous status settings.\r
1870 */\r
1871 pHandle->dmaStatus.startAddr = 0;\r
1872 pHandle->dmaStatus.availableWords = 0;\r
1873 pHandle->dmaStatus.isWrapped = 0;\r
1874 pHandle->dmaStatus.dbufAddress = 0;\r
1875 pHandle->dmaStatus.flushRequired = 1;\r
1876 pHandle->dmaStatus.dbufWords = (param.ccnt * etbHalfSize) / 4;\r
1877 \r
1878 /* Copy local structure to actual PaRAM memory locations */\r
1879 *(struct edma3_param *)etb1param = param;\r
1880 \r
1881 if(pConfig->mode != eDMA_Stop_Buffer)\r
1882 {\r
1883 \r
1884 /* Change the 3rd PaRAM to not link to 2nd for wrap processing, just\r
1885 * link to self for reloading purposes, Transfer chaining completion is\r
1886 * also not needed except for the 1st occurance.\r
1887 */\r
1888 param.options = PARAM_OPT_ITCINTEN | PARAM_OPT_TCINTEN | PARAM_OPT_AB_SYNC;\r
1889 param.link_bcnt = PARAM_LINK(etb3param);\r
1890 }\r
1891 else\r
1892 {\r
1893 /* If the DMA mode has been configured as non-circular, configure etbparam3 to disable ETB trace\r
1894 * set the link value to a NULL after disabling ETB trace.\r
1895 */\r
1896 \r
1897 param.options = PARAM_OPT_TCC_EARLY;\r
1898 param.src_addr = GET_GLOBAL_ADDR(&etb_disable);\r
1899 param.ab_cnt = (PARAM_BCNT(1) | PARAM_ACNT(4));\r
1900 param.dst_addr = ETB_CTL(pHandle->id);\r
1901 param.srcdst_bidx = 0;\r
1902 param.link_bcnt = PARAM_LINK(0xffff);\r
1903 param.srcdst_cidx = 0;\r
1904 param.ccnt = 1;\r
1905 }\r
1906 \r
1907 *(struct edma3_param *)etb3param = param;\r
1908 \r
1909 if(pConfig->mode != eDMA_Stop_Buffer)\r
1910 { \r
1911 /* 2nd PaRAM configuration, no transfer chaining completion, but an early\r
1912 * link completion.\r
1913 */\r
1914 param.options = PARAM_OPT_TCC_EARLY;\r
1915 }\r
1916 else\r
1917 {\r
1918 /* For Stop on full buffer mode, link to etb3param which disables ETB trace capture */\r
1919 param.options = (PARAM_OPT_TCC_EARLY | PARAM_OPT_ITCINTEN | PARAM_OPT_TCINTEN |\r
1920 PARAM_OPT_TCCHEN |\r
1921 PARAM_OPT_TCC(pConfig->etbChannel));\r
1922 } \r
1923 \r
1924 param.src_addr = GET_GLOBAL_ADDR(&etbLib_bufferWrapped[pHandle->id][1]);\r
1925 param.ab_cnt = PARAM_BCNT(1) | PARAM_ACNT(4);\r
1926 param.dst_addr = GET_GLOBAL_ADDR(&etbLib_bufferWrapped[pHandle->id][0]);\r
1927 param.srcdst_bidx = 0;\r
1928 param.link_bcnt = PARAM_LINK(etb3param);\r
1929 param.srcdst_cidx = 0;\r
1930 param.ccnt = 1;\r
1931 \r
1932 /* Copy local structure to actual PaRAM memory locations */\r
1933 *(struct edma3_param *)etb2param = param;\r
1934 \r
1935 /* Enable event for specific channel that is used to clear the INTCx\r
1936 * interrupt status. This is the EDMA event that is used to start the DMA\r
1937 * transactions.\r
1938 */\r
1939 if(pConfig->clrChannel > 31)\r
1940 {\r
1941 EDMA3_EESRH_REG(pConfig->cc) = (1 << (pConfig->clrChannel-32));\r
1942 }\r
1943 else\r
1944 {\r
1945 EDMA3_EESR_REG(pConfig->cc) = (1 << pConfig->clrChannel);\r
1946 }\r
1947 \r
1948 #elif defined(C6657) || defined(C66AK2Hxx) || defined(C66AK2Exx)\r
1949 \r
1950 uint32_t paramBase;\r
1951 uint32_t etbSize;\r
1952 uint32_t etbHalfSize;\r
1953 uint32_t etb1param;\r
1954 uint32_t etb2param;\r
1955 uint32_t etb3param;\r
1956 struct edma3_param param;\r
1957 \r
1958 /* Fixed location to store DMA configuration parameters */\r
1959 static DMAConfigInt dmaConfig[NUM_ETB_INSTANCES];\r
1960 \r
1961 if(!pHandle || (pHandle->ulContext != ETB_UNLOCK_VAL) || !pConfig)\r
1962 {\r
1963 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1964 }\r
1965 \r
1966 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
1967 {\r
1968 if ((TI_ETB_TI_MODE & *((volatile uint32_t*)ETB_TI_CTL(pHandle->id))) != TI_ETB_TI_MODE )\r
1969 {\r
1970 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
1971 }\r
1972 }\r
1973 \r
1974 /* Store configuration information */\r
1975 \r
1976 #if defined(C6657)\r
1977 \r
1978 dmaConfig[Handle_index(pHandle->id)].cc = 2; //The ETB half-full and full events are directly connected to EDMA CC in C6657\r
1979 if(pHandle->id == SYS_ETB_ID)\r
1980 {\r
1981 dmaConfig[Handle_index(pHandle->id)].etbhalfChannel = EDMACC_TETBHFULLINT; //ETB half-full event\r
1982 dmaConfig[Handle_index(pHandle->id)].etbfullChannel = EDMACC_TETBFULLINT; //ETB full event\r
1983 }\r
1984 else\r
1985 {\r
1986 dmaConfig[Handle_index(pHandle->id)].etbhalfChannel = EDMACC_TETBHFULLINT0 + pHandle->id; //ETB half-full event\r
1987 dmaConfig[Handle_index(pHandle->id)].etbfullChannel = EDMACC_TETBFULLINT0 + pHandle->id; //ETB full event\r
1988 }\r
1989 \r
1990 #endif\r
1991 \r
1992 #if defined(C66AK2Hxx)\r
1993 \r
1994 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
1995 {\r
1996 if(pHandle->id < 4)\r
1997 {\r
1998 dmaConfig[Handle_index(pHandle->id)].cc = 3; //The core 0-3 ETB half-full and full events are directly connected to EDMA CC # 3 in 6AK2Hxx\r
1999 }\r
2000 else\r
2001 {\r
2002 dmaConfig[Handle_index(pHandle->id)].cc = 2; //The core 4-7 ETB half-full and full events are directly connected to EDMA CC # 2 in 6AK2Hxx\r
2003 }\r
2004 \r
2005 if(pHandle->id < 4)\r
2006 {\r
2007 dmaConfig[Handle_index(pHandle->id)].etbhalfChannel = EDMACC3_TETBHFULLINT0 + (pHandle->id * 2); //ETB half-full event\r
2008 dmaConfig[Handle_index(pHandle->id)].etbfullChannel = EDMACC3_TETBFULLINT0 + (pHandle->id * 2); //ETB full event\r
2009 }\r
2010 else\r
2011 {\r
2012 dmaConfig[Handle_index(pHandle->id)].etbhalfChannel = EDMACC2_TETBHFULLINT4 + ((pHandle->id-4) * 2); //ETB half-full event\r
2013 dmaConfig[Handle_index(pHandle->id)].etbfullChannel = EDMACC2_TETBFULLINT4 + ((pHandle->id-4) * 2); //ETB full event\r
2014 }\r
2015 }\r
2016 else\r
2017 {\r
2018 //Setup SYS ETB or CSSTM ETB for DMA drain mode\r
2019 //TBR system bridge operation\r
2020 \r
2021 // Setup TBR in system bridge (DMA) mode\r
2022 *((volatile uint32_t*)ETB_CTL(pHandle->id)) |= TBR_BRIDGE_MODE;\r
2023 \r
2024 dmaConfig[Handle_index(pHandle->id)].cc = 4; //The DebugSS TBR and Tetris TBR DMA events are directly connected to EDMA CC # 3 in 6AK2Hxx\r
2025 \r
2026 #if defined(C66AK2Hxx_CSSTM_ETB)\r
2027 \r
2028 dmaConfig[Handle_index(pHandle->id)].etbhalfChannel = EDMACC4_TETRISTBR_DMAINT; //TBR DMA event\r
2029 \r
2030 #else\r
2031 \r
2032 dmaConfig[Handle_index(pHandle->id)].etbhalfChannel = EDMACC4_DBGTBR_DMAINT; //TBR DMA event\r
2033 \r
2034 #endif\r
2035 //Setup DMA trigger thresholds\r
2036 *((volatile uint32_t*)TBR_OUTLVL(pHandle->id)) = ((TBR_NUMBLOCK << 8) | TBR_BLOCKSZ);\r
2037 \r
2038 //Enable DMA trigger\r
2039 *((volatile uint32_t*)TBR_IRQENABLE_SET(pHandle->id)) = TBR_IRST_DAV;\r
2040 \r
2041 }\r
2042 \r
2043 #endif\r
2044 \r
2045 dmaConfig[Handle_index(pHandle->id)].linkparam[0] = pConfig->linkparam[0];\r
2046 dmaConfig[Handle_index(pHandle->id)].linkparam[1] = pConfig->linkparam[1];\r
2047 dmaConfig[Handle_index(pHandle->id)].linkparam[2] = pConfig->linkparam[2];\r
2048 dmaConfig[Handle_index(pHandle->id)].dbufAddress = pConfig->dbufAddress;\r
2049 dmaConfig[Handle_index(pHandle->id)].dbufWords = pConfig->dbufWords;\r
2050 dmaConfig[Handle_index(pHandle->id)].mode = pConfig->mode;\r
2051 pHandle->pDmaConfig = &dmaConfig[Handle_index(pHandle->id)];\r
2052 \r
2053 /* Validate the Channel Controller value and set the Parameter RAM base\r
2054 * address value\r
2055 */\r
2056 switch(pHandle->pDmaConfig->cc)\r
2057 {\r
2058 case 0:\r
2059 paramBase = EDMA_TPCC_PARAM_BASE_ADDR(0);\r
2060 break;\r
2061 case 1:\r
2062 paramBase = EDMA_TPCC_PARAM_BASE_ADDR(1);\r
2063 break;\r
2064 case 2:\r
2065 paramBase = EDMA_TPCC_PARAM_BASE_ADDR(2);\r
2066 break;\r
2067 case 3:\r
2068 paramBase = EDMA_TPCC_PARAM_BASE_ADDR(3);\r
2069 break;\r
2070 case 4:\r
2071 paramBase = EDMA_TPCC_PARAM_BASE_ADDR(4);\r
2072 break;\r
2073 default:\r
2074 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2075 }\r
2076 \r
2077 // Mapping linkparam[0] to the ETB half channel\r
2078 EDMA3_DCHMAP_REG(pHandle->pDmaConfig->cc,pHandle->pDmaConfig->etbhalfChannel) = (pHandle->pDmaConfig->linkparam[0] << 5);\r
2079 \r
2080 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
2081 {\r
2082 // Mapping ETB full channel is only required for TI-ETB\r
2083 // Mapping linkparam[0] to the ETB full channel\r
2084 EDMA3_DCHMAP_REG(pHandle->pDmaConfig->cc,pHandle->pDmaConfig->etbfullChannel) = (pHandle->pDmaConfig->linkparam[0] << 5);\r
2085 }\r
2086 \r
2087 /* Calculate the param address for etb1param, etb2param and etb3param\r
2088 */\r
2089 \r
2090 etb1param = paramBase + (0x20 * pConfig->linkparam[0]);\r
2091 etb2param = paramBase + (0x20 * pConfig->linkparam[1]);\r
2092 etb3param = paramBase + (0x20 * pConfig->linkparam[2]);\r
2093 \r
2094 etbLib_bufferWrapped[pHandle->id][0] = 0;\r
2095 etbLib_bufferWrapped[pHandle->id][1] = 1;\r
2096 \r
2097 /* Create the PaRAM entries that will be used to transfer data from ETB RAM\r
2098 * Burst Data Read Register locations to a drain buffer in memory. The\r
2099 * second PaRAM is used once to transfer a buffer wrapped flag that is used\r
2100 * to indicate the drain buffer has wrapped. It is linked to the 3rd PaRAM\r
2101 * that is used to reload with initial values to transfer data from ETB.\r
2102 */\r
2103 param.options = (PARAM_OPT_ITCINTEN | PARAM_OPT_TCINTEN |\r
2104 PARAM_OPT_TCCHEN |\r
2105 PARAM_OPT_TCC(pHandle->pDmaConfig->etbhalfChannel) |\r
2106 PARAM_OPT_AB_SYNC);\r
2107 \r
2108 /* Get the size of the ETB for this instance to determine the count values\r
2109 * required for the EDMA parameter ram (PaRAM) configuration. The size if\r
2110 * provided in words, convert to bytes for calculations. The count values\r
2111 * for the EDMA are in bytes.\r
2112 */\r
2113 \r
2114 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
2115 {\r
2116 // get ETB buffer size\r
2117 etbSize = *((volatile uint32_t*)ETB_RDP(pHandle->id));\r
2118 \r
2119 // get starting address of the ETB buffer\r
2120 param.src_addr = ETB_RBD(pHandle->id);\r
2121 }\r
2122 else\r
2123 {\r
2124 // get TBR buffer size\r
2125 etbSize = (*((volatile uint32_t*)ETB_RDP(pHandle->id)));\r
2126 etbSize = (1 << (etbSize-1)) << 10;\r
2127 \r
2128 // get starting address of the TBR buffer\r
2129 param.src_addr = TBR_RBD;\r
2130 }\r
2131 \r
2132 etbSize *= 4;\r
2133 etbHalfSize = etbSize / 2;\r
2134 \r
2135 param.ab_cnt = PARAM_BCNT(etbHalfSize / ETB_BURST_SIZE) | PARAM_ACNT(ETB_BURST_SIZE);\r
2136 param.dst_addr = pConfig->dbufAddress;\r
2137 param.srcdst_bidx = PARAM_DST_BIDX(ETB_BURST_SIZE);\r
2138 param.link_bcnt = PARAM_LINK(etb2param);\r
2139 param.srcdst_cidx = PARAM_DST_CIDX(etbHalfSize);\r
2140 param.ccnt = (pConfig->dbufWords*4) / etbHalfSize;\r
2141 \r
2142 /* Set the DMA status to the actual number of words used in the provided\r
2143 * buffer, also reset any previous status settings.\r
2144 */\r
2145 pHandle->dmaStatus.startAddr = 0;\r
2146 pHandle->dmaStatus.availableWords = 0;\r
2147 pHandle->dmaStatus.isWrapped = 0;\r
2148 pHandle->dmaStatus.dbufAddress = 0;\r
2149 pHandle->dmaStatus.flushRequired = 1;\r
2150 pHandle->dmaStatus.dbufWords = (param.ccnt * etbHalfSize) / 4;\r
2151 \r
2152 /* Copy local structure to actual PaRAM memory locations */\r
2153 *(struct edma3_param *)etb1param = param;\r
2154 \r
2155 if(pConfig->mode != eDMA_Stop_Buffer)\r
2156 {\r
2157 \r
2158 /* Change the 3rd PaRAM to not link to 2nd for wrap processing, just\r
2159 * link to self for reloading purposes, Transfer chaining completion is\r
2160 * also not needed except for the 1st occurance.\r
2161 */\r
2162 param.options = PARAM_OPT_ITCINTEN | PARAM_OPT_TCINTEN | PARAM_OPT_AB_SYNC;\r
2163 param.link_bcnt = PARAM_LINK(etb3param);\r
2164 }\r
2165 else\r
2166 {\r
2167 /* If the DMA mode has been configured as non-circular, configure etbparam3 to disable ETB trace\r
2168 * set the link value to a NULL after disabling ETB trace.\r
2169 */\r
2170 \r
2171 param.options = PARAM_OPT_TCC_EARLY;\r
2172 param.src_addr = GET_GLOBAL_ADDR(&etb_disable);\r
2173 param.ab_cnt = (PARAM_BCNT(1) | PARAM_ACNT(4));\r
2174 param.dst_addr = ETB_CTL(pHandle->id);\r
2175 param.srcdst_bidx = 0;\r
2176 param.link_bcnt = PARAM_LINK(0xffff);\r
2177 param.srcdst_cidx = 0;\r
2178 param.ccnt = 1;\r
2179 }\r
2180 \r
2181 *(struct edma3_param *)etb3param = param;\r
2182 \r
2183 if(pConfig->mode != eDMA_Stop_Buffer)\r
2184 { \r
2185 /* 2nd PaRAM configuration, no transfer chaining completion, but an early\r
2186 * link completion.\r
2187 */\r
2188 param.options = PARAM_OPT_TCC_EARLY;\r
2189 }\r
2190 else\r
2191 {\r
2192 /* For Stop on full buffer mode, link to etb3param which disables ETB trace capture */\r
2193 param.options = (PARAM_OPT_TCC_EARLY | PARAM_OPT_ITCINTEN | PARAM_OPT_TCINTEN |\r
2194 PARAM_OPT_TCCHEN |\r
2195 PARAM_OPT_TCC(pHandle->pDmaConfig->etbhalfChannel));\r
2196 } \r
2197 \r
2198 param.src_addr = GET_GLOBAL_ADDR(&etbLib_bufferWrapped[pHandle->id][1]);\r
2199 param.ab_cnt = PARAM_BCNT(1) | PARAM_ACNT(4);\r
2200 param.dst_addr = GET_GLOBAL_ADDR(&etbLib_bufferWrapped[pHandle->id][0]);\r
2201 param.srcdst_bidx = 0;\r
2202 param.link_bcnt = PARAM_LINK(etb3param);\r
2203 param.srcdst_cidx = 0;\r
2204 param.ccnt = 1;\r
2205 \r
2206 /* Copy local structure to actual PaRAM memory locations */\r
2207 *(struct edma3_param *)etb2param = param;\r
2208 \r
2209 /* Enable event for etb half and etb full channel that. This is the EDMA event that is used to start the DMA\r
2210 * transactions.\r
2211 */\r
2212 if(pHandle->pDmaConfig->etbhalfChannel > 31)\r
2213 {\r
2214 EDMA3_EESRH_REG(pHandle->pDmaConfig->cc) = (1 << (pHandle->pDmaConfig->etbhalfChannel-32));\r
2215 }\r
2216 else\r
2217 {\r
2218 EDMA3_EESR_REG(pHandle->pDmaConfig->cc) = (1 << pHandle->pDmaConfig->etbhalfChannel);\r
2219 }\r
2220 \r
2221 if(pHandle->pDmaConfig->etbfullChannel > 31)\r
2222 {\r
2223 EDMA3_EESRH_REG(pHandle->pDmaConfig->cc) = (1 << (pHandle->pDmaConfig->etbfullChannel-32));\r
2224 }\r
2225 else\r
2226 {\r
2227 EDMA3_EESR_REG(pHandle->pDmaConfig->cc) = (1 << pHandle->pDmaConfig->etbfullChannel);\r
2228 }\r
2229 \r
2230 #endif\r
2231 \r
2232 return eETB_Success;\r
2233 }\r
2234 \r
2235 /******************************************************************************/\r
2236 /*! \copydoc ETB_flush_dma\r
2237 */\r
2238 eETB_Error ETB_flush_dma(ETBHandle* pHandle, DMAStatus *pStatus)\r
2239 {\r
2240 #if defined(C6670) || defined(C6678)\r
2241 \r
2242 int32_t remWords;\r
2243 uint32_t rwp;\r
2244 uint32_t rrp;\r
2245 uint16_t paramIdx;\r
2246 uint32_t paramAddress;\r
2247 volatile uint32_t cntr = 0;\r
2248 \r
2249 // For C6678, Index = 0 (CIC2), Index = 1 (CIC3)\r
2250 // For C6670, Index = 0 (CIC1), Index = 1 (CIC2)\r
2251 uint8_t cic_index = 0;\r
2252 \r
2253 if(!pHandle || !pStatus)\r
2254 {\r
2255 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2256 }\r
2257 if(!pHandle->pDmaConfig)\r
2258 {\r
2259 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2260 }\r
2261 \r
2262 #if defined(C6670)\r
2263 if(!(pHandle->pDmaConfig->cic == eCIC_1 || pHandle->pDmaConfig->cic == eCIC_2))\r
2264 {\r
2265 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2266 }\r
2267 \r
2268 #elif defined(C6678)\r
2269 if(!(pHandle->pDmaConfig->cic == eCIC_2 || pHandle->pDmaConfig->cic == eCIC_3))\r
2270 {\r
2271 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2272 }\r
2273 \r
2274 #endif\r
2275 \r
2276 #if defined(C6670)\r
2277 \r
2278 cic_index = pHandle->pDmaConfig->cic - 1;\r
2279 \r
2280 #elif defined(C6678)\r
2281 \r
2282 cic_index = pHandle->pDmaConfig->cic - 2;\r
2283 \r
2284 #endif\r
2285 \r
2286 rwp = *((volatile uint32_t*)ETB_RWP(pHandle->id));\r
2287 rrp = *((volatile uint32_t*)ETB_RRP(pHandle->id));\r
2288 \r
2289 remWords = rwp - rrp;\r
2290 // printf(" rwp: %x, rrp: %x, diff: %d\n", rwp, rrp, remWords);\r
2291 \r
2292 if(remWords > 0)\r
2293 {\r
2294 int32_t remBytes;\r
2295 uint16_t clrParamIdx;\r
2296 \r
2297 remBytes = (remWords * 4);\r
2298 /* Change the PaRAM set value for the DMA channel that handles the ETB\r
2299 * event to the drain PaRAM. This method is more efficient than copying\r
2300 * the PaRAM contents.\r
2301 */\r
2302 paramIdx = (EDMA3_DCHMAP_REG(pHandle->pDmaConfig->cc,\r
2303 pHandle->pDmaConfig->etbChannel) >> 5);\r
2304 clrParamIdx = (EDMA3_DCHMAP_REG(pHandle->pDmaConfig->cc,\r
2305 pHandle->pDmaConfig->clrChannel) >> 5);\r
2306 EDMA3_DCHMAP_REG(pHandle->pDmaConfig->cc,\r
2307 pHandle->pDmaConfig->clrChannel) = (paramIdx<<5);\r
2308 paramAddress = EDMA_TPCC_PARAM_BASE_ADDR(pHandle->pDmaConfig->cc) +\r
2309 (0x20 * paramIdx);\r
2310 \r
2311 /* Check for buffer wrap */\r
2312 if(etbLib_bufferWrapped[pHandle->id][0])\r
2313 {\r
2314 pStatus->availableWords = pHandle->dmaStatus.dbufWords;\r
2315 pStatus->startAddr = PARAM_DST_REG(paramAddress) + remBytes;\r
2316 pStatus->isWrapped = 1;\r
2317 }\r
2318 else\r
2319 {\r
2320 pStatus->availableWords = (PARAM_DST_REG(paramAddress) -\r
2321 pHandle->pDmaConfig->dbufAddress) / 4;\r
2322 pStatus->availableWords += remWords;\r
2323 pStatus->startAddr = pHandle->pDmaConfig->dbufAddress;\r
2324 pStatus->isWrapped = 0;\r
2325 }\r
2326 \r
2327 /* Copy the DMA status into the handle for later management. The status\r
2328 * value for the number of words may be different than what was in the\r
2329 * configuration structure. This value is set during configuration.\r
2330 */\r
2331 pStatus->dbufAddress = pHandle->pDmaConfig->dbufAddress;\r
2332 pStatus->dbufWords = pHandle->dmaStatus.dbufWords;\r
2333 pStatus->flushRequired = pHandle->dmaStatus.flushRequired;\r
2334 pHandle->dmaStatus = *pStatus;\r
2335 \r
2336 /* If the mode has been set to non-circular and the buffer wrapped flag\r
2337 * is set, then the memory buffer if full, otherwise continue the\r
2338 * configuration for the final DMA.\r
2339 */\r
2340 if((pHandle->pDmaConfig->mode == eDMA_Stop_Buffer) &&\r
2341 (etbLib_bufferWrapped[pHandle->id][0]))\r
2342 {\r
2343 /* If the buffer wrapped, the startAddr value is incorrect from\r
2344 * above, set back to beginning of the buffer.\r
2345 */\r
2346 pStatus->startAddr = pHandle->pDmaConfig->dbufAddress;\r
2347 pHandle->dmaStatus.startAddr = pHandle->pDmaConfig->dbufAddress;\r
2348 return eETB_Success;\r
2349 }\r
2350 \r
2351 // Update the 3 symbols which are required for CCS ETB receiver\r
2352 etbLib_buffer_start_addr[pHandle->id] = pHandle->pDmaConfig->dbufAddress; //CCS ETB receiver will always get a linearized buffer for the non-EDMA ETB drain case\r
2353 etbLib_buffer_size[pHandle->id] = pStatus->availableWords * 4; //Number of bytes available \r
2354 etbLib_buffer_data_start[pHandle->id] = pStatus->startAddr; //circular buffer wrap point\r
2355 \r
2356 if(remBytes > ETB_BURST_SIZE)\r
2357 {\r
2358 uint16_t transCnt;\r
2359 \r
2360 /* Split the transfer into burst transactions.\r
2361 * Any remaining data beyond an even multiple of burst size bytes\r
2362 * will get linked for a single remaining transaction.\r
2363 */\r
2364 transCnt = remBytes / ETB_BURST_SIZE;\r
2365 PARAM_AB_CNT_REG(paramAddress) &= ~PARAM_BCNT_MASK;\r
2366 PARAM_AB_CNT_REG(paramAddress) |= PARAM_BCNT(transCnt);\r
2367 PARAM_CCNT_REG(paramAddress) = 1;\r
2368 \r
2369 /* Adjust the remaining byte count */\r
2370 remBytes -= (transCnt * ETB_BURST_SIZE);\r
2371 }\r
2372 else\r
2373 {\r
2374 PARAM_AB_CNT_REG(paramAddress) = PARAM_BCNT(1) | PARAM_ACNT(remBytes);\r
2375 PARAM_CCNT_REG(paramAddress) = 1;\r
2376 remBytes = 0;\r
2377 }\r
2378 /* If there are remaining bytes to transfer, setup link param for final\r
2379 * transaction.\r
2380 */\r
2381 if(remBytes > 0)\r
2382 {\r
2383 uint32_t etb3param;\r
2384 \r
2385 etb3param = EDMA_TPCC_PARAM_BASE_ADDR(pHandle->pDmaConfig->cc) +\r
2386 (0x20 * pHandle->pDmaConfig->linkparam[2]);\r
2387 \r
2388 /* Further ETB PaRAM modifications */\r
2389 PARAM_OPT_REG(paramAddress) = (PARAM_OPT_TCCHEN |\r
2390 PARAM_OPT_TCC(pHandle->pDmaConfig->clrChannel) |\r
2391 PARAM_OPT_AB_SYNC);\r
2392 PARAM_LINK_REG(paramAddress) &= ~PARAM_LINK_MASK;\r
2393 PARAM_LINK_REG(paramAddress) |= PARAM_LINK(etb3param);\r
2394 \r
2395 /* ETB linked PaRAM modifications */\r
2396 PARAM_OPT_REG(etb3param) = (PARAM_OPT_TCINTEN |\r
2397 PARAM_OPT_TCC(pHandle->pDmaConfig->clrChannel) |\r
2398 PARAM_OPT_AB_SYNC);\r
2399 PARAM_AB_CNT_REG(etb3param) = PARAM_BCNT(1) | PARAM_ACNT(remBytes);\r
2400 PARAM_DST_REG(etb3param) = PARAM_DST_REG(paramAddress) +\r
2401 (PARAM_BCNT_VALUE(paramAddress) * ETB_BURST_SIZE);\r
2402 PARAM_CCNT_REG(etb3param) = 1;\r
2403 PARAM_LINK_REG(etb3param) &= ~PARAM_LINK_MASK;\r
2404 PARAM_LINK_REG(etb3param) |= PARAM_LINK(0xffff);\r
2405 }\r
2406 else\r
2407 {\r
2408 PARAM_OPT_REG(paramAddress) = (PARAM_OPT_TCINTEN |\r
2409 PARAM_OPT_TCC(pHandle->pDmaConfig->clrChannel) |\r
2410 PARAM_OPT_AB_SYNC);\r
2411 }\r
2412 \r
2413 CIC_STATUS_CLR_INDEX_REG(pHandle->pDmaConfig->cic) = etbLib_cpCicEventClearValue[cic_index][pHandle->id][0];\r
2414 CIC_STATUS_CLR_INDEX_REG(pHandle->pDmaConfig->cic) = etbLib_cpCicEventClearValue[cic_index][pHandle->id][1];\r
2415 \r
2416 if(pHandle->pDmaConfig->clrChannel > 31)\r
2417 {\r
2418 EDMA3_ICRH_REG(pHandle->pDmaConfig->cc) =\r
2419 (1 << (pHandle->pDmaConfig->clrChannel - 32));\r
2420 }\r
2421 else\r
2422 {\r
2423 EDMA3_ICR_REG(pHandle->pDmaConfig->cc) =\r
2424 (1 << pHandle->pDmaConfig->clrChannel);\r
2425 }\r
2426 \r
2427 /* Force an event manually from the ETB interrupt register */\r
2428 *((volatile uint32_t*)ETB_IRST(pHandle->id)) = 1;\r
2429 \r
2430 /* Poll the interrupt pending bit for transaction completion */\r
2431 cntr = 0;\r
2432 if(pHandle->pDmaConfig->clrChannel > 31)\r
2433 {\r
2434 while((EDMA3_IPRH_REG(pHandle->pDmaConfig->cc) &\r
2435 (1 << (pHandle->pDmaConfig->clrChannel - 32))) == 0)\r
2436 {\r
2437 if(cntr++ > ETB_DMA_TIMEOUT)\r
2438 break;\r
2439 }\r
2440 \r
2441 CIC_STATUS_CLR_INDEX_REG(pHandle->pDmaConfig->cic) = etbLib_cpCicEventClearValue[cic_index][pHandle->id][0];\r
2442 CIC_STATUS_CLR_INDEX_REG(pHandle->pDmaConfig->cic) = etbLib_cpCicEventClearValue[cic_index][pHandle->id][1];\r
2443 \r
2444 EDMA3_ICRH_REG(pHandle->pDmaConfig->cc) =\r
2445 (1 << (pHandle->pDmaConfig->clrChannel - 32));\r
2446 }\r
2447 else\r
2448 {\r
2449 while((EDMA3_IPR_REG(pHandle->pDmaConfig->cc) &\r
2450 (1 << pHandle->pDmaConfig->clrChannel)) == 0)\r
2451 {\r
2452 if(cntr++ > ETB_DMA_TIMEOUT)\r
2453 break;\r
2454 }\r
2455 \r
2456 CIC_STATUS_CLR_INDEX_REG(pHandle->pDmaConfig->cic) = etbLib_cpCicEventClearValue[cic_index][pHandle->id][0];\r
2457 CIC_STATUS_CLR_INDEX_REG(pHandle->pDmaConfig->cic) = etbLib_cpCicEventClearValue[cic_index][pHandle->id][1];\r
2458 \r
2459 EDMA3_ICR_REG(pHandle->pDmaConfig->cc) =\r
2460 (1 << pHandle->pDmaConfig->clrChannel);\r
2461 }\r
2462 \r
2463 /* Restore DMA Channel map for Clear Channel PaRAM index */\r
2464 EDMA3_DCHMAP_REG(pHandle->pDmaConfig->cc,\r
2465 pHandle->pDmaConfig->clrChannel) = (clrParamIdx<<5);\r
2466 \r
2467 // printf("Pending Cntr: %d\n", cntr);\r
2468 }\r
2469 else if(remWords < 0)\r
2470 {\r
2471 // printf(" *** remWords < 0, %d\n",remWords);\r
2472 /* Report error if < 0, otherwise nothing to read from ETB */\r
2473 return eETB_Overflow;\r
2474 \r
2475 }\r
2476 \r
2477 #elif defined(C6657) || defined(C66AK2Hxx) || defined(C66AK2Exx)\r
2478 \r
2479 int32_t remWords, remBytes;\r
2480 uint32_t rwp;\r
2481 uint32_t rrp;\r
2482 uint32_t paramAddress;\r
2483 uint16_t paramIdx;\r
2484 uint32_t retry, status;\r
2485 volatile uint32_t cntr = 0;\r
2486 \r
2487 if(!pHandle || !pStatus)\r
2488 {\r
2489 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2490 }\r
2491 if(!pHandle->pDmaConfig)\r
2492 {\r
2493 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2494 }\r
2495 \r
2496 /* Change the PaRAM set value for the DMA channel that handles the ETB\r
2497 * event to the drain PaRAM. This method is more efficient than copying\r
2498 * the PaRAM contents.\r
2499 */\r
2500 paramIdx = (EDMA3_DCHMAP_REG(pHandle->pDmaConfig->cc,\r
2501 pHandle->pDmaConfig->etbhalfChannel) >> 5);\r
2502 paramAddress = EDMA_TPCC_PARAM_BASE_ADDR(pHandle->pDmaConfig->cc) +\r
2503 (0x20 * paramIdx);\r
2504 \r
2505 if(check_etb_type(pHandle->id) == ETB_TYPE)\r
2506 {\r
2507 rwp = *((volatile uint32_t*)ETB_RWP(pHandle->id));\r
2508 rrp = *((volatile uint32_t*)ETB_RRP(pHandle->id));\r
2509 \r
2510 remWords = rwp - rrp;\r
2511 // printf(" rwp: %x, rrp: %x, diff: %d\n", rwp, rrp, remWords);\r
2512 \r
2513 if(remWords > 0)\r
2514 {\r
2515 remBytes = (remWords * 4);\r
2516 \r
2517 //Get EDMA buffer information\r
2518 if(get_edma_buffer_info(pHandle, pStatus, paramAddress, paramIdx, remWords))\r
2519 {\r
2520 return eETB_Success;\r
2521 }\r
2522 \r
2523 if(remBytes > ETB_BURST_SIZE)\r
2524 {\r
2525 uint16_t transCnt;\r
2526 \r
2527 /* Split the transfer into burst transactions.\r
2528 * Any remaining data beyond an even multiple of burst size bytes\r
2529 * will get linked for a single remaining transaction.\r
2530 */\r
2531 transCnt = remBytes / ETB_BURST_SIZE;\r
2532 PARAM_AB_CNT_REG(paramAddress) &= ~PARAM_BCNT_MASK;\r
2533 PARAM_AB_CNT_REG(paramAddress) |= PARAM_BCNT(transCnt);\r
2534 PARAM_CCNT_REG(paramAddress) = 1;\r
2535 \r
2536 /* Adjust the remaining byte count */\r
2537 remBytes -= (transCnt * ETB_BURST_SIZE);\r
2538 }\r
2539 else\r
2540 {\r
2541 PARAM_AB_CNT_REG(paramAddress) = PARAM_BCNT(1) | PARAM_ACNT(remBytes);\r
2542 PARAM_CCNT_REG(paramAddress) = 1;\r
2543 remBytes = 0;\r
2544 }\r
2545 /* If there are remaining bytes to transfer, setup link param for final\r
2546 * transaction.\r
2547 */\r
2548 if(remBytes > 0)\r
2549 {\r
2550 uint32_t etb3param;\r
2551 \r
2552 etb3param = EDMA_TPCC_PARAM_BASE_ADDR(pHandle->pDmaConfig->cc) +\r
2553 (0x20 * pHandle->pDmaConfig->linkparam[2]);\r
2554 \r
2555 /* Further ETB PaRAM modifications */\r
2556 PARAM_OPT_REG(paramAddress) = (PARAM_OPT_TCCHEN |\r
2557 PARAM_OPT_TCC(pHandle->pDmaConfig->etbhalfChannel) |\r
2558 PARAM_OPT_AB_SYNC);\r
2559 PARAM_LINK_REG(paramAddress) &= ~PARAM_LINK_MASK;\r
2560 PARAM_LINK_REG(paramAddress) |= PARAM_LINK(etb3param);\r
2561 \r
2562 /* ETB linked PaRAM modifications */\r
2563 PARAM_OPT_REG(etb3param) = (PARAM_OPT_TCINTEN |\r
2564 PARAM_OPT_TCC(pHandle->pDmaConfig->etbhalfChannel) |\r
2565 PARAM_OPT_AB_SYNC);\r
2566 PARAM_AB_CNT_REG(etb3param) = PARAM_BCNT(1) | PARAM_ACNT(remBytes);\r
2567 PARAM_DST_REG(etb3param) = PARAM_DST_REG(paramAddress) +\r
2568 (PARAM_BCNT_VALUE(paramAddress) * ETB_BURST_SIZE);\r
2569 PARAM_CCNT_REG(etb3param) = 1;\r
2570 PARAM_LINK_REG(etb3param) &= ~PARAM_LINK_MASK;\r
2571 PARAM_LINK_REG(etb3param) |= PARAM_LINK(0xffff);\r
2572 }\r
2573 else\r
2574 {\r
2575 PARAM_OPT_REG(paramAddress) = (PARAM_OPT_TCINTEN |\r
2576 PARAM_OPT_TCC(pHandle->pDmaConfig->etbhalfChannel) |\r
2577 PARAM_OPT_AB_SYNC);\r
2578 }\r
2579 \r
2580 if(pHandle->pDmaConfig->etbhalfChannel > 31)\r
2581 {\r
2582 EDMA3_ICRH_REG(pHandle->pDmaConfig->cc) =\r
2583 (1 << (pHandle->pDmaConfig->etbhalfChannel - 32));\r
2584 }\r
2585 else\r
2586 {\r
2587 EDMA3_ICR_REG(pHandle->pDmaConfig->cc) =\r
2588 (1 << pHandle->pDmaConfig->etbhalfChannel);\r
2589 }\r
2590 \r
2591 /* Force an event manually from the ETB interrupt register */\r
2592 *((volatile uint32_t*)ETB_IRST(pHandle->id)) = 1;\r
2593 \r
2594 /* Poll the interrupt pending bit for transaction completion */\r
2595 cntr = 0;\r
2596 if(pHandle->pDmaConfig->etbhalfChannel > 31)\r
2597 {\r
2598 while((EDMA3_IPRH_REG(pHandle->pDmaConfig->cc) &\r
2599 (1 << (pHandle->pDmaConfig->etbhalfChannel - 32))) == 0)\r
2600 {\r
2601 if(cntr++ > ETB_DMA_TIMEOUT)\r
2602 break;\r
2603 }\r
2604 \r
2605 EDMA3_ICRH_REG(pHandle->pDmaConfig->cc) =\r
2606 (1 << (pHandle->pDmaConfig->etbhalfChannel - 32));\r
2607 }\r
2608 else\r
2609 {\r
2610 while((EDMA3_IPR_REG(pHandle->pDmaConfig->cc) &\r
2611 (1 << pHandle->pDmaConfig->etbhalfChannel)) == 0)\r
2612 {\r
2613 if(cntr++ > ETB_DMA_TIMEOUT)\r
2614 break;\r
2615 }\r
2616 \r
2617 EDMA3_ICR_REG(pHandle->pDmaConfig->cc) =\r
2618 (1 << pHandle->pDmaConfig->etbhalfChannel);\r
2619 }\r
2620 }\r
2621 else if(remWords < 0)\r
2622 {\r
2623 // printf(" *** remWords < 0, %d\n",remWords);\r
2624 /* Report error if < 0, otherwise nothing to read from ETB */\r
2625 return eETB_Overflow;\r
2626 \r
2627 }\r
2628 }\r
2629 else\r
2630 {\r
2631 //Perform an Output flush from the TBR\r
2632 // Wait for any previous output flush to complete\r
2633 retry = 50000; // Give enough time for a DMA transfer equal to half the size of the TBR\r
2634 do\r
2635 {\r
2636 status = *(volatile uint32_t*)ETB_FFCR(pHandle->id);\r
2637 retry--;\r
2638 }while( ( ( status & TBR_OUTFLUSH_INPROGRESS ) != 0 ) && ( retry != 0 ) );\r
2639 \r
2640 // Return error if timeout occurs on the above operation\r
2641 if (retry == 0)\r
2642 {\r
2643 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2644 }\r
2645 \r
2646 // Issue an output flush\r
2647 status = *(volatile uint32_t*)ETB_FFCR(pHandle->id);\r
2648 *(volatile uint32_t*)ETB_FFCR(pHandle->id) = status | TBR_OUTFLUSH_START;\r
2649 \r
2650 // Wait for output flush to complete\r
2651 retry = 50000;\r
2652 do\r
2653 {\r
2654 status = *(volatile uint32_t*)ETB_FFCR(pHandle->id);\r
2655 retry--;\r
2656 }while(((status & TBR_OUTFLUSH_INPROGRESS) != 0 ) && (retry != 0));\r
2657 \r
2658 // Return error if timeout occurs on the above operation\r
2659 if (retry == 0)\r
2660 {\r
2661 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2662 }\r
2663 \r
2664 // Wait for final DMA transfer to complete\r
2665 //retry = 50000; // Give enough time for a DMA transfer equal to half the size of the TBR\r
2666 retry = 500;\r
2667 do\r
2668 {\r
2669 status = *((volatile uint32_t*)ETB_STS(pHandle->id));\r
2670 retry--;\r
2671 }while(((status & TBR_DRAIN_INPROGRESS) != TBR_DRAIN_INPROGRESS) && ( retry != 0 ));\r
2672 \r
2673 // Return error if timeout occurs on the above operation\r
2674 if (retry == 0)\r
2675 {\r
2676 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2677 }\r
2678 \r
2679 //Make sure there are no pending read requests on the TBR slave port\r
2680 retry = 50000;\r
2681 do\r
2682 {\r
2683 status = *((volatile uint32_t*)TBR_SICTRL(pHandle->id));\r
2684 retry--;\r
2685 }while(((status & TBR_READ_REQ_PENDING) != 0) && ( retry != 0 ));\r
2686 \r
2687 // Return error if timeout occurs on the above operation\r
2688 if (retry == 0)\r
2689 {\r
2690 RETURN_ETB_CALLBACK(pHandle->id, eETB_Error_Program);\r
2691 }\r
2692 \r
2693 //Get EDMA buffer information\r
2694 if(get_edma_buffer_info(pHandle, pStatus, paramAddress, paramIdx, 0))\r
2695 {\r
2696 return eETB_Success;\r
2697 }\r
2698 }\r
2699 \r
2700 #endif\r
2701 \r
2702 return eETB_Success;\r
2703 }\r
2704 \r
2705 /******************************************************************************/\r
2706 /*! \copydoc ETB_setDmaStatus\r
2707 */\r
2708 void ETB_setDmaStatus(ETBHandle* pHandle, DMAStatus *pStatus)\r
2709 {\r
2710 if(!pHandle || !pStatus)\r
2711 {\r
2712 return;\r
2713 }\r
2714 if(!pHandle->pDmaConfig)\r
2715 {\r
2716 return;\r
2717 }\r
2718 pHandle->dmaStatus = *pStatus;\r
2719 }\r
2720 #endif\r
2721 \r
2722 /******************************************************************************/\r
2723 /*! \copydoc ETB_getProperties\r
2724 */\r
2725 void ETB_getProperties(ETBProperties *pProperties)\r
2726 {\r
2727 \r
2728 #ifdef DMA_SUPPORT\r
2729 \r
2730 pProperties->is_dma_supported = 1;\r
2731 \r
2732 #else\r
2733 \r
2734 pProperties->is_dma_supported = 0;\r
2735 \r
2736 #endif\r
2737 \r
2738 return;\r
2739 }\r