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raw | patch | inline | side by side (parent: 19086a8)
author | Jianzhong Xu <a0869574local@uda0869574b> | |
Tue, 15 Dec 2015 21:20:23 +0000 (16:20 -0500) | ||
committer | Jianzhong Xu <a0869574local@uda0869574b> | |
Tue, 15 Dec 2015 21:20:23 +0000 (16:20 -0500) |
Makefile | patch | blob | history | |
examples/dsponly/Makefile | [new file with mode: 0644] | patch | blob |
examples/dsponly/dgemm_test/Makefile | [new file with mode: 0644] | patch | blob |
examples/dsponly/dgemm_test/Makefile.common | [new file with mode: 0644] | patch | blob |
examples/dsponly/dgemm_test/Makefile.libomp | [new file with mode: 0644] | patch | blob |
examples/dsponly/dgemm_test/config.bld | [new file with mode: 0644] | patch | blob |
examples/dsponly/dgemm_test/config_c6678.c | [new file with mode: 0644] | patch | blob |
examples/dsponly/dgemm_test/dgemm_test.c | [new file with mode: 0644] | patch | blob |
examples/dsponly/dgemm_test/omp_config.cfg | [new file with mode: 0644] | patch | blob |
examples/dsponly/dgemm_test/omp_config_bm.cfg | [new file with mode: 0644] | patch | blob |
examples/dsponly/setup_env_rtos_yocto.sh | [new file with mode: 0755] | patch | blob |
diff --git a/Makefile b/Makefile
index 944b7937f21b75715e15211ceb4fd94afd617a07..a42fdba8394caebf2b088e5534ef1fd950de3129 100644 (file)
--- a/Makefile
+++ b/Makefile
BLIS_VERSION = $(shell cat $(LINALG_BLIS_DIR)/version)
CBLAS_HEADERS =$(LINALG_CBLAS_DIR)/include/cblas.h
+CBLAS_HEADERS +=$(LINALG_TICBLAS_DIR)/ticblas.h
CLAPACK_HEADERS =$(LINALG_CLAPACK_DIR)/INCLUDE/blaswrap.h
CLAPACK_HEADERS+=$(LINALG_CLAPACK_DIR)/INCLUDE/clapack.h
CLAPACK_HEADERS+=$(LINALG_CLAPACK_DIR)/INCLUDE/f2c.h
cd ../$(LINALG_TICBLAS_DIR)/src; make MEM_MODEL=$(MEM_MODEL) TARGET=$(TARGET) LIBOS=$(LIBOS); cd ../lib; \
echo "combining BLIS, CBLAS, and TICBLAS libraries into one: libcblas.ae66"; \
mkdir -p objs; cd objs; rm *; ar x ../../../blis/install/c66xMedium/lib/libblis.ae66; mmv 'cblas*.o' 'blis_cblas#1.o'; \
- ar -x ../../../cblas/lib/C66/libcblas.ae66; ar -x ../libticblas.ae66; chmod +rw *;ar -cr ../libcblas.ae66 *; cd ../../..;
+ ar -x ../../../cblas/lib/C66/libcblas.ae66; ar -x ../libticblas.ae66; chmod +rw *;cd ../../..; \
+ mkdir -p lib; cd lib; rm *; ar -cr libcblas.ae66 ../ticblas/lib/objs/*;
ARMplusDSP:
cp docs/* ${DESTDIR}/usr/share/doc/ti-linalg
installDSPlib:
- install -m 755 -d ${DESTDIR}/usr/include
- install -m 755 -d ${DESTDIR}/usr/lib
- install -m 755 -d ${DESTDIR}/usr/share/doc/ti-linalg
- install -m 755 -d ${DESTDIR}/usr/share/ti/examples/linalg
- cp $(CBLAS_HEADERS) ${DESTDIR}/usr/include
- cp -r ./examples/* ${DESTDIR}/usr/share/ti/examples/linalg
- cp $(LINALG_TICBLAS_DIR)/lib/libcblas.ae66 ${DESTDIR}/usr/lib/
- cp docs/* ${DESTDIR}/usr/share/doc/ti-linalg
+ install -m 755 -d ${DESTDIR}/include
+ install -m 755 -d ${DESTDIR}/lib
+ cp $(CBLAS_HEADERS) ${DESTDIR}/include
+ cp ./lib/libcblas.ae66 ${DESTDIR}/lib
+ cp -r docs ${DESTDIR}
diff --git a/examples/dsponly/Makefile b/examples/dsponly/Makefile
--- /dev/null
@@ -0,0 +1,21 @@
+.SILENT:
+
+MFS = $(wildcard */Makefile)
+DIRS = $(patsubst %/Makefile,%,$(MFS))
+
+all:
+ for dir in $(DIRS); do \
+ echo "=============== " $$dir " =================" ; \
+ $(MAKE) -C $$dir; \
+ done
+
+test:
+ for dir in $(DIRS); do \
+ echo "=============== " $$dir " =================" ; \
+ $(MAKE) -C $$dir run; \
+ done
+
+clean:
+ for dir in $(DIRS); do \
+ $(MAKE) -C $$dir clean; \
+ done
diff --git a/examples/dsponly/dgemm_test/Makefile b/examples/dsponly/dgemm_test/Makefile
--- /dev/null
@@ -0,0 +1,7 @@
+# Default to RTSC mode
+USE_BIOS ?= 1
+
+testfiles = dgemm_test.c config_c6678.c
+outfile = dgemm_test.out
+
+include Makefile.common
diff --git a/examples/dsponly/dgemm_test/Makefile.common b/examples/dsponly/dgemm_test/Makefile.common
--- /dev/null
@@ -0,0 +1,58 @@
+# Makefile to build OpenMP applications
+
+
+default: all
+
+include Makefile.libomp
+
+
+#
+# Compiler option configuration
+#
+LNK_CMD = $(CFGDIR)/linker.cmd
+OPT_CMD = $(CFGDIR)/compiler.opt
+CL_OPTS = -@ $(OPT_CMD) -mv6600 --omp -I $(OMP_DIR)/packages/ti/runtime/openmp
+CL_OPTS += -I$(FC_DIR)/packages -I$(XDAIS_DIR)/packages -I$(EDMA3_DIR)/packages -I$(LIBARCH_DIR) -I$(LINALG_DIR)/include
+LNK_OPTS = -x -c --priority -w
+CL = $(CGTROOT)/bin/cl6x
+RTS_LIB = $(CGTROOT)/lib/libc.a
+LIBARCH_LIB = $(LIBARCH_DIR)/lib/libArch.ae66
+LINALG_LIB = $(LINALG_DIR)/lib/libcblas.ae66
+
+ifeq ($(BUILD_TYPE),debug)
+ CL_OPTS += -g --optimize_with_debug=on
+else
+ CL_OPTS += -o3
+endif
+
+
+ifneq ($(MAKECMDGOALS),clean)
+ifeq ($(TARGET),SOC_AM572x)
+CL_OPTS += -DTI_AM572 -DDEVICE_AM572x
+else ifeq ($(TARGET),SOC_K2H)
+CL_OPTS += -DTI_C6636 -DDEVICE_K2H
+else ifeq ($(TARGET),SOC_C6678)
+CL_OPTS += -DTI_C6678 -DDEVICE_C6678 -DLIB_RTOS
+else
+$(error must specify one of: \
+ TARGET=SOC_K2H \
+ TARGET=SOC_C6678 \
+ TARGET=SOC_AM572X
+endif
+endif
+
+all: $(outfile)
+
+
+%.out: $(testfiles) libomp_config
+ echo compiling $<
+ $(CL) $(CL_OPTS) $< $(testfiles) -z $(LNK_OPTS) -o $@ -m $*.map $(LNK_CMD) $(RTS_LIB) $(LIBARCH_LIB) $(LINALG_LIB)
+
+clean: libomp_clean
+ @rm -rf *.map *.out *.obj *.mak
+
+#
+# Cleans libomp artifacts
+#
+realclean: libomp_clean
+ @rm -rf *.map *.out *.obj *.mak
diff --git a/examples/dsponly/dgemm_test/Makefile.libomp b/examples/dsponly/dgemm_test/Makefile.libomp
--- /dev/null
@@ -0,0 +1,79 @@
+#
+# Makefile.libomp
+#
+
+
+#
+# Check if required environment variables are defined
+#
+
+ifneq ($(MAKECMDGOALS),clean)
+ifeq ($(OMP_DIR),)
+$(call error,ERROR - OMP_DIR NOT DEFINED)
+endif
+
+ifeq ($(XDC_DIR),)
+$(call error,ERROR - XDC_DIR NOT DEFINED)
+endif
+
+# Path to C6000 compiler tools
+ifeq ($(CGTROOT),)
+$(call error,ERROR - CGTROOT NOT DEFINED)
+endif
+
+# Paths to BIOS, IPC modules
+ifeq ($(USE_BIOS),1)
+ifeq ($(BIOS_DIR),)
+$(call error,ERROR - BIOS_DIR NOT DEFINED)
+endif
+ifeq ($(IPC_DIR),)
+$(call error,ERROR - IPC_DIR NOT DEFINED)
+endif
+endif
+endif
+
+
+# Configuration file used (without the .cfg extension)
+ifeq ($(USE_BIOS),1)
+CFGDIR = omp_config
+else
+CFGDIR = omp_config_bm
+endif
+
+# Set BUILD_TYPE to debug/release to pick appropriate libraries
+BUILD_TYPE = release
+
+# Platform file
+ifeq ($(TARGET),SOC_AM572x)
+export PDK_DIR=$(AM572_PDK_DIR)
+XDCPLATFORM = ti.runtime.openmp.platforms.am57x
+else ifeq ($(TARGET),SOC_C6678)
+export PDK_DIR=$(C6678_PDK_DIR)
+XDCPLATFORM = ti.runtime.openmp.platforms.evm6678
+else ifeq ($(TARGET),SOC_K2H)
+export PDK_DIR=$(C6636_PDK_DIR)
+XDCPLATFORM = ti.runtime.openmp.platforms.evmTCI6636K2H
+endif
+
+
+# Include . to find config.bld
+ifeq ($(USE_BIOS),1)
+XDCPATH = $(PDK_DIR)/packages;$(OMP_DIR)/packages;$(BIOS_DIR)/packages;$(IPC_DIR)/packages;$(FC_DIR)/packages;$(XDAIS_DIR)/packages;$(EDMA3_DIR)/packages;.
+else
+XDCPATH = $(PDK_DIR)/packages;$(OMP_DIR)/packages;$(BIOS_DIR)/packages;.
+endif
+
+XS = $(XDC_DIR)/xs
+XDC = $(XDC_DIR)/xdc
+XDCTARGET = ti.targets.elf.C66
+
+# Generate and build libomp config packages
+libomp_config:
+ @echo making $(CFGDIR) files
+ $(XS) --xdcpath "$(XDCPATH)" xdc.tools.configuro -c $(CGTROOT) --cb -t $(XDCTARGET) -p $(XDCPLATFORM) -r $(BUILD_TYPE) $(CFGDIR).cfg
+
+libomp_clean:
+ @echo Removing $(CFGDIR)
+ @rm -rf $(CFGDIR)/
+
+
diff --git a/examples/dsponly/dgemm_test/config.bld b/examples/dsponly/dgemm_test/config.bld
--- /dev/null
@@ -0,0 +1,21 @@
+/*
+ * ======== config.bld ========
+ * Sample Build configuration script
+ */
+
+/* Get the Tools Base directory from the Environment Variable. */
+var tiCgtDir = java.lang.System.getenv("CGTROOT");
+if (!tiCgtDir)
+{
+ throw new Error("CGTROOT environment variable not set");
+}
+
+//Setup for c66 target
+var C66 = xdc.useModule('ti.targets.elf.C66');
+C66.rootDir = tiCgtDir;
+C66.ccOpts.suffix += " -mi10 -mo ";
+
+//list interested targets in Build.targets array
+Build.targets = [
+ C66,
+ ];
diff --git a/examples/dsponly/dgemm_test/config_c6678.c b/examples/dsponly/dgemm_test/config_c6678.c
--- /dev/null
@@ -0,0 +1,834 @@
+/* ======================================================================= */
+/* TEXAS INSTRUMENTS, INC. */
+/* */
+/* FFTLIB FFT Library */
+/* */
+/* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ */
+/* */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following conditions */
+/* are met: */
+/* */
+/* Redistributions of source code must retain the above copyright */
+/* notice, this list of conditions and the following disclaimer. */
+/* */
+/* Redistributions in binary form must reproduce the above copyright */
+/* notice, this list of conditions and the following disclaimer in the */
+/* documentation and/or other materials provided with the */
+/* distribution. */
+/* */
+/* Neither the name of Texas Instruments Incorporated nor the names of */
+/* its contributors may be used to endorse or promote products derived */
+/* from this software without specific prior written permission. */
+/* */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */
+/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */
+/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */
+/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */
+/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */
+/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */
+/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */
+/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
+/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */
+/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* */
+/* ======================================================================= */
+
+#include <xdc/std.h>
+#include <ti/sdo/edma3/rm/edma3_rm.h>
+#include <ti/sdo/fc/edma3/edma3_config.h>
+
+#define EDMA_MGR_NUM_EDMA_INSTANCES 3
+
+/* In the arrays below, each bit of a 32-bit word corresponds to a single */
+/* PaRAMSet/EDMAChannel/QDMAChannel/TCC owned by the corresponding region, */
+/* i.e., can be used for general purpose EDMA tranfers, or reserved for */
+/* EDMA transfers by hardware peripherals (cannot be used for general */
+/* purpose EDMA tranfers) */
+
+#define DMA_CHANNEL_TO_EVENT_MAPPING_0 (0x00000000u)
+#define DMA_CHANNEL_TO_EVENT_MAPPING_1 (0x00000000u)
+
+/* EDMA3_InstanceInitConfig sample0 with region neither owning nor */
+/* reserving any EDMA resources */
+#define regionSample0 \
+{ \
+ /* Resources owned by Region */ \
+ /* ownPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
+ \
+ /* ownDmaChannels */ \
+ {0x00000000u, 0x00000000u}, \
+ \
+ /* ownQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* ownTccs */ \
+ {0x00000000u, 0x00000000u}, \
+ \
+ /* Resources reserved by Region */ \
+ /* resvdPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
+ \
+ /* resvdDmaChannels */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
+ \
+ /* resvdQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* resvdTccs */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
+}
+
+/* EDMA3_InstanceInitConfig sample1 with region owning PaRAM sets 64-105, */
+/* and EDMA channel 0-7, but not reserving any EDMA resources */
+/* Note that the first N PaRAM sets (N=number of EDMA channels available */
+/* on an EDMA instance) are reserved in EDMA3 LLD ). */
+#define regionSample1 \
+{ \
+ /* Resources owned by Region */ \
+ /* ownPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, \
+ 0xFFFFFFFFu, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
+ \
+ /* ownDmaChannels */ \
+ {0x0000FFFFu, 0x00000000u}, \
+ \
+ /* ownQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* ownTccs */ \
+ {0x0000FFFFu, 0x00000000u}, \
+ \
+ /* Resources reserved by Region */ \
+ /* resvdPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
+ \
+ /* resvdDmaChannels */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
+ \
+ /* resvdQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* resvdTccs */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
+}
+
+
+/* EDMA3_InstanceInitConfig sample2 with region owning PaRAM sets 106-147, */
+/* and EDMA channel 8-15, but not reserving any EDMA resources */
+#define regionSample2 \
+{ \
+ /* Resources owned by Region */ \
+ /* ownPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
+ \
+ /* ownDmaChannels */ \
+ {0xFFFF0000u, 0x00000000u}, \
+ \
+ /* ownQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* ownTccs */ \
+ {0xFFFF0000u, 0x00000000u}, \
+ \
+ /* Resources reserved by Region */ \
+ /* resvdPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
+ \
+ /* resvdDmaChannels */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
+ \
+ /* resvdQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* resvdTccs */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
+}
+
+/* EDMA3_InstanceInitConfig sample3 with region owning PaRAM sets 148-189, */
+/* and EDMA channel 16-23, but not reserving any EDMA resources */
+#define regionSample3 \
+{ \
+ /* Resources owned by Region */ \
+ /* ownPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
+ \
+ /* ownDmaChannels */ \
+ {0x00000000u, 0x0000FFFFu}, \
+ \
+ /* ownQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* ownTccs */ \
+ {0x00000000u, 0x0000FFFFu}, \
+ \
+ /* Resources reserved by Region */ \
+ /* resvdPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
+ \
+ /* resvdDmaChannels */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
+ \
+ /* resvdQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* resvdTccs */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
+}
+
+/* EDMA3_InstanceInitConfig sample4 with region owning PaRAM sets 190-231, */
+/* and EDMA channel 24-31, but not reserving any EDMA resources */
+#define regionSample4 \
+{ \
+ /* Resources owned by Region */ \
+ /* ownPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0xFFFFFFFFu, \
+ 0xFFFFFFFFu, 0xFFFFFFFFu, 0x00000000u, 0x00000000u}, \
+ \
+ /* ownDmaChannels */ \
+ {0x00000000u, 0xFFFF0000u}, \
+ \
+ /* ownQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* ownTccs */ \
+ {0x00000000u, 0xFFFF0000u}, \
+ \
+ /* Resources reserved by Region */ \
+ /* resvdPaRAMSets */ \
+ {0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u, \
+ 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u}, \
+ \
+ /* resvdDmaChannels */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1}, \
+ \
+ /* resvdQdmaChannels */ \
+ {0x00000000u}, \
+ \
+ /* resvdTccs */ \
+ {DMA_CHANNEL_TO_EVENT_MAPPING_0, DMA_CHANNEL_TO_EVENT_MAPPING_1} \
+}
+
+#define NUM_EDMA_INSTANCES 3
+const EDMA3_InstanceInitConfig C6678_config[NUM_EDMA_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+ /* EDMA3 INSTANCE# 0 */
+ { regionSample0, regionSample0, regionSample0, regionSample0,
+ regionSample0, regionSample0, regionSample0, regionSample0
+ },
+ /* EDMA3 INSTANCE# 1 */
+ { regionSample1, regionSample2, regionSample3, regionSample4,
+ regionSample0, regionSample0, regionSample0, regionSample0
+ },
+ /* EDMA3 INSTANCE# 2 */
+ { regionSample0, regionSample0, regionSample0, regionSample0,
+ regionSample1, regionSample2, regionSample3, regionSample4
+ }
+};
+
+const EDMA3_InstanceInitConfig edmaMgrInstanceInitConfig[EDMA_MGR_NUM_EDMA_INSTANCES][EDMA3_MAX_REGIONS] =
+{
+ /* EDMA3 INSTANCE# 0 */
+ { regionSample0, regionSample0, regionSample0, regionSample0,
+ regionSample0, regionSample0, regionSample0, regionSample0
+ },
+ /* EDMA3 INSTANCE# 1 */
+ { regionSample1, regionSample2, regionSample3, regionSample4,
+ regionSample0, regionSample0, regionSample0, regionSample0
+ },
+ /* EDMA3 INSTANCE# 2 */
+ { regionSample0, regionSample0, regionSample0, regionSample0,
+ regionSample1, regionSample2, regionSample3, regionSample4
+ }
+};
+
+int32_t edmaMgrRegion2Instance[EDMA3_MAX_REGIONS] = {1,1,1,1,2,2,2,2};
+
+/* Driver Object Initialization Configuration */
+EDMA3_GblConfigParams edmaMgrGblConfigParams [EDMA_MGR_NUM_EDMA_INSTANCES] =
+ {
+ {
+ /* EDMA3 INSTANCE# 0 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 16u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 128u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 2u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 2u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02700000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02760000u,
+ (void *)0x02768000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 38u,
+ /** Interrupt no. for CC Error */
+ 32u,
+ /** Interrupt no. for TCs Error */
+ {
+ 34u,
+ 35u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS,
+ EDMA3_MAX_PARAM_SETS, EDMA3_MAX_PARAM_SETS
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ /* DMA channels 16-63 DOES NOT exist */
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC,
+ EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC, EDMA3_MAX_TCC
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0x00000000u,
+ 0x00000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 1 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02720000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02770000u,
+ (void *)0x02778000u,
+ (void *)0x02780000u,
+ (void *)0x02788000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 8u,
+ /** Interrupt no. for CC Error */
+ 0u,
+ /** Interrupt no. for TCs Error */
+ {
+ 2u,
+ 3u,
+ 4u,
+ 5u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 128u,
+ 64u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFF000000u
+ }
+ },
+
+ {
+ /* EDMA3 INSTANCE# 2 */
+ /** Total number of DMA Channels supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of QDMA Channels supported by the EDMA3 Controller */
+ 8u,
+ /** Total number of TCCs supported by the EDMA3 Controller */
+ 64u,
+ /** Total number of PaRAM Sets supported by the EDMA3 Controller */
+ 512u,
+ /** Total number of Event Queues in the EDMA3 Controller */
+ 4u,
+ /** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
+ 4u,
+ /** Number of Regions on this EDMA3 controller */
+ 8u,
+
+ /**
+ * \brief Channel mapping existence
+ * A value of 0 (No channel mapping) implies that there is fixed association
+ * for a channel number to a parameter entry number or, in other words,
+ * PaRAM entry n corresponds to channel n.
+ */
+ 1u,
+
+ /** Existence of memory protection feature */
+ 1u,
+
+ /** Global Register Region of CC Registers */
+ (void *)0x02740000u,
+ /** Transfer Controller (TC) Registers */
+ {
+ (void *)0x02790000u,
+ (void *)0x02798000u,
+ (void *)0x027A0000u,
+ (void *)0x027A8000u,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL,
+ (void *)NULL
+ },
+ /** Interrupt no. for Transfer Completion */
+ 24u,
+ /** Interrupt no. for CC Error */
+ 16u,
+ /** Interrupt no. for TCs Error */
+ {
+ 18u,
+ 19u,
+ 20u,
+ 21u,
+ 0u,
+ 0u,
+ 0u,
+ 0u,
+ },
+
+ /**
+ * \brief EDMA3 TC priority setting
+ *
+ * User can program the priority of the Event Queues
+ * at a system-wide level. This means that the user can set the
+ * priority of an IO initiated by either of the TCs (Transfer Controllers)
+ * relative to IO initiated by the other bus masters on the
+ * device (ARM, DSP, USB, etc)
+ */
+ {
+ 0u,
+ 1u,
+ 2u,
+ 3u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+ /**
+ * \brief To Configure the Threshold level of number of events
+ * that can be queued up in the Event queues. EDMA3CC error register
+ * (CCERR) will indicate whether or not at any instant of time the
+ * number of events queued up in any of the event queues exceeds
+ * or equals the threshold/watermark value that is set
+ * in the queue watermark threshold register (QWMTHRA).
+ */
+ {
+ 16u,
+ 16u,
+ 16u,
+ 16u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief To Configure the Default Burst Size (DBS) of TCs.
+ * An optimally-sized command is defined by the transfer controller
+ * default burst size (DBS). Different TCs can have different
+ * DBS values. It is defined in Bytes.
+ */
+ {
+ 128u,
+ 64u,
+ 64u,
+ 128u,
+ 0u,
+ 0u,
+ 0u,
+ 0u
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a Parameter RAM set,
+ * if it exists, otherwise of no use.
+ */
+ {
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP,
+ EDMA3_RM_CH_NO_PARAM_MAP, EDMA3_RM_CH_NO_PARAM_MAP
+ },
+
+ /**
+ * \brief Mapping from each DMA channel to a TCC. This specific
+ * TCC code will be returned when the transfer is completed
+ * on the mapped channel.
+ */
+ {
+ 0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
+ 8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
+ 16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
+ 24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
+ 32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
+ EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP
+ },
+
+ /**
+ * \brief Mapping of DMA channels to Hardware Events from
+ * various peripherals, which use EDMA for data transfer.
+ * All channels need not be mapped, some can be free also.
+ */
+ {
+ 0xFFFFFFFFu,
+ 0xFF000000u
+ }
+ },
+ };
+
+
+int32_t *ti_sdo_fc_edmamgr_region2Instance = (int32_t*)&edmaMgrRegion2Instance[0];
+EDMA3_GblConfigParams *ti_sdo_fc_edmamgr_edma3GblConfigParams = (EDMA3_GblConfigParams*)&edmaMgrGblConfigParams[0];
+EDMA3_InstanceInitConfig *ti_sdo_fc_edmamgr_edma3RegionConfig = (EDMA3_InstanceInitConfig*)&edmaMgrInstanceInitConfig[0][0];
diff --git a/examples/dsponly/dgemm_test/dgemm_test.c b/examples/dsponly/dgemm_test/dgemm_test.c
--- /dev/null
@@ -0,0 +1,271 @@
+/******************************************************************************
+* FILE: dgemm_test.c
+******************************************************************************/
+#include <omp.h>
+#include <stdio.h>
+#include <libarch.h>
+#include <ticblas.h>
+#include <cblas.h>
+
+/* use small memory model of BLAS */
+#define BLAS_L2_BUF_SIZE (256*1024UL) /* 256KB */
+#define BLAS_MSMC_BUF_SIZE (2*1024*1024UL) /* 2MB */
+#define BLAS_L3_DDR_SIZE_ZERO (0)
+
+size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
+
+#pragma DATA_SECTION(blas_msmc_buf, ".blas_msmc")
+#pragma DATA_ALIGN(blas_msmc_buf,32)
+char blas_msmc_buf[BLAS_MSMC_BUF_SIZE];
+
+#pragma DATA_SECTION(blas_l2_buf, ".blas_l2")
+#pragma DATA_ALIGN(blas_l2_buf,32)
+char blas_l2_buf[BLAS_L2_BUF_SIZE];
+
+int config_mem_for_ticblas(double *msmc_buf, double *l2_buf, size_t msmc_buf_size, size_t l2_buf_size);
+int reconfig_mem_after_ticblas();
+void matrix_gen(double *A, double *B, double *C, int m, int k, int n);
+void test_edma();
+
+int main (int argc, char *argv[])
+{
+ double *A, *B, *C;
+ int m, n, k, err, l2_cache_size;
+ double alpha, beta;
+
+ int nthreads, tid;
+
+#if 1
+/* Fork a team of threads giving them their own copies of variables */
+#pragma omp parallel private(nthreads, tid)
+ {
+
+ /* Obtain thread number */
+ tid = omp_get_thread_num();
+ printf("Hello World from thread = %d\n", tid);
+
+ /* Only master thread does this */
+ if (tid == 0)
+ {
+ nthreads = omp_get_num_threads();
+ printf("Number of threads = %d\n", nthreads);
+ }
+
+ } /* All threads join master thread and disband */
+#endif
+
+ //printf("Testing EDMA manager.\n");
+
+ //test_edma();
+
+ m = k = n = 1000;
+ alpha = 0.7;
+ beta = 1.3;
+
+ /* Allocate memory for matrices */
+ A = (double *)malloc( m*k*sizeof( double ) );
+ B = (double *)malloc( k*n*sizeof( double ) );
+ C = (double *)malloc( m*n*sizeof( double ) );
+ if (A == NULL || B == NULL || C == NULL) {
+ printf( "\nERROR: Can't allocate memory for matrices. Aborting... \n\n");
+ free(A);
+ free(B);
+ free(C);
+ return 1;
+ }
+ else {
+ printf("Matrix A address: 0x%x, Matrix B address: 0x%x, Matrix C address: 0x%x.\n", (unsigned int)A, (unsigned int)B, (unsigned int)C);
+ }
+
+ /* Initialize random number generator */
+ srand(123456789);
+
+ matrix_gen(A, B, C, m, k, n);
+
+ switch (CACHE_getL2Size())
+ {
+ case CACHE_0KCACHE: l2_cache_size = 0; break;
+ case CACHE_32KCACHE: l2_cache_size = (32 << 10); break;
+ case CACHE_64KCACHE: l2_cache_size = (64 << 10); break;
+ case CACHE_128KCACHE: l2_cache_size = (128 << 10); break;
+ case CACHE_256KCACHE: l2_cache_size = (256 << 10); break;
+ case CACHE_512KCACHE: l2_cache_size = (512 << 10); break;
+ case CACHE_1024KCACHE: l2_cache_size = (1024 << 10); break;
+ default: l2_cache_size = (1024 << 10); break;
+ }
+
+ printf("CACHE_getL2Size() returns %d, L2 Cache size is %d.\n", CACHE_getL2Size(), l2_cache_size);
+ printf("lib_get_L2_SRAM_size() returns %d, lib_get_L2_total_size() returns %d.\n", lib_get_L2_SRAM_size(), lib_get_L2_total_size());
+
+ //err = config_mem_for_ticblas((double *)blas_msmc_buf, (size_t)BLAS_MSMC_BUF_SIZE);
+ err = config_mem_for_ticblas((double *)blas_msmc_buf, (double *)blas_l2_buf, (size_t)BLAS_MSMC_BUF_SIZE, (size_t)BLAS_L2_BUF_SIZE);
+ if(err) {
+ printf("Memory configuration for BLAS failed with error code %d.\n", err);
+ }
+
+ cblas_dgemm(CblasColMajor, CblasNoTrans, CblasNoTrans, m, n, k, alpha, A, k, B, n, beta, C, n);
+
+ reconfig_mem_after_ticblas();
+
+ return 0;
+}
+
+void test_edma()
+{
+ //lib_emt_Handle test_emt_handle;
+ EdmaMgr_Handle test_edma_handle;
+ int coreID, edma_err;
+
+ coreID = lib_get_coreID();
+
+ printf("Core ID is %d\n", coreID);
+
+ edma_err = EdmaMgr_init(coreID, NULL);
+
+ printf("EdmaMgr_init finished.\n");
+
+ if(edma_err != EdmaMgr_SUCCESS) {
+ printf("EdmaMgr_init fails. Error code is %d.\n", edma_err);
+ }
+ else {
+ printf("EdmaMgr_init succeeds.\n");
+ }
+
+ /* Use external memory transfer API */
+ //lib_emt_init();
+ //if((test_emt_handle=lib_emt_alloc(1))==NULL) {
+ if((test_edma_handle=EdmaMgr_alloc(1))==NULL) {
+ printf("External memory transfer handle allocation error!\n");
+ return;
+ }
+ else {
+ printf("External memory transfer handle allocation succeeded!\n");
+ }
+}
+
+
+void matrix_gen(double *A, double *B, double *C, int m, int k, int n)
+{
+
+ int i;
+ for (i = 0; i < (m*k); i++) {
+ A[i] = (double)rand()/RAND_MAX;
+ }
+
+ for (i = 0; i < (k*n); i++) {
+ B[i] = (double)rand()/RAND_MAX;
+ }
+
+ for (i = 0; i < (m*n); i++) {
+ C[i] = (double)rand()/RAND_MAX;
+ }
+
+}
+
+int config_mem_for_ticblas(double *msmc_buf, double *l2_buf, size_t msmc_buf_size, size_t l2_buf_size)
+{
+ size_t smem_size_vfast, smem_size_fast, smem_size_med, smem_size_slow;
+ void *l1d_SRAM_ptr, *l2_SRAM_ptr;
+ int l1d_cfg_err, l2_cfg_err, tid;
+
+ /* First, verify the provided/available memory meet requirements */
+ tiCblasGetSizes(&smem_size_vfast, &smem_size_fast, &smem_size_med, &smem_size_slow);
+
+ printf("BLAS memory requirements - vfast size: %d, fast size: %d, medium size: %d, slow size: %d.\n", smem_size_vfast, smem_size_fast, smem_size_med, smem_size_slow);
+
+ if( (smem_size_vfast> lib_get_L1D_total_size()) /* total available L1D */
+ //||(smem_size_fast > lib_get_L2_total_size()) /* total available L2 */
+ ||(smem_size_fast > l2_buf_size) /* total available L2 */
+ ||(smem_size_med > msmc_buf_size) /* provided MSMC memory */
+ ||(smem_size_slow > BLAS_L3_DDR_SIZE_ZERO) /* DDR not used */
+ ) {
+ return(-2);
+ }
+
+ /* Configure L1D if necessary */
+ l1D_SRAM_size_orig = lib_get_L1D_SRAM_size(); /* get current L1D SRAM size */
+ l1d_cfg_err = LIB_CACHE_SUCCESS;
+ printf("Original L1D SRAM size is: %d\n", l1D_SRAM_size_orig);
+ printf("Required L1D SRAM size is: %d\n", smem_size_vfast);
+ if(l1D_SRAM_size_orig < smem_size_vfast) { /* configure L1D if needs more SRAM */
+ #pragma omp parallel
+ {
+ l1d_cfg_err = lib_L1D_config_SRAM(smem_size_vfast);
+ }
+ }
+
+ #pragma omp parallel
+ {
+ tid = omp_get_thread_num();
+ printf("New L1D SRAM size from thread %d is: %d\n", tid, lib_get_L1D_SRAM_size());
+ }
+
+ /* Configure L2 if necessary */
+ l2_SRAM_size_orig = lib_get_L2_SRAM_size(); /* get current L2 SRAM size */
+ l2_cfg_err = LIB_CACHE_SUCCESS;
+ printf("Original L2 SRAM size is: %d\n", l2_SRAM_size_orig);
+ printf("Required L2 SRAM size is: %d\n", smem_size_fast);
+ if(l2_SRAM_size_orig < smem_size_fast) { /* configure L2 if needs more SRAM */
+ printf("Configuring L2 for each core:\n");
+ #pragma omp parallel
+ {
+ l2_cfg_err = lib_L2_config_SRAM(smem_size_fast);
+ }
+ }
+
+ if(l1d_cfg_err || l2_cfg_err) {
+ return(-3);
+ }
+
+ #pragma omp parallel
+ {
+ tid = omp_get_thread_num();
+ printf("New L2 SRAM size from thread %d is: %d\n", tid, lib_get_L2_SRAM_size());
+ }
+
+ /* get L1D and L2 SRAM base address */
+ l1d_SRAM_ptr = lib_get_L1D_SRAM_base();
+ //l2_SRAM_ptr = lib_get_L2_SRAM_base();
+
+ /* pass allocated memories for heap initialization */
+ return(tiCblasInit(l1d_SRAM_ptr, smem_size_vfast,
+ //l2_SRAM_ptr, smem_size_fast,
+ l2_buf, smem_size_fast,
+ msmc_buf, smem_size_med,
+ NULL, BLAS_L3_DDR_SIZE_ZERO));
+} /* config_mem_for_ticblas */
+
+/*==============================================================================
+ * This function reconfigures L1D and L2 after processing is finished
+ *============================================================================*/
+int reconfig_mem_after_ticblas()
+{
+ int l1d_cfg_err, l2_cfg_err;
+
+ /* configure L1D back */
+ l1d_cfg_err = LIB_CACHE_SUCCESS;
+ if(l1D_SRAM_size_orig!=lib_get_L1D_SRAM_size()) {
+ #pragma omp parallel
+ {
+ l1d_cfg_err = lib_L1D_config_SRAM(l1D_SRAM_size_orig);
+ }
+ }
+
+ l2_cfg_err = LIB_CACHE_SUCCESS;
+ if(l2_SRAM_size_orig <= lib_get_L2_SRAM_size()) {
+ #pragma omp parallel
+ {
+ l2_cfg_err = lib_L2_config_SRAM(l2_SRAM_size_orig);
+ }
+ }
+
+ /* configure L1D and L2 back */
+ if(l1d_cfg_err || l2_cfg_err) {
+ return(-4);
+ }
+
+ printf("L1D SRAM size set to: %d\n", lib_get_L1D_SRAM_size());
+ printf("L2 SRAM size set to: %d\n", lib_get_L2_SRAM_size());
+
+ return(TICBLAS_SUCCESS);
+} /* reconfig_mem_after_ticblas */
diff --git a/examples/dsponly/dgemm_test/omp_config.cfg b/examples/dsponly/dgemm_test/omp_config.cfg
--- /dev/null
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2012-2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Import configuration for using FC EDMA */
+var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');
+RMAN.useDSKT2 = false;
+RMAN.persistentAllocFxn = "EdmaMgr_heap_alloc";
+RMAN.persistentFreeFxn = "EdmaMgr_heap_free";
+var EdmaMgr = xdc.useModule('ti.sdo.fc.edmamgr.EdmaMgr');
+
+/***************************/
+/* SECTION MAPPING */
+/***************************/
+var program = xdc.useModule('xdc.cfg.Program');
+
+program.sectMap[".args"] = new Program.SectionSpec();
+program.sectMap[".bss"] = new Program.SectionSpec();
+program.sectMap[".cinit"] = new Program.SectionSpec();
+program.sectMap[".cio"] = new Program.SectionSpec();
+program.sectMap[".const"] = new Program.SectionSpec();
+program.sectMap[".data"] = new Program.SectionSpec();
+program.sectMap[".far"] = new Program.SectionSpec();
+program.sectMap[".fardata"] = new Program.SectionSpec();
+program.sectMap[".neardata"] = new Program.SectionSpec();
+program.sectMap[".rodata"] = new Program.SectionSpec();
+program.sectMap[".stack"] = new Program.SectionSpec();
+program.sectMap[".switch"] = new Program.SectionSpec();
+program.sectMap[".sysmem"] = new Program.SectionSpec();
+program.sectMap[".text"] = new Program.SectionSpec();
+program.sectMap[".blas_msmc"] = new Program.SectionSpec();
+program.sectMap[".blas_l2"] = new Program.SectionSpec();
+
+// Must place these sections in core local memory
+program.sectMap[".args"].loadSegment = "L2SRAM";
+program.sectMap[".cio"].loadSegment = "L2SRAM";
+
+// Variables in the following data sections can potentially be 'shared' in
+// OpenMP. These sections must be placed in shared memory.
+program.sectMap[".bss"].loadSegment = "DDR3";
+program.sectMap[".cinit"].loadSegment = "DDR3";
+program.sectMap[".const"].loadSegment = "DDR3";
+program.sectMap[".data"].loadSegment = "DDR3";
+program.sectMap[".far"].loadSegment = "DDR3";
+program.sectMap[".fardata"].loadSegment = "DDR3";
+program.sectMap[".neardata"].loadSegment = "DDR3";
+program.sectMap[".rodata"].loadSegment = "DDR3";
+program.sectMap[".sysmem"].loadSegment = "DDR3";
+program.sectMap[".blas_l2"].loadSegment = "L2SRAM";
+program.sectMap[".blas_msmc"].loadSegment = "MSMCSRAM";
+
+// Code sections shared by cores - place in shared memory to avoid duplication
+//program.sectMap[".switch"].loadSegment = program.platform.codeMemory;
+//program.sectMap[".text"].loadSegment = program.platform.codeMemory;
+program.sectMap[".switch"].loadSegment = "DDR3";
+program.sectMap[".text"].loadSegment = "DDR3";
+
+// Size the default stack and place it in L2SRAM
+var deviceName = String(Program.cpu.deviceName);
+if (deviceName.search("DRA7XX") == -1) { program.stack = 0x10000; }
+else { program.stack = 0x8000; }
+program.sectMap[".stack"].loadSegment = "L2SRAM";
+
+// Since there are no arguments passed to main, set .args size to 0
+program.argSize = 0;
+
+
+/********************************/
+/* OPENMP RUNTIME CONFIGURATION */
+/********************************/
+
+// Include OMP runtime in the build
+var ompSettings = xdc.useModule("ti.runtime.openmp.Settings");
+
+// Set to true if the application uses or has dependencies on BIOS components
+ompSettings.usingRtsc = true;
+
+if (ompSettings.usingRtsc)
+{
+ /* Configure OpenMP for BIOS
+ * - OpenMP.configureCores(masterCoreId, numberofCoresInRuntime)
+ * Configures the id of the master core and the number of cores
+ * available to the runtime.
+ */
+
+ var OpenMP = xdc.useModule('ti.runtime.ompbios.OpenMP');
+
+ // Configure the index of the master core and the number of cores available
+ // to the runtime. The cores are contiguous.
+ OpenMP.masterCoreIdx = 0;
+
+ // Setup number of cores based on the device
+ if (deviceName.search("DRA7XX") != -1) { OpenMP.numCores = 2; }
+ else if (deviceName.search("6670") != -1) { OpenMP.numCores = 4; }
+ else if (deviceName.search("6657") != -1) { OpenMP.numCores = 2; }
+ else { OpenMP.numCores = 8; }
+
+ // Pull in memory ranges described in Platform.xdc to configure the runtime
+ var ddr3 = Program.cpu.memoryMap["DDR3"];
+ var ddr3_nc = Program.cpu.memoryMap["DDR3_NC"];
+ var msmc = Program.cpu.memoryMap["MSMCSRAM"];
+ var msmcNcVirt = Program.cpu.memoryMap["OMP_MSMC_NC_VIRT"];
+ var msmcNcPhy = Program.cpu.memoryMap["OMP_MSMC_NC_PHY"];
+
+ // Initialize the runtime with memory range information
+ if (deviceName.search("DRA7XX") == -1) {
+ OpenMP.msmcBase = msmc.base
+ OpenMP.msmcSize = msmc.len;
+
+ OpenMP.msmcNoCacheVirtualBase = msmcNcVirt.base;
+ OpenMP.msmcNoCacheVirtualSize = msmcNcVirt.len;
+
+ OpenMP.msmcNoCachePhysicalBase = msmcNcPhy.base;
+ }
+ else
+ {
+ OpenMP.allocateStackFromHeap = true;
+ OpenMP.allocateStackFromHeapSize = 0x010000;
+
+ OpenMP.hasMsmc = false;
+ OpenMP.ddrNoCacheBase = ddr3_nc.base;
+ OpenMP.ddrNoCacheSize = ddr3_nc.len;
+ }
+
+ OpenMP.ddrBase = ddr3.base;
+ OpenMP.ddrSize = ddr3.len;
+
+ // Configure memory allocation using HeapOMP
+ // HeapOMP handles
+ // - Memory allocation requests from BIOS components (core local memory)
+ // - Shared memory allocation by utilizing the IPC module to enable
+ // multiple cores to allocate memory out of the same heap - used by malloc
+ if (deviceName.search("DRA7XX") == -1) {
+ var HeapOMP = xdc.useModule('ti.runtime.ompbios.HeapOMP');
+
+ // Shared Region 0 must be initialized for IPC
+ var sharedRegionId = 0;
+
+ // Size of the core local heap
+ var localHeapSize = 0x8000;
+
+ // Size of the heap shared by all the cores
+ var sharedHeapSize = 0x08000000;
+
+ // Initialize a Shared Region & create a heap in the DDR3 memory region
+ var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
+ SharedRegion.setEntryMeta( sharedRegionId,
+ { base: ddr3.base,
+ len: sharedHeapSize,
+ ownerProcId: OpenMP.masterCoreIdx,
+ cacheEnable: true,
+ createHeap: true,
+ isValid: true,
+ name: "DDR3_SR0",
+ });
+
+ // Configure and setup HeapOMP
+ HeapOMP.configure(sharedRegionId, localHeapSize);
+ }
+ else
+ {
+ OpenMP.useIpcSharedHeap = false;
+ OpenMP.allocateLocalHeapSize = 0x8000
+ OpenMP.allocateSharedHeapSize = 0x00800000
+ }
+
+
+ var Startup = xdc.useModule('xdc.runtime.Startup');
+ Startup.lastFxns.$add('&__TI_omp_initialize_rtsc_mode');
+}
+else
+{
+ /* Size the heap. It must be placed in shared memory */
+ program.heap = sharedHeapSize;
+}
diff --git a/examples/dsponly/dgemm_test/omp_config_bm.cfg b/examples/dsponly/dgemm_test/omp_config_bm.cfg
--- /dev/null
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2012-2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Include OMP runtime in the build */
+var omp = xdc.useModule("ti.runtime.openmp.Settings");
+
+/* Set up section mappings */
+var program = xdc.useModule('xdc.cfg.Program');
+program.sectMap[".args"] = new Program.SectionSpec();
+program.sectMap[".bss"] = new Program.SectionSpec();
+program.sectMap[".cinit"] = new Program.SectionSpec();
+program.sectMap[".cio"] = new Program.SectionSpec();
+program.sectMap[".const"] = new Program.SectionSpec();
+program.sectMap[".data"] = new Program.SectionSpec();
+program.sectMap[".far"] = new Program.SectionSpec();
+program.sectMap[".fardata"] = new Program.SectionSpec();
+program.sectMap[".neardata"] = new Program.SectionSpec();
+program.sectMap[".rodata"] = new Program.SectionSpec();
+program.sectMap[".stack"] = new Program.SectionSpec();
+program.sectMap[".switch"] = new Program.SectionSpec();
+program.sectMap[".sysmem"] = new Program.SectionSpec();
+program.sectMap[".text"] = new Program.SectionSpec();
+
+/* Must place these sections in core local memory */
+program.sectMap[".args"].loadSegment = "L2SRAM";
+program.sectMap[".cio"].loadSegment = "L2SRAM";
+program.sectMap[".stack"].loadSegment = "L2SRAM";
+
+/* Must place these sections in shared memory - DDR3/MSMC */
+program.sectMap[".bss"].loadSegment = "DDR3";
+program.sectMap[".cinit"].loadSegment = "DDR3";
+program.sectMap[".const"].loadSegment = "DDR3";
+program.sectMap[".data"].loadSegment = "DDR3";
+program.sectMap[".far"].loadSegment = "DDR3";
+program.sectMap[".fardata"].loadSegment = "DDR3";
+program.sectMap[".neardata"].loadSegment = "DDR3";
+program.sectMap[".rodata"].loadSegment = "DDR3";
+program.sectMap[".sysmem"].loadSegment = "DDR3";
+program.sectMap[".switch"].loadSegment = program.platform.codeMemory;
+program.sectMap[".text"].loadSegment = program.platform.codeMemory;
+
+/* Size the default stack */
+var deviceName = String(Program.cpu.deviceName);
+if (deviceName.search("DRA7XX") == -1) { program.stack = 0x20000; }
+else { program.stack = 0x08000; }
+
+if (deviceName.search("DRA7XX") == -1) { program.heap = 0x08000000; }
+else { program.heap = 0x00800000; }
+
diff --git a/examples/dsponly/setup_env_rtos_yocto.sh b/examples/dsponly/setup_env_rtos_yocto.sh
--- /dev/null
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+export BIOS_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-sysbios-tree"
+export IPC_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-ipc-tree"
+export XDC_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-xdctools-tree"
+export OMP_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-omp-tree"
+export C6678_PDK_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-pdk-tree"
+export PDK_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-pdk-tree"
+export CGTROOT="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/x86_64-linux/usr/share/ti/cgt-c6x"
+export XDAIS_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-xdais-tree"
+export FC_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-framework-components-tree"
+export LIBARCH_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-libarch-tree"
+export EDMA3_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-edma3lld-tree"
+export LINALG_DIR="/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/share/ti/ti-linalg-tree"
+export PATH="/home/a0869574local/yocoto/tisdk-rtos/sources/oe-core/scripts:/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/x86_64-linux/usr/bin/arm-linux-gnueabi:/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/c667x-evm/usr/bin/crossscripts:/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/x86_64-linux/usr/sbin:/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/x86_64-linux/usr/bin:/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/x86_64-linux/sbin:/home/a0869574local/yocoto/tisdk-rtos/build/arago-tmp-external-linaro-toolchain/sysroots/x86_64-linux/bin:/home/a0869574local/gcc-linaro-4.9-2015.05-x86_64_arm-linux-gnueabihf/bin:/home/a0869574local/gcc-linaro-4.9-2015.05-x86_64_arm-linux-gnueabihf/bin:/home/a0869574local/yocoto/tisdk-rtos/sources/oe-core/scripts:/home/a0869574local/yocoto/tisdk-rtos/sources/bitbake/bin:/home/a0869574local/gcc-linaro-4.9-2015.05-x86_64_arm-linux-gnueabihf/bin:/home/a0869574local/yocoto/tisdk-rtos/sources/oe-core/scripts:/home/a0869574local/yocoto/tisdk-rtos/sources/bitbake/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games"