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raw | patch | inline | side by side (parent: d374425)
raw | patch | inline | side by side (parent: d374425)
author | Jianzhong Xu <xuj@ti.com> | |
Wed, 25 May 2016 18:49:01 +0000 (18:49 +0000) | ||
committer | Jianzhong Xu <xuj@ti.com> | |
Wed, 25 May 2016 18:49:01 +0000 (18:49 +0000) |
src/ti/linalg/blasblisacc/src/facade.c | patch | blob | history | |
src/ti/linalg/blasblisacc/src/ti_cblas_mem_config.c | patch | blob | history |
index 8f896eacaf667c66b619766ffaf867448b17fd1b..d1f0939cf40aeacdac3f3251b1b4963bf78a89e0 100644 (file)
* This file contains functions of the DSP OpenCL layer of ARM+DSP CBLAS library.
*============================================================================*/
-extern int bli_l3_mem_config(void *msmc_buf, size_t msmc_buf_size, void *ddr_buf, size_t ddr_buf_size,
+extern int blas_mem_config(void *msmc_buf, size_t msmc_buf_size, void *ddr_buf, size_t ddr_buf_size,
size_t *l1D_SRAM_size_orig, size_t *l2_SRAM_size_orig);
-extern int bli_l3_mem_reconfig(size_t l1D_SRAM_size_orig, size_t l2_SRAM_size_orig);
+extern int blas_mem_reconfig(size_t l1D_SRAM_size_orig, size_t l2_SRAM_size_orig);
void cblas_caxpy_facade(const int N, const void *alpha, const void *X, const int incX, void *Y, const int incY)
@@ -66,14 +66,14 @@ void cblas_cgemm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_TRANSPOSE
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_cgemm(Order, TransA, TransB, M, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_cgemv_facade(const enum CBLAS_ORDER order, const enum CBLAS_TRANSPOSE TransA, const int M, const int N, const void *alpha, const void *A, const int lda, const void *X, const int incX, const void *beta, void *Y, const int incY)
@@ -100,14 +100,14 @@ void cblas_chemm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_chemm(Order, Side, Uplo, M, N, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_chemv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const int N, const void *alpha, const void *A, const int lda, const void *X, const int incX, const void *beta, void *Y, const int incY)
@@ -129,28 +129,28 @@ void cblas_cher2k_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Upl
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_cher2k(Order, Uplo, Trans, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_cherk_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE Trans, const int N, const int K, const float alpha, const void *A, const int lda, const float beta, void *C, const int ldc, void *l3_buf, size_t l3_buf_size, void *ddr_buf, size_t ddr_buf_size, int *err_code)
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_cherk(Order, Uplo, Trans, N, K, alpha, A, lda, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_chpmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const int N, const void *alpha, const void *Ap, const void *X, const int incX, const void *beta, void *Y, const int incY)
@@ -192,42 +192,42 @@ void cblas_csymm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_csymm(Order, Side, Uplo, M, N, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_csyr2k_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE Trans, const int N, const int K, const void *alpha, const void *A, const int lda, const void *B, const int ldb, const void *beta, void *C, const int ldc, void *l3_buf, size_t l3_buf_size, void *ddr_buf, size_t ddr_buf_size, int *err_code)
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_csyr2k(Order, Uplo, Trans, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_csyrk_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE Trans, const int N, const int K, const void *alpha, const void *A, const int lda, const void *beta, void *C, const int ldc, void *l3_buf, size_t l3_buf_size, void *ddr_buf, size_t ddr_buf_size, int *err_code)
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_csyrk(Order, Uplo, Trans, N, K, alpha, A, lda, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_ctbmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const int K, const void *A, const int lda, void *X, const int incX)
@@ -254,14 +254,14 @@ void cblas_ctrmm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_ctrmm(Order, Side, Uplo, TransA, Diag, M, N, alpha, A, lda, B, ldb);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_ctrmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const void *A, const int lda, void *X, const int incX)
@@ -273,14 +273,14 @@ void cblas_ctrsm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_ctrsm(Order, Side, Uplo, TransA, Diag, M, N, alpha, A, lda, B, ldb);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_ctrsv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const void *A, const int lda, void *X, const int incX)
@@ -317,14 +317,14 @@ void cblas_dgemm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_TRANSPOSE
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_dgemm(Order, TransA, TransB, M, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_dgemv_facade(const enum CBLAS_ORDER order, const enum CBLAS_TRANSPOSE TransA, const int M, const int N, const double alpha, const double *A, const int lda, const double *X, const int incX, const double beta, double *Y, const int incY)
@@ -401,14 +401,14 @@ void cblas_dsymm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_dsymm(Order, Side, Uplo, M, N, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_dsymv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const int N, const double alpha, const double *A, const int lda, const double *X, const int incX, const double beta, double *Y, const int incY)
@@ -430,28 +430,28 @@ void cblas_dsyr2k_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Upl
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_dsyr2k(Order, Uplo, Trans, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_dsyrk_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE Trans, const int N, const int K, const double alpha, const double *A, const int lda, const double beta, double *C, const int ldc, void *l3_buf, size_t l3_buf_size, void *ddr_buf, size_t ddr_buf_size, int *err_code)
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_dsyrk(Order, Uplo, Trans, N, K, alpha, A, lda, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_dtbmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const int K, const double *A, const int lda, double *X, const int incX)
@@ -478,14 +478,14 @@ void cblas_dtrmm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_dtrmm(Order, Side, Uplo, TransA, Diag, M, N, alpha, A, lda, B, ldb);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_dtrmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const double *A, const int lda, double *X, const int incX)
@@ -497,14 +497,14 @@ void cblas_dtrsm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_dtrsm(Order, Side, Uplo, TransA, Diag, M, N, alpha, A, lda, B, ldb);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_dtrsv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const double *A, const int lda, double *X, const int incX)
@@ -586,14 +586,14 @@ void cblas_sgemm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_TRANSPOSE
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_sgemm(Order, TransA, TransB, M, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_sgemv_facade(const enum CBLAS_ORDER order, const enum CBLAS_TRANSPOSE TransA, const int M, const int N, const float alpha, const float *A, const int lda, const float *X, const int incX, const float beta, float *Y, const int incY)
@@ -665,14 +665,14 @@ void cblas_ssymm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_ssymm(Order, Side, Uplo, M, N, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_ssymv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const int N, const float alpha, const float *A, const int lda, const float *X, const int incX, const float beta, float *Y, const int incY)
@@ -694,28 +694,28 @@ void cblas_ssyr2k_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Upl
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_ssyr2k(Order, Uplo, Trans, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_ssyrk_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE Trans, const int N, const int K, const float alpha, const float *A, const int lda, const float beta, float *C, const int ldc, void *l3_buf, size_t l3_buf_size, void *ddr_buf, size_t ddr_buf_size, int *err_code)
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_ssyrk(Order, Uplo, Trans, N, K, alpha, A, lda, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_stbmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const int K, const float *A, const int lda, float *X, const int incX)
@@ -742,14 +742,14 @@ void cblas_strmm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_strmm(Order, Side, Uplo, TransA, Diag, M, N, alpha, A, lda, B, ldb);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_strmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const float *A, const int lda, float *X, const int incX)
@@ -761,14 +761,14 @@ void cblas_strsm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_strsm(Order, Side, Uplo, TransA, Diag, M, N, alpha, A, lda, B, ldb);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_strsv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const float *A, const int lda, float *X, const int incX)
@@ -815,14 +815,14 @@ void cblas_zgemm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_TRANSPOSE
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_zgemm(Order, TransA, TransB, M, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_zgemv_facade(const enum CBLAS_ORDER order, const enum CBLAS_TRANSPOSE TransA, const int M, const int N, const void *alpha, const void *A, const int lda, const void *X, const int incX, const void *beta, void *Y, const int incY)
@@ -849,14 +849,14 @@ void cblas_zhemm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_zhemm(Order, Side, Uplo, M, N, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_zhemv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const int N, const void *alpha, const void *A, const int lda, const void *X, const int incX, const void *beta, void *Y, const int incY)
@@ -878,28 +878,28 @@ void cblas_zher2k_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Upl
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_zher2k(Order, Uplo, Trans, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_zherk_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE Trans, const int N, const int K, const double alpha, const void *A, const int lda, const double beta, void *C, const int ldc, void *l3_buf, size_t l3_buf_size, void *ddr_buf, size_t ddr_buf_size, int *err_code)
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_zherk(Order, Uplo, Trans, N, K, alpha, A, lda, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_zhpmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const int N, const void *alpha, const void *Ap, const void *X, const int incX, const void *beta, void *Y, const int incY)
@@ -936,42 +936,42 @@ void cblas_zsymm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_zsymm(Order, Side, Uplo, M, N, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_zsyr2k_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE Trans, const int N, const int K, const void *alpha, const void *A, const int lda, const void *B, const int ldb, const void *beta, void *C, const int ldc, void *l3_buf, size_t l3_buf_size, void *ddr_buf, size_t ddr_buf_size, int *err_code)
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_zsyr2k(Order, Uplo, Trans, N, K, alpha, A, lda, B, ldb, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_zsyrk_facade(const enum CBLAS_ORDER Order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE Trans, const int N, const int K, const void *alpha, const void *A, const int lda, const void *beta, void *C, const int ldc, void *l3_buf, size_t l3_buf_size, void *ddr_buf, size_t ddr_buf_size, int *err_code)
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_zsyrk(Order, Uplo, Trans, N, K, alpha, A, lda, beta, C, ldc);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_ztbmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const int K, const void *A, const int lda, void *X, const int incX)
@@ -998,14 +998,14 @@ void cblas_ztrmm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_ztrmm(Order, Side, Uplo, TransA, Diag, M, N, alpha, A, lda, B, ldb);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_ztrmv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const void *A, const int lda, void *X, const int incX)
@@ -1017,14 +1017,14 @@ void cblas_ztrsm_facade(const enum CBLAS_ORDER Order, const enum CBLAS_SIDE Side
{
size_t l1D_SRAM_size_orig, l2_SRAM_size_orig;
- *err_code = bli_l3_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
+ *err_code = blas_mem_config(l3_buf, l3_buf_size, ddr_buf, ddr_buf_size, &l1D_SRAM_size_orig, &l2_SRAM_size_orig);
if(*err_code != TICBLAS_SUCCESS) {
return;
}
cblas_ztrsm(Order, Side, Uplo, TransA, Diag, M, N, alpha, A, lda, B, ldb);
- *err_code = bli_l3_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
+ *err_code = blas_mem_reconfig(l1D_SRAM_size_orig, l2_SRAM_size_orig);
}
void cblas_ztrsv_facade(const enum CBLAS_ORDER order, const enum CBLAS_UPLO Uplo, const enum CBLAS_TRANSPOSE TransA, const enum CBLAS_DIAG Diag, const int N, const void *A, const int lda, void *X, const int incX)
diff --git a/src/ti/linalg/blasblisacc/src/ti_cblas_mem_config.c b/src/ti/linalg/blasblisacc/src/ti_cblas_mem_config.c
index 54d6e276bb3b2dd50f1cf3fcac6400a1fbf90948..03ff98cce0d86b5ad9f7bd7d376064b25e95a5de 100644 (file)
* l1D_SRAM_size_orig - original L1D SRAM size
* l2_SRAM_size_orig - original L2 SRAM size
*============================================================================*/
-int bli_l3_mem_config(void *msmc_buf, size_t msmc_buf_size,
+int blas_mem_config(void *msmc_buf, size_t msmc_buf_size,
void *ddr_buf, size_t ddr_buf_size,
size_t *l1D_SRAM_size_orig, size_t *l2_SRAM_size_orig)
{
#ifdef TI_CBLAS_DEBUG
malloc_size = 0;
- printf("Memory buffers passed to bli_l3_mem_config are: MSMC base 0x%x, size %d, DDR base 0x%x, size%d.\n",
+ printf("Memory buffers passed to blas_mem_config are: MSMC base 0x%x, size %d, DDR base 0x%x, size%d.\n",
(unsigned int)msmc_buf, msmc_buf_size, (unsigned int) ddr_buf, ddr_buf_size);
printf("Before calling BLIS, malloc_size is %d.\n", malloc_size);
#endif
#endif
return(blas_ret_err_code);
-} /* bli_l3_mem_config */
+} /* blas_mem_config */
/*==============================================================================
* This function reconfigures L1D and L2 after processing is finished
*============================================================================*/
-int bli_l3_mem_reconfig(size_t l1D_SRAM_size_orig, size_t l2_SRAM_size_orig)
+int blas_mem_reconfig(size_t l1D_SRAM_size_orig, size_t l2_SRAM_size_orig)
{
int l1d_cfg_err, l2_cfg_err;
#endif
return(TICBLAS_SUCCESS);
-} /* bli_l3_mem_reconfig */
+} /* blas_mem_reconfig */
/* Nothing after this line */