From 15e204c4e5724cc946b10b73ea4b3d6bf92b1d1b Mon Sep 17 00:00:00 2001 From: Venkateswara Rao Mandela Date: Sat, 18 Nov 2017 12:41:53 +0530 Subject: [PATCH 1/1] initial version --- .gitignore | 5 + Makefile | 53 +++++++ README.md | 110 +++++++++++++++ common.h | 41 ++++++ linker.ld | 20 +++ main.c | 385 ++++++++++++++++++++++++++++++++++++++++++++++++++ manifest.html | 271 +++++++++++++++++++++++++++++++++++ mkimage.c | 140 ++++++++++++++++++ startup.s | 12 ++ umlo | Bin 0 -> 820 bytes 10 files changed, 1037 insertions(+) create mode 100644 .gitignore create mode 100644 Makefile create mode 100644 README.md create mode 100644 common.h create mode 100644 linker.ld create mode 100644 main.c create mode 100644 manifest.html create mode 100644 mkimage.c create mode 100644 startup.s create mode 100644 umlo diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..57ab95c --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +umlo.elf +umlo.bin +sym_map.txt +mkimage +disasm.txt diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..8530e45 --- /dev/null +++ b/Makefile @@ -0,0 +1,53 @@ +# +# SPDX-License-Identifier: BSD-3-Clause +# +CROSS_COMPILE=arm-none-eabi- +CC=$(CROSS_COMPILE)gcc +AS=$(CROSS_COMPILE)as +LD=$(CROSS_COMPILE)gcc +OBJCOPY=$(CROSS_COMPILE)objcopy + +# Build options for development +# CONFIG_UMLO_BASE=0x40300000 +# CFLAGS=-O0 -g + +# Build options for release +CONFIG_UMLO_BASE=0x40330000 +CFLAGS=-Os -fdata-sections -ffunction-sections -mcpu=cortex-a15 + +OUTPUTS=umlo.elf umlo.bin umlo + +DEBUG_OUTPUTS=sym_map.txt disasm.txt + +all: $(OUTPUTS) +COBJS=startup.o main.o + +# -Wl,--print-gc-sections Add this to debug pruned sections + +umlo.elf: linker.ld $(COBJS) + $(LD) -Wl,--defsym,CONFIG_UMLO_BASE=$(CONFIG_UMLO_BASE) \ + -T linker.ld $(COBJS) \ + -nostdlib -lgcc -o $@ -Wl,--gc-sections + du -b $@ + +umlo.bin: umlo.elf + $(OBJCOPY) -O binary $< $@ + du -b $@ + +umlo: umlo.bin mkimage + ./mkimage -a $(CONFIG_UMLO_BASE) $< $@ + du -b $@ + +mkimage: mkimage.c + gcc mkimage.c -o mkimage + +sym_map.txt: umlo.elf + readelf -a $< > $@ + +disasm.txt : umlo.elf + arm-linux-gnueabihf-objdump -S $< > $@ + +clean: + rm -f *.o + rm -f $(OUTPUTS) $(DEBUG_OUTPUTS) + rm -f mkimage diff --git a/README.md b/README.md new file mode 100644 index 0000000..8605d78 --- /dev/null +++ b/README.md @@ -0,0 +1,110 @@ +# Purpose + +On DRA7xx, Boot ROM copies the first stage boot loader(MLO/SPL) from +QSPI at a conservative speed of 11 MBps. A 120 KB binary takes around +11 ms to be copied from QSPI into OCMC. Usually this is not an +issue. However there are usecases(e.g. CAN response) where we need to +have a specific functionality available in less than 100 ms. In such +usecases, the time spent in ROM copy forms a significant portion (10%) +of the usecase time. The micro bootloader(`umlo`) built in this +project speeds up this copy. + +`umlo` first sets up the QSPI interface to the maximum speed possible +on DRA7xx i.e. 76.8 MHz interface clock, Quad Mode and Mode 0 +operation. Then `umlo` copies the `MLO` to the execution address in +OCMC and jumps to it. + +With this change, we see the time taken to enter a 120 KB MLO reduce +from 24.5 ms to 19 ms, a saving of 5.5 ms. + +Please refer to manifest.html for license information. + +# Build Instructions + +This tool is compiled and tested with `gcc-arm-none-eabi-4_9-2015q3`. +However any baremetal compiler supporting Cortex A15 should work. +Please make sure that you have the toolchain installed and have +`arm-none-eabi-gcc` in the path. + +Run `make` to produce the required binaries. + +If you are modifiying the toolchain, please ensure that the `CROSS_COMPILE` +option is set correctly in the Makefile. + +# Flashing instructions + +1. Flash the output file `umlo` to offset 0x0 in QSPI. + +2. Flash the actual MLO from your normal build process to offset + 0x10000 (64 KB). + +Nothing else needs to change. + +Reboot the EVM in QSPI4 boot mode. `umlo` boots and reads the actual +MLO from offset 0x10000 into OCMC and jumps to it. You will not see +any difference in execution except a slight speed up in reading MLO. + +For information on measuring time to enter MLO, please see [1] +in references. + +## Undoing the changes + +If you suspect a problem is being introduced due to `umlo`, you can +remove it by erasing the first 64 KB of QSPI. This will cause +Boot ROM to jump to your MLO. + +# Development Notes + +1. We used the peripheral boot feature of the DRA7xx Boot ROM heavily for +testing `umlo` during development. If you are customizing `umlo`, +please see [2] and [3] in references on how to use perhipheral boot +for debugging. + +2. The `Makefile` has two sets of build options, one for development + and another for release. Please switch to the development build + options when debugging. + +3. The file `main.c` contains an infinite loop function + `wait_for_debugger()`. You can call this function at the point + where you want to halt execution in code and single step via CCS + from that point. + + +# Caveats + +1. `umlo` expects that the first 512 bytes of the acutal MLO is the CH Header + and skips it. This is the case when MLO is produced from building U-Boot. + Please modify the code in `main.c` if this assumption is not true for the + `MLO` from your build. + +2. `umlo` does not do any SPI flash specific configuration. `umlo` + expects that the SPI flash has quad read mode enabled. It has only + been tested on TI EVM's which have a Spansion flash device. + +3. `umlo` is loaded to address 0x40330000 to avoid any overlap with the actual + MLO. Please modify this address in the `Makefile` if the actual MLO runtime + locations overlap with 0x40330000. + + CONFIG_UMLO_BASE=0x40300000 + +# Support + +For support, please post any questions to + + + +# References + +1. Linux Boot Time Optimizations on DRA7xx devices + + + +2. Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices + + + +3. DRA7xx Bootswitch - Utility for Peripheral boot + + + +4. Please see the chapter "Initialization" in the Device TRM. diff --git a/common.h b/common.h new file mode 100644 index 0000000..14d0ce9 --- /dev/null +++ b/common.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2017 + * Texas Instruments Incorporated, + * + * Venkateswara Rao Mandela + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __COMMON_H +#define __COMMON_H +#include + +typedef uint32_t u32; +typedef uint16_t u16; +typedef int16_t s16; +typedef uint8_t u8; + +#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) +#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) +#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) +#define FLD_MOD(orig, val, start, end) (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) + +static inline u32 reg_read32(u32 addr) { + u32 reg; + reg = *((volatile u32 *) addr); + return reg; +} + +static inline void reg_write32(u32 addr, u32 val) { + *((volatile u32 *) addr) = val; +} + +static inline u16 reg_read16(u32 addr) { + u16 reg; + reg = *((volatile u16 *) addr); + return reg; +} + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#endif diff --git a/linker.ld b/linker.ld new file mode 100644 index 0000000..d21a8fb --- /dev/null +++ b/linker.ld @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2017 + * Texas Instruments Incorporated, + * + * Venkateswara Rao Mandela + * + * SPDX-License-Identifier: BSD-3-Clause + */ +ENTRY(_Reset) +SECTIONS +{ + . = CONFIG_UMLO_BASE; + .startup . : { startup.o(.text) } + .text : { *(.text) } + .data : { *(.data) } + .bss : { *(.bss COMMON) } + . = ALIGN(8); + . = . + 0x1000; /* 4kB of stack memory */ + stack_top = .; +} diff --git a/main.c b/main.c new file mode 100644 index 0000000..8bf140b --- /dev/null +++ b/main.c @@ -0,0 +1,385 @@ +/* + * (C) Copyright 2017 + * Texas Instruments Incorporated, + * + * Venkateswara Rao Mandela + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "common.h" + +typedef void __attribute__((noreturn)) (*mlo_func_proto)(uint32_t *); + +#define COUNTER32K_CR (0x4AE04030) +#define QSPI_MMAP_BASE (0x5C000000) +#define CM_L3MAIN1_TPCC_CLKCTRL (0x4A008770) +#define CM_L3MAIN1_TPTC1_CLKCTRL (0x4A008778) +#define CM_L3MAIN1_TPTC2_CLKCTRL (0x4A008780) +#define CM_L4PER2_QSPI_CLKCTRL (0x4A009838) +#define CTRL_CORE_CONTROL_IO_2 (0x4A002558) +#define EDMA_BASE (0x43300000) +#define EDMA_PARAM_0 (0x43304000) +#define EDMA_TPCC_ESR (0x43301010) +#define EDMA_TPCC_EESR (0x43301030) +#define EDMA_TPCC_IPR (0x43301068) +#define EDMA_TPCC_ICR (0x43301070) + +#define QSPI_CMD_READ_QUAD (0x6c << 0) +#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8) +#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10) +#define QSPI_SETUP0_READ_QUAD (0x3 << 12) +#define QSPI_CMD_WRITE (0x12 << 16) +#define QSPI_NUM_DUMMY_BITS (0x0 << 24) +#define QSPI_SPI_CLOCK_CNTRL_REG (0x4B300040) +#define QSPI_SPI_DC_REG (0x4B300044) +#define QSPI_SPI_STATUS_REG (0x4B30004C) +#define QSPI_SPI_SETUP0_REG (0x4B300054) +#define QSPI_SPI_SWITCH_REG (0x4B300064) +#define QSPI_SPI_CMD_REG (0x4B300048) + +#define CTRL_CORE_PAD_GPMC_A13 (0x4A003474) +#define CTRL_CORE_PAD_GPMC_A14 (0x4A003478) +#define CTRL_CORE_PAD_GPMC_A15 (0x4A00347C) +#define CTRL_CORE_PAD_GPMC_A16 (0x4A003480) +#define CTRL_CORE_PAD_GPMC_A17 (0x4A003484) +#define CTRL_CORE_PAD_GPMC_A18 (0x4A003488) +#define CTRL_CORE_PAD_GPMC_CS2 (0x4A0034B8) + + +#define CM_DIV_H13_DPLL_PER (0x4A008160) + +struct edma_param_entry { + /** OPT field of PaRAM Set */ + u32 opt; + + /** + * @brief Starting byte address of Source + * For FIFO mode, src_addr must be a 256-bit aligned address. + */ + u32 src_addr; + + /** + * @brief Number of bytes in each Array (ACNT) + */ + u16 a_cnt; + + /** + * @brief Number of Arrays in each Frame (BCNT) + */ + u16 b_cnt; + + /** + * @brief Starting byte address of destination + * For FIFO mode, dest_addr must be a 256-bit aligned address. + * i.e. 5 LSBs should be 0. + */ + u32 dest_addr; + + /** + * @brief Index between consec. arrays of a Source Frame (SRCBIDX) + */ + s16 src_bidx; + + /** + * @brief Index between consec. arrays of a Destination Frame (DSTBIDX) + */ + s16 dest_bidx; + + /** + * @brief Address for linking (AutoReloading of a PaRAM Set) + * This must point to a valid aligned 32-byte PaRAM set + * A value of 0xFFFF means no linking + */ + u16 link_addr; + + /** + * @brief Reload value of the numArrInFrame (BCNT) + * Relevant only for A-sync transfers + */ + u16 b_cnt_reload; + + /** + * @brief Index between consecutive frames of a Source Block (SRCCIDX) + */ + s16 src_cidx; + + /** + * @brief Index between consecutive frames of a Dest Block (DSTCIDX) + */ + s16 dest_cidx; + + /** + * @brief Number of Frames in a block (CCNT) + */ + u16 c_cnt; + + /** + * @brief reserved member. + */ + u16 rsv; +} __packed; +u32 edma_clkctrl[2] = { + CM_L3MAIN1_TPTC1_CLKCTRL, + CM_L3MAIN1_TPTC2_CLKCTRL, +}; + +volatile int ccs_dbg_flag = 1; +void wait_for_debugger(void) +{ + ccs_dbg_flag = 1; + while (ccs_dbg_flag == 1) { + asm(" NOP"); + } + return; +} + +static u32 read_fast_counter(void) +{ + u32 reg_val = (u32) reg_read16(COUNTER32K_CR); + reg_val |= (u32)(reg_read16(COUNTER32K_CR+2) << 16); + return reg_val; +} + +static void wait_qspi_idle(void) +{ + u32 addr = QSPI_SPI_STATUS_REG; + u32 val, reg; + + do { + reg = reg_read32(addr); + val = FLD_GET(reg, 0, 0); + } while (val != 0); +} + +u32 pinmux[7] = { + CTRL_CORE_PAD_GPMC_A13, + CTRL_CORE_PAD_GPMC_A14, + CTRL_CORE_PAD_GPMC_A15, + CTRL_CORE_PAD_GPMC_A16, + CTRL_CORE_PAD_GPMC_A17, + CTRL_CORE_PAD_GPMC_A18, + CTRL_CORE_PAD_GPMC_CS2, +}; +void set_qspi_pinmux(void) +{ + u32 i = 0; + + /* Match pinmux settings from ROM */ + for (i = 0; i < 7; i++) { + reg_write32(pinmux[i], 0x40001); + } + reg_write32(pinmux[6], 0x60001); + +} +void set_qspi_clock(void) +{ + /* set qspi clock to 76.8 MHz */ + u32 addr = CM_L4PER2_QSPI_CLKCTRL; + u32 reg; + u32 t; + u32 div = 0; + + /* Reset QSPI CLKCTRL to default */ + reg_write32(addr, 0x0); + + /* Wait until QSPI is off */ + do { + reg = reg_read32(addr); + t = FLD_GET(reg, 17, 16); + } while (t != 3); + + + /* Set DPLL PER divider to 10 => output 76.8 MHz */ + reg = reg_read32(CM_DIV_H13_DPLL_PER); + reg= FLD_MOD(reg, 10, 5, 0); + reg_write32(CM_DIV_H13_DPLL_PER, reg); + + reg = 0x0; +#if 1 + /* Default Clock is from DPLL_PER H13*/ + reg = FLD_MOD(reg, 1, 24, 24); + /* Set divider to 1 for interface clock of 76.8 MHz */ + reg = FLD_MOD(reg, 0, 26, 25); +#else + /* Default Clock is from 128 MHz clock */ + reg = FLD_MOD(reg, 0, 24, 24); + /* Set divider to 1 to for interface clock of 64 MHz */ + reg = FLD_MOD(reg, 1, 26, 25); +#endif + /* Enable QSPI. */ + reg = FLD_MOD(reg, 2, 1, 0); + reg_write32(addr, reg); + do { + reg = reg_read32(addr); + t = FLD_GET(reg, 17, 16); + } while (t != 0); + + wait_qspi_idle(); + + /* turn off QSPI clock */ + reg = reg_read32(QSPI_SPI_CLOCK_CNTRL_REG); + reg = FLD_MOD(reg, 0, 31, 31); + reg_write32(QSPI_SPI_CLOCK_CNTRL_REG, reg); + + /* write divider */ + reg = FLD_MOD(reg, div, 15, 0); + reg_write32(QSPI_SPI_CLOCK_CNTRL_REG, reg); + + /* enable qspi clock */ + reg = FLD_MOD(reg, 1, 31, 31); + reg_write32(QSPI_SPI_CLOCK_CNTRL_REG, reg); + + /* Set the Mode for CS0 to mode 0 */ + addr = QSPI_SPI_DC_REG; + reg = reg_read32(addr); + reg = FLD_MOD(reg, 0, 4, 0); + reg_write32(addr, reg); + + return; +} + +void enable_qspi_mmap(void) +{ + u32 addr = CTRL_CORE_CONTROL_IO_2; + u32 reg; + + + /* Setup command for CS 0 */ + reg = (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES | + QSPI_SETUP0_NUM_D_BYTES_8_BITS | + QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE | + QSPI_NUM_DUMMY_BITS); + + reg_write32(QSPI_SPI_SETUP0_REG, reg); + + reg_write32(QSPI_SPI_SWITCH_REG, 0x1); + + reg = reg_read32(addr); + reg = FLD_MOD(reg, 1, 10, 8); + reg_write32(addr, reg); +} + +void disable_qspi_mmap(void) +{ + u32 addr = CTRL_CORE_CONTROL_IO_2; + u32 reg; + + reg = reg_read32(addr); + reg = FLD_MOD(reg, 0, 10, 8); + reg_write32(addr, reg); +} + +void enable_edma(void) +{ + u32 i = 0; + for(i = 0; i < 2; i++) { + u32 addr = edma_clkctrl[i]; + u32 reg; + u32 t; + + reg = reg_read32(addr); + reg = FLD_MOD(reg, 1, 1, 0); + + reg_write32(addr, reg); + + do { + reg = reg_read32(addr); + t = FLD_GET(reg, 17, 16); + } while (t != 0); + } + + /* Enable Channel 0 */ + reg_write32(EDMA_TPCC_EESR,0x1); + /* Clear any pending interrupts for channel 0 */ + reg_write32(EDMA_TPCC_ICR,0x1); +} + +void disable_edma(void) +{ + u32 i = 0; + + /* Clear any pending interrupts for channel 0 */ + reg_write32(EDMA_TPCC_ICR,0x1); + for(i = 0; i < 2; i++) { + u32 addr = edma_clkctrl[i]; + u32 reg; + u32 t; + + reg = reg_read32(addr); + reg = FLD_MOD(reg, 0, 1, 0); + + reg_write32(addr, reg); + + do { + reg = reg_read32(addr); + t = FLD_GET(reg, 17, 16); + } while (t != 3); + } +} + +void edma_copy(u32 src, u32 dst, u32 len) +{ + u32 reg = 0; + const u32 max_acnt = (1 << 4); + struct edma_param_entry *edma_param; + + edma_param = (struct edma_param_entry *)EDMA_PARAM_0; + edma_param->opt = 0; + edma_param->src_addr = ((u32) src); + edma_param->dest_addr = ((u32) dst); + edma_param->a_cnt = max_acnt; + edma_param->b_cnt = (len + max_acnt - 1) >> 4; + edma_param->c_cnt = 1; + edma_param->src_bidx = max_acnt; + edma_param->dest_bidx = max_acnt; + edma_param->src_cidx = 0; + edma_param->dest_cidx = 0; + edma_param->link_addr = 0xFFFF; + + reg = 0; + reg = FLD_MOD(reg, 1, 20, 20); /* TCINTEN */ + reg = FLD_MOD(reg, 1, 2, 2); /* ABSYNC */ + reg = FLD_MOD(reg, 1, 3, 3); /* STATIC */ + edma_param->opt = reg; + reg_write32(EDMA_TPCC_ESR,0x01); + do { + reg = reg_read32(EDMA_TPCC_IPR); + } while(FLD_GET(reg, 0 , 0) != 1); + /* Clear any pending interrupts for channel 0 */ + reg_write32(EDMA_TPCC_ICR,0x1); +} + +volatile u32 entry_cnt = 1; +volatile u32 exit_cnt = 1; +volatile u32 boot_addr_copy = 1; +void main_loop(uint32_t boot_addr) +{ + u32 len; + u32 entry_point_addr; + u32 src_addr; + u32 base; + mlo_func_proto mlo_entry; + + boot_addr_copy = boot_addr; + /* find entry time */ + entry_cnt = read_fast_counter(); + enable_edma(); + set_qspi_pinmux(); + set_qspi_clock(); + enable_qspi_mmap(); + + /* Find length */ + base = QSPI_MMAP_BASE + 0x10000 + 0x200; + len = *((uint32_t *)(base)); + entry_point_addr = *((uint32_t *)(base + 4)); + src_addr = base + 8; + edma_copy(src_addr, entry_point_addr, len - 8); + mlo_entry = (mlo_func_proto)(entry_point_addr); + + disable_qspi_mmap(); + disable_edma(); + exit_cnt = read_fast_counter(); + + /* Jump to the newly loaded image */ + mlo_entry((uint32_t *)boot_addr_copy); +} diff --git a/manifest.html b/manifest.html new file mode 100644 index 0000000..f596be5 --- /dev/null +++ b/manifest.html @@ -0,0 +1,271 @@ + + + + + + + Manifest File + + + + + +
+
+ +
+
+
+
+

+ +dra7xx-umlo Manifest + +

+ +

+ +11-22-2017 + +

+ + +

+ +Manifest ID - SRAS00004505 + +

+
+

Legend

+

(explanation of the fields in the Manifest Table below)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Software Name + +The name of the application or file +
+Version + +Version of the application or file +
+License Type + +Type of license(s) under which TI will be providing +software to the licensee (e.g. BSD-3-Clause, GPL-2.0, TI Text File License, TI +Commercial License). The license could be under Commercial terms or Open Source. See Open Source Reference License Disclaimer in +the Disclaimers Section. Whenever possible, TI will use an SPDX Short Identifier for an Open Source +License. TI Commercial license terms are not usually included in the manifest and are conveyed through a variety +of means such as a clickwrap license upon install, +a signed license agreement and so forth. +
+Location + +The directory name and path on the media or a specific file where the Software is located. Typically fully qualified path names +are not used and instead the relevant top level directory of the application is given. +A notation often used in the manifests is [as installed]/directory/*. Note that the asterisk implies that all +files under that directory are licensed as the License Type field denotes. Any exceptions to this will +generally be denoted as [as installed]/directory/* except as noted below which means as shown in subsequent rows of +the manifest. +
+Delivered As + +This field will either be “Source”, “Binary” or “Source +and Binary” and is the primary form the content of the Software is delivered +in. If the Software is delivered in an archive format, this field +applies to the contents of the archive. If the word Limited is used +with Source, as in “Limited Source” or “Limited Source and Binary” then +only portions of the Source for the application are provided. +
+Modified by TI + +This field will either be “Yes” or “No”. A “Yes” means +TI has made changes to the Software. A “No” means TI has not made any +changes. Note: This field is not applicable for Software “Obtained +from” TI. +
+Obtained from + +This field specifies from where or from whom TI obtained +the Software. It may be a URL to an Open Source site, a 3rd +party licensor, or TI. See Links Disclaimer in the Disclaimers +Section. +
+
+

Disclaimers

+

Export Control Classification Number (ECCN)

+

Any use of ECCNs listed in the Manifest is at the user’s risk +and without recourse to TI. Your +company, as the exporter of record, is responsible for determining the +correct classification of any item at +the time of export. Any export classification by TI of Software is for +TI’s internal use only and shall not be construed as a representation +or warranty +regarding the proper export classification for such Software or whether +an export +license or other documentation is required for exporting such Software

+

Links in the Manifest

+

Any +links appearing on this Manifest +(for example in the “Obtained from” field) were verified at the time +the Manifest was created. TI makes no guarantee that any listed links +will +remain active in the future.

+

Open Source License References

+

Your company is responsible for confirming the +applicable license terms for any open source Software +listed in this Manifest that was not “Obtained from” TI. Any open +source license +specified in this Manifest for Software that was +not “Obtained from” TI is for TI’s internal use only and shall not be +construed as a representation or warranty regarding the proper open +source license terms +for such Software.

+
+

Export Information

+

ECCN for Software included in this release:

+Publicly Available +
+ + + + + +

+ dra7xx-umlo Manifest Table +

+ + +

+ + See the Legend above for a description of these columns. + +

+ +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Software NameVersionLicense TypeDelivered AsModified by TI
+ umlo + + 1.0 + + BSD-3-Clause + + Binary + + Yes + Location + [install-location]/umlo +
Obtained from + TI +
+ Rest of the source files + + 1.0 + + BSD-3-Clause + + Source + + Yes + Location + [install-location]/* +
Obtained from + TI +
+ +

+

+

+ +

+

Credits

+




+
+

Licenses

+

dra7xx-umlo Licenses




/* Copyright 2017 Texas Instruments Incorporated
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TI is a global semiconductor design and manufacturing company. Innovate + with 100,000+ analog ICs and embedded processors, along with software, tools + and the industry's largest sales/support staff.

+
+ \ No newline at end of file diff --git a/mkimage.c b/mkimage.c new file mode 100644 index 0000000..7025def --- /dev/null +++ b/mkimage.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2017 + * Texas Instruments Incorporated, + * + * Venkateswara Rao Mandela + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include +#define _BSD_SOURCE +#include + +void usage(char *str) { + printf("Usage is %s -a \n", + str); +} +void * read_file(char *filename, size_t *f_size) { + + FILE *fp; + void *mptr = NULL; + size_t file_size=1024; + size_t nread; + + + fp=fopen(filename,"rb"); + if(fp==NULL) { + printf("Could not open file %s\n\n",filename); + goto err_ret; + /* + } else { + printf("Loaded file %s\n\n",filename); + */ + } + fseek(fp,0,SEEK_END); + file_size = ftell(fp); + fseek(fp,0,SEEK_SET); + + /* + printf("%s found; size is %d bytes\n",filename,file_size); + */ + mptr = (void *)malloc(file_size); + assert(mptr!=NULL); + memset(mptr,0x00,file_size); + + nread = fread(mptr,sizeof(uint8_t),file_size,fp); + + if(nread != file_size){ + printf("file %s : partially read %lu/%lu\n", + filename, + nread, file_size); + } + + fclose(fp); + + *f_size = file_size; + err_ret: + return mptr; +} + +void print_bytes(void *ptr, uint32_t n) { + uint32_t i = 0; + uint8_t *p = (uint8_t *) ptr; + for (i = 0; i < n; i++) + printf("%02x ", p[i]); + printf("\n"); +} +/* + * Add an 8 byte header to the binary. + * + * first four bytes size of the image including the GP HEADER + * load address + */ +int main(int argc, char *argv[]) { + + uint32_t arg_cnt = 0; + uint32_t load_addr = 0; + uint32_t cnt = 0; + size_t inp_size; + void *iptr; + FILE *fout; + uint32_t out_val = 0; + + if (argc != 5) + usage(argv[0]); + + arg_cnt++; + if (strcmp(argv[arg_cnt],"-a") != 0) { + printf("load_addr should be first argument\n"); + usage(argv[0]); + exit(1); + } + arg_cnt++; + + cnt = sscanf(argv[arg_cnt],"%x", &load_addr); + if (cnt != 1) { + printf("unable to read load address in hex from %s\n", + argv[arg_cnt]); + usage(argv[0]); + exit(1); + } + arg_cnt++; + iptr = read_file(argv[arg_cnt], &inp_size); + if(iptr == NULL){ + printf("Could not read %s\n",argv[arg_cnt]); + usage(argv[0]); + exit(1); + } + + arg_cnt++; + fout = fopen(argv[arg_cnt], "wb"); + if (fout == NULL) { + printf("Could not open %s for output\n", argv[arg_cnt]); + usage(argv[0]); + exit(1); + } + + out_val = inp_size + 8; + print_bytes(&out_val,sizeof(out_val)); + cnt = fwrite(&out_val, sizeof(uint8_t), + sizeof(out_val), fout); + assert(cnt == 4); + + out_val = load_addr; + print_bytes(&out_val,sizeof(out_val)); + cnt = fwrite(&out_val, sizeof(uint8_t), + sizeof(out_val), fout); + assert(cnt == 4); + + cnt = fwrite(iptr, sizeof(uint8_t), + inp_size, fout); + assert(cnt == inp_size); + fclose(fout); + + free(iptr); + return 0; +} diff --git a/startup.s b/startup.s new file mode 100644 index 0000000..7000a55 --- /dev/null +++ b/startup.s @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2017 + * Texas Instruments Incorporated, + * + * Venkateswara Rao Mandela + * + * SPDX-License-Identifier: BSD-3-Clause + */ +.global _Reset +_Reset: + LDR sp, =stack_top +B main_loop diff --git a/umlo b/umlo new file mode 100644 index 0000000000000000000000000000000000000000..77c37d2d3fe7b2bd42a3148bd30f3a4b2597f49e GIT binary patch literal 820 zcmYjPziSgw9RJ>3w4nriZI>WoUt)#~im#->AO#PTL1KrJI0Vd)!68D24h|g(wz;B? z^#TQ_+~!)ULntnKtAj)TfL}>BlO6Ao`_N za8`jX$q|=m#Lkj`X(?~AKy6KQz<=WSW?uQ6L!6|?x8wWKm0fWy%8*6Z=};MeplfB1 zYvm!g%F(4mE&UgD+oID|d|Rk7`A^KhHe@HelH@mFZ^|KCw4B(k z7_wdXs$I;zi#ki%7v^ji28pkM+*SEaH&R}7L`~YKrcIzm>M2qDx`dua+cV@?;Q0do zJnT-@=Y@?>TN|G4R0oMJQ?vbGnMhL8=$+;KkHfzOKM9{ny=Moyuq#dKU}{6h6?A8$ ziTiW$!PHLU0-OvN1ui=&_q>C95UReJ#*E+WgRldVm<63AF$d@Q9cQqE*(_4iIqjOc zgLbk*b6=*f>EB1c8*(ry7K11!JQgC*XEKZomy@M1It9ieM1G(%>=^h2%=fvK_8~gvs?qIUG$nMG m%x=l*W^Jom#`)DcHFtqMU>`UH-T`A^_bq$?9*}uN3H|{z+*#TH literal 0 HcmV?d00001 -- 2.39.2