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raw | patch | inline | side by side (parent: 04da564)
| author | Pradeep Venkatasubbarao <pradeepv@ti.com> | |
| Tue, 3 Dec 2013 11:01:25 +0000 (16:31 +0530) | ||
| committer | Pradeep Venkatasubbarao <pradeepv@ti.com> | |
| Tue, 3 Dec 2013 11:01:25 +0000 (16:31 +0530) |
Now DSP can allocate upto 64MB.
Signed-off-by: Pradeep Venkatasubbarao <pradeepv@ti.com>
Signed-off-by: Pradeep Venkatasubbarao <pradeepv@ti.com>
diff --git a/Makefile b/Makefile
index a65ac9a8fb6712f87fc5768b51c12317a2edb017..46bf5b88105f2368d218129654dfe043fd99a754 100644 (file)
--- a/Makefile
+++ b/Makefile
BIOSVERSION ?= bios_6_35_02_45
IPCVERSION ?= ipc_3_10_00_08
CEVERSION ?= codec_engine_3_24_00_08
-#FCVERSION ?= framework_components_3_24_00_09
-FCVERSION ?= framework_components_3_24_02_14_eng
+FCVERSION ?= framework_components_3_24_02_15
XDAISVERSION ?= xdais_7_24_00_04
OSALVERSION ?= osal_1_24_00_09
# TI Compiler Settings
-export CGT_C66X_ELF_INSTALL_DIR ?= /opt/ti/TI_CGT_TI_C66X_7.2.3
+export C66XCGTOOLSPATH ?= /opt/ti/C6000CGT7.4.2
# Define where the sources are
DSPDCEMMSRC = $(shell pwd)
@echo ".\c"
@echo "done"
-omap5_config: unconfig
- @echo "Creating new config\c"
- @echo DSP_CONFIG = omap5_smp_config > bldcfg.mk
- @echo ".\c"
- @echo MYXDCARGS=\"profile=$(PROFILE) trace_level=$(TRACELEVEL) hw_type=OMAP5 hw_version=$(HWVERSION) BIOS_type=non-SMP\" >> bldcfg.mk
- @echo ".\c"
- @echo CHIP = OMAP5 >> bldcfg.mk
- @echo ".\c"
- @echo FORSMP = 0 >> bldcfg.mk
- @echo ".\c"
- @echo DSPBINNAME = "omap5-dsp.xe66x" >> bldcfg.mk
- @echo INTBINNAME = "dsp.xe66x" >> bldcfg.mk
- @echo ".\c"
- @echo "done"
-
clean: config
export XDCARGS=$(MYXDCARGS); \
$(XDCROOT)/xdc --jobs=$(JOBS) clean -PD $(DSPDCEMMSRC)/platform/ti/dce/baseimage/.
@echo "ERROR: IPCSRC not set. Exiting..."
@echo "For more info, use 'make help'"
@exit 1
-else ifeq ($(CGT_C66X_ELF_INSTALL_DIR),)
- @echo "ERROR: CGT_C66X_ELF_INSTALL_DIR not set. Exiting..."
+else ifeq ($(C66XCGTOOLSPATH),)
+ @echo "ERROR: C66XCGTOOLSPATH not set. Exiting..."
@echo "For more info, use 'make help'"
@exit 1
endif
dspbin: build
ifeq ($(FORSMP),0)
- $(CGT_C66X_ELF_INSTALL_DIR)/bin/strip6x $(DSPDCEMMSRC)/platform/ti/dce/baseimage/out/dsp/$(PROFILE)/$(INTBINNAME) -o=$(DSPBINNAME)
+ $(C66XCGTOOLSPATH)/bin/strip6x $(DSPDCEMMSRC)/platform/ti/dce/baseimage/out/dsp/$(PROFILE)/$(INTBINNAME) -o=$(DSPBINNAME)
else
@echo "***********Not yet implemented************"
endif
@echo "FC := $(FCPROD)"
@echo "CE := $(CEPROD)"
@echo "XDAIS := $(XDAISPROD)"
- @echo "CGT_C66X_ELF_INSTALL_DIR := $(CGT_C66X_ELF_INSTALL_DIR)"
+ @echo "C66XCGTOOLSPATH := $(C66XCGTOOLSPATH)"
@echo " "
sources:
@echo "Please export the following variables: "
@echo " 1. BIOSTOOLSROOT - Directory where all the BIOS tools are installed."
@echo " If not mentioned, picks up the default, /opt/ti"
- @echo " 2. CGT_C66X_ELF_INSTALL_DIR - DSP Code Generation Tools installation path"
+ @echo " 2. C66XCGTOOLSPATH - DSP Code Generation Tools installation path"
@echo " If not mentioned, tries the default install location, /opt/ti/TI_CGT_TI_ARM_5.0.1"
@echo " 3. IPCSRC - Absolute path of the $(IPCVERSION)"
@echo " 4. [Optional] - Any of the following variables can be defined to customize your build."
@echo " FCVERSION = $(FCPROD)"
@echo " XDAISVERSION = $(XDAISPROD)"
@echo " OSALVERSION = $(OSALPROD)"
- @echo " CGT_C66X_ELF_INSTALL_DIR = $(CGT_C66X_ELF_INSTALL_DIR)"
+ @echo " C66XCGTOOLSPATH = $(C66XCGTOOLSPATH)"
@echo " "
@echo "Use the appropriate make targets from the following: "
@echo " Configure Platform: "
diff --git a/build/config.bld b/build/config.bld
index 60ee3fb97050ab1d6eaaa07e3efb23aa41cf72b6..d459ec5e95bbd41590eb0fb72accacf13cf08b85 100644 (file)
--- a/build/config.bld
+++ b/build/config.bld
* --- External Memory ---
* Virtual Physical Size Comment
* ------------------------------------------------------------------------
- * 9500_0000 ????_???? 10_0000 ( ~1 MB) EXT_CODE
- * 9510_0000 ????_???? 10_0000 ( 1 MB) EXT_DATA
- * 9520_0000 ????_???? 30_0000 ( 3 MB) EXT_HEAP
+ * 9500_0000 ????_???? 20_0000 ( ~2 MB) EXT_CODE
+ * 9520_0000 ????_???? 20_0000 ( 2 MB) EXT_DATA
+ * 9540_0000 ????_???? 280_0000 ( 40 MB) EXT_HEAP
* 9F00_0000 9F00_0000 6_0000 ( 384 kB) TRACE_BUF
* 9F06_0000 9F06_0000 1_0000 ( 64 kB) EXC_DATA
* 9F07_0000 9F07_0000 2_0000 ( 128 kB) PM_DATA (Power mgmt)
*/
var evmDRA7XX_ExtMemMapDsp1 = {
- EXT_CODE: { name: "EXT_CODE", base: 0x95000000, len: 0x100000, space: "code", access: "RWX" },
- EXT_DATA: { name: "EXT_DATA", base: 0x95100000, len: 0x00100000, space: "data", access: "RW" },
- EXT_HEAP: { name: "EXT_HEAP", base: 0x95200000, len: 0x0300000, space: "data", access: "RW" },
+ EXT_CODE: { name: "EXT_CODE", base: 0x95000000, len: 0x200000, space: "code", access: "RWX" },
+ EXT_DATA: { name: "EXT_DATA", base: 0x95200000, len: 0x00200000, space: "data", access: "RW" },
+ EXT_HEAP: { name: "EXT_HEAP", base: 0x95400000, len: 0x02800000, space: "data", access: "RW" },
TRACE_BUF: { name: "TRACE_BUF", base: 0x9F000000, len: 0x00060000, space: "data", access: "RW" },
EXC_DATA: { name: "EXC_DATA", base: 0x9F060000, len: 0x00010000, space: "data", access: "RW" },
PM_DATA: { name: "PM_DATA", base: 0x9F070000, len: 0x00020000, space: "data", access: "RWX" }
* Setup for dsp target
************************************/
var dsp_tgt = xdc.useModule('ti.targets.elf.C66');
-dsp_tgt.rootDir = java.lang.System.getenv("CGT_C66X_ELF_INSTALL_DIR");
+dsp_tgt.rootDir = java.lang.System.getenv("C66XCGTOOLSPATH");
dsp_tgt.ccOpts.suffix += " --gcc -D___DSPBIOS___ -DDSP";
dsp_tgt.ccOpts.suffix += " -ms ";
//dsp_tgt.ccOpts.suffix += " -pden -pds=48 ";
HwVer = ES10;
var build_vayu = true;
print("Selected Vayu for ES10");
-
+
dsp_tgt.ccOpts.suffix += " -DBUILD_FOR_VAYU";
dsp_tgt.ccOpts.suffix += " -DVAYU_ES10";
dsp_tgt.platform = dsp_tgt.platforms[0];
-
+
}
-
+
/************************************
* Setup for WIN target
************************************/
diff --git a/platform/ti/dce/baseimage/custom_rsc_table_vayu_dsp.h b/platform/ti/dce/baseimage/custom_rsc_table_vayu_dsp.h
index c8891cf2648141390d303398bec10acf8be8c512..c28912722f433920a74e869b733b56c53e4c2e3c 100644 (file)
-/*\r
- * Copyright (c) 2013, Texas Instruments Incorporated\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- *\r
- * * Neither the name of Texas Instruments Incorporated nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
- \r
-/*\r
- * ======== custom_rsc_table_vayu_ipu.h ========\r
- *\r
- * Define the VAYU/DRA7xx custom resource table entries for all IPU cores. This will be\r
- * incorporated into corresponding base images, and used by the remoteproc\r
- * on the host-side to allocated/reserve resources.\r
- *\r
- */\r
-\r
-#ifndef __CUSTOM_RSC_TABLE_VAYU_DSP_H__\r
-#define __CUSTOM_RSC_TABLE_VAYU_DSP_H__\r
-\r
-#include <ti/ipc/remoteproc/rsc_types.h>\r
-\r
-/* DSP Memory Map */\r
-#define L4_DRA7XX_BASE 0x4A000000\r
-\r
-/* L4_CFG & L4_WKUP */\r
-#define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)\r
-#define DSP_PERIPHERAL_L4CFG 0x4A000000\r
-\r
-#define L4_PERIPHERAL_L4PER1 0x48000000\r
-#define DSP_PERIPHERAL_L4PER1 0x48000000\r
-\r
-#define L4_PERIPHERAL_L4PER2 0x48400000\r
-#define DSP_PERIPHERAL_L4PER2 0x48400000\r
-\r
-#define L4_PERIPHERAL_L4PER3 0x48800000\r
-#define DSP_PERIPHERAL_L4PER3 0x48800000\r
-\r
-#define L4_PERIPHERAL_L4EMU 0x54000000\r
-#define DSP_PERIPHERAL_L4EMU 0x54000000\r
-\r
-#define L3_PERIPHERAL_DMM 0x4E000000\r
-#define DSP_PERIPHERAL_DMM 0x4E000000\r
-\r
-\r
-#define L3_PERIPHERAL_ISS 0x52000000\r
-#define DSP_PERIPHERAL_ISS 0x52000000\r
-\r
-#define L3_TILER_MODE_0_1 0x60000000\r
-#define DSP_TILER_MODE_0_1 0x60000000\r
-\r
-#define L3_TILER_MODE_2 0x70000000\r
-#define DSP_TILER_MODE_2 0x70000000\r
-\r
-#define L3_TILER_MODE_3 0x78000000\r
-#define DSP_TILER_MODE_3 0x78000000\r
-\r
-#define DSP_MEM_TEXT 0x95000000\r
-#define DSP_MEM_IOBUFS 0x80000000\r
-#define DSP_MEM_DATA 0x95100000\r
-#define DSP_MEM_HEAP 0x95200000\r
-\r
-#define DSP_MEM_IPC_DATA 0x9F000000\r
-#define DSP_MEM_IPC_VRING 0xA0000000\r
-#define DSP_MEM_RPMSG_VRING0 0xA0000000\r
-#define DSP_MEM_RPMSG_VRING1 0xA0004000\r
-#define DSP_MEM_VRING_BUFS0 0xA0040000\r
-#define DSP_MEM_VRING_BUFS1 0xA0080000\r
-\r
-#define DSP_MEM_IPC_VRING_SIZE SZ_1M\r
-#define DSP_MEM_IPC_DATA_SIZE SZ_1M\r
-\r
-#define DSP_MEM_TEXT_SIZE SZ_1M\r
-\r
-#define DSP_MEM_DATA_SIZE SZ_1M\r
-#define DSP_MEM_HEAP_SIZE (SZ_1M * 3)\r
-#define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)\r
-\r
-/*\r
- * Assign fixed RAM addresses to facilitate a fixed MMU table.\r
- * PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together.\r
- */\r
-/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */\r
-\r
-#define PHYS_MEM_IPC_VRING 0x95000000\r
-#define PHYS_MEM_IOBUFS 0xBA300000\r
-\r
-/*\r
- * Sizes of the virtqueues (expressed in number of buffers supported,\r
- * and must be power of 2)\r
- */\r
-#define DSP_RPMSG_VQ0_SIZE 256\r
-#define DSP_RPMSG_VQ1_SIZE 256\r
-\r
-/* flip up bits whose indices represent features we support */\r
-#define RPMSG_DSP_C0_FEATURES 1\r
-\r
-struct my_resource_table {\r
- struct resource_table base;\r
-\r
- UInt32 offset[18]; /* Should match 'num' in actual definition */\r
-\r
- /* rpmsg vdev entry */\r
- struct fw_rsc_vdev rpmsg_vdev;\r
- struct fw_rsc_vdev_vring rpmsg_vring0;\r
- struct fw_rsc_vdev_vring rpmsg_vring1;\r
-\r
- /* text carveout entry */\r
- struct fw_rsc_carveout text_cout;\r
-\r
- /* data carveout entry */\r
- struct fw_rsc_carveout data_cout;\r
- /* heap carveout entry */\r
- struct fw_rsc_carveout heap_cout;\r
-\r
- /* ipcdata carveout entry */\r
- struct fw_rsc_carveout ipcdata_cout;\r
-\r
- /* trace entry */\r
- struct fw_rsc_trace trace;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem0;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem1;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem2;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem3;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem4;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem5;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem6;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem7;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem8;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem9;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem10;\r
-\r
- /* devmem entry */\r
- struct fw_rsc_devmem devmem11;\r
-};\r
-\r
-extern char ti_trace_SysMin_Module_State_0_outbuf__A;\r
-#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A\r
-\r
-#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")\r
-#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)\r
-\r
-struct my_resource_table ti_ipc_remoteproc_ResourceTable = {\r
- 1, /* we're the first version that implements this */\r
- 18, /* number of entries in the table */\r
- 0, 0, /* reserved, must be zero */\r
- /* offsets to entries */\r
- {\r
- offsetof(struct my_resource_table, rpmsg_vdev),\r
- offsetof(struct my_resource_table, text_cout),\r
- offsetof(struct my_resource_table, data_cout),\r
- offsetof(struct my_resource_table, heap_cout),\r
- offsetof(struct my_resource_table, ipcdata_cout),\r
- offsetof(struct my_resource_table, trace),\r
- offsetof(struct my_resource_table, devmem0),\r
- offsetof(struct my_resource_table, devmem1),\r
- offsetof(struct my_resource_table, devmem2),\r
- offsetof(struct my_resource_table, devmem3),\r
- offsetof(struct my_resource_table, devmem4),\r
- offsetof(struct my_resource_table, devmem5),\r
- offsetof(struct my_resource_table, devmem6),\r
- offsetof(struct my_resource_table, devmem7),\r
- offsetof(struct my_resource_table, devmem8),\r
- offsetof(struct my_resource_table, devmem9),\r
- offsetof(struct my_resource_table, devmem10),\r
- offsetof(struct my_resource_table, devmem11),\r
- },\r
-\r
- /* rpmsg vdev entry */\r
- {\r
- TYPE_VDEV, VIRTIO_ID_RPMSG, 0,\r
- RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },\r
- /* no config data */\r
- },\r
- /* the two vrings */\r
- { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },\r
- { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },\r
-\r
- {\r
- TYPE_CARVEOUT,\r
- DSP_MEM_TEXT, 0,\r
- DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",\r
- },\r
-\r
- {\r
- TYPE_CARVEOUT,\r
- DSP_MEM_DATA, 0,\r
- DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",\r
- },\r
-\r
- {\r
- TYPE_CARVEOUT,\r
- DSP_MEM_HEAP, 0,\r
- DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",\r
- },\r
-\r
- {\r
- TYPE_CARVEOUT,\r
- DSP_MEM_IPC_DATA, 0,\r
- DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",\r
- },\r
-\r
- {\r
- TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,\r
- DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,\r
- DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,\r
- SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_TILER_MODE_2, L3_TILER_MODE_2,\r
- SZ_128M, 0, 0, "DSP_TILER_MODE_2",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_TILER_MODE_3, L3_TILER_MODE_3,\r
- SZ_128M, 0, 0, "DSP_TILER_MODE_3",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,\r
- SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,\r
- SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,\r
- SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,\r
- SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,\r
- SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,\r
- SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",\r
- },\r
-\r
- {\r
- TYPE_DEVMEM,\r
- DSP_PERIPHERAL_ISS, L3_PERIPHERAL_ISS,\r
- SZ_256K, 0, 0, "DSP_PERIPHERAL_ISS",\r
- },\r
-};\r
-\r
-#endif /* __CUSTOM_RSC_TABLE_VAYU_DSP_H__ */\r
-\r
+/*
+ * Copyright (c) 2013, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * ======== custom_rsc_table_vayu_ipu.h ========
+ *
+ * Define the VAYU/DRA7xx custom resource table entries for all IPU cores. This will be
+ * incorporated into corresponding base images, and used by the remoteproc
+ * on the host-side to allocated/reserve resources.
+ *
+ */
+
+#ifndef __CUSTOM_RSC_TABLE_VAYU_DSP_H__
+#define __CUSTOM_RSC_TABLE_VAYU_DSP_H__
+
+#include <ti/ipc/remoteproc/rsc_types.h>
+
+/* DSP Memory Map */
+#define L4_DRA7XX_BASE 0x4A000000
+
+/* L4_CFG & L4_WKUP */
+#define L4_PERIPHERAL_L4CFG (L4_DRA7XX_BASE)
+#define DSP_PERIPHERAL_L4CFG 0x4A000000
+
+#define L4_PERIPHERAL_L4PER1 0x48000000
+#define DSP_PERIPHERAL_L4PER1 0x48000000
+
+#define L4_PERIPHERAL_L4PER2 0x48400000
+#define DSP_PERIPHERAL_L4PER2 0x48400000
+
+#define L4_PERIPHERAL_L4PER3 0x48800000
+#define DSP_PERIPHERAL_L4PER3 0x48800000
+
+#define L4_PERIPHERAL_L4EMU 0x54000000
+#define DSP_PERIPHERAL_L4EMU 0x54000000
+
+#define L3_PERIPHERAL_DMM 0x4E000000
+#define DSP_PERIPHERAL_DMM 0x4E000000
+
+
+#define L3_PERIPHERAL_ISS 0x52000000
+#define DSP_PERIPHERAL_ISS 0x52000000
+
+#define L3_TILER_MODE_0_1 0x60000000
+#define DSP_TILER_MODE_0_1 0x60000000
+
+#define L3_TILER_MODE_2 0x70000000
+#define DSP_TILER_MODE_2 0x70000000
+
+#define L3_TILER_MODE_3 0x78000000
+#define DSP_TILER_MODE_3 0x78000000
+
+#define DSP_MEM_TEXT 0x95000000
+#define DSP_MEM_IOBUFS 0x80000000
+#define DSP_MEM_DATA 0x95200000
+#define DSP_MEM_HEAP 0x95400000
+
+#define DSP_MEM_IPC_DATA 0x9F000000
+#define DSP_MEM_IPC_VRING 0xA0000000
+#define DSP_MEM_RPMSG_VRING0 0xA0000000
+#define DSP_MEM_RPMSG_VRING1 0xA0004000
+#define DSP_MEM_VRING_BUFS0 0xA0040000
+#define DSP_MEM_VRING_BUFS1 0xA0080000
+
+#define DSP_MEM_IPC_VRING_SIZE SZ_1M
+#define DSP_MEM_IPC_DATA_SIZE SZ_1M
+
+#define DSP_MEM_TEXT_SIZE (SZ_1M * 2)
+
+#define DSP_MEM_DATA_SIZE (SZ_1M * 2)
+#define DSP_MEM_HEAP_SIZE (SZ_1M * 40)
+#define DSP_MEM_IOBUFS_SIZE (SZ_1M * 90)
+
+/*
+ * Assign fixed RAM addresses to facilitate a fixed MMU table.
+ * PHYS_MEM_IPC_VRING & PHYS_MEM_IPC_DATA MUST be together.
+ */
+/* See CMA BASE addresses in Linux side: arch/arm/mach-omap2/remoteproc.c */
+
+#define PHYS_MEM_IPC_VRING 0x99800000
+#define PHYS_MEM_IOBUFS 0xBA300000
+
+/*
+ * Sizes of the virtqueues (expressed in number of buffers supported,
+ * and must be power of 2)
+ */
+#define DSP_RPMSG_VQ0_SIZE 256
+#define DSP_RPMSG_VQ1_SIZE 256
+
+/* flip up bits whose indices represent features we support */
+#define RPMSG_DSP_C0_FEATURES 1
+
+struct my_resource_table {
+ struct resource_table base;
+
+ UInt32 offset[18]; /* Should match 'num' in actual definition */
+
+ /* rpmsg vdev entry */
+ struct fw_rsc_vdev rpmsg_vdev;
+ struct fw_rsc_vdev_vring rpmsg_vring0;
+ struct fw_rsc_vdev_vring rpmsg_vring1;
+
+ /* text carveout entry */
+ struct fw_rsc_carveout text_cout;
+
+ /* data carveout entry */
+ struct fw_rsc_carveout data_cout;
+ /* heap carveout entry */
+ struct fw_rsc_carveout heap_cout;
+
+ /* ipcdata carveout entry */
+ struct fw_rsc_carveout ipcdata_cout;
+
+ /* trace entry */
+ struct fw_rsc_trace trace;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem0;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem1;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem2;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem3;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem4;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem5;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem6;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem7;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem8;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem9;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem10;
+
+ /* devmem entry */
+ struct fw_rsc_devmem devmem11;
+};
+
+extern char ti_trace_SysMin_Module_State_0_outbuf__A;
+#define TRACEBUFADDR (UInt32)&ti_trace_SysMin_Module_State_0_outbuf__A
+
+#pragma DATA_SECTION(ti_ipc_remoteproc_ResourceTable, ".resource_table")
+#pragma DATA_ALIGN(ti_ipc_remoteproc_ResourceTable, 4096)
+
+struct my_resource_table ti_ipc_remoteproc_ResourceTable = {
+ 1, /* we're the first version that implements this */
+ 18, /* number of entries in the table */
+ 0, 0, /* reserved, must be zero */
+ /* offsets to entries */
+ {
+ offsetof(struct my_resource_table, rpmsg_vdev),
+ offsetof(struct my_resource_table, text_cout),
+ offsetof(struct my_resource_table, data_cout),
+ offsetof(struct my_resource_table, heap_cout),
+ offsetof(struct my_resource_table, ipcdata_cout),
+ offsetof(struct my_resource_table, trace),
+ offsetof(struct my_resource_table, devmem0),
+ offsetof(struct my_resource_table, devmem1),
+ offsetof(struct my_resource_table, devmem2),
+ offsetof(struct my_resource_table, devmem3),
+ offsetof(struct my_resource_table, devmem4),
+ offsetof(struct my_resource_table, devmem5),
+ offsetof(struct my_resource_table, devmem6),
+ offsetof(struct my_resource_table, devmem7),
+ offsetof(struct my_resource_table, devmem8),
+ offsetof(struct my_resource_table, devmem9),
+ offsetof(struct my_resource_table, devmem10),
+ offsetof(struct my_resource_table, devmem11),
+ },
+
+ /* rpmsg vdev entry */
+ {
+ TYPE_VDEV, VIRTIO_ID_RPMSG, 0,
+ RPMSG_DSP_C0_FEATURES, 0, 0, 0, 2, { 0, 0 },
+ /* no config data */
+ },
+ /* the two vrings */
+ { DSP_MEM_RPMSG_VRING0, 4096, DSP_RPMSG_VQ0_SIZE, 1, 0 },
+ { DSP_MEM_RPMSG_VRING1, 4096, DSP_RPMSG_VQ1_SIZE, 2, 0 },
+
+ {
+ TYPE_CARVEOUT,
+ DSP_MEM_TEXT, 0,
+ DSP_MEM_TEXT_SIZE, 0, 0, "DSP_MEM_TEXT",
+ },
+
+ {
+ TYPE_CARVEOUT,
+ DSP_MEM_DATA, 0,
+ DSP_MEM_DATA_SIZE, 0, 0, "DSP_MEM_DATA",
+ },
+
+ {
+ TYPE_CARVEOUT,
+ DSP_MEM_HEAP, 0,
+ DSP_MEM_HEAP_SIZE, 0, 0, "DSP_MEM_HEAP",
+ },
+
+ {
+ TYPE_CARVEOUT,
+ DSP_MEM_IPC_DATA, 0,
+ DSP_MEM_IPC_DATA_SIZE, 0, 0, "DSP_MEM_IPC_DATA",
+ },
+
+ {
+ TYPE_TRACE, TRACEBUFADDR, 0x8000, 0, "trace:dsp",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_MEM_IPC_VRING, PHYS_MEM_IPC_VRING,
+ DSP_MEM_IPC_VRING_SIZE, 0, 0, "DSP_MEM_IPC_VRING",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_MEM_IOBUFS, PHYS_MEM_IOBUFS,
+ DSP_MEM_IOBUFS_SIZE, 0, 0, "DSP_MEM_IOBUFS",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_TILER_MODE_0_1, L3_TILER_MODE_0_1,
+ SZ_256M, 0, 0, "DSP_TILER_MODE_0_1",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_TILER_MODE_2, L3_TILER_MODE_2,
+ SZ_128M, 0, 0, "DSP_TILER_MODE_2",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_TILER_MODE_3, L3_TILER_MODE_3,
+ SZ_128M, 0, 0, "DSP_TILER_MODE_3",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_L4CFG, L4_PERIPHERAL_L4CFG,
+ SZ_16M, 0, 0, "DSP_PERIPHERAL_L4CFG",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_L4PER1, L4_PERIPHERAL_L4PER1,
+ SZ_2M, 0, 0, "DSP_PERIPHERAL_L4PER1",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_L4PER2, L4_PERIPHERAL_L4PER2,
+ SZ_4M, 0, 0, "DSP_PERIPHERAL_L4PER2",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_L4PER3, L4_PERIPHERAL_L4PER3,
+ SZ_8M, 0, 0, "DSP_PERIPHERAL_L4PER3",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_L4EMU, L4_PERIPHERAL_L4EMU,
+ SZ_16M, 0, 0, "DSP_PERIPHERAL_L4EMU",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_DMM, L3_PERIPHERAL_DMM,
+ SZ_1M, 0, 0, "DSP_PERIPHERAL_DMM",
+ },
+
+ {
+ TYPE_DEVMEM,
+ DSP_PERIPHERAL_ISS, L3_PERIPHERAL_ISS,
+ SZ_256K, 0, 0, "DSP_PERIPHERAL_ISS",
+ },
+};
+
+#endif /* __CUSTOM_RSC_TABLE_VAYU_DSP_H__ */
+
index c4e15445d0f91d16eb9c3482bcf61d0625a39f30..9669492c19607e54e53160846b739ac64f0161ce 100644 (file)
-/*\r
- * Copyright (c) 2011, Texas Instruments Incorporated\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- *\r
- * * Neither the name of Texas Instruments Incorporated nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- */\r
-\r
-\r
-var hw_OMAP4 = 0;\r
-var hw_OMAP5 = 1;\r
-var hw_VAYU = 2;\r
-var VIRTIO = 0;\r
-var ZEBU = 0;\r
-var ES10 = 1;\r
-var ES20 = 2;\r
-\r
-var Program = xdc.useModule('xdc.cfg.Program');\r
-\r
-var cfgArgs = prog.build.cfgArgs;\r
-\r
-Program.global.HwType = cfgArgs.HwType;\r
-Program.global.enableSMP = cfgArgs.enableSMP;\r
-Program.global.HwVer = cfgArgs.HwVer;\r
-Program.global.coreName = "dsp";\r
-\r
-print("HwType = " + Program.global.HwType);\r
-\r
-if(Program.global.HwType == hw_VAYU)\r
-{\r
- // xdc.loadCapsule("ti/configs/vayu/IpcCommon.cfg.xs");\r
- xdc.includeFile("ti/configs/vayu/Dsp1.cfg");\r
- \r
-}\r
-else\r
-{\r
- // xdc.loadCapsule("ti/configs/omap54xx/IpcCommon.cfg.xs");\r
- xdc.includeFile("ti/configs/omap54xx/Dsp.cfg");\r
- xdc.includeFile("ti/configs/omap54xx/DspAmmu.cfg");\r
-}\r
-\r
-xdc.loadPackage('ti.ipc.mm');\r
-xdc.loadPackage('ti.ipc.ipcmgr');\r
-xdc.loadPackage('ti.srvmgr');\r
-xdc.loadPackage('ti.srvmgr.omaprpc');\r
-\r
-// Disabling default IpcCommon trace\r
-var Registry = xdc.useModule('xdc.runtime.Registry');\r
-var Diags = xdc.useModule('xdc.runtime.Diags');\r
-var Task = xdc.useModule('ti.sysbios.knl.Task');\r
-Task.common$.namedInstance = true;\r
-\r
-Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF;\r
-Registry.common$.diags_EXIT = Diags.RUNTIME_OFF;\r
-Registry.common$.diags_USER1 = Diags.RUNTIME_OFF;\r
-Registry.common$.diags_INFO = Diags.RUNTIME_OFF;\r
-Registry.common$.diags_LIFECYCLE = Diags.ALWAYS_ON;\r
-Registry.common$.diags_STATUS = Diags.ALWAYS_ON;\r
-Diags.setMaskEnabled = true;\r
-\r
-var Memory = xdc.useModule('xdc.runtime.Memory');\r
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');\r
-var GateHwi = xdc.useModule('ti.sysbios.gates.GateHwi');\r
-HeapMem.common$.gate = GateHwi.create();\r
-\r
-\r
-var heapMemParams = new HeapMem.Params;\r
-heapMemParams.size = 0x280000; // 2.5MB\r
-heapMemParams.sectionName = ".systemHeap";\r
-var heap0 = HeapMem.create(heapMemParams);\r
-Memory.defaultHeapInstance = heap0;\r
-Program.global.heap0 = heap0;\r
-\r
-/*\r
- * Setup memory map.\r
- */\r
-\r
-/* Mark heaps as NOINIT for optimizing boot-time */\r
-Program.sectMap[".systemHeap"] = new Program.SectionSpec();\r
-Program.sectMap[".systemHeap"].loadSegment = "EXT_HEAP";\r
-Program.sectMap[".systemHeap"].type = "NOINIT";\r
-\r
-\r
-/* ----------------------------- VERSION CONFIGURATION ---------------------*/\r
-var commonBld = xdc.loadCapsule("build/common.bld");\r
-commonBld.GetVersionTag();\r
-\r
-/*\r
- * ======== CODEC ENGINE configurations ========\r
- */\r
-\r
-var Global = xdc.useModule('ti.sdo.ce.osal.Global');\r
-Global.runtimeEnv = Global.DSPBIOS;\r
-\r
-xdc.useModule('ti.sdo.ce.global.Settings').profile = "debug";\r
-xdc.loadPackage('ti.sdo.ce.video').profile = "debug";\r
-xdc.loadPackage('ti.sdo.ce.video3').profile = "debug";\r
-xdc.loadPackage('ti.sdo.ce.alg').profile = "debug";\r
-\r
-var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');\r
-\r
-var ipcSettings = xdc.useModule('ti.sdo.ce.ipc.Settings');\r
-ipcSettings.ipc = xdc.useModule('ti.sdo.ce.ipc.bios.Ipc');\r
-// set to true to enable debugging of codec engine\r
-xdc.useModule('ti.sdo.ce.Settings').checked = true;\r
-\r
-/* Enable Memory Translation module that operates on the BIOS Resource Table */\r
-var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');\r
-Resource.customTable = true;\r
-\r
-// Load decoder/encoder APIs:\r
-var VIDDEC2 = xdc.useModule('ti.sdo.ce.video2.IVIDDEC2');\r
-var UNIVERSAL = xdc.useModule('ti.sdo.ce.universal.IUNIVERSAL');\r
-\r
-// load whatever codecs are available in the build\r
-var codecs = [];\r
-\r
-function loadCodec(pkg, name)\r
-{\r
- try {\r
- var codec = xdc.useModule(pkg);\r
- print('loading: ' + name);\r
- codecs.push({ name: name, mod: codec, local: true });\r
- } catch(e) {\r
- print('no package: ' + pkg);\r
- }\r
-}\r
-\r
-loadCodec('ti.sdo.codecs.universal.ce.UNIVERSAL', 'dsp_universalCopy');\r
-\r
-var engine = xdc.useModule('ti.sdo.ce.Engine');\r
-var myEngine = engine.create("dsp_vidsvr", codecs);\r
-\r
-xdc.useModule('ti.sysbios.knl.Task');\r
-var Task = xdc.useModule('ti.sysbios.knl.Task');\r
-Task.defaultStackSize = 12 * 0x400;\r
-\r
-/* ----------------------------- Configure BIOS--------------------------------*/\r
-\r
-BIOS = xdc.useModule('ti.sysbios.BIOS');\r
-BIOS.addUserStartupFunction('&IpcMgr_rpmsgStartup');\r
-\r
-BIOS.clockEnabled = true;\r
-BIOS.libType = BIOS.LibType_Custom;\r
-BIOS.smpEnabled = false;\r
-\r
-\r
-var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');\r
-if(Program.global.HwType == hw_OMAP5 || Program.global.HwType == hw_VAYU)\r
-{\r
- /*\r
- BIOS assumes that default frequency is 38.4 MHz. On OMAP5, SYS_CLK is used to source\r
- Hence it is clocked at 19.2 MHz.\r
-\r
- Locally setting the BIOS configuration for GPT and CTM for OMAP5 till actual changes are\r
- present in omap54xx/ipu/Platform.xdc\r
- */\r
- Timer.intFreq.hi = 0;\r
- Timer.intFreq.lo = 19200000;\r
- BIOS.cpuFreq.hi = 0;\r
- BIOS.cpuFreq.lo = 600000000;\r
-}\r
-\r
-Program.sectMap[".plt"] = "EXT_DATA";\r
-\r
-\r
-/* IPC 3.x is no longer providing version capability. If needed, then IPC needs to implement it. */\r
- /* Version module; this will produce a .version section with trees infos. Read\r
- * with "readelf -p .version <base_image>" */\r
-// xdc.useModule('ti.utils.Version');\r
-\r
+/*
+ * Copyright (c) 2011, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+var hw_OMAP4 = 0;
+var hw_OMAP5 = 1;
+var hw_VAYU = 2;
+var VIRTIO = 0;
+var ZEBU = 0;
+var ES10 = 1;
+var ES20 = 2;
+
+var Program = xdc.useModule('xdc.cfg.Program');
+
+var cfgArgs = prog.build.cfgArgs;
+
+Program.global.HwType = cfgArgs.HwType;
+Program.global.enableSMP = cfgArgs.enableSMP;
+Program.global.HwVer = cfgArgs.HwVer;
+Program.global.coreName = "dsp";
+
+print("HwType = " + Program.global.HwType);
+
+//*************************************
+var System = xdc.useModule('xdc.runtime.System');
+var SysMin = xdc.useModule('ti.trace.SysMin');
+System.SupportProxy = SysMin;
+SysMin.bufSize = 0x8000;
+
+var Memory = xdc.useModule('xdc.runtime.Memory');
+Memory.defaultHeapSize = 0x20000;
+
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+
+var Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
+Cache.setMarMeta(0xa0000000, 0x02000000, Cache.Mar_DISABLE);
+var L1cache = new Cache.Size();
+L1cache.l1dSize = Cache.L1Size_0K;
+
+xdc.loadPackage('ti.sdo.ipc.family.vayu');
+xdc.useModule('ti.sdo.ipc.family.vayu.InterruptDsp');
+xdc.loadPackage('ti.ipc.rpmsg');
+xdc.loadPackage('ti.ipc.family.vayu');
+
+/* Enable Memory Translation module that operates on the BIOS Resource Table */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.loadSegment = "EXT_CODE"
+
+/* Modules used in Power Management */
+xdc.loadPackage('ti.pm');
+
+/* Idle function that periodically flushes the unicache */
+var Idle = xdc.useModule('ti.sysbios.knl.Idle');
+Idle.addFunc('&VirtQueue_cacheWb');
+
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var List = xdc.useModule('ti.sdo.utils.List');
+
+xdc.useModule('ti.sysbios.xdcruntime.GateThreadSupport');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.common$.namedInstance = true;
+
+var Assert = xdc.useModule('xdc.runtime.Assert');
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var LoggerSys = xdc.useModule('xdc.runtime.LoggerSys');
+var LoggerSysParams = new LoggerSys.Params();
+
+/* Enable Logger: */
+Defaults.common$.logger = LoggerSys.create(LoggerSysParams);
+
+/* Enable runtime Diags_setMask() for non-XDC spec'd modules: */
+var Text = xdc.useModule('xdc.runtime.Text');
+Text.isLoaded = true;
+
+var Main = xdc.useModule('xdc.runtime.Main');
+Main.common$.diags_ASSERT = Diags.ALWAYS_ON;
+Main.common$.diags_INTERNAL = Diags.ALWAYS_ON;
+
+var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
+Hwi.enableException = true;
+
+/* -------------------------------- DSP ----------------------------------*/
+var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');
+MultiProc.setConfig("DSP1", ["HOST", "IPU2", "IPU1", "DSP2", "DSP1"]);
+
+/* --------------------------- TICK --------------------------------------*/
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+Clock.tickSource = Clock.TickSource_NULL;
+
+//**************************************
+xdc.loadPackage('ti.ipc.mm');
+xdc.loadPackage('ti.ipc.ipcmgr');
+xdc.loadPackage('ti.srvmgr');
+xdc.loadPackage('ti.srvmgr.omaprpc');
+
+// Disabling default IpcCommon trace
+var Registry = xdc.useModule('xdc.runtime.Registry');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.common$.namedInstance = true;
+
+Registry.common$.diags_ENTRY = Diags.RUNTIME_OFF;
+Registry.common$.diags_EXIT = Diags.RUNTIME_OFF;
+Registry.common$.diags_USER1 = Diags.RUNTIME_OFF;
+Registry.common$.diags_INFO = Diags.RUNTIME_OFF;
+Registry.common$.diags_LIFECYCLE = Diags.ALWAYS_ON;
+Registry.common$.diags_STATUS = Diags.ALWAYS_ON;
+Diags.setMaskEnabled = true;
+
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var GateHwi = xdc.useModule('ti.sysbios.gates.GateHwi');
+HeapMem.common$.gate = GateHwi.create();
+
+
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 0x2400000; // 36MB
+heapMemParams.sectionName = ".systemHeap";
+var heap0 = HeapMem.create(heapMemParams);
+Memory.defaultHeapInstance = heap0;
+Program.global.heap0 = heap0;
+
+/*
+ * Setup memory map.
+ */
+
+/* Mark heaps as NOINIT for optimizing boot-time */
+Program.sectMap[".systemHeap"] = new Program.SectionSpec();
+Program.sectMap[".systemHeap"].loadSegment = "EXT_HEAP";
+Program.sectMap[".systemHeap"].type = "NOINIT";
+Program.sectMap[".tracebuf"] = "TRACE_BUF";
+Program.sectMap[".errorbuf"] = "EXC_DATA";
+
+/* ----------------------------- VERSION CONFIGURATION ---------------------*/
+var commonBld = xdc.loadCapsule("build/common.bld");
+commonBld.GetVersionTag();
+
+/*
+ * ======== CODEC ENGINE configurations ========
+ */
+
+var Global = xdc.useModule('ti.sdo.ce.osal.Global');
+Global.runtimeEnv = Global.DSPBIOS;
+
+xdc.useModule('ti.sdo.ce.global.Settings').profile = "debug";
+xdc.loadPackage('ti.sdo.ce.video').profile = "debug";
+xdc.loadPackage('ti.sdo.ce.video3').profile = "debug";
+xdc.loadPackage('ti.sdo.ce.alg').profile = "debug";
+
+var HeapBufMP = xdc.useModule('ti.sdo.ipc.heaps.HeapBufMP');
+
+var ipcSettings = xdc.useModule('ti.sdo.ce.ipc.Settings');
+ipcSettings.ipc = xdc.useModule('ti.sdo.ce.ipc.bios.Ipc');
+// set to true to enable debugging of codec engine
+xdc.useModule('ti.sdo.ce.Settings').checked = true;
+
+/* Enable Memory Translation module that operates on the BIOS Resource Table */
+var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
+Resource.customTable = true;
+
+// Load decoder/encoder APIs:
+var VIDDEC2 = xdc.useModule('ti.sdo.ce.video2.IVIDDEC2');
+var UNIVERSAL = xdc.useModule('ti.sdo.ce.universal.IUNIVERSAL');
+
+// load whatever codecs are available in the build
+var codecs = [];
+
+function loadCodec(pkg, name)
+{
+ try {
+ var codec = xdc.useModule(pkg);
+ print('loading: ' + name);
+ codecs.push({ name: name, mod: codec, local: true });
+ } catch(e) {
+ print('no package: ' + pkg);
+ }
+}
+
+loadCodec('ti.sdo.codecs.universal.ce.UNIVERSAL', 'dsp_universalCopy');
+
+var engine = xdc.useModule('ti.sdo.ce.Engine');
+var myEngine = engine.create("dsp_vidsvr", codecs);
+
+xdc.useModule('ti.sysbios.knl.Task');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 12 * 0x400;
+
+/* ----------------------------- Configure BIOS--------------------------------*/
+
+BIOS = xdc.useModule('ti.sysbios.BIOS');
+BIOS.addUserStartupFunction('&IpcMgr_rpmsgStartup');
+
+BIOS.clockEnabled = true;
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.smpEnabled = false;
+
+
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+/*
+BIOS assumes that default frequency is 38.4 MHz. On OMAP5, SYS_CLK is used to source
+Hence it is clocked at 19.2 MHz.
+
+Locally setting the BIOS configuration for GPT and CTM for OMAP5 till actual changes are
+present in omap54xx/ipu/Platform.xdc
+*/
+Timer.intFreq.hi = 0;
+Timer.intFreq.lo = 19200000;
+BIOS.cpuFreq.hi = 0;
+BIOS.cpuFreq.lo = 600000000;
+
+Program.sectMap[".plt"] = "EXT_DATA";
+
+
+/* IPC 3.x is no longer providing version capability. If needed, then IPC needs to implement it. */
+ /* Version module; this will produce a .version section with trees infos. Read
+ * with "readelf -p .version <base_image>" */
+// xdc.useModule('ti.utils.Version');
+
index 0186203e3114b63ad10057d965862ae874332f2d..3694c3c3d78e6f8d7994de7ef65a91079004b9f2 100644 (file)
System_printf("\n\n **** DSPMM VERSION INFO **** \n\nCompile DATE %s TIME %s \n", __DATE__, __TIME__);\r
\r
System_printf("\n** DSPMM VERSION INFO END ** \n");\r
-\r
+#if 0\r
System_printf("Trace Buffer PA 0x%x Trace Level %d\\r
\nTrace Usage: level:[0-4: 0-no trace, 1-err, 2-debug, 3-info, 4-CE,FC,IPC traces] \n\n",\r
MEMUTILS_getPhysicalAddr((Ptr)(TRACEBUFADDR)), dce_debug);\r
+#endif\r
}\r
\r
int main(int argc, char * *argv)\r
index 0b7093d102663f9b9c85b13e8dbd68329686a91d..875b33e37134bf69e5e7f538d4e6e11aade3ac60 100644 (file)
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
*/\r
- \r
+\r
#include <stdlib.h>\r
#include <stdint.h>\r
#include <string.h>\r
\r
/* VIDDEC2 Decoder Server static function declarations */\r
static VIDDEC2_Handle viddec2_create(Engine_Handle engine, String name, VIDDEC2_Params *params);\r
-static int viddec2_reloc(VIDDEC2_Handle handle, uint8_t *ptr, uint32_t len); \r
-static int viddec2_control(VIDDEC2_Handle handle, VIDDEC2_Cmd id, VIDDEC2_DynamicParams *dynParams, \r
+static int viddec2_reloc(VIDDEC2_Handle handle, uint8_t *ptr, uint32_t len);\r
+static int viddec2_control(VIDDEC2_Handle handle, VIDDEC2_Cmd id, VIDDEC2_DynamicParams *dynParams,\r
VIDDEC2_Status *status );\r
static int viddec2_process(VIDDEC2_Handle handle, XDM1_BufDesc *inBufs,\r
XDM_BufDesc *outBufs, VIDDEC2_InArgs *inArgs, VIDDEC2_OutArgs *outArgs );\r
-static int viddec2_delete(VIDDEC2_Handle handle); \r
- \r
+static int viddec2_delete(VIDDEC2_Handle handle);\r
+\r
static struct {\r
CreateFxn create;\r
ControlFxn control;\r
},\r
};\r
\r
-\r
+#define UNIVERSAL_COPY_EXAMPLE\r
/* Static version string buffer.\r
* Note: codec version can be large. For example, h264vdec needs more than\r
* 58 characters, or the query will fail. */\r
* it gets populated in the future versions of framework components.\r
*\r
* Forced off mode during video decode/encode is not supported. */\r
-#if 0 \r
+#if 0\r
static void dce_suspend()\r
{\r
INFO("Preparing for suspend...");\r
}\r
#endif\r
\r
+#ifdef UNIVERSAL_COPY_EXAMPLE\r
static void get_universal_version(UNIVERSAL_Handle h, char *buffer, unsigned size)\r
{\r
UNIVERSAL_DynamicParams params =\r
@@ -180,20 +181,59 @@ static void get_universal_version(UNIVERSAL_Handle h, char *buffer, unsigned siz
ERROR("Unknown version Error = %d:: buffer = %p size = %d", s, buffer, size);\r
}\r
}\r
+#else\r
+static void get_viddec2_version(VIDDEC2_Handle h, char *buffer, unsigned size)\r
+{\r
+ VIDDEC2_DynamicParams params =\r
+ {\r
+ .size = sizeof(VIDDEC2_DynamicParams),\r
+ };\r
+\r
+ VIDDEC2_Status status =\r
+ {\r
+ .size = sizeof(VIDDEC2_Status),\r
+ .data =\r
+ {\r
+ .buf = (XDAS_Int8 *)buffer,\r
+ .bufSize = (XDAS_Int32)size,\r
+ },\r
+ };\r
+\r
+ XDAS_Int32 s;\r
+\r
+ memset(buffer, 0, size);\r
+ s = VIDDEC2_control(h, XDM_GETVERSION, ¶ms, &status);\r
+\r
+ if( s != VIDDEC2_EOK ) {\r
+ ERROR("Unknown version Error = %d:: buffer = %p size = %d", s, buffer, size);\r
+ }\r
+}\r
+\r
+#endif\r
\r
// VIDDEC2_create wrapper, to display version string in the trace.\r
static VIDDEC2_Handle viddec2_create(Engine_Handle engine, String name, VIDDEC2_Params *params)\r
{\r
+#ifdef UNIVERSAL_COPY_EXAMPLE\r
UNIVERSAL_Handle h;\r
\r
DEBUG(">> engine=%08x, name=%s, params=%p", engine, name, params);\r
\r
h = UNIVERSAL_create(engine, name, (IUNIVERSAL_Params*)params);\r
- \r
- get_universal_version(h, version_buffer, VERSION_SIZE);\r
- \r
- INFO("Created codec %s: version %s", name, version_buffer);\r
-\r
+ if(h){\r
+ get_universal_version(h, version_buffer, VERSION_SIZE);\r
+ INFO("Created codec %s: version %s", name, version_buffer);\r
+ }\r
+#else\r
+ VIDDEC2_Handle h;\r
+\r
+ h = VIDDEC2_create(engine, name, params);\r
+\r
+ if( h ) {\r
+ get_viddec2_version(h, version_buffer, VERSION_SIZE);\r
+ INFO("Created viddec2 %s: version %s", name, version_buffer);\r
+ }\r
+#endif\r
return ((VIDDEC2_Handle)h);\r
}\r
\r
\r
}\r
\r
-static int viddec2_control(VIDDEC2_Handle handle, VIDDEC2_Cmd id, VIDDEC2_DynamicParams *dynParams, \r
+static int viddec2_control(VIDDEC2_Handle handle, VIDDEC2_Cmd id, VIDDEC2_DynamicParams *dynParams,\r
VIDDEC2_Status *status )\r
{\r
int ret = 0;\r
+#ifdef UNIVERSAL_COPY_EXAMPLE\r
UNIVERSAL_DynamicParams udynParam;\r
UNIVERSAL_Status ustatus;\r
- \r
+\r
udynParam.size = sizeof(UNIVERSAL_DynamicParams);\r
ustatus.size = sizeof(UNIVERSAL_Status);\r
- //System_printf("command id is %d\n", id);\r
\r
if(id == XDM_GETVERSION){\r
ustatus.data.numBufs = 1;\r
ustatus.data.descs[0].buf = status->data.buf;\r
ustatus.data.descs[0].bufSize = status->data.bufSize;\r
}\r
- \r
- ret = UNIVERSAL_control((UNIVERSAL_Handle)handle, (UNIVERSAL_Cmd)id, \r
+\r
+ ret = UNIVERSAL_control((UNIVERSAL_Handle)handle, (UNIVERSAL_Cmd)id,\r
&udynParam, &ustatus);\r
\r
/*universal copy supports only XDM_GETVERSION cmd id */\r
- /*This is to return success to VIDDEC2 application in case of other cmd ids */ \r
+ /*This is to return success to VIDDEC2 application in case of other cmd ids */\r
if(ret == IUNIVERSAL_EFAIL)ret = IUNIVERSAL_EOK;\r
- \r
+#else\r
+ ret = VIDDEC2_control(handle, id, dynParams, status);\r
+#endif\r
return ret;\r
}\r
\r
static int viddec2_process(VIDDEC2_Handle handle, XDM1_BufDesc *inBufs,\r
XDM_BufDesc *outBufs, VIDDEC2_InArgs *inArgs, VIDDEC2_OutArgs *outArgs )\r
-{ \r
+{\r
int ret = 0;\r
+#ifdef UNIVERSAL_COPY_EXAMPLE\r
XDM1_BufDesc inBuf, outBuf;\r
UNIVERSAL_InArgs inArg;\r
UNIVERSAL_OutArgs outArg;\r
- \r
+\r
inArg.size = sizeof(UNIVERSAL_InArgs);\r
- outArg.size = sizeof(UNIVERSAL_OutArgs); \r
+ outArg.size = sizeof(UNIVERSAL_OutArgs);\r
outArg.extendedError = 0;\r
- //System_printf("Before VIDDEC2 process\n");\r
- \r
- //System_printf("outptr = 0x%x, size = %d\n",outBufs->bufs[0],outBufs->bufSizes[0]);\r
+\r
inBuf.numBufs = 1;\r
outBuf.numBufs = 1;\r
inBuf.descs[0].buf = inBufs->descs[0].buf;\r
inBuf.descs[0].bufSize = inBufs->descs[0].bufSize;\r
- \r
+\r
outBuf.descs[0].buf = outBufs->bufs[0];\r
outBuf.descs[0].bufSize = outBufs->bufSizes[0];\r
- \r
- ret = UNIVERSAL_process((UNIVERSAL_Handle)handle, &inBuf, &outBuf, NULL, \r
- &inArg, &outArg);\r
\r
- //System_printf("After VIDDEC2 process\n");\r
- return ret; \r
+ ret = UNIVERSAL_process((UNIVERSAL_Handle)handle, &inBuf, &outBuf, NULL,\r
+ &inArg, &outArg);\r
+#else\r
+ ret = VIDDEC2_process(handle, inBufs, outBufs, inArgs, outArgs);\r
+#endif\r
+ return ret;\r
}\r
\r
static int viddec2_delete(VIDDEC2_Handle handle)\r
{\r
- //System_printf("Deleting VIDDEC2\n"); \r
+#ifdef UNIVERSAL_COPY_EXAMPLE\r
UNIVERSAL_delete((UNIVERSAL_Handle)handle);\r
+#else\r
+ VIDDEC2_delete(handle);\r
+#endif\r
return 0;\r
}\r
- \r
+\r
\r
/*\r
* RPC message handlers\r
\r
FCSettings_init();\r
Diags_setMask(FCSETTINGS_MODNAME "+12345678LEXAIZFS");\r
- \r
+\r
CESettings_init();\r
Diags_setMask(CESETTINGS_MODNAME "+12345678LEXAIZFS");\r
- \r
+\r
/*\r
* Enable use of runtime Diags_setMask per module:\r
*\r
Diags_setMask("ti.ipc.rpmsg.RPMessage=EXLFS");\r
Diags_setMask("ti.ipc.rpmsg.VirtQueue=EXLFS");\r
}\r
- \r
+\r
CERuntime_init();\r
\r
if( !suspend_initialised ) {\r
dce_engine_open *engine_open_msg = (dce_engine_open *)payload[0].data;\r
Engine_Handle eng_handle = NULL;\r
Uint32 num_params = MmRpc_NUM_PARAMETERS(size);\r
- \r
+\r
DEBUG(">> engine_open");\r
if( num_params != 1 ) {\r
ERROR("Invalid number of params sent");\r
}\r
\r
dce_inv(engine_open_msg);\r
- \r
+\r
eng_handle = Engine_open(engine_open_msg->name, engine_open_msg->engine_attrs, &engine_open_msg->error_code);\r
DEBUG("<< engine=%08x, ec=%d", eng_handle, engine_open_msg->error_code);\r
- \r
+\r
dce_clean(engine_open_msg);\r
\r
return ((Int32)eng_handle);\r
ERROR("invalid number of params sent");\r
return (-1);\r
}\r
- \r
+\r
if(codec_id != OMAP_DCE_VIDDEC2){\r
ERROR("invalid codec id sent");\r
return (-1);\r
dce_inv(static_params);\r
\r
codec_handle = (void *)codec_fxns[codec_id].create(engine, codec_name, static_params);\r
- \r
+\r
DEBUG("<< codec_handle=%08x", codec_handle);\r
\r
dce_clean(static_params);\r
ERROR("invalid number of params sent");\r
return (-1);\r
}\r
- \r
+\r
if(codec_id != OMAP_DCE_VIDDEC2){\r
ERROR("invalid codec id sent");\r
return (-1);\r
dce_inv(status);\r
\r
ret = (uint32_t) codec_fxns[codec_id].control(codec_handle, cmd_id, dyn_params, status);\r
- \r
+\r
DEBUG("<< result=%d", ret);\r
\r
dce_clean(dyn_params);\r
ERROR("invalid number of params sent");\r
return (-1);\r
}\r
- \r
+\r
if(codec_id != OMAP_DCE_VIDDEC2){\r
ERROR("invalid codec id sent");\r
return (-1);\r
}\r
- \r
+\r
version_buf = (void *)(H2P((MemHeader *)((IVIDDEC2_Status *)status)->data.buf));\r
- \r
+\r
dce_inv(dyn_params);\r
dce_inv(status);\r
dce_inv(version_buf);\r
- \r
+\r
ret = (uint32_t) codec_fxns[codec_id].control(codec_handle, XDM_GETVERSION, dyn_params, status);\r
\r
DEBUG("<< result=%d", ret);\r
void *outBufptr = (void *)payload[6].data;\r
Int32 ret = 0;\r
void *outBufSize = NULL;\r
- \r
+\r
DEBUG(">> codec_process");\r
\r
if( num_params != 7 ) {\r
ERROR("invalid codec id sent");\r
return (-1);\r
}\r
- \r
+\r
outBufSize = (void *)(H2P((MemHeader *)((XDM_BufDesc *)outBufs)->bufSizes));\r
\r
dce_inv(inBufs);\r
dce_inv(outArgs);\r
dce_inv(outBufptr);\r
dce_inv(outBufSize);\r
- \r
+\r
DEBUG(">> codec=%p, inBufs=%p, outBufs=%p, inArgs=%p, outArgs=%p codec_id=%d",\r
codec, inBufs, outBufs, inArgs, outArgs, codec_id);\r
\r
ret = codec_fxns[codec_id].process((void *)codec, inBufs, outBufs, inArgs, outArgs);\r
- \r
+\r
\r
DEBUG("<< ret=%d extendedError=%08x", ret, ((VIDDEC3_OutArgs *)outArgs)->extendedError);\r
\r
ERROR("invalid number of params sent");\r
return (-1);\r
}\r
- \r
+\r
if(codec_id != OMAP_DCE_VIDDEC2){\r
ERROR("invalid codec id sent");\r
return (-1);\r
{\r
int err = 0;\r
dce_connect dce_connect_msg;\r
- \r
+\r
err = MmServiceMgr_init(); // MmServiceMgr_init() will always return MmServiceMgr_S_SUCCESS.\r
\r
// setup the RCM Server create params\r
\r
// Get the Service Manager handle\r
err = MmServiceMgr_register(SERVER_NAME, &rpc_Params, &dce_fxnSigTab, dce_SrvDelNotification);\r
- \r
+\r
if( err < 0 ) {\r
DEBUG("failed to start " SERVER_NAME " \n");\r
//err = -1;\r
params.instance->name = "dce-server";\r
params.priority = Thread_Priority_ABOVE_NORMAL;\r
Task_create(dce_main, ¶ms, NULL);\r
- \r
+\r
return (TRUE);\r
}\r
\r