1 /*
2 * armboot - Startup Code for ARM925 CPU-core
3 *
4 * Copyright (c) 2003 Texas Instruments
5 *
6 * ----- Adapted for OMAP1510 from ARM920 code ------
7 *
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
33 #include <asm-offsets.h>
34 #include <config.h>
35 #include <version.h>
37 /*
38 *************************************************************************
39 *
40 * Jump vector table as in table 3.1 in [1]
41 *
42 *************************************************************************
43 */
46 .globl _start
47 _start: b reset
48 ldr pc, _undefined_instruction
49 ldr pc, _software_interrupt
50 ldr pc, _prefetch_abort
51 ldr pc, _data_abort
52 ldr pc, _not_used
53 ldr pc, _irq
54 ldr pc, _fiq
56 _undefined_instruction: .word undefined_instruction
57 _software_interrupt: .word software_interrupt
58 _prefetch_abort: .word prefetch_abort
59 _data_abort: .word data_abort
60 _not_used: .word not_used
61 _irq: .word irq
62 _fiq: .word fiq
64 .balignl 16,0xdeadbeef
67 /*
68 *************************************************************************
69 *
70 * Startup Code (reset vector)
71 *
72 * do important init only if we don't start from memory!
73 * setup Memory and board specific bits prior to relocation.
74 * relocate armboot to ram
75 * setup stack
76 *
77 *************************************************************************
78 */
80 .globl _TEXT_BASE
81 _TEXT_BASE:
82 .word CONFIG_SYS_TEXT_BASE
84 /*
85 * These are defined in the board-specific linker script.
86 * Subtracting _start from them lets the linker put their
87 * relative position in the executable instead of leaving
88 * them null.
89 */
90 .globl _bss_start_ofs
91 _bss_start_ofs:
92 .word __bss_start - _start
94 .globl _bss_end_ofs
95 _bss_end_ofs:
96 .word __bss_end__ - _start
98 .globl _end_ofs
99 _end_ofs:
100 .word _end - _start
102 #ifdef CONFIG_USE_IRQ
103 /* IRQ stack memory (calculated at run-time) */
104 .globl IRQ_STACK_START
105 IRQ_STACK_START:
106 .word 0x0badc0de
108 /* IRQ stack memory (calculated at run-time) */
109 .globl FIQ_STACK_START
110 FIQ_STACK_START:
111 .word 0x0badc0de
112 #endif
114 /* IRQ stack memory (calculated at run-time) + 8 bytes */
115 .globl IRQ_STACK_START_IN
116 IRQ_STACK_START_IN:
117 .word 0x0badc0de
119 /*
120 * the actual reset code
121 */
123 reset:
124 /*
125 * set the cpu to SVC32 mode
126 */
127 mrs r0,cpsr
128 bic r0,r0,#0x1f
129 orr r0,r0,#0xd3
130 msr cpsr,r0
132 /*
133 * Set up 925T mode
134 */
135 mov r1, #0x81 /* Set ARM925T configuration. */
136 mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */
138 /*
139 * turn off the watchdog, unlock/diable sequence
140 */
141 mov r1, #0xF5
142 ldr r0, =WDTIM_MODE
143 strh r1, [r0]
144 mov r1, #0xA0
145 strh r1, [r0]
147 /*
148 * mask all IRQs by setting all bits in the INTMR - default
149 */
150 mov r1, #0xffffffff
151 ldr r0, =REG_IHL1_MIR
152 str r1, [r0]
153 ldr r0, =REG_IHL2_MIR
154 str r1, [r0]
156 /*
157 * wait for dpll to lock
158 */
159 ldr r0, =CK_DPLL1
160 mov r1, #0x10
161 strh r1, [r0]
162 poll1:
163 ldrh r1, [r0]
164 ands r1, r1, #0x01
165 beq poll1
167 /*
168 * we do sys-critical inits only at reboot,
169 * not when booting from ram!
170 */
171 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
172 bl cpu_init_crit
173 #endif
175 bl _main
177 /*------------------------------------------------------------------------------*/
179 /*
180 * void relocate_code (addr_sp, gd, addr_moni)
181 *
182 * This "function" does not return, instead it continues in RAM
183 * after relocating the monitor code.
184 *
185 */
186 .globl relocate_code
187 relocate_code:
188 mov r4, r0 /* save addr_sp */
189 mov r5, r1 /* save addr of gd */
190 mov r6, r2 /* save addr of destination */
192 adr r0, _start
193 cmp r0, r6
194 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
195 beq relocate_done /* skip relocation */
196 mov r1, r6 /* r1 <- scratch for copy_loop */
197 ldr r3, _bss_start_ofs
198 add r2, r0, r3 /* r2 <- source end address */
200 copy_loop:
201 ldmia r0!, {r9-r10} /* copy from source address [r0] */
202 stmia r1!, {r9-r10} /* copy to target address [r1] */
203 cmp r0, r2 /* until source end address [r2] */
204 blo copy_loop
206 #ifndef CONFIG_SPL_BUILD
207 /*
208 * fix .rel.dyn relocations
209 */
210 ldr r0, _TEXT_BASE /* r0 <- Text base */
211 sub r9, r6, r0 /* r9 <- relocation offset */
212 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
213 add r10, r10, r0 /* r10 <- sym table in FLASH */
214 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
215 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
216 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
217 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
218 fixloop:
219 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
220 add r0, r0, r9 /* r0 <- location to fix up in RAM */
221 ldr r1, [r2, #4]
222 and r7, r1, #0xff
223 cmp r7, #23 /* relative fixup? */
224 beq fixrel
225 cmp r7, #2 /* absolute fixup? */
226 beq fixabs
227 /* ignore unknown type of fixup */
228 b fixnext
229 fixabs:
230 /* absolute fix: set location to (offset) symbol value */
231 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
232 add r1, r10, r1 /* r1 <- address of symbol in table */
233 ldr r1, [r1, #4] /* r1 <- symbol value */
234 add r1, r1, r9 /* r1 <- relocated sym addr */
235 b fixnext
236 fixrel:
237 /* relative fix: increase location by offset */
238 ldr r1, [r0]
239 add r1, r1, r9
240 fixnext:
241 str r1, [r0]
242 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
243 cmp r2, r3
244 blo fixloop
245 #endif
247 relocate_done:
249 mov pc, lr
251 _rel_dyn_start_ofs:
252 .word __rel_dyn_start - _start
253 _rel_dyn_end_ofs:
254 .word __rel_dyn_end - _start
255 _dynsym_start_ofs:
256 .word __dynsym_start - _start
258 .globl c_runtime_cpu_setup
259 c_runtime_cpu_setup:
261 mov pc, lr
263 /*
264 *************************************************************************
265 *
266 * CPU_init_critical registers
267 *
268 * setup important registers
269 * setup memory timing
270 *
271 *************************************************************************
272 */
275 cpu_init_crit:
276 /*
277 * flush v4 I/D caches
278 */
279 mov r0, #0
280 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
281 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
283 /*
284 * disable MMU stuff and caches
285 */
286 mrc p15, 0, r0, c1, c0, 0
287 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
288 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
289 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
290 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
291 mcr p15, 0, r0, c1, c0, 0
293 /*
294 * Go setup Memory and board specific bits prior to relocation.
295 */
296 mov ip, lr /* perserve link reg across call */
297 bl lowlevel_init /* go setup pll,mux,memory */
298 mov lr, ip /* restore link */
299 mov pc, lr /* back to my caller */
300 /*
301 *************************************************************************
302 *
303 * Interrupt handling
304 *
305 *************************************************************************
306 */
308 @
309 @ IRQ stack frame.
310 @
311 #define S_FRAME_SIZE 72
313 #define S_OLD_R0 68
314 #define S_PSR 64
315 #define S_PC 60
316 #define S_LR 56
317 #define S_SP 52
319 #define S_IP 48
320 #define S_FP 44
321 #define S_R10 40
322 #define S_R9 36
323 #define S_R8 32
324 #define S_R7 28
325 #define S_R6 24
326 #define S_R5 20
327 #define S_R4 16
328 #define S_R3 12
329 #define S_R2 8
330 #define S_R1 4
331 #define S_R0 0
333 #define MODE_SVC 0x13
334 #define I_BIT 0x80
336 /*
337 * use bad_save_user_regs for abort/prefetch/undef/swi ...
338 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
339 */
341 .macro bad_save_user_regs
342 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack
343 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
345 ldr r2, IRQ_STACK_START_IN
346 ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs)
347 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
349 add r5, sp, #S_SP
350 mov r1, lr
351 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
352 mov r0, sp @ save current stack into r0 (param register)
353 .endm
355 .macro irq_save_user_regs
356 sub sp, sp, #S_FRAME_SIZE
357 stmia sp, {r0 - r12} @ Calling r0-r12
358 add r8, sp, #S_PC @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
359 stmdb r8, {sp, lr}^ @ Calling SP, LR
360 str lr, [r8, #0] @ Save calling PC
361 mrs r6, spsr
362 str r6, [r8, #4] @ Save CPSR
363 str r0, [r8, #8] @ Save OLD_R0
364 mov r0, sp
365 .endm
367 .macro irq_restore_user_regs
368 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
369 mov r0, r0
370 ldr lr, [sp, #S_PC] @ Get PC
371 add sp, sp, #S_FRAME_SIZE
372 subs pc, lr, #4 @ return & move spsr_svc into cpsr
373 .endm
375 .macro get_bad_stack
376 ldr r13, IRQ_STACK_START_IN
378 str lr, [r13] @ save caller lr in position 0 of saved stack
379 mrs lr, spsr @ get the spsr
380 str lr, [r13, #4] @ save spsr in position 1 of saved stack
382 mov r13, #MODE_SVC @ prepare SVC-Mode
383 @ msr spsr_c, r13
384 msr spsr, r13 @ switch modes, make sure moves will execute
385 mov lr, pc @ capture return pc
386 movs pc, lr @ jump to next instruction & switch modes.
387 .endm
389 .macro get_irq_stack @ setup IRQ stack
390 ldr sp, IRQ_STACK_START
391 .endm
393 .macro get_fiq_stack @ setup FIQ stack
394 ldr sp, FIQ_STACK_START
395 .endm
397 /*
398 * exception handlers
399 */
400 .align 5
401 undefined_instruction:
402 get_bad_stack
403 bad_save_user_regs
404 bl do_undefined_instruction
406 .align 5
407 software_interrupt:
408 get_bad_stack
409 bad_save_user_regs
410 bl do_software_interrupt
412 .align 5
413 prefetch_abort:
414 get_bad_stack
415 bad_save_user_regs
416 bl do_prefetch_abort
418 .align 5
419 data_abort:
420 get_bad_stack
421 bad_save_user_regs
422 bl do_data_abort
424 .align 5
425 not_used:
426 get_bad_stack
427 bad_save_user_regs
428 bl do_not_used
430 #ifdef CONFIG_USE_IRQ
432 .align 5
433 irq:
434 get_irq_stack
435 irq_save_user_regs
436 bl do_irq
437 irq_restore_user_regs
439 .align 5
440 fiq:
441 get_fiq_stack
442 /* someone ought to write a more effiction fiq_save_user_regs */
443 irq_save_user_regs
444 bl do_fiq
445 irq_restore_user_regs
447 #else
449 .align 5
450 irq:
451 get_bad_stack
452 bad_save_user_regs
453 bl do_irq
455 .align 5
456 fiq:
457 get_bad_stack
458 bad_save_user_regs
459 bl do_fiq
461 #endif
463 .align 5
464 .globl reset_cpu
465 reset_cpu:
466 ldr r1, rstctl1 /* get clkm1 reset ctl */
467 mov r3, #0x3 /* dsp_en + arm_rst = global reset */
468 strh r3, [r1] /* force reset */
469 mov r0, r0
470 _loop_forever:
471 b _loop_forever
472 rstctl1:
473 .word 0xfffece10