1 /*
2 * armboot - Startup Code for ARM926EJS CPU-core
3 *
4 * Copyright (c) 2003 Texas Instruments
5 *
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
34 #include <asm-offsets.h>
35 #include <config.h>
36 #include <common.h>
37 #include <version.h>
39 #if defined(CONFIG_OMAP1610)
40 #include <./configs/omap1510.h>
41 #elif defined(CONFIG_OMAP730)
42 #include <./configs/omap730.h>
43 #endif
45 /*
46 *************************************************************************
47 *
48 * Jump vector table as in table 3.1 in [1]
49 *
50 *************************************************************************
51 */
54 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
55 .globl _start
56 _start:
57 .globl _NOR_BOOT_CFG
58 _NOR_BOOT_CFG:
59 .word CONFIG_SYS_DV_NOR_BOOT_CFG
60 b reset
61 #else
62 .globl _start
63 _start:
64 b reset
65 #endif
66 #ifdef CONFIG_SPL_BUILD
67 /* No exception handlers in preloader */
68 ldr pc, _hang
69 ldr pc, _hang
70 ldr pc, _hang
71 ldr pc, _hang
72 ldr pc, _hang
73 ldr pc, _hang
74 ldr pc, _hang
76 _hang:
77 .word do_hang
78 /* pad to 64 byte boundary */
79 .word 0x12345678
80 .word 0x12345678
81 .word 0x12345678
82 .word 0x12345678
83 .word 0x12345678
84 .word 0x12345678
85 .word 0x12345678
86 #else
87 ldr pc, _undefined_instruction
88 ldr pc, _software_interrupt
89 ldr pc, _prefetch_abort
90 ldr pc, _data_abort
91 ldr pc, _not_used
92 ldr pc, _irq
93 ldr pc, _fiq
95 _undefined_instruction:
96 .word undefined_instruction
97 _software_interrupt:
98 .word software_interrupt
99 _prefetch_abort:
100 .word prefetch_abort
101 _data_abort:
102 .word data_abort
103 _not_used:
104 .word not_used
105 _irq:
106 .word irq
107 _fiq:
108 .word fiq
110 #endif /* CONFIG_SPL_BUILD */
111 .balignl 16,0xdeadbeef
114 /*
115 *************************************************************************
116 *
117 * Startup Code (reset vector)
118 *
119 * do important init only if we don't start from memory!
120 * setup Memory and board specific bits prior to relocation.
121 * relocate armboot to ram
122 * setup stack
123 *
124 *************************************************************************
125 */
127 .globl _TEXT_BASE
128 _TEXT_BASE:
129 #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
130 .word CONFIG_SYS_TEXT_BASE
131 #else
132 #ifdef CONFIG_SPL_BUILD
133 .word CONFIG_SPL_TEXT_BASE
134 #else
135 .word CONFIG_SYS_TEXT_BASE
136 #endif
137 #endif
139 /*
140 * These are defined in the board-specific linker script.
141 * Subtracting _start from them lets the linker put their
142 * relative position in the executable instead of leaving
143 * them null.
144 */
145 .globl _bss_start_ofs
146 _bss_start_ofs:
147 .word __bss_start - _start
149 .globl _bss_end_ofs
150 _bss_end_ofs:
151 .word __bss_end__ - _start
153 .globl _end_ofs
154 _end_ofs:
155 .word _end - _start
157 #ifdef CONFIG_NAND_U_BOOT
158 .globl _end
159 _end:
160 .word __bss_end__
161 #endif
163 #ifdef CONFIG_USE_IRQ
164 /* IRQ stack memory (calculated at run-time) */
165 .globl IRQ_STACK_START
166 IRQ_STACK_START:
167 .word 0x0badc0de
169 /* IRQ stack memory (calculated at run-time) */
170 .globl FIQ_STACK_START
171 FIQ_STACK_START:
172 .word 0x0badc0de
173 #endif
175 /* IRQ stack memory (calculated at run-time) + 8 bytes */
176 .globl IRQ_STACK_START_IN
177 IRQ_STACK_START_IN:
178 .word 0x0badc0de
180 /*
181 * the actual reset code
182 */
184 reset:
185 /*
186 * set the cpu to SVC32 mode
187 */
188 mrs r0,cpsr
189 bic r0,r0,#0x1f
190 orr r0,r0,#0xd3
191 msr cpsr,r0
193 /*
194 * we do sys-critical inits only at reboot,
195 * not when booting from ram!
196 */
197 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
198 bl cpu_init_crit
199 #endif
201 /* Set stackpointer in internal RAM to call board_init_f */
202 call_board_init_f:
203 #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
204 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
205 #else
206 #ifdef CONFIG_SPL_BUILD
207 ldr sp, =(CONFIG_SPL_STACK)
208 #else
209 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
210 #endif
211 #endif
212 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
213 ldr r0,=0x00000000
214 bl board_init_f
216 /*------------------------------------------------------------------------------*/
218 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
219 /*
220 * void relocate_code (addr_sp, gd, addr_moni)
221 *
222 * This "function" does not return, instead it continues in RAM
223 * after relocating the monitor code.
224 *
225 */
226 .globl relocate_code
227 relocate_code:
228 mov r4, r0 /* save addr_sp */
229 mov r5, r1 /* save addr of gd */
230 mov r6, r2 /* save addr of destination */
232 /* Set up the stack */
233 stack_setup:
234 mov sp, r4
236 adr r0, _start
237 sub r9, r6, r0 /* r9 <- relocation offset */
238 cmp r0, r6
239 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
240 beq clear_bss /* skip relocation */
241 mov r1, r6 /* r1 <- scratch for copy loop */
242 ldr r3, _bss_start_ofs
243 add r2, r0, r3 /* r2 <- source end address */
245 copy_loop:
246 ldmia r0!, {r9-r10} /* copy from source address [r0] */
247 stmia r1!, {r9-r10} /* copy to target address [r1] */
248 cmp r0, r2 /* until source end address [r2] */
249 blo copy_loop
251 #ifndef CONFIG_SPL_BUILD
252 /*
253 * fix .rel.dyn relocations
254 */
255 ldr r0, _TEXT_BASE /* r0 <- Text base */
256 sub r9, r6, r0 /* r9 <- relocation offset */
257 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
258 add r10, r10, r0 /* r10 <- sym table in FLASH */
259 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
260 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
261 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
262 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
263 fixloop:
264 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
265 add r0, r0, r9 /* r0 <- location to fix up in RAM */
266 ldr r1, [r2, #4]
267 and r7, r1, #0xff
268 cmp r7, #23 /* relative fixup? */
269 beq fixrel
270 cmp r7, #2 /* absolute fixup? */
271 beq fixabs
272 /* ignore unknown type of fixup */
273 b fixnext
274 fixabs:
275 /* absolute fix: set location to (offset) symbol value */
276 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
277 add r1, r10, r1 /* r1 <- address of symbol in table */
278 ldr r1, [r1, #4] /* r1 <- symbol value */
279 add r1, r1, r9 /* r1 <- relocated sym addr */
280 b fixnext
281 fixrel:
282 /* relative fix: increase location by offset */
283 ldr r1, [r0]
284 add r1, r1, r9
285 fixnext:
286 str r1, [r0]
287 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
288 cmp r2, r3
289 blo fixloop
290 #endif
292 clear_bss:
293 #ifdef CONFIG_SPL_BUILD
294 /* No relocation for SPL */
295 ldr r0, =__bss_start
296 ldr r1, =__bss_end__
297 #else
298 ldr r0, _bss_start_ofs
299 ldr r1, _bss_end_ofs
300 mov r4, r6 /* reloc addr */
301 add r0, r0, r4
302 add r1, r1, r4
303 #endif
304 mov r2, #0x00000000 /* clear */
306 clbss_l:cmp r0, r1 /* clear loop... */
307 bhs clbss_e /* if reached end of bss, exit */
308 str r2, [r0]
309 add r0, r0, #4
310 b clbss_l
311 clbss_e:
313 #ifndef CONFIG_SPL_BUILD
314 bl coloured_LED_init
315 bl red_led_on
316 #endif
318 /*
319 * We are done. Do not return, instead branch to second part of board
320 * initialization, now running from RAM.
321 */
322 #ifdef CONFIG_NAND_SPL
323 ldr r0, _nand_boot_ofs
324 mov pc, r0
326 _nand_boot_ofs:
327 .word nand_boot
328 #else
329 ldr r0, _board_init_r_ofs
330 ldr r1, _TEXT_BASE
331 add lr, r0, r1
332 add lr, lr, r9
333 /* setup parameters for board_init_r */
334 mov r0, r5 /* gd_t */
335 mov r1, r6 /* dest_addr */
336 /* jump to it ... */
337 mov pc, lr
339 _board_init_r_ofs:
340 .word board_init_r - _start
341 #endif
343 _rel_dyn_start_ofs:
344 .word __rel_dyn_start - _start
345 _rel_dyn_end_ofs:
346 .word __rel_dyn_end - _start
347 _dynsym_start_ofs:
348 .word __dynsym_start - _start
349 #endif
351 /*
352 *************************************************************************
353 *
354 * CPU_init_critical registers
355 *
356 * setup important registers
357 * setup memory timing
358 *
359 *************************************************************************
360 */
361 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
362 cpu_init_crit:
363 /*
364 * flush D cache before disabling it
365 */
366 mov r0, #0
367 flush_dcache:
368 mrc p15, 0, r15, c7, c10, 3
369 bne flush_dcache
371 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
372 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
374 /*
375 * disable MMU and D cache
376 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
377 */
378 mrc p15, 0, r0, c1, c0, 0
379 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
380 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
381 #ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
382 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
383 #else
384 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
385 #endif
386 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
387 #ifndef CONFIG_SYS_ICACHE_OFF
388 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
389 #endif
390 mcr p15, 0, r0, c1, c0, 0
392 /*
393 * Go setup Memory and board specific bits prior to relocation.
394 */
395 mov ip, lr /* perserve link reg across call */
396 bl lowlevel_init /* go setup pll,mux,memory */
397 mov lr, ip /* restore link */
398 mov pc, lr /* back to my caller */
399 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
401 #ifndef CONFIG_SPL_BUILD
402 /*
403 *************************************************************************
404 *
405 * Interrupt handling
406 *
407 *************************************************************************
408 */
410 @
411 @ IRQ stack frame.
412 @
413 #define S_FRAME_SIZE 72
415 #define S_OLD_R0 68
416 #define S_PSR 64
417 #define S_PC 60
418 #define S_LR 56
419 #define S_SP 52
421 #define S_IP 48
422 #define S_FP 44
423 #define S_R10 40
424 #define S_R9 36
425 #define S_R8 32
426 #define S_R7 28
427 #define S_R6 24
428 #define S_R5 20
429 #define S_R4 16
430 #define S_R3 12
431 #define S_R2 8
432 #define S_R1 4
433 #define S_R0 0
435 #define MODE_SVC 0x13
436 #define I_BIT 0x80
438 /*
439 * use bad_save_user_regs for abort/prefetch/undef/swi ...
440 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
441 */
443 .macro bad_save_user_regs
444 @ carve out a frame on current user stack
445 sub sp, sp, #S_FRAME_SIZE
446 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
447 ldr r2, IRQ_STACK_START_IN
448 @ get values for "aborted" pc and cpsr (into parm regs)
449 ldmia r2, {r2 - r3}
450 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
451 add r5, sp, #S_SP
452 mov r1, lr
453 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
454 mov r0, sp @ save current stack into r0 (param register)
455 .endm
457 .macro irq_save_user_regs
458 sub sp, sp, #S_FRAME_SIZE
459 stmia sp, {r0 - r12} @ Calling r0-r12
460 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
461 add r8, sp, #S_PC
462 stmdb r8, {sp, lr}^ @ Calling SP, LR
463 str lr, [r8, #0] @ Save calling PC
464 mrs r6, spsr
465 str r6, [r8, #4] @ Save CPSR
466 str r0, [r8, #8] @ Save OLD_R0
467 mov r0, sp
468 .endm
470 .macro irq_restore_user_regs
471 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
472 mov r0, r0
473 ldr lr, [sp, #S_PC] @ Get PC
474 add sp, sp, #S_FRAME_SIZE
475 subs pc, lr, #4 @ return & move spsr_svc into cpsr
476 .endm
478 .macro get_bad_stack
479 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
481 str lr, [r13] @ save caller lr in position 0 of saved stack
482 mrs lr, spsr @ get the spsr
483 str lr, [r13, #4] @ save spsr in position 1 of saved stack
484 mov r13, #MODE_SVC @ prepare SVC-Mode
485 @ msr spsr_c, r13
486 msr spsr, r13 @ switch modes, make sure moves will execute
487 mov lr, pc @ capture return pc
488 movs pc, lr @ jump to next instruction & switch modes.
489 .endm
491 .macro get_irq_stack @ setup IRQ stack
492 ldr sp, IRQ_STACK_START
493 .endm
495 .macro get_fiq_stack @ setup FIQ stack
496 ldr sp, FIQ_STACK_START
497 .endm
498 #endif /* CONFIG_SPL_BUILD */
500 /*
501 * exception handlers
502 */
503 #ifdef CONFIG_SPL_BUILD
504 .align 5
505 do_hang:
506 ldr sp, _TEXT_BASE /* switch to abort stack */
507 1:
508 bl 1b /* hang and never return */
509 #else /* !CONFIG_SPL_BUILD */
510 .align 5
511 undefined_instruction:
512 get_bad_stack
513 bad_save_user_regs
514 bl do_undefined_instruction
516 .align 5
517 software_interrupt:
518 get_bad_stack
519 bad_save_user_regs
520 bl do_software_interrupt
522 .align 5
523 prefetch_abort:
524 get_bad_stack
525 bad_save_user_regs
526 bl do_prefetch_abort
528 .align 5
529 data_abort:
530 get_bad_stack
531 bad_save_user_regs
532 bl do_data_abort
534 .align 5
535 not_used:
536 get_bad_stack
537 bad_save_user_regs
538 bl do_not_used
540 #ifdef CONFIG_USE_IRQ
542 .align 5
543 irq:
544 get_irq_stack
545 irq_save_user_regs
546 bl do_irq
547 irq_restore_user_regs
549 .align 5
550 fiq:
551 get_fiq_stack
552 /* someone ought to write a more effiction fiq_save_user_regs */
553 irq_save_user_regs
554 bl do_fiq
555 irq_restore_user_regs
557 #else
559 .align 5
560 irq:
561 get_bad_stack
562 bad_save_user_regs
563 bl do_irq
565 .align 5
566 fiq:
567 get_bad_stack
568 bad_save_user_regs
569 bl do_fiq
571 #endif
572 #endif /* CONFIG_SPL_BUILD */