1 /*
2 * armboot - Startup Code for ARM926EJS CPU-core
3 *
4 * Copyright (c) 2003 Texas Instruments
5 *
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
7 *
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
34 #include <asm-offsets.h>
35 #include <config.h>
36 #include <common.h>
37 #include <version.h>
39 #if defined(CONFIG_OMAP1610)
40 #include <./configs/omap1510.h>
41 #elif defined(CONFIG_OMAP730)
42 #include <./configs/omap730.h>
43 #endif
45 /*
46 *************************************************************************
47 *
48 * Jump vector table as in table 3.1 in [1]
49 *
50 *************************************************************************
51 */
54 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
55 .globl _start
56 _start:
57 .globl _NOR_BOOT_CFG
58 _NOR_BOOT_CFG:
59 .word CONFIG_SYS_DV_NOR_BOOT_CFG
60 b reset
61 #else
62 .globl _start
63 _start:
64 b reset
65 #endif
66 #ifdef CONFIG_SPL_BUILD
67 /* No exception handlers in preloader */
68 ldr pc, _hang
69 ldr pc, _hang
70 ldr pc, _hang
71 ldr pc, _hang
72 ldr pc, _hang
73 ldr pc, _hang
74 ldr pc, _hang
76 _hang:
77 .word do_hang
78 /* pad to 64 byte boundary */
79 .word 0x12345678
80 .word 0x12345678
81 .word 0x12345678
82 .word 0x12345678
83 .word 0x12345678
84 .word 0x12345678
85 .word 0x12345678
86 #else
87 ldr pc, _undefined_instruction
88 ldr pc, _software_interrupt
89 ldr pc, _prefetch_abort
90 ldr pc, _data_abort
91 ldr pc, _not_used
92 ldr pc, _irq
93 ldr pc, _fiq
95 _undefined_instruction:
96 .word undefined_instruction
97 _software_interrupt:
98 .word software_interrupt
99 _prefetch_abort:
100 .word prefetch_abort
101 _data_abort:
102 .word data_abort
103 _not_used:
104 .word not_used
105 _irq:
106 .word irq
107 _fiq:
108 .word fiq
110 #endif /* CONFIG_SPL_BUILD */
111 .balignl 16,0xdeadbeef
114 /*
115 *************************************************************************
116 *
117 * Startup Code (reset vector)
118 *
119 * do important init only if we don't start from memory!
120 * setup Memory and board specific bits prior to relocation.
121 * relocate armboot to ram
122 * setup stack
123 *
124 *************************************************************************
125 */
127 .globl _TEXT_BASE
128 _TEXT_BASE:
129 #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
130 .word CONFIG_SYS_TEXT_BASE
131 #else
132 #ifdef CONFIG_SPL_BUILD
133 .word CONFIG_SPL_TEXT_BASE
134 #else
135 .word CONFIG_SYS_TEXT_BASE
136 #endif
137 #endif
139 /*
140 * These are defined in the board-specific linker script.
141 * Subtracting _start from them lets the linker put their
142 * relative position in the executable instead of leaving
143 * them null.
144 */
145 .globl _bss_start_ofs
146 _bss_start_ofs:
147 .word __bss_start - _start
149 .globl _bss_end_ofs
150 _bss_end_ofs:
151 .word __bss_end__ - _start
153 .globl _end_ofs
154 _end_ofs:
155 .word _end - _start
157 #ifdef CONFIG_NAND_U_BOOT
158 .globl _end
159 _end:
160 .word __bss_end__
161 #endif
163 #ifdef CONFIG_USE_IRQ
164 /* IRQ stack memory (calculated at run-time) */
165 .globl IRQ_STACK_START
166 IRQ_STACK_START:
167 .word 0x0badc0de
169 /* IRQ stack memory (calculated at run-time) */
170 .globl FIQ_STACK_START
171 FIQ_STACK_START:
172 .word 0x0badc0de
173 #endif
175 /* IRQ stack memory (calculated at run-time) + 8 bytes */
176 .globl IRQ_STACK_START_IN
177 IRQ_STACK_START_IN:
178 .word 0x0badc0de
180 /*
181 * the actual reset code
182 */
184 reset:
185 /*
186 * set the cpu to SVC32 mode
187 */
188 mrs r0,cpsr
189 bic r0,r0,#0x1f
190 orr r0,r0,#0xd3
191 msr cpsr,r0
193 /*
194 * we do sys-critical inits only at reboot,
195 * not when booting from ram!
196 */
197 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
198 bl cpu_init_crit
199 #endif
201 /* Set stackpointer in internal RAM to call board_init_f */
202 call_board_init_f:
203 #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
204 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
205 #else
206 #ifdef CONFIG_SPL_BUILD
207 ldr sp, =(CONFIG_SPL_STACK)
208 #else
209 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
210 #endif
211 #endif
212 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
213 ldr r0,=0x00000000
214 bl board_init_f
216 /*------------------------------------------------------------------------------*/
218 /*
219 * void relocate_code (addr_sp, gd, addr_moni)
220 *
221 * This "function" does not return, instead it continues in RAM
222 * after relocating the monitor code.
223 *
224 */
225 .globl relocate_code
226 relocate_code:
227 mov r4, r0 /* save addr_sp */
228 mov r5, r1 /* save addr of gd */
229 mov r6, r2 /* save addr of destination */
231 /* Set up the stack */
232 stack_setup:
233 mov sp, r4
235 adr r0, _start
236 sub r9, r6, r0 /* r9 <- relocation offset */
237 cmp r0, r6
238 beq clear_bss /* skip relocation */
239 mov r1, r6 /* r1 <- scratch for copy loop */
240 ldr r3, _bss_start_ofs
241 add r2, r0, r3 /* r2 <- source end address */
243 copy_loop:
244 ldmia r0!, {r9-r10} /* copy from source address [r0] */
245 stmia r1!, {r9-r10} /* copy to target address [r1] */
246 cmp r0, r2 /* until source end address [r2] */
247 blo copy_loop
249 #ifndef CONFIG_SPL_BUILD
250 /*
251 * fix .rel.dyn relocations
252 */
253 ldr r0, _TEXT_BASE /* r0 <- Text base */
254 sub r9, r6, r0 /* r9 <- relocation offset */
255 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
256 add r10, r10, r0 /* r10 <- sym table in FLASH */
257 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
258 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
259 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
260 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
261 fixloop:
262 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
263 add r0, r0, r9 /* r0 <- location to fix up in RAM */
264 ldr r1, [r2, #4]
265 and r7, r1, #0xff
266 cmp r7, #23 /* relative fixup? */
267 beq fixrel
268 cmp r7, #2 /* absolute fixup? */
269 beq fixabs
270 /* ignore unknown type of fixup */
271 b fixnext
272 fixabs:
273 /* absolute fix: set location to (offset) symbol value */
274 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
275 add r1, r10, r1 /* r1 <- address of symbol in table */
276 ldr r1, [r1, #4] /* r1 <- symbol value */
277 add r1, r1, r9 /* r1 <- relocated sym addr */
278 b fixnext
279 fixrel:
280 /* relative fix: increase location by offset */
281 ldr r1, [r0]
282 add r1, r1, r9
283 fixnext:
284 str r1, [r0]
285 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
286 cmp r2, r3
287 blo fixloop
288 #endif
290 clear_bss:
291 #ifdef CONFIG_SPL_BUILD
292 /* No relocation for SPL */
293 ldr r0, =__bss_start
294 ldr r1, =__bss_end__
295 #else
296 ldr r0, _bss_start_ofs
297 ldr r1, _bss_end_ofs
298 mov r4, r6 /* reloc addr */
299 add r0, r0, r4
300 add r1, r1, r4
301 #endif
302 mov r2, #0x00000000 /* clear */
304 clbss_l:cmp r0, r1 /* clear loop... */
305 bhs clbss_e /* if reached end of bss, exit */
306 str r2, [r0]
307 add r0, r0, #4
308 b clbss_l
309 clbss_e:
311 #ifndef CONFIG_SPL_BUILD
312 bl coloured_LED_init
313 bl red_led_on
314 #endif
316 /*
317 * We are done. Do not return, instead branch to second part of board
318 * initialization, now running from RAM.
319 */
320 #ifdef CONFIG_NAND_SPL
321 ldr r0, _nand_boot_ofs
322 mov pc, r0
324 _nand_boot_ofs:
325 .word nand_boot
326 #else
327 ldr r0, _board_init_r_ofs
328 ldr r1, _TEXT_BASE
329 add lr, r0, r1
330 add lr, lr, r9
331 /* setup parameters for board_init_r */
332 mov r0, r5 /* gd_t */
333 mov r1, r6 /* dest_addr */
334 /* jump to it ... */
335 mov pc, lr
337 _board_init_r_ofs:
338 .word board_init_r - _start
339 #endif
341 _rel_dyn_start_ofs:
342 .word __rel_dyn_start - _start
343 _rel_dyn_end_ofs:
344 .word __rel_dyn_end - _start
345 _dynsym_start_ofs:
346 .word __dynsym_start - _start
348 /*
349 *************************************************************************
350 *
351 * CPU_init_critical registers
352 *
353 * setup important registers
354 * setup memory timing
355 *
356 *************************************************************************
357 */
358 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
359 cpu_init_crit:
360 /*
361 * flush D cache before disabling it
362 */
363 mov r0, #0
364 flush_dcache:
365 mrc p15, 0, r15, c7, c10, 3
366 bne flush_dcache
368 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
369 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
371 /*
372 * disable MMU and D cache
373 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
374 */
375 mrc p15, 0, r0, c1, c0, 0
376 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
377 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
378 #ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
379 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
380 #else
381 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
382 #endif
383 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
384 #ifndef CONFIG_SYS_ICACHE_OFF
385 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
386 #endif
387 mcr p15, 0, r0, c1, c0, 0
389 /*
390 * Go setup Memory and board specific bits prior to relocation.
391 */
392 mov ip, lr /* perserve link reg across call */
393 bl lowlevel_init /* go setup pll,mux,memory */
394 mov lr, ip /* restore link */
395 mov pc, lr /* back to my caller */
396 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
398 #ifndef CONFIG_SPL_BUILD
399 /*
400 *************************************************************************
401 *
402 * Interrupt handling
403 *
404 *************************************************************************
405 */
407 @
408 @ IRQ stack frame.
409 @
410 #define S_FRAME_SIZE 72
412 #define S_OLD_R0 68
413 #define S_PSR 64
414 #define S_PC 60
415 #define S_LR 56
416 #define S_SP 52
418 #define S_IP 48
419 #define S_FP 44
420 #define S_R10 40
421 #define S_R9 36
422 #define S_R8 32
423 #define S_R7 28
424 #define S_R6 24
425 #define S_R5 20
426 #define S_R4 16
427 #define S_R3 12
428 #define S_R2 8
429 #define S_R1 4
430 #define S_R0 0
432 #define MODE_SVC 0x13
433 #define I_BIT 0x80
435 /*
436 * use bad_save_user_regs for abort/prefetch/undef/swi ...
437 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
438 */
440 .macro bad_save_user_regs
441 @ carve out a frame on current user stack
442 sub sp, sp, #S_FRAME_SIZE
443 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
444 ldr r2, IRQ_STACK_START_IN
445 @ get values for "aborted" pc and cpsr (into parm regs)
446 ldmia r2, {r2 - r3}
447 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
448 add r5, sp, #S_SP
449 mov r1, lr
450 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
451 mov r0, sp @ save current stack into r0 (param register)
452 .endm
454 .macro irq_save_user_regs
455 sub sp, sp, #S_FRAME_SIZE
456 stmia sp, {r0 - r12} @ Calling r0-r12
457 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
458 add r8, sp, #S_PC
459 stmdb r8, {sp, lr}^ @ Calling SP, LR
460 str lr, [r8, #0] @ Save calling PC
461 mrs r6, spsr
462 str r6, [r8, #4] @ Save CPSR
463 str r0, [r8, #8] @ Save OLD_R0
464 mov r0, sp
465 .endm
467 .macro irq_restore_user_regs
468 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
469 mov r0, r0
470 ldr lr, [sp, #S_PC] @ Get PC
471 add sp, sp, #S_FRAME_SIZE
472 subs pc, lr, #4 @ return & move spsr_svc into cpsr
473 .endm
475 .macro get_bad_stack
476 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
478 str lr, [r13] @ save caller lr in position 0 of saved stack
479 mrs lr, spsr @ get the spsr
480 str lr, [r13, #4] @ save spsr in position 1 of saved stack
481 mov r13, #MODE_SVC @ prepare SVC-Mode
482 @ msr spsr_c, r13
483 msr spsr, r13 @ switch modes, make sure moves will execute
484 mov lr, pc @ capture return pc
485 movs pc, lr @ jump to next instruction & switch modes.
486 .endm
488 .macro get_irq_stack @ setup IRQ stack
489 ldr sp, IRQ_STACK_START
490 .endm
492 .macro get_fiq_stack @ setup FIQ stack
493 ldr sp, FIQ_STACK_START
494 .endm
495 #endif /* CONFIG_SPL_BUILD */
497 /*
498 * exception handlers
499 */
500 #ifdef CONFIG_SPL_BUILD
501 .align 5
502 do_hang:
503 ldr sp, _TEXT_BASE /* switch to abort stack */
504 1:
505 bl 1b /* hang and never return */
506 #else /* !CONFIG_SPL_BUILD */
507 .align 5
508 undefined_instruction:
509 get_bad_stack
510 bad_save_user_regs
511 bl do_undefined_instruction
513 .align 5
514 software_interrupt:
515 get_bad_stack
516 bad_save_user_regs
517 bl do_software_interrupt
519 .align 5
520 prefetch_abort:
521 get_bad_stack
522 bad_save_user_regs
523 bl do_prefetch_abort
525 .align 5
526 data_abort:
527 get_bad_stack
528 bad_save_user_regs
529 bl do_data_abort
531 .align 5
532 not_used:
533 get_bad_stack
534 bad_save_user_regs
535 bl do_not_used
537 #ifdef CONFIG_USE_IRQ
539 .align 5
540 irq:
541 get_irq_stack
542 irq_save_user_regs
543 bl do_irq
544 irq_restore_user_regs
546 .align 5
547 fiq:
548 get_fiq_stack
549 /* someone ought to write a more effiction fiq_save_user_regs */
550 irq_save_user_regs
551 bl do_fiq
552 irq_restore_user_regs
554 #else
556 .align 5
557 irq:
558 get_bad_stack
559 bad_save_user_regs
560 bl do_irq
562 .align 5
563 fiq:
564 get_bad_stack
565 bad_save_user_regs
566 bl do_fiq
568 #endif
569 #endif /* CONFIG_SPL_BUILD */