1 /*
2 *
3 * Clock initialization for OMAP4
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Aneesh V <aneesh@ti.com>
9 *
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32 #include <common.h>
33 #include <i2c.h>
34 #include <asm/omap_common.h>
35 #include <asm/gpio.h>
36 #include <asm/arch/clocks.h>
37 #include <asm/arch/sys_proto.h>
38 #include <asm/utils.h>
39 #include <asm/omap_gpio.h>
40 #include <asm/emif.h>
42 #ifndef CONFIG_SPL_BUILD
43 /*
44 * printing to console doesn't work unless
45 * this code is executed from SPL
46 */
47 #define printf(fmt, args...)
48 #define puts(s)
49 #endif
51 const u32 sys_clk_array[8] = {
52 12000000, /* 12 MHz */
53 20000000, /* 20 MHz */
54 16800000, /* 16.8 MHz */
55 19200000, /* 19.2 MHz */
56 26000000, /* 26 MHz */
57 27000000, /* 27 MHz */
58 38400000, /* 38.4 MHz */
59 };
61 static inline u32 __get_sys_clk_index(void)
62 {
63 s8 ind;
64 /*
65 * For ES1 the ROM code calibration of sys clock is not reliable
66 * due to hw issue. So, use hard-coded value. If this value is not
67 * correct for any board over-ride this function in board file
68 * From ES2.0 onwards you will get this information from
69 * CM_SYS_CLKSEL
70 */
71 if (omap_revision() == OMAP4430_ES1_0)
72 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
73 else {
74 /* SYS_CLKSEL - 1 to match the dpll param array indices */
75 ind = (readl((*prcm)->cm_sys_clksel) &
76 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
77 }
78 return ind;
79 }
81 u32 get_sys_clk_index(void)
82 __attribute__ ((weak, alias("__get_sys_clk_index")));
84 u32 get_sys_clk_freq(void)
85 {
86 u8 index = get_sys_clk_index();
87 return sys_clk_array[index];
88 }
90 void setup_post_dividers(u32 const base, const struct dpll_params *params)
91 {
92 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
94 /* Setup post-dividers */
95 if (params->m2 >= 0)
96 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
97 if (params->m3 >= 0)
98 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
99 if (params->m4_h11 >= 0)
100 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
101 if (params->m5_h12 >= 0)
102 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
103 if (params->m6_h13 >= 0)
104 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
105 if (params->m7_h14 >= 0)
106 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
107 if (params->h21 >= 0)
108 writel(params->h21, &dpll_regs->cm_div_h21_dpll);
109 if (params->h22 >= 0)
110 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
111 if (params->h23 >= 0)
112 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
113 if (params->h24 >= 0)
114 writel(params->h24, &dpll_regs->cm_div_h24_dpll);
115 }
117 static inline void do_bypass_dpll(u32 const base)
118 {
119 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
121 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
122 CM_CLKMODE_DPLL_DPLL_EN_MASK,
123 DPLL_EN_FAST_RELOCK_BYPASS <<
124 CM_CLKMODE_DPLL_EN_SHIFT);
125 }
127 static inline void wait_for_bypass(u32 const base)
128 {
129 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
131 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
132 LDELAY)) {
133 printf("Bypassing DPLL failed %x\n", base);
134 }
135 }
137 static inline void do_lock_dpll(u32 const base)
138 {
139 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
141 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
142 CM_CLKMODE_DPLL_DPLL_EN_MASK,
143 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
144 }
146 static inline void wait_for_lock(u32 const base)
147 {
148 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
150 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
151 &dpll_regs->cm_idlest_dpll, LDELAY)) {
152 printf("DPLL locking failed for %x\n", base);
153 hang();
154 }
155 }
157 inline u32 check_for_lock(u32 const base)
158 {
159 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
160 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
162 return lock;
163 }
165 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
166 {
167 u32 sysclk_ind = get_sys_clk_index();
168 return &dpll_data->mpu[sysclk_ind];
169 }
171 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
172 {
173 u32 sysclk_ind = get_sys_clk_index();
174 return &dpll_data->core[sysclk_ind];
175 }
177 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
178 {
179 u32 sysclk_ind = get_sys_clk_index();
180 return &dpll_data->per[sysclk_ind];
181 }
183 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
184 {
185 u32 sysclk_ind = get_sys_clk_index();
186 return &dpll_data->iva[sysclk_ind];
187 }
189 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
190 {
191 u32 sysclk_ind = get_sys_clk_index();
192 return &dpll_data->usb[sysclk_ind];
193 }
195 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
196 {
197 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
198 u32 sysclk_ind = get_sys_clk_index();
199 return &dpll_data->abe[sysclk_ind];
200 #else
201 return dpll_data->abe;
202 #endif
203 }
205 static const struct dpll_params *get_ddr_dpll_params
206 (struct dplls const *dpll_data)
207 {
208 u32 sysclk_ind = get_sys_clk_index();
210 if (!dpll_data->ddr)
211 return NULL;
212 return &dpll_data->ddr[sysclk_ind];
213 }
215 #ifdef CONFIG_DRIVER_TI_CPSW
216 static const struct dpll_params *get_gmac_dpll_params
217 (struct dplls const *dpll_data)
218 {
219 u32 sysclk_ind = get_sys_clk_index();
221 if (!dpll_data->gmac)
222 return NULL;
223 return &dpll_data->gmac[sysclk_ind];
224 }
225 #endif
227 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
228 u8 lock, char *dpll)
229 {
230 u32 temp, M, N;
231 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
233 if (!params)
234 return;
236 temp = readl(&dpll_regs->cm_clksel_dpll);
238 if (check_for_lock(base)) {
239 /*
240 * The Dpll has already been locked by rom code using CH.
241 * Check if M,N are matching with Ideal nominal opp values.
242 * If matches, skip the rest otherwise relock.
243 */
244 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
245 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
246 if ((M != (params->m)) || (N != (params->n))) {
247 debug("\n %s Dpll locked, but not for ideal M = %d,"
248 "N = %d values, current values are M = %d,"
249 "N= %d" , dpll, params->m, params->n,
250 M, N);
251 } else {
252 /* Dpll locked with ideal values for nominal opps. */
253 debug("\n %s Dpll already locked with ideal"
254 "nominal opp values", dpll);
255 goto setup_post_dividers;
256 }
257 }
259 bypass_dpll(base);
261 /* Set M & N */
262 temp &= ~CM_CLKSEL_DPLL_M_MASK;
263 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
265 temp &= ~CM_CLKSEL_DPLL_N_MASK;
266 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
268 writel(temp, &dpll_regs->cm_clksel_dpll);
270 /* Lock */
271 if (lock)
272 do_lock_dpll(base);
274 setup_post_dividers:
275 setup_post_dividers(base, params);
277 /* Wait till the DPLL locks */
278 if (lock)
279 wait_for_lock(base);
280 }
282 u32 omap_ddr_clk(void)
283 {
284 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
285 const struct dpll_params *core_dpll_params;
287 omap_rev = omap_revision();
288 sys_clk_khz = get_sys_clk_freq() / 1000;
290 core_dpll_params = get_core_dpll_params(*dplls_data);
292 debug("sys_clk %d\n ", sys_clk_khz * 1000);
294 /* Find Core DPLL locked frequency first */
295 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
296 (core_dpll_params->n + 1);
298 if (omap_rev < OMAP5430_ES1_0) {
299 /*
300 * DDR frequency is PHY_ROOT_CLK/2
301 * PHY_ROOT_CLK = Fdpll/2/M2
302 */
303 divider = 4;
304 } else {
305 /*
306 * DDR frequency is PHY_ROOT_CLK
307 * PHY_ROOT_CLK = Fdpll/2/M2
308 */
309 divider = 2;
310 }
312 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
313 ddr_clk *= 1000; /* convert to Hz */
314 debug("ddr_clk %d\n ", ddr_clk);
316 return ddr_clk;
317 }
319 /*
320 * Lock MPU dpll
321 *
322 * Resulting MPU frequencies:
323 * 4430 ES1.0 : 600 MHz
324 * 4430 ES2.x : 792 MHz (OPP Turbo)
325 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
326 */
327 void configure_mpu_dpll(void)
328 {
329 const struct dpll_params *params;
330 struct dpll_regs *mpu_dpll_regs;
331 u32 omap_rev;
332 omap_rev = omap_revision();
334 /*
335 * DCC and clock divider settings for 4460.
336 * DCC is required, if more than a certain frequency is required.
337 * For, 4460 > 1GHZ.
338 * 5430 > 1.4GHZ.
339 */
340 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
341 mpu_dpll_regs =
342 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
343 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
344 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
345 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
346 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
347 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
348 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
349 CM_CLKSEL_DCC_EN_MASK);
350 }
352 params = get_mpu_dpll_params(*dplls_data);
354 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
355 debug("MPU DPLL locked\n");
356 }
358 #ifdef CONFIG_USB_EHCI_OMAP
359 static void setup_usb_dpll(void)
360 {
361 const struct dpll_params *params;
362 u32 sys_clk_khz, sd_div, num, den;
364 sys_clk_khz = get_sys_clk_freq() / 1000;
365 /*
366 * USB:
367 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
368 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
369 * - where CLKINP is sys_clk in MHz
370 * Use CLKINP in KHz and adjust the denominator accordingly so
371 * that we have enough accuracy and at the same time no overflow
372 */
373 params = get_usb_dpll_params(*dplls_data);
374 num = params->m * sys_clk_khz;
375 den = (params->n + 1) * 250 * 1000;
376 num += den - 1;
377 sd_div = num / den;
378 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
379 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
380 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
382 /* Now setup the dpll with the regular function */
383 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
384 }
385 #endif
387 static void setup_dplls(void)
388 {
389 u32 temp;
390 const struct dpll_params *params;
392 debug("setup_dplls\n");
394 /* CORE dpll */
395 params = get_core_dpll_params(*dplls_data); /* default - safest */
396 /*
397 * Do not lock the core DPLL now. Just set it up.
398 * Core DPLL will be locked after setting up EMIF
399 * using the FREQ_UPDATE method(freq_update_core())
400 */
401 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
402 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
403 DPLL_NO_LOCK, "core");
404 else
405 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
406 DPLL_LOCK, "core");
407 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
408 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
409 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
410 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
411 writel(temp, (*prcm)->cm_clksel_core);
412 debug("Core DPLL configured\n");
414 /* lock PER dpll */
415 params = get_per_dpll_params(*dplls_data);
416 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
417 params, DPLL_LOCK, "per");
418 debug("PER DPLL locked\n");
420 /* MPU dpll */
421 configure_mpu_dpll();
423 #ifdef CONFIG_USB_EHCI_OMAP
424 setup_usb_dpll();
425 #endif
426 params = get_ddr_dpll_params(*dplls_data);
427 do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
428 params, DPLL_LOCK, "ddr");
430 #ifdef CONFIG_DRIVER_TI_CPSW
431 params = get_gmac_dpll_params(*dplls_data);
432 do_setup_dpll((*prcm)->cm_clkmode_dpll_gmac, params,
433 DPLL_LOCK, "gmac");
434 #endif
435 }
437 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
438 static void setup_non_essential_dplls(void)
439 {
440 u32 abe_ref_clk;
441 const struct dpll_params *params;
443 /* IVA */
444 clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
445 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
447 params = get_iva_dpll_params(*dplls_data);
448 do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
450 /* Configure ABE dpll */
451 params = get_abe_dpll_params(*dplls_data);
452 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
453 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
455 if (omap_revision() == DRA752_ES1_0)
456 /* Select the sys clk for dpll_abe */
457 clrsetbits_le32((*prcm)->cm_abe_pll_sys_clksel,
458 CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK,
459 CM_ABE_PLL_SYS_CLKSEL_SYSCLK2);
460 #else
461 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
462 /*
463 * We need to enable some additional options to achieve
464 * 196.608MHz from 32768 Hz
465 */
466 setbits_le32((*prcm)->cm_clkmode_dpll_abe,
467 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
468 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
469 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
470 CM_CLKMODE_DPLL_REGM4XEN_MASK);
471 /* Spend 4 REFCLK cycles at each stage */
472 clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
473 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
474 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
475 #endif
477 /* Select the right reference clk */
478 clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
479 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
480 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
481 /* Lock the dpll */
482 do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
483 }
484 #endif
486 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
487 {
488 u32 offset_code;
490 volt_offset -= pmic->base_offset;
492 offset_code = (volt_offset + pmic->step - 1) / pmic->step;
494 /*
495 * Offset codes 1-6 all give the base voltage in Palmas
496 * Offset code 0 switches OFF the SMPS
497 */
498 return offset_code + pmic->start_code;
499 }
501 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
502 {
503 u32 offset_code;
504 u32 offset = volt_mv;
505 int ret = 0;
507 if (!volt_mv)
508 return;
510 pmic->pmic_bus_init();
511 /* See if we can first get the GPIO if needed */
512 if (pmic->gpio_en)
513 ret = gpio_request(pmic->gpio, "PMIC_GPIO");
515 if (ret < 0) {
516 printf("%s: gpio %d request failed %d\n", __func__,
517 pmic->gpio, ret);
518 return;
519 }
521 /* Pull the GPIO low to select SET0 register, while we program SET1 */
522 if (pmic->gpio_en)
523 gpio_direction_output(pmic->gpio, 0);
525 /* convert to uV for better accuracy in the calculations */
526 offset *= 1000;
528 offset_code = get_offset_code(offset, pmic);
530 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
531 offset_code);
533 if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
534 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
536 if (pmic->gpio_en)
537 gpio_direction_output(pmic->gpio, 1);
538 }
540 static u32 optimize_vcore_voltage(struct volts const *v)
541 {
542 u32 val;
543 if (!v->value)
544 return 0;
545 if (!v->efuse.reg)
546 return v->value;
548 switch (v->efuse.reg_bits) {
549 case 16:
550 val = readw(v->efuse.reg);
551 break;
552 case 32:
553 val = readl(v->efuse.reg);
554 break;
555 default:
556 printf("Error: efuse 0x%08x bits=%d unknown\n",
557 v->efuse.reg, v->efuse.reg_bits);
558 return v->value;
559 }
561 if (!val) {
562 printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
563 v->efuse.reg, v->efuse.reg_bits, v->value);
564 return v->value;
565 }
567 debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
568 __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
569 return val;
570 }
572 /*
573 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
574 * We set the maximum voltages allowed here because Smart-Reflex is not
575 * enabled in bootloader. Voltage initialization in the kernel will set
576 * these to the nominal values after enabling Smart-Reflex
577 */
578 void scale_vcores(struct vcores_data const *vcores)
579 {
580 u32 val;
582 val = optimize_vcore_voltage(&vcores->core);
583 do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
585 val = optimize_vcore_voltage(&vcores->mpu);
586 do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
588 val = optimize_vcore_voltage(&vcores->mm);
589 do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
591 val = optimize_vcore_voltage(&vcores->gpu);
592 do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
594 val = optimize_vcore_voltage(&vcores->eve);
595 do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
597 val = optimize_vcore_voltage(&vcores->iva);
598 do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
600 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
601 /* Configure LDO SRAM "magic" bits */
602 writel(2, (*prcm)->prm_sldo_core_setup);
603 writel(2, (*prcm)->prm_sldo_mpu_setup);
604 writel(2, (*prcm)->prm_sldo_mm_setup);
605 }
606 }
608 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
609 {
610 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
611 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
612 debug("Enable clock domain - %x\n", clkctrl_reg);
613 }
615 static inline void wait_for_clk_enable(u32 clkctrl_addr)
616 {
617 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
618 u32 bound = LDELAY;
620 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
621 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
623 clkctrl = readl(clkctrl_addr);
624 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
625 MODULE_CLKCTRL_IDLEST_SHIFT;
626 if (--bound == 0) {
627 printf("Clock enable failed for 0x%x idlest 0x%x\n",
628 clkctrl_addr, clkctrl);
629 return;
630 }
631 }
632 }
634 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
635 u32 wait_for_enable)
636 {
637 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
638 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
639 debug("Enable clock module - %x\n", clkctrl_addr);
640 if (wait_for_enable)
641 wait_for_clk_enable(clkctrl_addr);
642 }
644 void freq_update_core(void)
645 {
646 u32 freq_config1 = 0;
647 const struct dpll_params *core_dpll_params;
648 u32 omap_rev = omap_revision();
650 core_dpll_params = get_core_dpll_params(*dplls_data);
651 /* Put EMIF clock domain in sw wakeup mode */
652 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
653 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
654 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
655 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
657 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
658 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
660 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
661 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
663 freq_config1 |= (core_dpll_params->m2 <<
664 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
665 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
667 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
668 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
669 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
670 puts("FREQ UPDATE procedure failed!!");
671 hang();
672 }
674 /*
675 * Putting EMIF in HW_AUTO is seen to be causing issues with
676 * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
677 * in OMAP5430 ES1.0 silicon
678 */
679 if (omap_rev != OMAP5430_ES1_0) {
680 /* Put EMIF clock domain back in hw auto mode */
681 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
682 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
683 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
684 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
685 }
686 }
688 void bypass_dpll(u32 const base)
689 {
690 do_bypass_dpll(base);
691 wait_for_bypass(base);
692 }
694 void lock_dpll(u32 const base)
695 {
696 do_lock_dpll(base);
697 wait_for_lock(base);
698 }
700 void setup_clocks_for_console(void)
701 {
702 /* Do not add any spl_debug prints in this function */
703 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
704 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
705 CD_CLKCTRL_CLKTRCTRL_SHIFT);
707 /* Enable all UARTs - console will be on one of them */
708 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
709 MODULE_CLKCTRL_MODULEMODE_MASK,
710 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
711 MODULE_CLKCTRL_MODULEMODE_SHIFT);
713 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
714 MODULE_CLKCTRL_MODULEMODE_MASK,
715 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
716 MODULE_CLKCTRL_MODULEMODE_SHIFT);
718 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
719 MODULE_CLKCTRL_MODULEMODE_MASK,
720 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
721 MODULE_CLKCTRL_MODULEMODE_SHIFT);
723 clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
724 MODULE_CLKCTRL_MODULEMODE_MASK,
725 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
726 MODULE_CLKCTRL_MODULEMODE_SHIFT);
728 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
729 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
730 CD_CLKCTRL_CLKTRCTRL_SHIFT);
731 }
733 void do_enable_clocks(u32 const *clk_domains,
734 u32 const *clk_modules_hw_auto,
735 u32 const *clk_modules_explicit_en,
736 u8 wait_for_enable)
737 {
738 u32 i, max = 100;
740 /* Put the clock domains in SW_WKUP mode */
741 for (i = 0; (i < max) && clk_domains[i]; i++) {
742 enable_clock_domain(clk_domains[i],
743 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
744 }
746 /* Clock modules that need to be put in HW_AUTO */
747 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
748 enable_clock_module(clk_modules_hw_auto[i],
749 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
750 wait_for_enable);
751 };
753 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
754 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
755 enable_clock_module(clk_modules_explicit_en[i],
756 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
757 wait_for_enable);
758 };
760 /* Put the clock domains in HW_AUTO mode now */
761 for (i = 0; (i < max) && clk_domains[i]; i++) {
762 enable_clock_domain(clk_domains[i],
763 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
764 }
765 }
767 void prcm_init(void)
768 {
769 switch (omap_hw_init_context()) {
770 case OMAP_INIT_CONTEXT_SPL:
771 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
772 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
773 enable_basic_clocks();
774 timer_init();
775 scale_vcores(*omap_vcores);
776 setup_dplls();
777 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
778 setup_non_essential_dplls();
779 enable_non_essential_clocks();
780 #endif
781 setup_warmreset_time();
782 break;
783 default:
784 break;
785 }
787 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
788 enable_basic_uboot_clocks();
789 }
791 void gpi2c_init(void)
792 {
793 static int gpi2c = 1;
795 if (gpi2c) {
796 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
797 gpi2c = 0;
798 }
799 }