1 /*
2 *
3 * Clock initialization for OMAP4
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Aneesh V <aneesh@ti.com>
9 *
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32 #include <common.h>
33 #include <i2c.h>
34 #include <asm/omap_common.h>
35 #include <asm/gpio.h>
36 #include <asm/arch/clocks.h>
37 #include <asm/arch/sys_proto.h>
38 #include <asm/utils.h>
39 #include <asm/omap_gpio.h>
40 #include <asm/emif.h>
42 #ifndef CONFIG_SPL_BUILD
43 /*
44 * printing to console doesn't work unless
45 * this code is executed from SPL
46 */
47 #define printf(fmt, args...)
48 #define puts(s)
49 #endif
51 const u32 sys_clk_array[8] = {
52 12000000, /* 12 MHz */
53 13000000, /* 13 MHz */
54 16800000, /* 16.8 MHz */
55 19200000, /* 19.2 MHz */
56 26000000, /* 26 MHz */
57 27000000, /* 27 MHz */
58 38400000, /* 38.4 MHz */
59 20000000, /* 20 MHz */
60 };
62 static inline u32 __get_sys_clk_index(void)
63 {
64 s8 ind;
65 /*
66 * For ES1 the ROM code calibration of sys clock is not reliable
67 * due to hw issue. So, use hard-coded value. If this value is not
68 * correct for any board over-ride this function in board file
69 * From ES2.0 onwards you will get this information from
70 * CM_SYS_CLKSEL
71 */
72 if (omap_revision() == OMAP4430_ES1_0)
73 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
74 else {
75 /* SYS_CLKSEL - 1 to match the dpll param array indices */
76 ind = (readl((*prcm)->cm_sys_clksel) &
77 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
78 /*
79 * SYS_CLKSEL value for 20MHz is 0. This is introduced newly
80 * in DRA7XX socs. SYS_CLKSEL -1 will be greater than
81 * NUM_SYS_CLK. So considering the last 3 bits as the index
82 * for the dpll param array.
83 */
84 ind &= CM_SYS_CLKSEL_SYS_CLKSEL_MASK;
85 }
86 return ind;
87 }
89 u32 get_sys_clk_index(void)
90 __attribute__ ((weak, alias("__get_sys_clk_index")));
92 u32 get_sys_clk_freq(void)
93 {
94 u8 index = get_sys_clk_index();
95 return sys_clk_array[index];
96 }
98 void setup_post_dividers(u32 const base, const struct dpll_params *params)
99 {
100 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
102 /* Setup post-dividers */
103 if (params->m2 >= 0)
104 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
105 if (params->m3 >= 0)
106 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
107 if (params->m4_h11 >= 0)
108 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
109 if (params->m5_h12 >= 0)
110 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
111 if (params->m6_h13 >= 0)
112 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
113 if (params->m7_h14 >= 0)
114 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
115 if (params->h21 >= 0)
116 writel(params->h21, &dpll_regs->cm_div_h21_dpll);
117 if (params->h22 >= 0)
118 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
119 if (params->h23 >= 0)
120 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
121 if (params->h24 >= 0)
122 writel(params->h24, &dpll_regs->cm_div_h24_dpll);
123 }
125 static inline void do_bypass_dpll(u32 const base)
126 {
127 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
129 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
130 CM_CLKMODE_DPLL_DPLL_EN_MASK,
131 DPLL_EN_FAST_RELOCK_BYPASS <<
132 CM_CLKMODE_DPLL_EN_SHIFT);
133 }
135 static inline void wait_for_bypass(u32 const base)
136 {
137 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
139 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
140 LDELAY)) {
141 printf("Bypassing DPLL failed %x\n", base);
142 }
143 }
145 static inline void do_lock_dpll(u32 const base)
146 {
147 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
149 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
150 CM_CLKMODE_DPLL_DPLL_EN_MASK,
151 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
152 }
154 static inline void wait_for_lock(u32 const base)
155 {
156 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
158 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
159 &dpll_regs->cm_idlest_dpll, LDELAY)) {
160 printf("DPLL locking failed for %x\n", base);
161 hang();
162 }
163 }
165 inline u32 check_for_lock(u32 const base)
166 {
167 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
168 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
170 return lock;
171 }
173 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
174 {
175 u32 sysclk_ind = get_sys_clk_index();
176 return &dpll_data->mpu[sysclk_ind];
177 }
179 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
180 {
181 u32 sysclk_ind = get_sys_clk_index();
182 return &dpll_data->core[sysclk_ind];
183 }
185 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
186 {
187 u32 sysclk_ind = get_sys_clk_index();
188 return &dpll_data->per[sysclk_ind];
189 }
191 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
192 {
193 u32 sysclk_ind = get_sys_clk_index();
194 return &dpll_data->iva[sysclk_ind];
195 }
197 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
198 {
199 u32 sysclk_ind = get_sys_clk_index();
200 return &dpll_data->usb[sysclk_ind];
201 }
203 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
204 {
205 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
206 u32 sysclk_ind = get_sys_clk_index();
207 return &dpll_data->abe[sysclk_ind];
208 #else
209 return dpll_data->abe;
210 #endif
211 }
213 static const struct dpll_params *get_ddr_dpll_params
214 (struct dplls const *dpll_data)
215 {
216 u32 sysclk_ind = get_sys_clk_index();
218 if (!dpll_data->ddr)
219 return NULL;
220 return &dpll_data->ddr[sysclk_ind];
221 }
223 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
224 u8 lock, char *dpll)
225 {
226 u32 temp, M, N;
227 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
229 if (!params)
230 return;
232 temp = readl(&dpll_regs->cm_clksel_dpll);
234 if (check_for_lock(base)) {
235 /*
236 * The Dpll has already been locked by rom code using CH.
237 * Check if M,N are matching with Ideal nominal opp values.
238 * If matches, skip the rest otherwise relock.
239 */
240 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
241 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
242 if ((M != (params->m)) || (N != (params->n))) {
243 debug("\n %s Dpll locked, but not for ideal M = %d,"
244 "N = %d values, current values are M = %d,"
245 "N= %d" , dpll, params->m, params->n,
246 M, N);
247 } else {
248 /* Dpll locked with ideal values for nominal opps. */
249 debug("\n %s Dpll already locked with ideal"
250 "nominal opp values", dpll);
251 goto setup_post_dividers;
252 }
253 }
255 bypass_dpll(base);
257 /* Set M & N */
258 temp &= ~CM_CLKSEL_DPLL_M_MASK;
259 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
261 temp &= ~CM_CLKSEL_DPLL_N_MASK;
262 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
264 writel(temp, &dpll_regs->cm_clksel_dpll);
266 /* Lock */
267 if (lock)
268 do_lock_dpll(base);
270 setup_post_dividers:
271 setup_post_dividers(base, params);
273 /* Wait till the DPLL locks */
274 if (lock)
275 wait_for_lock(base);
276 }
278 u32 omap_ddr_clk(void)
279 {
280 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
281 const struct dpll_params *core_dpll_params;
283 omap_rev = omap_revision();
284 sys_clk_khz = get_sys_clk_freq() / 1000;
286 core_dpll_params = get_core_dpll_params(*dplls_data);
288 debug("sys_clk %d\n ", sys_clk_khz * 1000);
290 /* Find Core DPLL locked frequency first */
291 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
292 (core_dpll_params->n + 1);
294 if (omap_rev < OMAP5430_ES1_0) {
295 /*
296 * DDR frequency is PHY_ROOT_CLK/2
297 * PHY_ROOT_CLK = Fdpll/2/M2
298 */
299 divider = 4;
300 } else {
301 /*
302 * DDR frequency is PHY_ROOT_CLK
303 * PHY_ROOT_CLK = Fdpll/2/M2
304 */
305 divider = 2;
306 }
308 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
309 ddr_clk *= 1000; /* convert to Hz */
310 debug("ddr_clk %d\n ", ddr_clk);
312 return ddr_clk;
313 }
315 /*
316 * Lock MPU dpll
317 *
318 * Resulting MPU frequencies:
319 * 4430 ES1.0 : 600 MHz
320 * 4430 ES2.x : 792 MHz (OPP Turbo)
321 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
322 */
323 void configure_mpu_dpll(void)
324 {
325 const struct dpll_params *params;
326 struct dpll_regs *mpu_dpll_regs;
327 u32 omap_rev;
328 omap_rev = omap_revision();
330 /*
331 * DCC and clock divider settings for 4460.
332 * DCC is required, if more than a certain frequency is required.
333 * For, 4460 > 1GHZ.
334 * 5430 > 1.4GHZ.
335 */
336 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
337 mpu_dpll_regs =
338 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
339 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
340 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
341 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
342 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
343 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
344 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
345 CM_CLKSEL_DCC_EN_MASK);
346 }
348 params = get_mpu_dpll_params(*dplls_data);
350 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
351 debug("MPU DPLL locked\n");
352 }
354 #ifdef CONFIG_USB_EHCI_OMAP
355 static void setup_usb_dpll(void)
356 {
357 const struct dpll_params *params;
358 u32 sys_clk_khz, sd_div, num, den;
360 sys_clk_khz = get_sys_clk_freq() / 1000;
361 /*
362 * USB:
363 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
364 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
365 * - where CLKINP is sys_clk in MHz
366 * Use CLKINP in KHz and adjust the denominator accordingly so
367 * that we have enough accuracy and at the same time no overflow
368 */
369 params = get_usb_dpll_params(*dplls_data);
370 num = params->m * sys_clk_khz;
371 den = (params->n + 1) * 250 * 1000;
372 num += den - 1;
373 sd_div = num / den;
374 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
375 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
376 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
378 /* Now setup the dpll with the regular function */
379 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
380 }
381 #endif
383 static void setup_dplls(void)
384 {
385 u32 temp;
386 const struct dpll_params *params;
388 debug("setup_dplls\n");
390 /* CORE dpll */
391 params = get_core_dpll_params(*dplls_data); /* default - safest */
392 /*
393 * Do not lock the core DPLL now. Just set it up.
394 * Core DPLL will be locked after setting up EMIF
395 * using the FREQ_UPDATE method(freq_update_core())
396 */
397 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
398 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
399 DPLL_NO_LOCK, "core");
400 else
401 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
402 DPLL_LOCK, "core");
403 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
404 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
405 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
406 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
407 writel(temp, (*prcm)->cm_clksel_core);
408 debug("Core DPLL configured\n");
410 /* lock PER dpll */
411 params = get_per_dpll_params(*dplls_data);
412 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
413 params, DPLL_LOCK, "per");
414 debug("PER DPLL locked\n");
416 /* MPU dpll */
417 configure_mpu_dpll();
419 #ifdef CONFIG_USB_EHCI_OMAP
420 setup_usb_dpll();
421 #endif
422 params = get_ddr_dpll_params(*dplls_data);
423 do_setup_dpll((*prcm)->cm_clkmode_dpll_ddrphy,
424 params, DPLL_LOCK, "ddr");
425 }
427 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
428 static void setup_non_essential_dplls(void)
429 {
430 u32 abe_ref_clk;
431 const struct dpll_params *params;
433 /* IVA */
434 clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
435 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
437 params = get_iva_dpll_params(*dplls_data);
438 do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
440 /* Configure ABE dpll */
441 params = get_abe_dpll_params(*dplls_data);
442 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
443 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
444 #else
445 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
446 /*
447 * We need to enable some additional options to achieve
448 * 196.608MHz from 32768 Hz
449 */
450 setbits_le32((*prcm)->cm_clkmode_dpll_abe,
451 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
452 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
453 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
454 CM_CLKMODE_DPLL_REGM4XEN_MASK);
455 /* Spend 4 REFCLK cycles at each stage */
456 clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
457 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
458 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
459 #endif
461 /* Select the right reference clk */
462 clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
463 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
464 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
465 /* Lock the dpll */
466 do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
467 }
468 #endif
470 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic)
471 {
472 u32 offset_code;
474 volt_offset -= pmic->base_offset;
476 offset_code = (volt_offset + pmic->step - 1) / pmic->step;
478 /*
479 * Offset codes 1-6 all give the base voltage in Palmas
480 * Offset code 0 switches OFF the SMPS
481 */
482 return offset_code + pmic->start_code;
483 }
485 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic)
486 {
487 u32 offset_code;
488 u32 offset = volt_mv;
489 int ret = 0;
491 if (!volt_mv)
492 return;
494 pmic->pmic_bus_init();
495 /* See if we can first get the GPIO if needed */
496 if (pmic->gpio_en)
497 ret = gpio_request(pmic->gpio, "PMIC_GPIO");
499 if (ret < 0) {
500 printf("%s: gpio %d request failed %d\n", __func__,
501 pmic->gpio, ret);
502 return;
503 }
505 /* Pull the GPIO low to select SET0 register, while we program SET1 */
506 if (pmic->gpio_en)
507 gpio_direction_output(pmic->gpio, 0);
509 /* convert to uV for better accuracy in the calculations */
510 offset *= 1000;
512 offset_code = get_offset_code(offset, pmic);
514 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
515 offset_code);
517 if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code))
518 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
520 if (pmic->gpio_en)
521 gpio_direction_output(pmic->gpio, 1);
522 }
524 static u32 optimize_vcore_voltage(struct volts const *v)
525 {
526 u32 val;
527 if (!v->value)
528 return 0;
529 if (!v->efuse.reg)
530 return v->value;
532 switch (v->efuse.reg_bits) {
533 case 16:
534 val = readw(v->efuse.reg);
535 break;
536 case 32:
537 val = readl(v->efuse.reg);
538 break;
539 default:
540 printf("Error: efuse 0x%08x bits=%d unknown\n",
541 v->efuse.reg, v->efuse.reg_bits);
542 return v->value;
543 }
545 if (!val) {
546 printf("Error: efuse 0x%08x bits=%d val=0, using %d\n",
547 v->efuse.reg, v->efuse.reg_bits, v->value);
548 return v->value;
549 }
551 debug("%s:efuse 0x%08x bits=%d Vnom=%d, using efuse value %d\n",
552 __func__, v->efuse.reg, v->efuse.reg_bits, v->value, val);
553 return val;
554 }
556 /*
557 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
558 * We set the maximum voltages allowed here because Smart-Reflex is not
559 * enabled in bootloader. Voltage initialization in the kernel will set
560 * these to the nominal values after enabling Smart-Reflex
561 */
562 void scale_vcores(struct vcores_data const *vcores)
563 {
564 u32 val;
566 val = optimize_vcore_voltage(&vcores->core);
567 do_scale_vcore(vcores->core.addr, val, vcores->core.pmic);
569 val = optimize_vcore_voltage(&vcores->mpu);
570 do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic);
572 val = optimize_vcore_voltage(&vcores->mm);
573 do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
575 val = optimize_vcore_voltage(&vcores->gpu);
576 do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
578 val = optimize_vcore_voltage(&vcores->eve);
579 do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic);
581 val = optimize_vcore_voltage(&vcores->iva);
582 do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic);
584 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
585 /* Configure LDO SRAM "magic" bits */
586 writel(2, (*prcm)->prm_sldo_core_setup);
587 writel(2, (*prcm)->prm_sldo_mpu_setup);
588 writel(2, (*prcm)->prm_sldo_mm_setup);
589 }
590 }
592 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
593 {
594 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
595 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
596 debug("Enable clock domain - %x\n", clkctrl_reg);
597 }
599 static inline void wait_for_clk_enable(u32 clkctrl_addr)
600 {
601 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
602 u32 bound = LDELAY;
604 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
605 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
607 clkctrl = readl(clkctrl_addr);
608 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
609 MODULE_CLKCTRL_IDLEST_SHIFT;
610 if (--bound == 0) {
611 printf("Clock enable failed for 0x%x idlest 0x%x\n",
612 clkctrl_addr, clkctrl);
613 return;
614 }
615 }
616 }
618 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
619 u32 wait_for_enable)
620 {
621 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
622 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
623 debug("Enable clock module - %x\n", clkctrl_addr);
624 if (wait_for_enable)
625 wait_for_clk_enable(clkctrl_addr);
626 }
628 void freq_update_core(void)
629 {
630 u32 freq_config1 = 0;
631 const struct dpll_params *core_dpll_params;
632 u32 omap_rev = omap_revision();
634 core_dpll_params = get_core_dpll_params(*dplls_data);
635 /* Put EMIF clock domain in sw wakeup mode */
636 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
637 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
638 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
639 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
641 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
642 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
644 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
645 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
647 freq_config1 |= (core_dpll_params->m2 <<
648 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
649 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
651 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
652 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
653 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
654 puts("FREQ UPDATE procedure failed!!");
655 hang();
656 }
658 /*
659 * Putting EMIF in HW_AUTO is seen to be causing issues with
660 * EMIF clocks and the master DLL. Keep EMIF in SW_WKUP
661 * in OMAP5430 ES1.0 silicon
662 */
663 if (omap_rev != OMAP5430_ES1_0) {
664 /* Put EMIF clock domain back in hw auto mode */
665 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
666 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
667 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
668 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
669 }
670 }
672 void bypass_dpll(u32 const base)
673 {
674 do_bypass_dpll(base);
675 wait_for_bypass(base);
676 }
678 void lock_dpll(u32 const base)
679 {
680 do_lock_dpll(base);
681 wait_for_lock(base);
682 }
684 void setup_clocks_for_console(void)
685 {
686 /* Do not add any spl_debug prints in this function */
687 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
688 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
689 CD_CLKCTRL_CLKTRCTRL_SHIFT);
691 /* Enable all UARTs - console will be on one of them */
692 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
693 MODULE_CLKCTRL_MODULEMODE_MASK,
694 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
695 MODULE_CLKCTRL_MODULEMODE_SHIFT);
697 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
698 MODULE_CLKCTRL_MODULEMODE_MASK,
699 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
700 MODULE_CLKCTRL_MODULEMODE_SHIFT);
702 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
703 MODULE_CLKCTRL_MODULEMODE_MASK,
704 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
705 MODULE_CLKCTRL_MODULEMODE_SHIFT);
707 clrsetbits_le32((*prcm)->cm_l4per_uart4_clkctrl,
708 MODULE_CLKCTRL_MODULEMODE_MASK,
709 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
710 MODULE_CLKCTRL_MODULEMODE_SHIFT);
712 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
713 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
714 CD_CLKCTRL_CLKTRCTRL_SHIFT);
715 }
717 void do_enable_clocks(u32 const *clk_domains,
718 u32 const *clk_modules_hw_auto,
719 u32 const *clk_modules_explicit_en,
720 u8 wait_for_enable)
721 {
722 u32 i, max = 100;
724 /* Put the clock domains in SW_WKUP mode */
725 for (i = 0; (i < max) && clk_domains[i]; i++) {
726 enable_clock_domain(clk_domains[i],
727 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
728 }
730 /* Clock modules that need to be put in HW_AUTO */
731 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
732 enable_clock_module(clk_modules_hw_auto[i],
733 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
734 wait_for_enable);
735 };
737 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
738 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
739 enable_clock_module(clk_modules_explicit_en[i],
740 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
741 wait_for_enable);
742 };
744 /* Put the clock domains in HW_AUTO mode now */
745 for (i = 0; (i < max) && clk_domains[i]; i++) {
746 enable_clock_domain(clk_domains[i],
747 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
748 }
749 }
751 void prcm_init(void)
752 {
753 switch (omap_hw_init_context()) {
754 case OMAP_INIT_CONTEXT_SPL:
755 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
756 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
757 enable_basic_clocks();
758 timer_init();
759 scale_vcores(*omap_vcores);
760 setup_dplls();
761 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
762 setup_non_essential_dplls();
763 enable_non_essential_clocks();
764 #endif
765 setup_warmreset_time();
766 break;
767 default:
768 break;
769 }
771 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
772 enable_basic_uboot_clocks();
773 }
775 void gpi2c_init(void)
776 {
777 static int gpi2c = 1;
779 if (gpi2c) {
780 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
781 gpi2c = 0;
782 }
783 }