1 /*
2 * EMIF programming
3 *
4 * (C) Copyright 2010
5 * Texas Instruments, <www.ti.com>
6 *
7 * Aneesh V <aneesh@ti.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
28 #include <common.h>
29 #include <asm/emif.h>
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/utils.h>
34 #include <linux/compiler.h>
36 void set_lpmode_selfrefresh(u32 base)
37 {
38 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
39 u32 reg;
41 reg = readl(&emif->emif_pwr_mgmt_ctrl);
42 reg &= ~EMIF_REG_LP_MODE_MASK;
43 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
44 reg &= ~EMIF_REG_SR_TIM_MASK;
45 writel(reg, &emif->emif_pwr_mgmt_ctrl);
47 /* dummy read for the new SR_TIM to be loaded */
48 readl(&emif->emif_pwr_mgmt_ctrl);
49 }
51 void force_emif_self_refresh()
52 {
53 set_lpmode_selfrefresh(EMIF1_BASE);
54 set_lpmode_selfrefresh(EMIF2_BASE);
55 }
57 inline u32 emif_num(u32 base)
58 {
59 if (base == EMIF1_BASE)
60 return 1;
61 else if (base == EMIF2_BASE)
62 return 2;
63 else
64 return 0;
65 }
68 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
69 {
70 u32 mr;
71 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
73 mr_addr |= cs << EMIF_REG_CS_SHIFT;
74 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
75 if (omap_revision() == OMAP4430_ES2_0)
76 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
77 else
78 mr = readl(&emif->emif_lpddr2_mode_reg_data);
79 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
80 cs, mr_addr, mr);
81 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
82 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
83 ((mr & 0xff000000) >> 24) == (mr & 0xff))
84 return mr & 0xff;
85 else
86 return mr;
87 }
89 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
90 {
91 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
93 mr_addr |= cs << EMIF_REG_CS_SHIFT;
94 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
95 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
96 }
98 void emif_reset_phy(u32 base)
99 {
100 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
101 u32 iodft;
103 iodft = readl(&emif->emif_iodft_tlgc);
104 iodft |= EMIF_REG_RESET_PHY_MASK;
105 writel(iodft, &emif->emif_iodft_tlgc);
106 }
108 static void do_lpddr2_init(u32 base, u32 cs)
109 {
110 u32 mr_addr;
112 /* Wait till device auto initialization is complete */
113 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
114 ;
115 set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
116 /*
117 * tZQINIT = 1 us
118 * Enough loops assuming a maximum of 2GHz
119 */
121 sdelay(2000);
123 if (omap_revision() >= OMAP5430_ES1_0)
124 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
125 else
126 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
128 set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
130 /*
131 * Enable refresh along with writing MR2
132 * Encoding of RL in MR2 is (RL - 2)
133 */
134 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
135 set_mr(base, cs, mr_addr, RL_FINAL - 2);
137 if (omap_revision() >= OMAP5430_ES1_0)
138 set_mr(base, cs, LPDDR2_MR3, 0x1);
139 }
141 static void lpddr2_init(u32 base, const struct emif_regs *regs)
142 {
143 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
145 /* Not NVM */
146 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
148 /*
149 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
150 * when EMIF_SDRAM_CONFIG register is written
151 */
152 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
154 /*
155 * Set the SDRAM_CONFIG and PHY_CTRL for the
156 * un-locked frequency & default RL
157 */
158 writel(regs->sdram_config_init, &emif->emif_sdram_config);
159 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
161 do_ext_phy_settings(base, regs);
163 do_lpddr2_init(base, CS0);
164 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
165 do_lpddr2_init(base, CS1);
167 writel(regs->sdram_config, &emif->emif_sdram_config);
168 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
170 /* Enable refresh now */
171 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
173 }
175 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
176 {
177 }
179 void emif_update_timings(u32 base, const struct emif_regs *regs)
180 {
181 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
183 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
184 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
185 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
186 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
187 if (omap_revision() == OMAP4430_ES1_0) {
188 /* ES1 bug EMIF should be in force idle during freq_update */
189 writel(0, &emif->emif_pwr_mgmt_ctrl);
190 } else {
191 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
192 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
193 }
194 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
195 writel(regs->zq_config, &emif->emif_zq_config);
196 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
197 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
199 if (omap_revision() >= OMAP5430_ES1_0) {
200 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
201 &emif->emif_l3_config);
202 } else if (omap_revision() >= OMAP4460_ES1_0) {
203 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
204 &emif->emif_l3_config);
205 } else {
206 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
207 &emif->emif_l3_config);
208 }
209 }
211 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
212 {
213 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
215 /* keep sdram in self-refresh */
216 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
217 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
218 __udelay(130);
220 /*
221 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
222 * Invert clock adds an additional half cycle delay on the command
223 * interface. The additional half cycle, is usually meant to enable
224 * leveling in the situation that DQS is later than CK on the board.It
225 * also helps provide some additional margin for leveling.
226 */
227 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
228 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
229 __udelay(130);
231 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
232 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
234 /* Launch Full leveling */
235 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
237 /* Wait till full leveling is complete */
238 readl(&emif->emif_rd_wr_lvl_ctl);
239 __udelay(130);
241 /* Read data eye leveling no of samples */
242 config_data_eye_leveling_samples(base);
244 /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
245 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
246 __udelay(130);
248 /* Launch Incremental leveling */
249 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
250 __udelay(130);
251 }
253 static void ddr3_init(u32 base, const struct emif_regs *regs)
254 {
255 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
256 u32 *ext_phy_ctrl_base = 0;
257 u32 *emif_ext_phy_ctrl_base = 0;
258 u32 i = 0;
260 /*
261 * Set SDRAM_CONFIG and PHY control registers to locked frequency
262 * and RL =7. As the default values of the Mode Registers are not
263 * defined, contents of mode Registers must be fully initialized.
264 * H/W takes care of this initialization
265 */
266 writel(regs->sdram_config_init, &emif->emif_sdram_config);
268 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
270 /* Update timing registers */
271 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
272 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
273 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
275 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
276 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
278 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
279 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
281 /* Configure external phy control timing registers */
282 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
283 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
284 /* Update shadow registers */
285 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
286 }
288 /*
289 * external phy 6-24 registers do not change with
290 * ddr frequency
291 */
292 for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
293 writel(ddr3_ext_phy_ctrl_const_base[i],
294 emif_ext_phy_ctrl_base++);
295 /* Update shadow registers */
296 writel(ddr3_ext_phy_ctrl_const_base[i],
297 emif_ext_phy_ctrl_base++);
298 }
300 /* enable leveling */
301 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
303 ddr3_leveling(base, regs);
304 }
306 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
307 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
309 /*
310 * Organization and refresh requirements for LPDDR2 devices of different
311 * types and densities. Derived from JESD209-2 section 2.4
312 */
313 const struct lpddr2_addressing addressing_table[] = {
314 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
315 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
316 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
317 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
318 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
319 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
320 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
321 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
322 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
323 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
324 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
325 };
327 static const u32 lpddr2_density_2_size_in_mbytes[] = {
328 8, /* 64Mb */
329 16, /* 128Mb */
330 32, /* 256Mb */
331 64, /* 512Mb */
332 128, /* 1Gb */
333 256, /* 2Gb */
334 512, /* 4Gb */
335 1024, /* 8Gb */
336 2048, /* 16Gb */
337 4096 /* 32Gb */
338 };
340 /*
341 * Calculate the period of DDR clock from frequency value and set the
342 * denominator and numerator in global variables for easy access later
343 */
344 static void set_ddr_clk_period(u32 freq)
345 {
346 /*
347 * period = 1/freq
348 * period_in_ns = 10^9/freq
349 */
350 *T_num = 1000000000;
351 *T_den = freq;
352 cancel_out(T_num, T_den, 200);
354 }
356 /*
357 * Convert time in nano seconds to number of cycles of DDR clock
358 */
359 static inline u32 ns_2_cycles(u32 ns)
360 {
361 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
362 }
364 /*
365 * ns_2_cycles with the difference that the time passed is 2 times the actual
366 * value(to avoid fractions). The cycles returned is for the original value of
367 * the timing parameter
368 */
369 static inline u32 ns_x2_2_cycles(u32 ns)
370 {
371 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
372 }
374 /*
375 * Find addressing table index based on the device's type(S2 or S4) and
376 * density
377 */
378 s8 addressing_table_index(u8 type, u8 density, u8 width)
379 {
380 u8 index;
381 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
382 return -1;
384 /*
385 * Look at the way ADDR_TABLE_INDEX* values have been defined
386 * in emif.h compared to LPDDR2_DENSITY_* values
387 * The table is layed out in the increasing order of density
388 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
389 * at the end
390 */
391 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
392 index = ADDR_TABLE_INDEX1GS2;
393 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
394 index = ADDR_TABLE_INDEX2GS2;
395 else
396 index = density;
398 debug("emif: addressing table index %d\n", index);
400 return index;
401 }
403 /*
404 * Find the the right timing table from the array of timing
405 * tables of the device using DDR clock frequency
406 */
407 static const struct lpddr2_ac_timings *get_timings_table(const struct
408 lpddr2_ac_timings const *const *device_timings,
409 u32 freq)
410 {
411 u32 i, temp, freq_nearest;
412 const struct lpddr2_ac_timings *timings = 0;
414 emif_assert(freq <= MAX_LPDDR2_FREQ);
415 emif_assert(device_timings);
417 /*
418 * Start with the maximum allowed frequency - that is always safe
419 */
420 freq_nearest = MAX_LPDDR2_FREQ;
421 /*
422 * Find the timings table that has the max frequency value:
423 * i. Above or equal to the DDR frequency - safe
424 * ii. The lowest that satisfies condition (i) - optimal
425 */
426 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
427 temp = device_timings[i]->max_freq;
428 if ((temp >= freq) && (temp <= freq_nearest)) {
429 freq_nearest = temp;
430 timings = device_timings[i];
431 }
432 }
433 debug("emif: timings table: %d\n", freq_nearest);
434 return timings;
435 }
437 /*
438 * Finds the value of emif_sdram_config_reg
439 * All parameters are programmed based on the device on CS0.
440 * If there is a device on CS1, it will be same as that on CS0 or
441 * it will be NVM. We don't support NVM yet.
442 * If cs1_device pointer is NULL it is assumed that there is no device
443 * on CS1
444 */
445 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
446 const struct lpddr2_device_details *cs1_device,
447 const struct lpddr2_addressing *addressing,
448 u8 RL)
449 {
450 u32 config_reg = 0;
452 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
453 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
454 EMIF_REG_IBANK_POS_SHIFT;
456 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
458 config_reg |= RL << EMIF_REG_CL_SHIFT;
460 config_reg |= addressing->row_sz[cs0_device->io_width] <<
461 EMIF_REG_ROWSIZE_SHIFT;
463 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
465 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
466 EMIF_REG_EBANK_SHIFT;
468 config_reg |= addressing->col_sz[cs0_device->io_width] <<
469 EMIF_REG_PAGESIZE_SHIFT;
471 return config_reg;
472 }
474 static u32 get_sdram_ref_ctrl(u32 freq,
475 const struct lpddr2_addressing *addressing)
476 {
477 u32 ref_ctrl = 0, val = 0, freq_khz;
478 freq_khz = freq / 1000;
479 /*
480 * refresh rate to be set is 'tREFI * freq in MHz
481 * division by 10000 to account for khz and x10 in t_REFI_us_x10
482 */
483 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
484 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
486 return ref_ctrl;
487 }
489 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
490 const struct lpddr2_min_tck *min_tck,
491 const struct lpddr2_addressing *addressing)
492 {
493 u32 tim1 = 0, val = 0;
494 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
495 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
497 if (addressing->num_banks == BANKS8)
498 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
499 (4 * (*T_num)) - 1;
500 else
501 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
503 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
505 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
506 tim1 |= val << EMIF_REG_T_RC_SHIFT;
508 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
509 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
511 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
512 tim1 |= val << EMIF_REG_T_WR_SHIFT;
514 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
515 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
517 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
518 tim1 |= val << EMIF_REG_T_RP_SHIFT;
520 return tim1;
521 }
523 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
524 const struct lpddr2_min_tck *min_tck)
525 {
526 u32 tim2 = 0, val = 0;
527 val = max(min_tck->tCKE, timings->tCKE) - 1;
528 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
530 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
531 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
533 /*
534 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
535 * same value
536 */
537 val = ns_2_cycles(timings->tXSR) - 1;
538 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
539 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
541 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
542 tim2 |= val << EMIF_REG_T_XP_SHIFT;
544 return tim2;
545 }
547 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
548 const struct lpddr2_min_tck *min_tck,
549 const struct lpddr2_addressing *addressing)
550 {
551 u32 tim3 = 0, val = 0;
552 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
553 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
555 val = ns_2_cycles(timings->tRFCab) - 1;
556 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
558 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
559 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
561 val = ns_2_cycles(timings->tZQCS) - 1;
562 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
564 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
565 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
567 return tim3;
568 }
570 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
571 const struct lpddr2_addressing *addressing,
572 u8 volt_ramp)
573 {
574 u32 zq = 0, val = 0;
575 if (volt_ramp)
576 val =
577 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
578 addressing->t_REFI_us_x10;
579 else
580 val =
581 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
582 addressing->t_REFI_us_x10;
583 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
585 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
587 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
589 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
591 /*
592 * Assuming that two chipselects have a single calibration resistor
593 * If there are indeed two calibration resistors, then this flag should
594 * be enabled to take advantage of dual calibration feature.
595 * This data should ideally come from board files. But considering
596 * that none of the boards today have calibration resistors per CS,
597 * it would be an unnecessary overhead.
598 */
599 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
601 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
603 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
605 return zq;
606 }
608 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
609 const struct lpddr2_addressing *addressing,
610 u8 is_derated)
611 {
612 u32 alert = 0, interval;
613 interval =
614 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
615 if (is_derated)
616 interval *= 4;
617 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
619 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
621 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
623 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
625 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
627 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
629 return alert;
630 }
632 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
633 {
634 u32 idle = 0, val = 0;
635 if (volt_ramp)
636 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
637 else
638 /*Maximum value in normal conditions - suggested by hw team */
639 val = 0x1FF;
640 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
642 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
644 return idle;
645 }
647 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
648 {
649 u32 phy = 0, val = 0;
651 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
653 if (freq <= 100000000)
654 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
655 else if (freq <= 200000000)
656 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
657 else
658 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
659 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
661 /* Other fields are constant magic values. Hardcode them together */
662 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
663 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
665 return phy;
666 }
668 static u32 get_emif_mem_size(struct emif_device_details *devices)
669 {
670 u32 size_mbytes = 0, temp;
672 if (!devices)
673 return 0;
675 if (devices->cs0_device_details) {
676 temp = devices->cs0_device_details->density;
677 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
678 }
680 if (devices->cs1_device_details) {
681 temp = devices->cs1_device_details->density;
682 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
683 }
684 /* convert to bytes */
685 return size_mbytes << 20;
686 }
688 /* Gets the encoding corresponding to a given DMM section size */
689 u32 get_dmm_section_size_map(u32 section_size)
690 {
691 /*
692 * Section size mapping:
693 * 0x0: 16-MiB section
694 * 0x1: 32-MiB section
695 * 0x2: 64-MiB section
696 * 0x3: 128-MiB section
697 * 0x4: 256-MiB section
698 * 0x5: 512-MiB section
699 * 0x6: 1-GiB section
700 * 0x7: 2-GiB section
701 */
702 section_size >>= 24; /* divide by 16 MB */
703 return log_2_n_round_down(section_size);
704 }
706 static void emif_calculate_regs(
707 const struct emif_device_details *emif_dev_details,
708 u32 freq, struct emif_regs *regs)
709 {
710 u32 temp, sys_freq;
711 const struct lpddr2_addressing *addressing;
712 const struct lpddr2_ac_timings *timings;
713 const struct lpddr2_min_tck *min_tck;
714 const struct lpddr2_device_details *cs0_dev_details =
715 emif_dev_details->cs0_device_details;
716 const struct lpddr2_device_details *cs1_dev_details =
717 emif_dev_details->cs1_device_details;
718 const struct lpddr2_device_timings *cs0_dev_timings =
719 emif_dev_details->cs0_device_timings;
721 emif_assert(emif_dev_details);
722 emif_assert(regs);
723 /*
724 * You can not have a device on CS1 without one on CS0
725 * So configuring EMIF without a device on CS0 doesn't
726 * make sense
727 */
728 emif_assert(cs0_dev_details);
729 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
730 /*
731 * If there is a device on CS1 it should be same type as CS0
732 * (or NVM. But NVM is not supported in this driver yet)
733 */
734 emif_assert((cs1_dev_details == NULL) ||
735 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
736 (cs0_dev_details->type == cs1_dev_details->type));
737 emif_assert(freq <= MAX_LPDDR2_FREQ);
739 set_ddr_clk_period(freq);
741 /*
742 * The device on CS0 is used for all timing calculations
743 * There is only one set of registers for timings per EMIF. So, if the
744 * second CS(CS1) has a device, it should have the same timings as the
745 * device on CS0
746 */
747 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
748 emif_assert(timings);
749 min_tck = cs0_dev_timings->min_tck;
751 temp = addressing_table_index(cs0_dev_details->type,
752 cs0_dev_details->density,
753 cs0_dev_details->io_width);
755 emif_assert((temp >= 0));
756 addressing = &(addressing_table[temp]);
757 emif_assert(addressing);
759 sys_freq = get_sys_clk_freq();
761 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
762 cs1_dev_details,
763 addressing, RL_BOOT);
765 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
766 cs1_dev_details,
767 addressing, RL_FINAL);
769 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
771 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
773 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
775 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
777 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
779 regs->temp_alert_config =
780 get_temp_alert_config(cs1_dev_details, addressing, 0);
782 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
783 LPDDR2_VOLTAGE_STABLE);
785 regs->emif_ddr_phy_ctlr_1_init =
786 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
788 regs->emif_ddr_phy_ctlr_1 =
789 get_ddr_phy_ctrl_1(freq, RL_FINAL);
791 regs->freq = freq;
793 print_timing_reg(regs->sdram_config_init);
794 print_timing_reg(regs->sdram_config);
795 print_timing_reg(regs->ref_ctrl);
796 print_timing_reg(regs->sdram_tim1);
797 print_timing_reg(regs->sdram_tim2);
798 print_timing_reg(regs->sdram_tim3);
799 print_timing_reg(regs->read_idle_ctrl);
800 print_timing_reg(regs->temp_alert_config);
801 print_timing_reg(regs->zq_config);
802 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
803 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
804 }
805 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
807 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
808 const char *get_lpddr2_type(u8 type_id)
809 {
810 switch (type_id) {
811 case LPDDR2_TYPE_S4:
812 return "LPDDR2-S4";
813 case LPDDR2_TYPE_S2:
814 return "LPDDR2-S2";
815 default:
816 return NULL;
817 }
818 }
820 const char *get_lpddr2_io_width(u8 width_id)
821 {
822 switch (width_id) {
823 case LPDDR2_IO_WIDTH_8:
824 return "x8";
825 case LPDDR2_IO_WIDTH_16:
826 return "x16";
827 case LPDDR2_IO_WIDTH_32:
828 return "x32";
829 default:
830 return NULL;
831 }
832 }
834 const char *get_lpddr2_manufacturer(u32 manufacturer)
835 {
836 switch (manufacturer) {
837 case LPDDR2_MANUFACTURER_SAMSUNG:
838 return "Samsung";
839 case LPDDR2_MANUFACTURER_QIMONDA:
840 return "Qimonda";
841 case LPDDR2_MANUFACTURER_ELPIDA:
842 return "Elpida";
843 case LPDDR2_MANUFACTURER_ETRON:
844 return "Etron";
845 case LPDDR2_MANUFACTURER_NANYA:
846 return "Nanya";
847 case LPDDR2_MANUFACTURER_HYNIX:
848 return "Hynix";
849 case LPDDR2_MANUFACTURER_MOSEL:
850 return "Mosel";
851 case LPDDR2_MANUFACTURER_WINBOND:
852 return "Winbond";
853 case LPDDR2_MANUFACTURER_ESMT:
854 return "ESMT";
855 case LPDDR2_MANUFACTURER_SPANSION:
856 return "Spansion";
857 case LPDDR2_MANUFACTURER_SST:
858 return "SST";
859 case LPDDR2_MANUFACTURER_ZMOS:
860 return "ZMOS";
861 case LPDDR2_MANUFACTURER_INTEL:
862 return "Intel";
863 case LPDDR2_MANUFACTURER_NUMONYX:
864 return "Numonyx";
865 case LPDDR2_MANUFACTURER_MICRON:
866 return "Micron";
867 default:
868 return NULL;
869 }
870 }
872 static void display_sdram_details(u32 emif_nr, u32 cs,
873 struct lpddr2_device_details *device)
874 {
875 const char *mfg_str;
876 const char *type_str;
877 char density_str[10];
878 u32 density;
880 debug("EMIF%d CS%d\t", emif_nr, cs);
882 if (!device) {
883 debug("None\n");
884 return;
885 }
887 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
888 type_str = get_lpddr2_type(device->type);
890 density = lpddr2_density_2_size_in_mbytes[device->density];
891 if ((density / 1024 * 1024) == density) {
892 density /= 1024;
893 sprintf(density_str, "%d GB", density);
894 } else
895 sprintf(density_str, "%d MB", density);
896 if (mfg_str && type_str)
897 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
898 }
900 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
901 struct lpddr2_device_details *lpddr2_device)
902 {
903 u32 mr = 0, temp;
905 mr = get_mr(base, cs, LPDDR2_MR0);
906 if (mr > 0xFF) {
907 /* Mode register value bigger than 8 bit */
908 return 0;
909 }
911 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
912 if (temp) {
913 /* Not SDRAM */
914 return 0;
915 }
916 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
918 if (temp) {
919 /* DNV supported - But DNV is only supported for NVM */
920 return 0;
921 }
923 mr = get_mr(base, cs, LPDDR2_MR4);
924 if (mr > 0xFF) {
925 /* Mode register value bigger than 8 bit */
926 return 0;
927 }
929 mr = get_mr(base, cs, LPDDR2_MR5);
930 if (mr > 0xFF) {
931 /* Mode register value bigger than 8 bit */
932 return 0;
933 }
935 if (!get_lpddr2_manufacturer(mr)) {
936 /* Manufacturer not identified */
937 return 0;
938 }
939 lpddr2_device->manufacturer = mr;
941 mr = get_mr(base, cs, LPDDR2_MR6);
942 if (mr >= 0xFF) {
943 /* Mode register value bigger than 8 bit */
944 return 0;
945 }
947 mr = get_mr(base, cs, LPDDR2_MR7);
948 if (mr >= 0xFF) {
949 /* Mode register value bigger than 8 bit */
950 return 0;
951 }
953 mr = get_mr(base, cs, LPDDR2_MR8);
954 if (mr >= 0xFF) {
955 /* Mode register value bigger than 8 bit */
956 return 0;
957 }
959 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
960 if (!get_lpddr2_type(temp)) {
961 /* Not SDRAM */
962 return 0;
963 }
964 lpddr2_device->type = temp;
966 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
967 if (temp > LPDDR2_DENSITY_32Gb) {
968 /* Density not supported */
969 return 0;
970 }
971 lpddr2_device->density = temp;
973 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
974 if (!get_lpddr2_io_width(temp)) {
975 /* IO width unsupported value */
976 return 0;
977 }
978 lpddr2_device->io_width = temp;
980 /*
981 * If all the above tests pass we should
982 * have a device on this chip-select
983 */
984 return 1;
985 }
987 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
988 struct lpddr2_device_details *lpddr2_dev_details)
989 {
990 u32 phy;
991 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
993 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
995 if (!lpddr2_dev_details)
996 return NULL;
998 /* Do the minimum init for mode register accesses */
999 if (!(running_from_sdram() || warm_reset())) {
1000 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1001 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1002 }
1004 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1005 return NULL;
1007 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1009 return lpddr2_dev_details;
1010 }
1011 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1013 static void do_sdram_init(u32 base)
1014 {
1015 const struct emif_regs *regs;
1016 u32 in_sdram, emif_nr;
1018 debug(">>do_sdram_init() %x\n", base);
1020 in_sdram = running_from_sdram();
1021 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1023 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1024 emif_get_reg_dump(emif_nr, ®s);
1025 if (!regs) {
1026 debug("EMIF: reg dump not provided\n");
1027 return;
1028 }
1029 #else
1030 /*
1031 * The user has not provided the register values. We need to
1032 * calculate it based on the timings and the DDR frequency
1033 */
1034 struct emif_device_details dev_details;
1035 struct emif_regs calculated_regs;
1037 /*
1038 * Get device details:
1039 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1040 * - Obtained from user otherwise
1041 */
1042 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1043 emif_reset_phy(base);
1044 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1045 &cs0_dev_details);
1046 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1047 &cs1_dev_details);
1048 emif_reset_phy(base);
1050 /* Return if no devices on this EMIF */
1051 if (!dev_details.cs0_device_details &&
1052 !dev_details.cs1_device_details) {
1053 emif_sizes[emif_nr - 1] = 0;
1054 return;
1055 }
1057 if (!in_sdram)
1058 emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
1060 /*
1061 * Get device timings:
1062 * - Default timings specified by JESD209-2 if
1063 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1064 * - Obtained from user otherwise
1065 */
1066 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1067 &dev_details.cs1_device_timings);
1069 /* Calculate the register values */
1070 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1071 regs = &calculated_regs;
1072 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1074 /*
1075 * Initializing the LPDDR2 device can not happen from SDRAM.
1076 * Changing the timing registers in EMIF can happen(going from one
1077 * OPP to another)
1078 */
1079 if (!(in_sdram || warm_reset())) {
1080 if (omap_revision() != OMAP5432_ES1_0)
1081 lpddr2_init(base, regs);
1082 else
1083 ddr3_init(base, regs);
1084 }
1086 /* Write to the shadow registers */
1087 emif_update_timings(base, regs);
1089 debug("<<do_sdram_init() %x\n", base);
1090 }
1092 void emif_post_init_config(u32 base)
1093 {
1094 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1095 u32 omap_rev = omap_revision();
1097 if (omap_rev == OMAP5430_ES1_0)
1098 return;
1100 /* reset phy on ES2.0 */
1101 if (omap_rev == OMAP4430_ES2_0)
1102 emif_reset_phy(base);
1104 /* Put EMIF back in smart idle on ES1.0 */
1105 if (omap_rev == OMAP4430_ES1_0)
1106 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1107 }
1109 void dmm_init(u32 base)
1110 {
1111 const struct dmm_lisa_map_regs *lisa_map_regs;
1113 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1114 emif_get_dmm_regs(&lisa_map_regs);
1115 #else
1116 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1117 u32 section_cnt, sys_addr;
1118 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1120 mapped_size = 0;
1121 section_cnt = 3;
1122 sys_addr = CONFIG_SYS_SDRAM_BASE;
1123 emif1_size = emif_sizes[0];
1124 emif2_size = emif_sizes[1];
1125 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1127 if (!emif1_size && !emif2_size)
1128 return;
1130 /* symmetric interleaved section */
1131 if (emif1_size && emif2_size) {
1132 mapped_size = min(emif1_size, emif2_size);
1133 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1134 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1135 /* only MSB */
1136 section_map |= (sys_addr >> 24) <<
1137 EMIF_SYS_ADDR_SHIFT;
1138 section_map |= get_dmm_section_size_map(mapped_size * 2)
1139 << EMIF_SYS_SIZE_SHIFT;
1140 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1141 emif1_size -= mapped_size;
1142 emif2_size -= mapped_size;
1143 sys_addr += (mapped_size * 2);
1144 section_cnt--;
1145 }
1147 /*
1148 * Single EMIF section(we can have a maximum of 1 single EMIF
1149 * section- either EMIF1 or EMIF2 or none, but not both)
1150 */
1151 if (emif1_size) {
1152 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1153 section_map |= get_dmm_section_size_map(emif1_size)
1154 << EMIF_SYS_SIZE_SHIFT;
1155 /* only MSB */
1156 section_map |= (mapped_size >> 24) <<
1157 EMIF_SDRC_ADDR_SHIFT;
1158 /* only MSB */
1159 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1160 section_cnt--;
1161 }
1162 if (emif2_size) {
1163 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1164 section_map |= get_dmm_section_size_map(emif2_size) <<
1165 EMIF_SYS_SIZE_SHIFT;
1166 /* only MSB */
1167 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1168 /* only MSB */
1169 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1170 section_cnt--;
1171 }
1173 if (section_cnt == 2) {
1174 /* Only 1 section - either symmetric or single EMIF */
1175 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1176 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1177 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1178 } else {
1179 /* 2 sections - 1 symmetric, 1 single EMIF */
1180 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1181 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1182 }
1184 /* TRAP for invalid TILER mappings in section 0 */
1185 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1187 lisa_map_regs = &lis_map_regs_calculated;
1188 #endif
1189 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1190 (struct dmm_lisa_map_regs *)base;
1192 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1193 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1194 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1195 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1197 writel(lisa_map_regs->dmm_lisa_map_3,
1198 &hw_lisa_map_regs->dmm_lisa_map_3);
1199 writel(lisa_map_regs->dmm_lisa_map_2,
1200 &hw_lisa_map_regs->dmm_lisa_map_2);
1201 writel(lisa_map_regs->dmm_lisa_map_1,
1202 &hw_lisa_map_regs->dmm_lisa_map_1);
1203 writel(lisa_map_regs->dmm_lisa_map_0,
1204 &hw_lisa_map_regs->dmm_lisa_map_0);
1206 if (omap_revision() >= OMAP4460_ES1_0) {
1207 hw_lisa_map_regs =
1208 (struct dmm_lisa_map_regs *)MA_BASE;
1210 writel(lisa_map_regs->dmm_lisa_map_3,
1211 &hw_lisa_map_regs->dmm_lisa_map_3);
1212 writel(lisa_map_regs->dmm_lisa_map_2,
1213 &hw_lisa_map_regs->dmm_lisa_map_2);
1214 writel(lisa_map_regs->dmm_lisa_map_1,
1215 &hw_lisa_map_regs->dmm_lisa_map_1);
1216 writel(lisa_map_regs->dmm_lisa_map_0,
1217 &hw_lisa_map_regs->dmm_lisa_map_0);
1218 }
1219 }
1221 /*
1222 * SDRAM initialization:
1223 * SDRAM initialization has two parts:
1224 * 1. Configuring the SDRAM device
1225 * 2. Update the AC timings related parameters in the EMIF module
1226 * (1) should be done only once and should not be done while we are
1227 * running from SDRAM.
1228 * (2) can and should be done more than once if OPP changes.
1229 * Particularly, this may be needed when we boot without SPL and
1230 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1231 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1232 * the frequency. So,
1233 * Doing (1) and (2) makes sense - first time initialization
1234 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1235 * Doing (1) and not (2) doen't make sense
1236 * See do_sdram_init() for the details
1237 */
1238 void sdram_init(void)
1239 {
1240 u32 in_sdram, size_prog, size_detect;
1241 u32 omap_rev = omap_revision();
1243 debug(">>sdram_init()\n");
1245 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1246 return;
1248 in_sdram = running_from_sdram();
1249 debug("in_sdram = %d\n", in_sdram);
1251 if (!(in_sdram || warm_reset())) {
1252 if (omap_rev != OMAP5432_ES1_0)
1253 bypass_dpll(&prcm->cm_clkmode_dpll_core);
1254 else
1255 writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
1256 }
1258 do_sdram_init(EMIF1_BASE);
1259 do_sdram_init(EMIF2_BASE);
1261 if (!in_sdram)
1262 dmm_init(DMM_BASE);
1264 if (!(in_sdram || warm_reset())) {
1265 emif_post_init_config(EMIF1_BASE);
1266 emif_post_init_config(EMIF2_BASE);
1267 }
1269 /* for the shadow registers to take effect */
1270 if (omap_rev != OMAP5432_ES1_0)
1271 freq_update_core();
1273 /* Do some testing after the init */
1274 if (!in_sdram) {
1275 size_prog = omap_sdram_size();
1276 size_prog = log_2_n_round_down(size_prog);
1277 size_prog = (1 << size_prog);
1279 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1280 size_prog);
1281 /* Compare with the size programmed */
1282 if (size_detect != size_prog) {
1283 printf("SDRAM: identified size not same as expected"
1284 " size identified: %x expected: %x\n",
1285 size_detect,
1286 size_prog);
1287 } else
1288 debug("get_ram_size() successful");
1289 }
1291 debug("<<sdram_init()\n");
1292 }