1 /*
2 * EMIF programming
3 *
4 * (C) Copyright 2010
5 * Texas Instruments, <www.ti.com>
6 *
7 * Aneesh V <aneesh@ti.com>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
28 #include <common.h>
29 #include <asm/emif.h>
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/utils.h>
35 void set_lpmode_selfrefresh(u32 base)
36 {
37 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
38 u32 reg;
40 reg = readl(&emif->emif_pwr_mgmt_ctrl);
41 reg &= ~EMIF_REG_LP_MODE_MASK;
42 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
43 reg &= ~EMIF_REG_SR_TIM_MASK;
44 writel(reg, &emif->emif_pwr_mgmt_ctrl);
46 /* dummy read for the new SR_TIM to be loaded */
47 readl(&emif->emif_pwr_mgmt_ctrl);
48 }
50 void force_emif_self_refresh()
51 {
52 set_lpmode_selfrefresh(EMIF1_BASE);
53 set_lpmode_selfrefresh(EMIF2_BASE);
54 }
56 inline u32 emif_num(u32 base)
57 {
58 if (base == EMIF1_BASE)
59 return 1;
60 else if (base == EMIF2_BASE)
61 return 2;
62 else
63 return 0;
64 }
67 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
68 {
69 u32 mr;
70 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
72 mr_addr |= cs << EMIF_REG_CS_SHIFT;
73 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
74 if (omap_revision() == OMAP4430_ES2_0)
75 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
76 else
77 mr = readl(&emif->emif_lpddr2_mode_reg_data);
78 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
79 cs, mr_addr, mr);
80 return mr;
81 }
83 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
84 {
85 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
87 mr_addr |= cs << EMIF_REG_CS_SHIFT;
88 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
89 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
90 }
92 void emif_reset_phy(u32 base)
93 {
94 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
95 u32 iodft;
97 iodft = readl(&emif->emif_iodft_tlgc);
98 iodft |= EMIF_REG_RESET_PHY_MASK;
99 writel(iodft, &emif->emif_iodft_tlgc);
100 }
102 static void do_lpddr2_init(u32 base, u32 cs)
103 {
104 u32 mr_addr;
106 /* Wait till device auto initialization is complete */
107 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
108 ;
109 set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
110 /*
111 * tZQINIT = 1 us
112 * Enough loops assuming a maximum of 2GHz
113 */
115 sdelay(2000);
117 if (omap_revision() >= OMAP5430_ES1_0)
118 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
119 else
120 set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
122 set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
124 /*
125 * Enable refresh along with writing MR2
126 * Encoding of RL in MR2 is (RL - 2)
127 */
128 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
129 set_mr(base, cs, mr_addr, RL_FINAL - 2);
131 if (omap_revision() >= OMAP5430_ES1_0)
132 set_mr(base, cs, LPDDR2_MR3, 0x1);
133 }
135 static void lpddr2_init(u32 base, const struct emif_regs *regs)
136 {
137 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
138 u32 *ext_phy_ctrl_base = 0;
139 u32 *emif_ext_phy_ctrl_base = 0;
140 u32 i = 0;
142 /* Not NVM */
143 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
145 /*
146 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
147 * when EMIF_SDRAM_CONFIG register is written
148 */
149 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
151 /*
152 * Set the SDRAM_CONFIG and PHY_CTRL for the
153 * un-locked frequency & default RL
154 */
155 writel(regs->sdram_config_init, &emif->emif_sdram_config);
156 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
158 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
159 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
161 if (omap_revision() >= OMAP5430_ES1_0) {
162 /* Configure external phy control timing registers */
163 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
164 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
165 /* Update shadow registers */
166 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
167 }
169 /*
170 * external phy 6-24 registers do not change with
171 * ddr frequency
172 */
173 for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
174 writel(ext_phy_ctrl_const_base[i],
175 emif_ext_phy_ctrl_base++);
176 /* Update shadow registers */
177 writel(ext_phy_ctrl_const_base[i],
178 emif_ext_phy_ctrl_base++);
179 }
180 }
182 do_lpddr2_init(base, CS0);
183 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
184 do_lpddr2_init(base, CS1);
186 writel(regs->sdram_config, &emif->emif_sdram_config);
187 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
189 /* Enable refresh now */
190 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
192 }
194 void emif_update_timings(u32 base, const struct emif_regs *regs)
195 {
196 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
198 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
199 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
200 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
201 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
202 if (omap_revision() == OMAP4430_ES1_0) {
203 /* ES1 bug EMIF should be in force idle during freq_update */
204 writel(0, &emif->emif_pwr_mgmt_ctrl);
205 } else {
206 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
207 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
208 }
209 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
210 writel(regs->zq_config, &emif->emif_zq_config);
211 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
212 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
214 if (omap_revision() >= OMAP5430_ES1_0) {
215 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
216 &emif->emif_l3_config);
217 } else if (omap_revision() >= OMAP4460_ES1_0) {
218 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
219 &emif->emif_l3_config);
220 } else {
221 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
222 &emif->emif_l3_config);
223 }
224 }
226 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
227 {
228 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
230 /* keep sdram in self-refresh */
231 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
232 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
233 __udelay(130);
235 /*
236 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
237 * Invert clock adds an additional half cycle delay on the command
238 * interface. The additional half cycle, is usually meant to enable
239 * leveling in the situation that DQS is later than CK on the board.It
240 * also helps provide some additional margin for leveling.
241 */
242 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
243 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
244 __udelay(130);
246 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
247 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
249 /* Launch Full leveling */
250 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
252 /* Wait till full leveling is complete */
253 readl(&emif->emif_rd_wr_lvl_ctl);
254 __udelay(130);
256 /* Read data eye leveling no of samples */
257 config_data_eye_leveling_samples(base);
259 /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
260 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
261 __udelay(130);
263 /* Launch Incremental leveling */
264 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
265 __udelay(130);
266 }
268 static void ddr3_init(u32 base, const struct emif_regs *regs)
269 {
270 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
271 u32 *ext_phy_ctrl_base = 0;
272 u32 *emif_ext_phy_ctrl_base = 0;
273 u32 i = 0;
275 /*
276 * Set SDRAM_CONFIG and PHY control registers to locked frequency
277 * and RL =7. As the default values of the Mode Registers are not
278 * defined, contents of mode Registers must be fully initialized.
279 * H/W takes care of this initialization
280 */
281 writel(regs->sdram_config_init, &emif->emif_sdram_config);
283 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
285 /* Update timing registers */
286 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
287 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
288 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
290 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
291 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
293 ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
294 emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
296 /* Configure external phy control timing registers */
297 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
298 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
299 /* Update shadow registers */
300 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
301 }
303 /*
304 * external phy 6-24 registers do not change with
305 * ddr frequency
306 */
307 for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
308 writel(ddr3_ext_phy_ctrl_const_base[i],
309 emif_ext_phy_ctrl_base++);
310 /* Update shadow registers */
311 writel(ddr3_ext_phy_ctrl_const_base[i],
312 emif_ext_phy_ctrl_base++);
313 }
315 /* enable leveling */
316 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
318 ddr3_leveling(base, regs);
319 }
321 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
322 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
324 /*
325 * Organization and refresh requirements for LPDDR2 devices of different
326 * types and densities. Derived from JESD209-2 section 2.4
327 */
328 const struct lpddr2_addressing addressing_table[] = {
329 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
330 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
331 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
332 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
333 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
334 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
335 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
336 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
337 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
338 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
339 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
340 };
342 static const u32 lpddr2_density_2_size_in_mbytes[] = {
343 8, /* 64Mb */
344 16, /* 128Mb */
345 32, /* 256Mb */
346 64, /* 512Mb */
347 128, /* 1Gb */
348 256, /* 2Gb */
349 512, /* 4Gb */
350 1024, /* 8Gb */
351 2048, /* 16Gb */
352 4096 /* 32Gb */
353 };
355 /*
356 * Calculate the period of DDR clock from frequency value and set the
357 * denominator and numerator in global variables for easy access later
358 */
359 static void set_ddr_clk_period(u32 freq)
360 {
361 /*
362 * period = 1/freq
363 * period_in_ns = 10^9/freq
364 */
365 *T_num = 1000000000;
366 *T_den = freq;
367 cancel_out(T_num, T_den, 200);
369 }
371 /*
372 * Convert time in nano seconds to number of cycles of DDR clock
373 */
374 static inline u32 ns_2_cycles(u32 ns)
375 {
376 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
377 }
379 /*
380 * ns_2_cycles with the difference that the time passed is 2 times the actual
381 * value(to avoid fractions). The cycles returned is for the original value of
382 * the timing parameter
383 */
384 static inline u32 ns_x2_2_cycles(u32 ns)
385 {
386 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
387 }
389 /*
390 * Find addressing table index based on the device's type(S2 or S4) and
391 * density
392 */
393 s8 addressing_table_index(u8 type, u8 density, u8 width)
394 {
395 u8 index;
396 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
397 return -1;
399 /*
400 * Look at the way ADDR_TABLE_INDEX* values have been defined
401 * in emif.h compared to LPDDR2_DENSITY_* values
402 * The table is layed out in the increasing order of density
403 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
404 * at the end
405 */
406 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
407 index = ADDR_TABLE_INDEX1GS2;
408 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
409 index = ADDR_TABLE_INDEX2GS2;
410 else
411 index = density;
413 debug("emif: addressing table index %d\n", index);
415 return index;
416 }
418 /*
419 * Find the the right timing table from the array of timing
420 * tables of the device using DDR clock frequency
421 */
422 static const struct lpddr2_ac_timings *get_timings_table(const struct
423 lpddr2_ac_timings const *const *device_timings,
424 u32 freq)
425 {
426 u32 i, temp, freq_nearest;
427 const struct lpddr2_ac_timings *timings = 0;
429 emif_assert(freq <= MAX_LPDDR2_FREQ);
430 emif_assert(device_timings);
432 /*
433 * Start with the maximum allowed frequency - that is always safe
434 */
435 freq_nearest = MAX_LPDDR2_FREQ;
436 /*
437 * Find the timings table that has the max frequency value:
438 * i. Above or equal to the DDR frequency - safe
439 * ii. The lowest that satisfies condition (i) - optimal
440 */
441 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
442 temp = device_timings[i]->max_freq;
443 if ((temp >= freq) && (temp <= freq_nearest)) {
444 freq_nearest = temp;
445 timings = device_timings[i];
446 }
447 }
448 debug("emif: timings table: %d\n", freq_nearest);
449 return timings;
450 }
452 /*
453 * Finds the value of emif_sdram_config_reg
454 * All parameters are programmed based on the device on CS0.
455 * If there is a device on CS1, it will be same as that on CS0 or
456 * it will be NVM. We don't support NVM yet.
457 * If cs1_device pointer is NULL it is assumed that there is no device
458 * on CS1
459 */
460 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
461 const struct lpddr2_device_details *cs1_device,
462 const struct lpddr2_addressing *addressing,
463 u8 RL)
464 {
465 u32 config_reg = 0;
467 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
468 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
469 EMIF_REG_IBANK_POS_SHIFT;
471 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
473 config_reg |= RL << EMIF_REG_CL_SHIFT;
475 config_reg |= addressing->row_sz[cs0_device->io_width] <<
476 EMIF_REG_ROWSIZE_SHIFT;
478 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
480 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
481 EMIF_REG_EBANK_SHIFT;
483 config_reg |= addressing->col_sz[cs0_device->io_width] <<
484 EMIF_REG_PAGESIZE_SHIFT;
486 return config_reg;
487 }
489 static u32 get_sdram_ref_ctrl(u32 freq,
490 const struct lpddr2_addressing *addressing)
491 {
492 u32 ref_ctrl = 0, val = 0, freq_khz;
493 freq_khz = freq / 1000;
494 /*
495 * refresh rate to be set is 'tREFI * freq in MHz
496 * division by 10000 to account for khz and x10 in t_REFI_us_x10
497 */
498 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
499 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
501 return ref_ctrl;
502 }
504 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
505 const struct lpddr2_min_tck *min_tck,
506 const struct lpddr2_addressing *addressing)
507 {
508 u32 tim1 = 0, val = 0;
509 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
510 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
512 if (addressing->num_banks == BANKS8)
513 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
514 (4 * (*T_num)) - 1;
515 else
516 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
518 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
520 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
521 tim1 |= val << EMIF_REG_T_RC_SHIFT;
523 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
524 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
526 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
527 tim1 |= val << EMIF_REG_T_WR_SHIFT;
529 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
530 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
532 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
533 tim1 |= val << EMIF_REG_T_RP_SHIFT;
535 return tim1;
536 }
538 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
539 const struct lpddr2_min_tck *min_tck)
540 {
541 u32 tim2 = 0, val = 0;
542 val = max(min_tck->tCKE, timings->tCKE) - 1;
543 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
545 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
546 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
548 /*
549 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
550 * same value
551 */
552 val = ns_2_cycles(timings->tXSR) - 1;
553 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
554 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
556 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
557 tim2 |= val << EMIF_REG_T_XP_SHIFT;
559 return tim2;
560 }
562 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
563 const struct lpddr2_min_tck *min_tck,
564 const struct lpddr2_addressing *addressing)
565 {
566 u32 tim3 = 0, val = 0;
567 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
568 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
570 val = ns_2_cycles(timings->tRFCab) - 1;
571 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
573 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
574 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
576 val = ns_2_cycles(timings->tZQCS) - 1;
577 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
579 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
580 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
582 return tim3;
583 }
585 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
586 const struct lpddr2_addressing *addressing,
587 u8 volt_ramp)
588 {
589 u32 zq = 0, val = 0;
590 if (volt_ramp)
591 val =
592 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
593 addressing->t_REFI_us_x10;
594 else
595 val =
596 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
597 addressing->t_REFI_us_x10;
598 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
600 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
602 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
604 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
606 /*
607 * Assuming that two chipselects have a single calibration resistor
608 * If there are indeed two calibration resistors, then this flag should
609 * be enabled to take advantage of dual calibration feature.
610 * This data should ideally come from board files. But considering
611 * that none of the boards today have calibration resistors per CS,
612 * it would be an unnecessary overhead.
613 */
614 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
616 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
618 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
620 return zq;
621 }
623 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
624 const struct lpddr2_addressing *addressing,
625 u8 is_derated)
626 {
627 u32 alert = 0, interval;
628 interval =
629 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
630 if (is_derated)
631 interval *= 4;
632 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
634 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
636 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
638 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
640 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
642 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
644 return alert;
645 }
647 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
648 {
649 u32 idle = 0, val = 0;
650 if (volt_ramp)
651 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
652 else
653 /*Maximum value in normal conditions - suggested by hw team */
654 val = 0x1FF;
655 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
657 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
659 return idle;
660 }
662 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
663 {
664 u32 phy = 0, val = 0;
666 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
668 if (freq <= 100000000)
669 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
670 else if (freq <= 200000000)
671 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
672 else
673 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
674 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
676 /* Other fields are constant magic values. Hardcode them together */
677 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
678 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
680 return phy;
681 }
683 static u32 get_emif_mem_size(struct emif_device_details *devices)
684 {
685 u32 size_mbytes = 0, temp;
687 if (!devices)
688 return 0;
690 if (devices->cs0_device_details) {
691 temp = devices->cs0_device_details->density;
692 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
693 }
695 if (devices->cs1_device_details) {
696 temp = devices->cs1_device_details->density;
697 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
698 }
699 /* convert to bytes */
700 return size_mbytes << 20;
701 }
703 /* Gets the encoding corresponding to a given DMM section size */
704 u32 get_dmm_section_size_map(u32 section_size)
705 {
706 /*
707 * Section size mapping:
708 * 0x0: 16-MiB section
709 * 0x1: 32-MiB section
710 * 0x2: 64-MiB section
711 * 0x3: 128-MiB section
712 * 0x4: 256-MiB section
713 * 0x5: 512-MiB section
714 * 0x6: 1-GiB section
715 * 0x7: 2-GiB section
716 */
717 section_size >>= 24; /* divide by 16 MB */
718 return log_2_n_round_down(section_size);
719 }
721 static void emif_calculate_regs(
722 const struct emif_device_details *emif_dev_details,
723 u32 freq, struct emif_regs *regs)
724 {
725 u32 temp, sys_freq;
726 const struct lpddr2_addressing *addressing;
727 const struct lpddr2_ac_timings *timings;
728 const struct lpddr2_min_tck *min_tck;
729 const struct lpddr2_device_details *cs0_dev_details =
730 emif_dev_details->cs0_device_details;
731 const struct lpddr2_device_details *cs1_dev_details =
732 emif_dev_details->cs1_device_details;
733 const struct lpddr2_device_timings *cs0_dev_timings =
734 emif_dev_details->cs0_device_timings;
736 emif_assert(emif_dev_details);
737 emif_assert(regs);
738 /*
739 * You can not have a device on CS1 without one on CS0
740 * So configuring EMIF without a device on CS0 doesn't
741 * make sense
742 */
743 emif_assert(cs0_dev_details);
744 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
745 /*
746 * If there is a device on CS1 it should be same type as CS0
747 * (or NVM. But NVM is not supported in this driver yet)
748 */
749 emif_assert((cs1_dev_details == NULL) ||
750 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
751 (cs0_dev_details->type == cs1_dev_details->type));
752 emif_assert(freq <= MAX_LPDDR2_FREQ);
754 set_ddr_clk_period(freq);
756 /*
757 * The device on CS0 is used for all timing calculations
758 * There is only one set of registers for timings per EMIF. So, if the
759 * second CS(CS1) has a device, it should have the same timings as the
760 * device on CS0
761 */
762 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
763 emif_assert(timings);
764 min_tck = cs0_dev_timings->min_tck;
766 temp = addressing_table_index(cs0_dev_details->type,
767 cs0_dev_details->density,
768 cs0_dev_details->io_width);
770 emif_assert((temp >= 0));
771 addressing = &(addressing_table[temp]);
772 emif_assert(addressing);
774 sys_freq = get_sys_clk_freq();
776 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
777 cs1_dev_details,
778 addressing, RL_BOOT);
780 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
781 cs1_dev_details,
782 addressing, RL_FINAL);
784 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
786 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
788 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
790 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
792 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
794 regs->temp_alert_config =
795 get_temp_alert_config(cs1_dev_details, addressing, 0);
797 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
798 LPDDR2_VOLTAGE_STABLE);
800 regs->emif_ddr_phy_ctlr_1_init =
801 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
803 regs->emif_ddr_phy_ctlr_1 =
804 get_ddr_phy_ctrl_1(freq, RL_FINAL);
806 regs->freq = freq;
808 print_timing_reg(regs->sdram_config_init);
809 print_timing_reg(regs->sdram_config);
810 print_timing_reg(regs->ref_ctrl);
811 print_timing_reg(regs->sdram_tim1);
812 print_timing_reg(regs->sdram_tim2);
813 print_timing_reg(regs->sdram_tim3);
814 print_timing_reg(regs->read_idle_ctrl);
815 print_timing_reg(regs->temp_alert_config);
816 print_timing_reg(regs->zq_config);
817 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
818 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
819 }
820 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
822 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
823 const char *get_lpddr2_type(u8 type_id)
824 {
825 switch (type_id) {
826 case LPDDR2_TYPE_S4:
827 return "LPDDR2-S4";
828 case LPDDR2_TYPE_S2:
829 return "LPDDR2-S2";
830 default:
831 return NULL;
832 }
833 }
835 const char *get_lpddr2_io_width(u8 width_id)
836 {
837 switch (width_id) {
838 case LPDDR2_IO_WIDTH_8:
839 return "x8";
840 case LPDDR2_IO_WIDTH_16:
841 return "x16";
842 case LPDDR2_IO_WIDTH_32:
843 return "x32";
844 default:
845 return NULL;
846 }
847 }
849 const char *get_lpddr2_manufacturer(u32 manufacturer)
850 {
851 switch (manufacturer) {
852 case LPDDR2_MANUFACTURER_SAMSUNG:
853 return "Samsung";
854 case LPDDR2_MANUFACTURER_QIMONDA:
855 return "Qimonda";
856 case LPDDR2_MANUFACTURER_ELPIDA:
857 return "Elpida";
858 case LPDDR2_MANUFACTURER_ETRON:
859 return "Etron";
860 case LPDDR2_MANUFACTURER_NANYA:
861 return "Nanya";
862 case LPDDR2_MANUFACTURER_HYNIX:
863 return "Hynix";
864 case LPDDR2_MANUFACTURER_MOSEL:
865 return "Mosel";
866 case LPDDR2_MANUFACTURER_WINBOND:
867 return "Winbond";
868 case LPDDR2_MANUFACTURER_ESMT:
869 return "ESMT";
870 case LPDDR2_MANUFACTURER_SPANSION:
871 return "Spansion";
872 case LPDDR2_MANUFACTURER_SST:
873 return "SST";
874 case LPDDR2_MANUFACTURER_ZMOS:
875 return "ZMOS";
876 case LPDDR2_MANUFACTURER_INTEL:
877 return "Intel";
878 case LPDDR2_MANUFACTURER_NUMONYX:
879 return "Numonyx";
880 case LPDDR2_MANUFACTURER_MICRON:
881 return "Micron";
882 default:
883 return NULL;
884 }
885 }
887 static void display_sdram_details(u32 emif_nr, u32 cs,
888 struct lpddr2_device_details *device)
889 {
890 const char *mfg_str;
891 const char *type_str;
892 char density_str[10];
893 u32 density;
895 debug("EMIF%d CS%d\t", emif_nr, cs);
897 if (!device) {
898 debug("None\n");
899 return;
900 }
902 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
903 type_str = get_lpddr2_type(device->type);
905 density = lpddr2_density_2_size_in_mbytes[device->density];
906 if ((density / 1024 * 1024) == density) {
907 density /= 1024;
908 sprintf(density_str, "%d GB", density);
909 } else
910 sprintf(density_str, "%d MB", density);
911 if (mfg_str && type_str)
912 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
913 }
915 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
916 struct lpddr2_device_details *lpddr2_device)
917 {
918 u32 mr = 0, temp;
920 mr = get_mr(base, cs, LPDDR2_MR0);
921 if (mr > 0xFF) {
922 /* Mode register value bigger than 8 bit */
923 return 0;
924 }
926 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
927 if (temp) {
928 /* Not SDRAM */
929 return 0;
930 }
931 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
933 if (temp) {
934 /* DNV supported - But DNV is only supported for NVM */
935 return 0;
936 }
938 mr = get_mr(base, cs, LPDDR2_MR4);
939 if (mr > 0xFF) {
940 /* Mode register value bigger than 8 bit */
941 return 0;
942 }
944 mr = get_mr(base, cs, LPDDR2_MR5);
945 if (mr >= 0xFF) {
946 /* Mode register value bigger than 8 bit */
947 return 0;
948 }
950 if (!get_lpddr2_manufacturer(mr)) {
951 /* Manufacturer not identified */
952 return 0;
953 }
954 lpddr2_device->manufacturer = mr;
956 mr = get_mr(base, cs, LPDDR2_MR6);
957 if (mr >= 0xFF) {
958 /* Mode register value bigger than 8 bit */
959 return 0;
960 }
962 mr = get_mr(base, cs, LPDDR2_MR7);
963 if (mr >= 0xFF) {
964 /* Mode register value bigger than 8 bit */
965 return 0;
966 }
968 mr = get_mr(base, cs, LPDDR2_MR8);
969 if (mr >= 0xFF) {
970 /* Mode register value bigger than 8 bit */
971 return 0;
972 }
974 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
975 if (!get_lpddr2_type(temp)) {
976 /* Not SDRAM */
977 return 0;
978 }
979 lpddr2_device->type = temp;
981 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
982 if (temp > LPDDR2_DENSITY_32Gb) {
983 /* Density not supported */
984 return 0;
985 }
986 lpddr2_device->density = temp;
988 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
989 if (!get_lpddr2_io_width(temp)) {
990 /* IO width unsupported value */
991 return 0;
992 }
993 lpddr2_device->io_width = temp;
995 /*
996 * If all the above tests pass we should
997 * have a device on this chip-select
998 */
999 return 1;
1000 }
1002 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1003 struct lpddr2_device_details *lpddr2_dev_details)
1004 {
1005 u32 phy;
1006 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1008 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1010 if (!lpddr2_dev_details)
1011 return NULL;
1013 /* Do the minimum init for mode register accesses */
1014 if (!(running_from_sdram() || warm_reset())) {
1015 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1016 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1017 }
1019 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1020 return NULL;
1022 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1024 return lpddr2_dev_details;
1025 }
1026 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1028 static void do_sdram_init(u32 base)
1029 {
1030 const struct emif_regs *regs;
1031 u32 in_sdram, emif_nr;
1033 debug(">>do_sdram_init() %x\n", base);
1035 in_sdram = running_from_sdram();
1036 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1038 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1039 emif_get_reg_dump(emif_nr, ®s);
1040 if (!regs) {
1041 debug("EMIF: reg dump not provided\n");
1042 return;
1043 }
1044 #else
1045 /*
1046 * The user has not provided the register values. We need to
1047 * calculate it based on the timings and the DDR frequency
1048 */
1049 struct emif_device_details dev_details;
1050 struct emif_regs calculated_regs;
1052 /*
1053 * Get device details:
1054 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1055 * - Obtained from user otherwise
1056 */
1057 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1058 emif_reset_phy(base);
1059 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1060 &cs0_dev_details);
1061 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1062 &cs1_dev_details);
1063 emif_reset_phy(base);
1065 /* Return if no devices on this EMIF */
1066 if (!dev_details.cs0_device_details &&
1067 !dev_details.cs1_device_details) {
1068 emif_sizes[emif_nr - 1] = 0;
1069 return;
1070 }
1072 if (!in_sdram)
1073 emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
1075 /*
1076 * Get device timings:
1077 * - Default timings specified by JESD209-2 if
1078 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1079 * - Obtained from user otherwise
1080 */
1081 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1082 &dev_details.cs1_device_timings);
1084 /* Calculate the register values */
1085 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1086 regs = &calculated_regs;
1087 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1089 /*
1090 * Initializing the LPDDR2 device can not happen from SDRAM.
1091 * Changing the timing registers in EMIF can happen(going from one
1092 * OPP to another)
1093 */
1094 if (!(in_sdram || warm_reset())) {
1095 if (omap_revision() != OMAP5432_ES1_0)
1096 lpddr2_init(base, regs);
1097 else
1098 ddr3_init(base, regs);
1099 }
1101 /* Write to the shadow registers */
1102 emif_update_timings(base, regs);
1104 debug("<<do_sdram_init() %x\n", base);
1105 }
1107 void emif_post_init_config(u32 base)
1108 {
1109 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1110 u32 omap_rev = omap_revision();
1112 if (omap_rev == OMAP5430_ES1_0)
1113 return;
1115 /* reset phy on ES2.0 */
1116 if (omap_rev == OMAP4430_ES2_0)
1117 emif_reset_phy(base);
1119 /* Put EMIF back in smart idle on ES1.0 */
1120 if (omap_rev == OMAP4430_ES1_0)
1121 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1122 }
1124 void dmm_init(u32 base)
1125 {
1126 const struct dmm_lisa_map_regs *lisa_map_regs;
1128 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1129 emif_get_dmm_regs(&lisa_map_regs);
1130 #else
1131 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1132 u32 section_cnt, sys_addr;
1133 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1135 mapped_size = 0;
1136 section_cnt = 3;
1137 sys_addr = CONFIG_SYS_SDRAM_BASE;
1138 emif1_size = emif_sizes[0];
1139 emif2_size = emif_sizes[1];
1140 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1142 if (!emif1_size && !emif2_size)
1143 return;
1145 /* symmetric interleaved section */
1146 if (emif1_size && emif2_size) {
1147 mapped_size = min(emif1_size, emif2_size);
1148 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1149 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1150 /* only MSB */
1151 section_map |= (sys_addr >> 24) <<
1152 EMIF_SYS_ADDR_SHIFT;
1153 section_map |= get_dmm_section_size_map(mapped_size * 2)
1154 << EMIF_SYS_SIZE_SHIFT;
1155 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1156 emif1_size -= mapped_size;
1157 emif2_size -= mapped_size;
1158 sys_addr += (mapped_size * 2);
1159 section_cnt--;
1160 }
1162 /*
1163 * Single EMIF section(we can have a maximum of 1 single EMIF
1164 * section- either EMIF1 or EMIF2 or none, but not both)
1165 */
1166 if (emif1_size) {
1167 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1168 section_map |= get_dmm_section_size_map(emif1_size)
1169 << EMIF_SYS_SIZE_SHIFT;
1170 /* only MSB */
1171 section_map |= (mapped_size >> 24) <<
1172 EMIF_SDRC_ADDR_SHIFT;
1173 /* only MSB */
1174 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1175 section_cnt--;
1176 }
1177 if (emif2_size) {
1178 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1179 section_map |= get_dmm_section_size_map(emif2_size) <<
1180 EMIF_SYS_SIZE_SHIFT;
1181 /* only MSB */
1182 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1183 /* only MSB */
1184 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1185 section_cnt--;
1186 }
1188 if (section_cnt == 2) {
1189 /* Only 1 section - either symmetric or single EMIF */
1190 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1191 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1192 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1193 } else {
1194 /* 2 sections - 1 symmetric, 1 single EMIF */
1195 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1196 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1197 }
1199 /* TRAP for invalid TILER mappings in section 0 */
1200 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1202 lisa_map_regs = &lis_map_regs_calculated;
1203 #endif
1204 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1205 (struct dmm_lisa_map_regs *)base;
1207 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1208 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1209 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1210 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1212 writel(lisa_map_regs->dmm_lisa_map_3,
1213 &hw_lisa_map_regs->dmm_lisa_map_3);
1214 writel(lisa_map_regs->dmm_lisa_map_2,
1215 &hw_lisa_map_regs->dmm_lisa_map_2);
1216 writel(lisa_map_regs->dmm_lisa_map_1,
1217 &hw_lisa_map_regs->dmm_lisa_map_1);
1218 writel(lisa_map_regs->dmm_lisa_map_0,
1219 &hw_lisa_map_regs->dmm_lisa_map_0);
1221 if (omap_revision() >= OMAP4460_ES1_0) {
1222 hw_lisa_map_regs =
1223 (struct dmm_lisa_map_regs *)MA_BASE;
1225 writel(lisa_map_regs->dmm_lisa_map_3,
1226 &hw_lisa_map_regs->dmm_lisa_map_3);
1227 writel(lisa_map_regs->dmm_lisa_map_2,
1228 &hw_lisa_map_regs->dmm_lisa_map_2);
1229 writel(lisa_map_regs->dmm_lisa_map_1,
1230 &hw_lisa_map_regs->dmm_lisa_map_1);
1231 writel(lisa_map_regs->dmm_lisa_map_0,
1232 &hw_lisa_map_regs->dmm_lisa_map_0);
1233 }
1234 }
1236 /*
1237 * SDRAM initialization:
1238 * SDRAM initialization has two parts:
1239 * 1. Configuring the SDRAM device
1240 * 2. Update the AC timings related parameters in the EMIF module
1241 * (1) should be done only once and should not be done while we are
1242 * running from SDRAM.
1243 * (2) can and should be done more than once if OPP changes.
1244 * Particularly, this may be needed when we boot without SPL and
1245 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1246 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1247 * the frequency. So,
1248 * Doing (1) and (2) makes sense - first time initialization
1249 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1250 * Doing (1) and not (2) doen't make sense
1251 * See do_sdram_init() for the details
1252 */
1253 void sdram_init(void)
1254 {
1255 u32 in_sdram, size_prog, size_detect;
1256 u32 omap_rev = omap_revision();
1258 debug(">>sdram_init()\n");
1260 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1261 return;
1263 in_sdram = running_from_sdram();
1264 debug("in_sdram = %d\n", in_sdram);
1266 if (!(in_sdram || warm_reset())) {
1267 if (omap_rev != OMAP5432_ES1_0)
1268 bypass_dpll(&prcm->cm_clkmode_dpll_core);
1269 else
1270 writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl);
1271 }
1273 do_sdram_init(EMIF1_BASE);
1274 do_sdram_init(EMIF2_BASE);
1276 if (!in_sdram)
1277 dmm_init(DMM_BASE);
1279 if (!(in_sdram || warm_reset())) {
1280 emif_post_init_config(EMIF1_BASE);
1281 emif_post_init_config(EMIF2_BASE);
1282 }
1284 /* for the shadow registers to take effect */
1285 if (omap_rev != OMAP5432_ES1_0)
1286 freq_update_core();
1288 /* Do some testing after the init */
1289 if (!in_sdram) {
1290 size_prog = omap_sdram_size();
1291 size_prog = log_2_n_round_down(size_prog);
1292 size_prog = (1 << size_prog);
1294 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1295 size_prog);
1296 /* Compare with the size programmed */
1297 if (size_detect != size_prog) {
1298 printf("SDRAM: identified size not same as expected"
1299 " size identified: %x expected: %x\n",
1300 size_detect,
1301 size_prog);
1302 } else
1303 debug("get_ram_size() successful");
1304 }
1306 debug("<<sdram_init()\n");
1307 }