1 /*
2 *
3 * Common functions for OMAP4/5 based boards
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30 #include <common.h>
31 #include <spl.h>
32 #include <asm/arch/sys_proto.h>
33 #include <asm/sizes.h>
34 #include <asm/emif.h>
35 #include <asm/omap_common.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
40 {
41 int i;
42 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
44 for (i = 0; i < size; i++, pad++)
45 writew(pad->val, base + pad->offset);
46 }
48 static void set_mux_conf_regs(void)
49 {
50 switch (omap_hw_init_context()) {
51 case OMAP_INIT_CONTEXT_SPL:
52 set_muxconf_regs_essential();
53 break;
54 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
55 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
56 set_muxconf_regs_non_essential();
57 #endif
58 break;
59 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
60 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
61 set_muxconf_regs_essential();
62 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
63 set_muxconf_regs_non_essential();
64 #endif
65 break;
66 }
67 }
69 u32 cortex_rev(void)
70 {
72 unsigned int rev;
74 /* Read Main ID Register (MIDR) */
75 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
77 return rev;
78 }
80 void omap_rev_string(void)
81 {
82 u32 omap_rev = omap_revision();
83 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
84 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
85 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
87 printf("OMAP%x ES%x.%x\n", omap_variant, major_rev,
88 minor_rev);
89 }
91 #ifdef CONFIG_SPL_BUILD
92 static void init_boot_params(void)
93 {
94 boot_params_ptr = (u32 *) &boot_params;
95 }
97 void spl_display_print(void)
98 {
99 omap_rev_string();
100 }
101 #endif
103 /*
104 * Routine: s_init
105 * Description: Does early system init of watchdog, muxing, andclocks
106 * Watchdog disable is done always. For the rest what gets done
107 * depends on the boot mode in which this function is executed
108 * 1. s_init of SPL running from SRAM
109 * 2. s_init of U-Boot running from FLASH
110 * 3. s_init of U-Boot loaded to SDRAM by SPL
111 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
112 * Configuration Header feature
113 * Please have a look at the respective functions to see what gets
114 * done in each of these cases
115 * This function is called with SRAM stack.
116 */
117 void s_init(void)
118 {
119 init_omap_revision();
120 hw_data_init();
122 #ifdef CONFIG_SPL_BUILD
123 if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
124 force_emif_self_refresh();
125 #endif
126 watchdog_init();
127 set_mux_conf_regs();
128 #ifdef CONFIG_SPL_BUILD
129 setup_clocks_for_console();
131 gd = &gdata;
133 preloader_console_init();
134 do_io_settings();
135 #endif
136 prcm_init();
137 #ifdef CONFIG_SPL_BUILD
138 timer_init();
140 /* For regular u-boot sdram_init() is called from dram_init() */
141 sdram_init();
142 init_boot_params();
143 #endif
144 }
146 /*
147 * Routine: wait_for_command_complete
148 * Description: Wait for posting to finish on watchdog
149 */
150 void wait_for_command_complete(struct watchdog *wd_base)
151 {
152 int pending = 1;
153 do {
154 pending = readl(&wd_base->wwps);
155 } while (pending);
156 }
158 /*
159 * Routine: watchdog_init
160 * Description: Shut down watch dogs
161 */
162 void watchdog_init(void)
163 {
164 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
166 writel(WD_UNLOCK1, &wd2_base->wspr);
167 wait_for_command_complete(wd2_base);
168 writel(WD_UNLOCK2, &wd2_base->wspr);
169 }
172 /*
173 * This function finds the SDRAM size available in the system
174 * based on DMM section configurations
175 * This is needed because the size of memory installed may be
176 * different on different versions of the board
177 */
178 u32 omap_sdram_size(void)
179 {
180 u32 section, i, valid;
181 u64 sdram_start = 0, sdram_end = 0, addr,
182 size, total_size = 0, trap_size = 0;
184 for (i = 0; i < 4; i++) {
185 section = __raw_readl(DMM_BASE + i*4);
186 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
187 (EMIF_SDRC_ADDRSPC_SHIFT);
188 addr = section & EMIF_SYS_ADDR_MASK;
190 /* See if the address is valid */
191 if ((addr >= DRAM_ADDR_SPACE_START) &&
192 (addr < DRAM_ADDR_SPACE_END)) {
193 size = ((section & EMIF_SYS_SIZE_MASK) >>
194 EMIF_SYS_SIZE_SHIFT);
195 size = 1 << size;
196 size *= SZ_16M;
198 if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
199 if (!sdram_start || (addr < sdram_start))
200 sdram_start = addr;
201 if (!sdram_end || ((addr + size) > sdram_end))
202 sdram_end = addr + size;
203 } else {
204 trap_size = size;
205 }
207 }
209 }
210 total_size = (sdram_end - sdram_start) - (trap_size);
212 return total_size;
213 }
216 /*
217 * Routine: dram_init
218 * Description: sets uboots idea of sdram size
219 */
220 int dram_init(void)
221 {
222 sdram_init();
223 gd->ram_size = omap_sdram_size();
224 return 0;
225 }
227 /*
228 * Print board information
229 */
230 int checkboard(void)
231 {
232 puts(sysinfo.board_string);
233 return 0;
234 }
236 /*
237 * get_device_type(): tell if GP/HS/EMU/TST
238 */
239 u32 get_device_type(void)
240 {
241 struct omap_sys_ctrl_regs *ctrl =
242 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
244 return (readl(&ctrl->control_status) &
245 (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
246 }
248 /*
249 * Print CPU information
250 */
251 int print_cpuinfo(void)
252 {
253 puts("CPU : ");
254 omap_rev_string();
256 return 0;
257 }
258 #ifndef CONFIG_SYS_DCACHE_OFF
259 void enable_caches(void)
260 {
261 /* Enable D-cache. I-cache is already enabled in start.S */
262 dcache_enable();
263 }
264 #endif