1 /*
2 *
3 * Common functions for OMAP4/5 based boards
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30 #include <common.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/sizes.h>
33 #include <asm/emif.h>
34 #include <asm/omap_common.h>
36 DECLARE_GLOBAL_DATA_PTR;
38 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
39 {
40 int i;
41 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
43 for (i = 0; i < size; i++, pad++)
44 writew(pad->val, base + pad->offset);
45 }
47 static void set_mux_conf_regs(void)
48 {
49 switch (omap_hw_init_context()) {
50 case OMAP_INIT_CONTEXT_SPL:
51 set_muxconf_regs_essential();
52 break;
53 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
54 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
55 set_muxconf_regs_non_essential();
56 #endif
57 break;
58 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
59 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
60 set_muxconf_regs_essential();
61 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
62 set_muxconf_regs_non_essential();
63 #endif
64 break;
65 }
66 }
68 u32 cortex_rev(void)
69 {
71 unsigned int rev;
73 /* Read Main ID Register (MIDR) */
74 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
76 return rev;
77 }
79 void omap_rev_string(void)
80 {
81 u32 omap_rev = omap_revision();
82 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
83 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
84 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
86 printf("OMAP%x ES%x.%x\n", omap_variant, major_rev,
87 minor_rev);
88 }
90 #ifdef CONFIG_SPL_BUILD
91 static void init_boot_params(void)
92 {
93 boot_params_ptr = (u32 *) &boot_params;
94 }
95 #endif
97 /*
98 * Routine: s_init
99 * Description: Does early system init of watchdog, muxing, andclocks
100 * Watchdog disable is done always. For the rest what gets done
101 * depends on the boot mode in which this function is executed
102 * 1. s_init of SPL running from SRAM
103 * 2. s_init of U-Boot running from FLASH
104 * 3. s_init of U-Boot loaded to SDRAM by SPL
105 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
106 * Configuration Header feature
107 * Please have a look at the respective functions to see what gets
108 * done in each of these cases
109 * This function is called with SRAM stack.
110 */
111 void s_init(void)
112 {
113 init_omap_revision();
114 watchdog_init();
115 set_mux_conf_regs();
116 #ifdef CONFIG_SPL_BUILD
117 setup_clocks_for_console();
118 preloader_console_init();
119 do_io_settings();
120 #endif
121 prcm_init();
122 #ifdef CONFIG_SPL_BUILD
123 timer_init();
125 /* For regular u-boot sdram_init() is called from dram_init() */
126 sdram_init();
127 init_boot_params();
128 #endif
129 }
131 /*
132 * Routine: wait_for_command_complete
133 * Description: Wait for posting to finish on watchdog
134 */
135 void wait_for_command_complete(struct watchdog *wd_base)
136 {
137 int pending = 1;
138 do {
139 pending = readl(&wd_base->wwps);
140 } while (pending);
141 }
143 /*
144 * Routine: watchdog_init
145 * Description: Shut down watch dogs
146 */
147 void watchdog_init(void)
148 {
149 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
151 writel(WD_UNLOCK1, &wd2_base->wspr);
152 wait_for_command_complete(wd2_base);
153 writel(WD_UNLOCK2, &wd2_base->wspr);
154 }
157 /*
158 * This function finds the SDRAM size available in the system
159 * based on DMM section configurations
160 * This is needed because the size of memory installed may be
161 * different on different versions of the board
162 */
163 u32 omap_sdram_size(void)
164 {
165 u32 section, i, total_size = 0, size, addr;
167 for (i = 0; i < 4; i++) {
168 section = __raw_readl(DMM_BASE + i*4);
169 addr = section & EMIF_SYS_ADDR_MASK;
170 /* See if the address is valid */
171 if ((addr >= DRAM_ADDR_SPACE_START) &&
172 (addr < DRAM_ADDR_SPACE_END)) {
173 size = ((section & EMIF_SYS_SIZE_MASK) >>
174 EMIF_SYS_SIZE_SHIFT);
175 size = 1 << size;
176 size *= SZ_16M;
177 total_size += size;
178 }
179 }
181 return total_size;
182 }
185 /*
186 * Routine: dram_init
187 * Description: sets uboots idea of sdram size
188 */
189 int dram_init(void)
190 {
191 sdram_init();
192 gd->ram_size = omap_sdram_size();
193 return 0;
194 }
196 /*
197 * Print board information
198 */
199 int checkboard(void)
200 {
201 puts(sysinfo.board_string);
202 return 0;
203 }
205 /*
206 * get_device_type(): tell if GP/HS/EMU/TST
207 */
208 u32 get_device_type(void)
209 {
210 struct omap_sys_ctrl_regs *ctrl =
211 (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
213 return (readl(&ctrl->control_status) &
214 (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
215 }
217 /*
218 * Print CPU information
219 */
220 int print_cpuinfo(void)
221 {
222 puts("CPU : ");
223 omap_rev_string();
225 return 0;
226 }
227 #ifndef CONFIG_SYS_DCACHE_OFF
228 void enable_caches(void)
229 {
230 /* Enable D-cache. I-cache is already enabled in start.S */
231 dcache_enable();
232 }
233 #endif