1 /*
2 *
3 * Common functions for OMAP4/5 based boards
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Author :
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30 #include <common.h>
31 #include <spl.h>
32 #include <asm/arch/sys_proto.h>
33 #include <asm/sizes.h>
34 #include <asm/emif.h>
35 #include <asm/omap_common.h>
36 #include <linux/compiler.h>
37 #include <asm/cache.h>
38 #include <asm/system.h>
40 #define ARMV7_DCACHE_WRITEBACK 0xe
41 #define ARMV7_DOMAIN_CLIENT 1
42 #define ARMV7_DOMAIN_MASK (0x3 << 0)
44 DECLARE_GLOBAL_DATA_PTR;
46 void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
47 {
48 int i;
49 struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
51 for (i = 0; i < size; i++, pad++)
52 writew(pad->val, base + pad->offset);
53 }
55 static void set_mux_conf_regs(void)
56 {
57 switch (omap_hw_init_context()) {
58 case OMAP_INIT_CONTEXT_SPL:
59 set_muxconf_regs_essential();
60 break;
61 case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL:
62 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
63 set_muxconf_regs_non_essential();
64 #endif
65 break;
66 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
67 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
68 set_muxconf_regs_essential();
69 #ifdef CONFIG_SYS_ENABLE_PADS_ALL
70 set_muxconf_regs_non_essential();
71 #endif
72 break;
73 }
74 }
76 u32 cortex_rev(void)
77 {
79 unsigned int rev;
81 /* Read Main ID Register (MIDR) */
82 asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
84 return rev;
85 }
87 void omap_rev_string(void)
88 {
89 u32 omap_rev = omap_revision();
90 u32 soc_variant = (omap_rev & 0xF0000000) >> 28;
91 u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16;
92 u32 major_rev = (omap_rev & 0x00000F00) >> 8;
93 u32 minor_rev = (omap_rev & 0x000000F0) >> 4;
95 if (soc_variant)
96 printf("OMAP");
97 else
98 printf("DRA");
99 printf("%x ES%x.%x\n", omap_variant, major_rev,
100 minor_rev);
101 }
103 #ifdef CONFIG_SPL_BUILD
104 void spl_display_print(void)
105 {
106 omap_rev_string();
107 }
108 #endif
110 void __weak srcomp_enable(void)
111 {
112 }
114 static void save_omap_boot_params(void)
115 {
116 u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
117 u8 boot_device;
118 u32 dev_desc, dev_data;
120 if ((rom_params < NON_SECURE_SRAM_START) ||
121 (rom_params > NON_SECURE_SRAM_END))
122 return;
124 /*
125 * rom_params can be type casted to omap_boot_parameters and
126 * used. But it not correct to assume that romcode structure
127 * encoding would be same as u-boot. So use the defined offsets.
128 */
129 gd->arch.omap_boot_params.omap_bootdevice = boot_device =
130 *((u8 *)(rom_params + BOOT_DEVICE_OFFSET));
132 gd->arch.omap_boot_params.ch_flags =
133 *((u8 *)(rom_params + CH_FLAGS_OFFSET));
135 if ((boot_device >= MMC_BOOT_DEVICES_START) &&
136 (boot_device <= MMC_BOOT_DEVICES_END)) {
137 if ((omap_hw_init_context() ==
138 OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) {
139 gd->arch.omap_boot_params.omap_bootmode =
140 *((u8 *)(rom_params + BOOT_MODE_OFFSET));
141 } else {
142 dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET));
143 dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET));
144 gd->arch.omap_boot_params.omap_bootmode =
145 *((u32 *)(dev_data + BOOT_MODE_OFFSET));
146 }
147 }
148 }
150 #ifdef CONFIG_ARCH_CPU_INIT
151 /*
152 * SOC specific cpu init
153 */
154 int arch_cpu_init(void)
155 {
156 save_omap_boot_params();
157 return 0;
158 }
159 #endif /* CONFIG_ARCH_CPU_INIT */
161 void __weak set_crossbar_regs(void)
162 {
163 }
165 /*
166 * Routine: s_init
167 * Description: Does early system init of watchdog, muxing, andclocks
168 * Watchdog disable is done always. For the rest what gets done
169 * depends on the boot mode in which this function is executed
170 * 1. s_init of SPL running from SRAM
171 * 2. s_init of U-Boot running from FLASH
172 * 3. s_init of U-Boot loaded to SDRAM by SPL
173 * 4. s_init of U-Boot loaded to SDRAM by ROM code using the
174 * Configuration Header feature
175 * Please have a look at the respective functions to see what gets
176 * done in each of these cases
177 * This function is called with SRAM stack.
178 */
179 void s_init(void)
180 {
181 /*
182 * Save the boot parameters passed from romcode.
183 * We cannot delay the saving further than this,
184 * to prevent overwrites.
185 */
186 #ifdef CONFIG_SPL_BUILD
187 save_omap_boot_params();
188 #endif
189 init_omap_revision();
190 hw_data_init();
192 #ifdef CONFIG_SPL_BUILD
193 if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0))
194 force_emif_self_refresh();
195 #endif
196 watchdog_init();
197 set_mux_conf_regs();
198 #ifdef CONFIG_SPL_BUILD
199 srcomp_enable();
200 setup_clocks_for_console();
202 gd = &gdata;
204 preloader_console_init();
205 do_io_settings();
206 #endif
207 prcm_init();
208 #ifdef CONFIG_SPL_BUILD
209 /* For regular u-boot sdram_init() is called from dram_init() */
210 sdram_init();
211 #endif
212 #ifndef CONFIG_SPL_BUILD
213 set_crossbar_regs();
214 #endif
215 }
217 /*
218 * Routine: wait_for_command_complete
219 * Description: Wait for posting to finish on watchdog
220 */
221 void wait_for_command_complete(struct watchdog *wd_base)
222 {
223 int pending = 1;
224 do {
225 pending = readl(&wd_base->wwps);
226 } while (pending);
227 }
229 /*
230 * Routine: watchdog_init
231 * Description: Shut down watch dogs
232 */
233 void watchdog_init(void)
234 {
235 struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE;
237 writel(WD_UNLOCK1, &wd2_base->wspr);
238 wait_for_command_complete(wd2_base);
239 writel(WD_UNLOCK2, &wd2_base->wspr);
240 }
243 /*
244 * This function finds the SDRAM size available in the system
245 * based on DMM section configurations
246 * This is needed because the size of memory installed may be
247 * different on different versions of the board
248 */
249 u32 omap_sdram_size(void)
250 {
251 u32 section, i, valid;
252 u64 sdram_start = 0, sdram_end = 0, addr,
253 size, total_size = 0, trap_size = 0;
255 for (i = 0; i < 4; i++) {
256 section = __raw_readl(DMM_BASE + i*4);
257 valid = (section & EMIF_SDRC_ADDRSPC_MASK) >>
258 (EMIF_SDRC_ADDRSPC_SHIFT);
259 addr = section & EMIF_SYS_ADDR_MASK;
261 /* See if the address is valid */
262 if ((addr >= DRAM_ADDR_SPACE_START) &&
263 (addr < DRAM_ADDR_SPACE_END)) {
264 size = ((section & EMIF_SYS_SIZE_MASK) >>
265 EMIF_SYS_SIZE_SHIFT);
266 size = 1 << size;
267 size *= SZ_16M;
269 if (valid != DMM_SDRC_ADDR_SPC_INVALID) {
270 if (!sdram_start || (addr < sdram_start))
271 sdram_start = addr;
272 if (!sdram_end || ((addr + size) > sdram_end))
273 sdram_end = addr + size;
274 } else {
275 trap_size = size;
276 }
278 }
280 }
281 total_size = (sdram_end - sdram_start) - (trap_size);
283 return total_size;
284 }
287 /*
288 * Routine: dram_init
289 * Description: sets uboots idea of sdram size
290 */
291 int dram_init(void)
292 {
293 sdram_init();
294 gd->ram_size = omap_sdram_size();
295 return 0;
296 }
298 /*
299 * Print board information
300 */
301 int checkboard(void)
302 {
303 puts(sysinfo.board_string);
304 return 0;
305 }
307 /*
308 * get_device_type(): tell if GP/HS/EMU/TST
309 */
310 u32 get_device_type(void)
311 {
312 return (readl((*ctrl)->control_status) &
313 (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
314 }
316 /*
317 * Print CPU information
318 */
319 int print_cpuinfo(void)
320 {
321 puts("CPU : ");
322 omap_rev_string();
324 return 0;
325 }
326 #ifndef CONFIG_SYS_DCACHE_OFF
327 void enable_caches(void)
328 {
329 /* Enable D-cache. I-cache is already enabled in start.S */
330 dcache_enable();
331 }
333 void dram_bank_mmu_setup(int bank)
334 {
335 bd_t *bd = gd->bd;
336 int i;
338 u32 start = bd->bi_dram[bank].start >> 20;
339 u32 size = bd->bi_dram[bank].size >> 20;
340 u32 end = start + size;
342 debug("%s: bank: %d\n", __func__, bank);
343 for (i = start; i < end; i++)
344 set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
346 }
348 void arm_init_domains(void)
349 {
350 u32 reg;
352 reg = get_dacr();
353 /*
354 * Set DOMAIN to client access so that all permissions
355 * set in pagetables are validated by the mmu.
356 */
357 reg &= ~ARMV7_DOMAIN_MASK;
358 reg |= ARMV7_DOMAIN_CLIENT;
359 set_dacr(reg);
360 }
361 #endif