1 /*
2 *
3 * Clock initialization for OMAP4
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Aneesh V <aneesh@ti.com>
9 *
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32 #include <common.h>
33 #include <asm/omap_common.h>
34 #include <asm/gpio.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
40 #ifndef CONFIG_SPL_BUILD
41 /*
42 * printing to console doesn't work unless
43 * this code is executed from SPL
44 */
45 #define printf(fmt, args...)
46 #define puts(s)
47 #endif
49 #define abs(x) (((x) < 0) ? ((x)*-1) : (x))
51 struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
53 const u32 sys_clk_array[8] = {
54 12000000, /* 12 MHz */
55 13000000, /* 13 MHz */
56 16800000, /* 16.8 MHz */
57 19200000, /* 19.2 MHz */
58 26000000, /* 26 MHz */
59 27000000, /* 27 MHz */
60 38400000, /* 38.4 MHz */
61 };
63 /*
64 * The M & N values in the following tables are created using the
65 * following tool:
66 * tools/omap/clocks_get_m_n.c
67 * Please use this tool for creating the table for any new frequency.
68 */
70 /* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
71 static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
72 {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
73 {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
74 {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
75 {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
76 {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
77 {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
78 {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
79 };
81 /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
82 static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
83 {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
84 {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
85 {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
86 {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
87 {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
88 {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
89 {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
90 };
92 /* dpll locked at 1200 MHz - MPU clk at 600 MHz */
93 static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
94 {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
95 {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
96 {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
97 {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
98 {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
99 {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
100 {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
101 };
103 static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
104 {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
105 {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
106 {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
107 {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
108 {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
109 {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
110 {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
111 };
113 static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
114 {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
115 {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
116 {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
117 {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
118 {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
119 {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
120 {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
121 };
123 static const struct dpll_params
124 core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
125 {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
126 {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
127 {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
128 {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
129 {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
130 {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
131 {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
132 };
134 static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
135 {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
136 {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
137 {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
138 {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
139 {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
140 {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
141 {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
142 };
144 static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
145 {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
146 {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
147 {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
148 {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
149 {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
150 {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
151 {412, 16, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
152 };
154 /* ABE M & N values with sys_clk as source */
155 static const struct dpll_params
156 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
157 {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
158 {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
159 {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
160 {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
161 {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
162 {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
163 {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
164 };
166 /* ABE M & N values with 32K clock as source */
167 static const struct dpll_params abe_dpll_params_32k_196608khz = {
168 750, 0, 1, 1, -1, -1, -1, -1
169 };
171 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
172 {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
173 {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
174 {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
175 {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
176 {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
177 {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
178 {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
179 };
181 void setup_post_dividers(u32 *const base, const struct dpll_params *params)
182 {
183 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
185 /* Setup post-dividers */
186 if (params->m2 >= 0)
187 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
188 if (params->m3 >= 0)
189 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
190 if (params->m4 >= 0)
191 writel(params->m4, &dpll_regs->cm_div_m4_dpll);
192 if (params->m5 >= 0)
193 writel(params->m5, &dpll_regs->cm_div_m5_dpll);
194 if (params->m6 >= 0)
195 writel(params->m6, &dpll_regs->cm_div_m6_dpll);
196 if (params->m7 >= 0)
197 writel(params->m7, &dpll_regs->cm_div_m7_dpll);
198 }
200 /*
201 * Lock MPU dpll
202 *
203 * Resulting MPU frequencies:
204 * 4430 ES1.0 : 600 MHz
205 * 4430 ES2.x : 792 MHz (OPP Turbo)
206 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
207 */
208 const struct dpll_params *get_mpu_dpll_params(void)
209 {
210 u32 omap_rev, sysclk_ind;
212 omap_rev = omap_revision();
213 sysclk_ind = get_sys_clk_index();
215 if (omap_rev == OMAP4430_ES1_0)
216 return &mpu_dpll_params_1200mhz[sysclk_ind];
217 else if (omap_rev < OMAP4460_ES1_0)
218 return &mpu_dpll_params_1600mhz[sysclk_ind];
219 else
220 return &mpu_dpll_params_1400mhz[sysclk_ind];
221 }
223 const struct dpll_params *get_core_dpll_params(void)
224 {
225 u32 sysclk_ind = get_sys_clk_index();
227 switch (omap_revision()) {
228 case OMAP4430_ES1_0:
229 return &core_dpll_params_es1_1524mhz[sysclk_ind];
230 case OMAP4430_ES2_0:
231 case OMAP4430_SILICON_ID_INVALID:
232 /* safest */
233 return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
234 default:
235 return &core_dpll_params_1600mhz[sysclk_ind];
236 }
237 }
240 const struct dpll_params *get_per_dpll_params(void)
241 {
242 u32 sysclk_ind = get_sys_clk_index();
243 return &per_dpll_params_1536mhz[sysclk_ind];
244 }
246 const struct dpll_params *get_iva_dpll_params(void)
247 {
248 u32 sysclk_ind = get_sys_clk_index();
249 return &iva_dpll_params_1862mhz[sysclk_ind];
250 }
252 const struct dpll_params *get_usb_dpll_params(void)
253 {
254 u32 sysclk_ind = get_sys_clk_index();
255 return &usb_dpll_params_1920mhz[sysclk_ind];
256 }
258 const struct dpll_params *get_abe_dpll_params(void)
259 {
260 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
261 u32 sysclk_ind = get_sys_clk_index();
262 return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
263 #else
264 return &abe_dpll_params_32k_196608khz;
265 #endif
266 }
268 /*
269 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
270 * We set the maximum voltages allowed here because Smart-Reflex is not
271 * enabled in bootloader. Voltage initialization in the kernel will set
272 * these to the nominal values after enabling Smart-Reflex
273 */
274 void scale_vcores(void)
275 {
276 u32 volt, omap_rev;
278 omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
280 omap_rev = omap_revision();
281 /* TPS - supplies vdd_mpu on 4460 */
282 if (omap_rev >= OMAP4460_ES1_0) {
283 volt = 1203;
284 do_scale_tps62361(TPS62361_VSEL0_GPIO,
285 TPS62361_REG_ADDR_SET1, volt);
286 }
288 /*
289 * VCORE 1
290 *
291 * 4430 : supplies vdd_mpu
292 * Setting a high voltage for Nitro mode as smart reflex is not enabled.
293 * We use the maximum possible value in the AVS range because the next
294 * higher voltage in the discrete range (code >= 0b111010) is way too
295 * high
296 *
297 * 4460 : supplies vdd_core
298 */
299 if (omap_rev < OMAP4460_ES1_0) {
300 volt = 1325;
301 do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
302 } else {
303 volt = 1200;
304 do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
305 }
307 /* VCORE 2 - supplies vdd_iva */
308 volt = 1200;
309 do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
311 /*
312 * VCORE 3
313 * 4430 : supplies vdd_core
314 * 4460 : not connected
315 */
316 if (omap_rev < OMAP4460_ES1_0) {
317 volt = 1200;
318 do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
319 }
320 }
322 /*
323 * Enable essential clock domains, modules and
324 * do some additional special settings needed
325 */
326 void enable_basic_clocks(void)
327 {
328 u32 *const clk_domains_essential[] = {
329 &prcm->cm_l4per_clkstctrl,
330 &prcm->cm_l3init_clkstctrl,
331 &prcm->cm_memif_clkstctrl,
332 &prcm->cm_l4cfg_clkstctrl,
333 0
334 };
336 u32 *const clk_modules_hw_auto_essential[] = {
337 &prcm->cm_memif_emif_1_clkctrl,
338 &prcm->cm_memif_emif_2_clkctrl,
339 &prcm->cm_l4cfg_l4_cfg_clkctrl,
340 &prcm->cm_wkup_gpio1_clkctrl,
341 &prcm->cm_l4per_gpio2_clkctrl,
342 &prcm->cm_l4per_gpio3_clkctrl,
343 &prcm->cm_l4per_gpio4_clkctrl,
344 &prcm->cm_l4per_gpio5_clkctrl,
345 &prcm->cm_l4per_gpio6_clkctrl,
346 &prcm->cm_l3init_usbphy_clkctrl,
347 &prcm->cm_clksel_usb_60mhz,
348 &prcm->cm_l3init_hsusbtll_clkctrl,
349 0
350 };
352 u32 *const clk_modules_explicit_en_essential[] = {
353 &prcm->cm_wkup_gptimer1_clkctrl,
354 &prcm->cm_l3init_hsmmc1_clkctrl,
355 &prcm->cm_l3init_hsmmc2_clkctrl,
356 &prcm->cm_l4per_gptimer2_clkctrl,
357 &prcm->cm_wkup_wdtimer2_clkctrl,
358 &prcm->cm_l4per_uart3_clkctrl,
359 &prcm->cm_l3init_fsusb_clkctrl,
360 &prcm->cm_l3init_hsusbhost_clkctrl,
361 0
362 };
364 /* Enable optional additional functional clock for GPIO4 */
365 setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
366 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
368 /* Enable 96 MHz clock for MMC1 & MMC2 */
369 setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
370 HSMMC_CLKCTRL_CLKSEL_MASK);
371 setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
372 HSMMC_CLKCTRL_CLKSEL_MASK);
374 /* Select 32KHz clock as the source of GPTIMER1 */
375 setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
376 GPTIMER1_CLKCTRL_CLKSEL_MASK);
378 /* Enable optional 48M functional clock for USB PHY */
379 setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
380 USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
382 do_enable_clocks(clk_domains_essential,
383 clk_modules_hw_auto_essential,
384 clk_modules_explicit_en_essential,
385 1);
386 }
388 void enable_basic_uboot_clocks(void)
389 {
390 u32 *const clk_domains_essential[] = {
391 0
392 };
394 u32 *const clk_modules_hw_auto_essential[] = {
395 &prcm->cm_l3init_hsusbotg_clkctrl,
396 &prcm->cm_l3init_usbphy_clkctrl,
397 0
398 };
400 u32 *const clk_modules_explicit_en_essential[] = {
401 &prcm->cm_l4per_mcspi1_clkctrl,
402 &prcm->cm_l4per_i2c1_clkctrl,
403 &prcm->cm_l4per_i2c2_clkctrl,
404 &prcm->cm_l4per_i2c3_clkctrl,
405 &prcm->cm_l4per_i2c4_clkctrl,
406 0
407 };
409 do_enable_clocks(clk_domains_essential,
410 clk_modules_hw_auto_essential,
411 clk_modules_explicit_en_essential,
412 1);
413 }
415 /*
416 * Enable non-essential clock domains, modules and
417 * do some additional special settings needed
418 */
419 void enable_non_essential_clocks(void)
420 {
421 u32 *const clk_domains_non_essential[] = {
422 &prcm->cm_mpu_m3_clkstctrl,
423 &prcm->cm_ivahd_clkstctrl,
424 &prcm->cm_dsp_clkstctrl,
425 &prcm->cm_dss_clkstctrl,
426 &prcm->cm_sgx_clkstctrl,
427 &prcm->cm1_abe_clkstctrl,
428 &prcm->cm_c2c_clkstctrl,
429 &prcm->cm_cam_clkstctrl,
430 &prcm->cm_dss_clkstctrl,
431 &prcm->cm_sdma_clkstctrl,
432 0
433 };
435 u32 *const clk_modules_hw_auto_non_essential[] = {
436 &prcm->cm_mpu_m3_mpu_m3_clkctrl,
437 &prcm->cm_ivahd_ivahd_clkctrl,
438 &prcm->cm_ivahd_sl2_clkctrl,
439 &prcm->cm_dsp_dsp_clkctrl,
440 &prcm->cm_l3_2_gpmc_clkctrl,
441 &prcm->cm_l3instr_l3_3_clkctrl,
442 &prcm->cm_l3instr_l3_instr_clkctrl,
443 &prcm->cm_l3instr_intrconn_wp1_clkctrl,
444 &prcm->cm_l3init_hsi_clkctrl,
445 &prcm->cm_l3init_hsusbtll_clkctrl,
446 0
447 };
449 u32 *const clk_modules_explicit_en_non_essential[] = {
450 &prcm->cm1_abe_aess_clkctrl,
451 &prcm->cm1_abe_pdm_clkctrl,
452 &prcm->cm1_abe_dmic_clkctrl,
453 &prcm->cm1_abe_mcasp_clkctrl,
454 &prcm->cm1_abe_mcbsp1_clkctrl,
455 &prcm->cm1_abe_mcbsp2_clkctrl,
456 &prcm->cm1_abe_mcbsp3_clkctrl,
457 &prcm->cm1_abe_slimbus_clkctrl,
458 &prcm->cm1_abe_timer5_clkctrl,
459 &prcm->cm1_abe_timer6_clkctrl,
460 &prcm->cm1_abe_timer7_clkctrl,
461 &prcm->cm1_abe_timer8_clkctrl,
462 &prcm->cm1_abe_wdt3_clkctrl,
463 &prcm->cm_l4per_gptimer9_clkctrl,
464 &prcm->cm_l4per_gptimer10_clkctrl,
465 &prcm->cm_l4per_gptimer11_clkctrl,
466 &prcm->cm_l4per_gptimer3_clkctrl,
467 &prcm->cm_l4per_gptimer4_clkctrl,
468 &prcm->cm_l4per_hdq1w_clkctrl,
469 &prcm->cm_l4per_mcbsp4_clkctrl,
470 &prcm->cm_l4per_mcspi2_clkctrl,
471 &prcm->cm_l4per_mcspi3_clkctrl,
472 &prcm->cm_l4per_mcspi4_clkctrl,
473 &prcm->cm_l4per_mmcsd3_clkctrl,
474 &prcm->cm_l4per_mmcsd4_clkctrl,
475 &prcm->cm_l4per_mmcsd5_clkctrl,
476 &prcm->cm_l4per_uart1_clkctrl,
477 &prcm->cm_l4per_uart2_clkctrl,
478 &prcm->cm_l4per_uart4_clkctrl,
479 &prcm->cm_wkup_keyboard_clkctrl,
480 &prcm->cm_wkup_wdtimer2_clkctrl,
481 &prcm->cm_cam_iss_clkctrl,
482 &prcm->cm_cam_fdif_clkctrl,
483 &prcm->cm_dss_dss_clkctrl,
484 &prcm->cm_sgx_sgx_clkctrl,
485 &prcm->cm_l3init_hsusbhost_clkctrl,
486 &prcm->cm_l3init_fsusb_clkctrl,
487 0
488 };
490 /* Enable optional functional clock for ISS */
491 setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
493 /* Enable all optional functional clocks of DSS */
494 setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
496 do_enable_clocks(clk_domains_non_essential,
497 clk_modules_hw_auto_non_essential,
498 clk_modules_explicit_en_non_essential,
499 0);
501 /* Put camera module in no sleep mode */
502 clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
503 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
504 MODULE_CLKCTRL_MODULEMODE_SHIFT);
505 }