ARM: OMAP4+: Make control module register structure generic
[glsdk/glsdk-u-boot.git] / arch / arm / cpu / armv7 / omap4 / prcm-regs.c
1 /*
2  *
3  * HW regs data for OMAP4
4  *
5  * (C) Copyright 2013
6  * Texas Instruments, <www.ti.com>
7  *
8  * Sricharan R <r.sricharan@ti.com>
9  *
10  * See file CREDITS for list of people who contributed to this
11  * project.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License as
15  * published by the Free Software Foundation; either version 2 of
16  * the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26  * MA 02111-1307 USA
27  */
29 #include <asm/omap_common.h>
31 struct prcm_regs const omap4_prcm = {
32         /* cm1.ckgen */
33         .cm_clksel_core  = 0x4a004100,
34         .cm_clksel_abe = 0x4a004108,
35         .cm_dll_ctrl = 0x4a004110,
36         .cm_clkmode_dpll_core = 0x4a004120,
37         .cm_idlest_dpll_core = 0x4a004124,
38         .cm_autoidle_dpll_core = 0x4a004128,
39         .cm_clksel_dpll_core = 0x4a00412c,
40         .cm_div_m2_dpll_core = 0x4a004130,
41         .cm_div_m3_dpll_core = 0x4a004134,
42         .cm_div_m4_dpll_core = 0x4a004138,
43         .cm_div_m5_dpll_core = 0x4a00413c,
44         .cm_div_m6_dpll_core = 0x4a004140,
45         .cm_div_m7_dpll_core = 0x4a004144,
46         .cm_ssc_deltamstep_dpll_core = 0x4a004148,
47         .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
48         .cm_emu_override_dpll_core = 0x4a004150,
49         .cm_clkmode_dpll_mpu = 0x4a004160,
50         .cm_idlest_dpll_mpu = 0x4a004164,
51         .cm_autoidle_dpll_mpu = 0x4a004168,
52         .cm_clksel_dpll_mpu = 0x4a00416c,
53         .cm_div_m2_dpll_mpu = 0x4a004170,
54         .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
55         .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
56         .cm_bypclk_dpll_mpu = 0x4a00419c,
57         .cm_clkmode_dpll_iva = 0x4a0041a0,
58         .cm_idlest_dpll_iva = 0x4a0041a4,
59         .cm_autoidle_dpll_iva = 0x4a0041a8,
60         .cm_clksel_dpll_iva = 0x4a0041ac,
61         .cm_div_m4_dpll_iva = 0x4a0041b8,
62         .cm_div_m5_dpll_iva = 0x4a0041bc,
63         .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
64         .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
65         .cm_bypclk_dpll_iva = 0x4a0041dc,
66         .cm_clkmode_dpll_abe = 0x4a0041e0,
67         .cm_idlest_dpll_abe = 0x4a0041e4,
68         .cm_autoidle_dpll_abe = 0x4a0041e8,
69         .cm_clksel_dpll_abe = 0x4a0041ec,
70         .cm_div_m2_dpll_abe = 0x4a0041f0,
71         .cm_div_m3_dpll_abe = 0x4a0041f4,
72         .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
73         .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
74         .cm_clkmode_dpll_ddrphy = 0x4a004220,
75         .cm_idlest_dpll_ddrphy = 0x4a004224,
76         .cm_autoidle_dpll_ddrphy = 0x4a004228,
77         .cm_clksel_dpll_ddrphy = 0x4a00422c,
78         .cm_div_m2_dpll_ddrphy = 0x4a004230,
79         .cm_div_m4_dpll_ddrphy = 0x4a004238,
80         .cm_div_m5_dpll_ddrphy = 0x4a00423c,
81         .cm_div_m6_dpll_ddrphy = 0x4a004240,
82         .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
83         .cm_shadow_freq_config1 = 0x4a004260,
84         .cm_mpu_mpu_clkctrl = 0x4a004320,
86         /* cm1.dsp */
87         .cm_dsp_clkstctrl = 0x4a004400,
88         .cm_dsp_dsp_clkctrl = 0x4a004420,
90         /* cm1.abe */
91         .cm1_abe_clkstctrl = 0x4a004500,
92         .cm1_abe_l4abe_clkctrl = 0x4a004520,
93         .cm1_abe_aess_clkctrl = 0x4a004528,
94         .cm1_abe_pdm_clkctrl = 0x4a004530,
95         .cm1_abe_dmic_clkctrl = 0x4a004538,
96         .cm1_abe_mcasp_clkctrl = 0x4a004540,
97         .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
98         .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
99         .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
100         .cm1_abe_slimbus_clkctrl = 0x4a004560,
101         .cm1_abe_timer5_clkctrl = 0x4a004568,
102         .cm1_abe_timer6_clkctrl = 0x4a004570,
103         .cm1_abe_timer7_clkctrl = 0x4a004578,
104         .cm1_abe_timer8_clkctrl = 0x4a004580,
105         .cm1_abe_wdt3_clkctrl = 0x4a004588,
107         /* cm2.ckgen */
108         .cm_clksel_mpu_m3_iss_root = 0x4a008100,
109         .cm_clksel_usb_60mhz = 0x4a008104,
110         .cm_scale_fclk = 0x4a008108,
111         .cm_core_dvfs_perf1 = 0x4a008110,
112         .cm_core_dvfs_perf2 = 0x4a008114,
113         .cm_core_dvfs_perf3 = 0x4a008118,
114         .cm_core_dvfs_perf4 = 0x4a00811c,
115         .cm_core_dvfs_current = 0x4a008124,
116         .cm_iva_dvfs_perf_tesla = 0x4a008128,
117         .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
118         .cm_iva_dvfs_perf_abe = 0x4a008130,
119         .cm_iva_dvfs_current = 0x4a008138,
120         .cm_clkmode_dpll_per = 0x4a008140,
121         .cm_idlest_dpll_per = 0x4a008144,
122         .cm_autoidle_dpll_per = 0x4a008148,
123         .cm_clksel_dpll_per = 0x4a00814c,
124         .cm_div_m2_dpll_per = 0x4a008150,
125         .cm_div_m3_dpll_per = 0x4a008154,
126         .cm_div_m4_dpll_per = 0x4a008158,
127         .cm_div_m5_dpll_per = 0x4a00815c,
128         .cm_div_m6_dpll_per = 0x4a008160,
129         .cm_div_m7_dpll_per = 0x4a008164,
130         .cm_ssc_deltamstep_dpll_per = 0x4a008168,
131         .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
132         .cm_emu_override_dpll_per = 0x4a008170,
133         .cm_clkmode_dpll_usb = 0x4a008180,
134         .cm_idlest_dpll_usb = 0x4a008184,
135         .cm_autoidle_dpll_usb = 0x4a008188,
136         .cm_clksel_dpll_usb = 0x4a00818c,
137         .cm_div_m2_dpll_usb = 0x4a008190,
138         .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
139         .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
140         .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
141         .cm_clkmode_dpll_unipro = 0x4a0081c0,
142         .cm_idlest_dpll_unipro = 0x4a0081c4,
143         .cm_autoidle_dpll_unipro = 0x4a0081c8,
144         .cm_clksel_dpll_unipro = 0x4a0081cc,
145         .cm_div_m2_dpll_unipro = 0x4a0081d0,
146         .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
147         .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
149         /* cm2.core */
150         .cm_l3_1_clkstctrl = 0x4a008700,
151         .cm_l3_1_dynamicdep = 0x4a008708,
152         .cm_l3_1_l3_1_clkctrl = 0x4a008720,
153         .cm_l3_2_clkstctrl = 0x4a008800,
154         .cm_l3_2_dynamicdep = 0x4a008808,
155         .cm_l3_2_l3_2_clkctrl = 0x4a008820,
156         .cm_l3_2_gpmc_clkctrl = 0x4a008828,
157         .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
158         .cm_mpu_m3_clkstctrl = 0x4a008900,
159         .cm_mpu_m3_staticdep = 0x4a008904,
160         .cm_mpu_m3_dynamicdep = 0x4a008908,
161         .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
162         .cm_sdma_clkstctrl = 0x4a008a00,
163         .cm_sdma_staticdep = 0x4a008a04,
164         .cm_sdma_dynamicdep = 0x4a008a08,
165         .cm_sdma_sdma_clkctrl = 0x4a008a20,
166         .cm_memif_clkstctrl = 0x4a008b00,
167         .cm_memif_dmm_clkctrl = 0x4a008b20,
168         .cm_memif_emif_fw_clkctrl = 0x4a008b28,
169         .cm_memif_emif_1_clkctrl = 0x4a008b30,
170         .cm_memif_emif_2_clkctrl = 0x4a008b38,
171         .cm_memif_dll_clkctrl = 0x4a008b40,
172         .cm_memif_emif_h1_clkctrl = 0x4a008b50,
173         .cm_memif_emif_h2_clkctrl = 0x4a008b58,
174         .cm_memif_dll_h_clkctrl = 0x4a008b60,
175         .cm_c2c_clkstctrl = 0x4a008c00,
176         .cm_c2c_staticdep = 0x4a008c04,
177         .cm_c2c_dynamicdep = 0x4a008c08,
178         .cm_c2c_sad2d_clkctrl = 0x4a008c20,
179         .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
180         .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
181         .cm_l4cfg_clkstctrl = 0x4a008d00,
182         .cm_l4cfg_dynamicdep = 0x4a008d08,
183         .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
184         .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
185         .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
186         .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
187         .cm_l3instr_clkstctrl = 0x4a008e00,
188         .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
189         .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
190         .cm_l3instr_intrconn_wp1_clkct = 0x4a008e40,
191         .cm_ivahd_clkstctrl = 0x4a008f00,
193         /* cm2.ivahd */
194         .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
195         .cm_ivahd_sl2_clkctrl = 0x4a008f28,
197         /* cm2.cam */
198         .cm_cam_clkstctrl = 0x4a009000,
199         .cm_cam_iss_clkctrl = 0x4a009020,
200         .cm_cam_fdif_clkctrl = 0x4a009028,
202         /* cm2.dss */
203         .cm_dss_clkstctrl = 0x4a009100,
204         .cm_dss_dss_clkctrl = 0x4a009120,
206         /* cm2.sgx */
207         .cm_sgx_clkstctrl = 0x4a009200,
208         .cm_sgx_sgx_clkctrl = 0x4a009220,
210         /* cm2.l3init */
211         .cm_l3init_clkstctrl = 0x4a009300,
212         .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
213         .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
214         .cm_l3init_hsi_clkctrl = 0x4a009338,
215         .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
216         .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
217         .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
218         .cm_l3init_p1500_clkctrl = 0x4a009378,
219         .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
220         .cm_l3init_usbphy_clkctrl = 0x4a0093e0,
222         /* cm2.l4per */
223         .cm_l4per_clkstctrl = 0x4a009400,
224         .cm_l4per_dynamicdep = 0x4a009408,
225         .cm_l4per_adc_clkctrl = 0x4a009420,
226         .cm_l4per_gptimer10_clkctrl = 0x4a009428,
227         .cm_l4per_gptimer11_clkctrl = 0x4a009430,
228         .cm_l4per_gptimer2_clkctrl = 0x4a009438,
229         .cm_l4per_gptimer3_clkctrl = 0x4a009440,
230         .cm_l4per_gptimer4_clkctrl = 0x4a009448,
231         .cm_l4per_gptimer9_clkctrl = 0x4a009450,
232         .cm_l4per_elm_clkctrl = 0x4a009458,
233         .cm_l4per_gpio2_clkctrl = 0x4a009460,
234         .cm_l4per_gpio3_clkctrl = 0x4a009468,
235         .cm_l4per_gpio4_clkctrl = 0x4a009470,
236         .cm_l4per_gpio5_clkctrl = 0x4a009478,
237         .cm_l4per_gpio6_clkctrl = 0x4a009480,
238         .cm_l4per_hdq1w_clkctrl = 0x4a009488,
239         .cm_l4per_hecc1_clkctrl = 0x4a009490,
240         .cm_l4per_hecc2_clkctrl = 0x4a009498,
241         .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
242         .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
243         .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
244         .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
245         .cm_l4per_l4per_clkctrl = 0x4a0094c0,
246         .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
247         .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
248         .cm_l4per_mcbsp4_clkctrl = 0x4a0094e0,
249         .cm_l4per_mgate_clkctrl = 0x4a0094e8,
250         .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
251         .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
252         .cm_l4per_mcspi3_clkctrl = 0x4a009500,
253         .cm_l4per_mcspi4_clkctrl = 0x4a009508,
254         .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
255         .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
256         .cm_l4per_msprohg_clkctrl = 0x4a009530,
257         .cm_l4per_slimbus2_clkctrl = 0x4a009538,
258         .cm_l4per_uart1_clkctrl = 0x4a009540,
259         .cm_l4per_uart2_clkctrl = 0x4a009548,
260         .cm_l4per_uart3_clkctrl = 0x4a009550,
261         .cm_l4per_uart4_clkctrl = 0x4a009558,
262         .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
263         .cm_l4per_i2c5_clkctrl = 0x4a009568,
264         .cm_l4sec_clkstctrl = 0x4a009580,
265         .cm_l4sec_staticdep = 0x4a009584,
266         .cm_l4sec_dynamicdep = 0x4a009588,
267         .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
268         .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
269         .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
270         .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
271         .cm_l4sec_rng_clkctrl = 0x4a0095c0,
272         .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
273         .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
275         /* l4 wkup regs */
276         .cm_abe_pll_ref_clksel = 0x4a30610c,
277         .cm_sys_clksel = 0x4a306110,
278         .cm_wkup_clkstctrl = 0x4a307800,
279         .cm_wkup_l4wkup_clkctrl = 0x4a307820,
280         .cm_wkup_wdtimer1_clkctrl = 0x4a307828,
281         .cm_wkup_wdtimer2_clkctrl = 0x4a307830,
282         .cm_wkup_gpio1_clkctrl = 0x4a307838,
283         .cm_wkup_gptimer1_clkctrl = 0x4a307840,
284         .cm_wkup_gptimer12_clkctrl = 0x4a307848,
285         .cm_wkup_synctimer_clkctrl = 0x4a307850,
286         .cm_wkup_usim_clkctrl = 0x4a307858,
287         .cm_wkup_sarram_clkctrl = 0x4a307860,
288         .cm_wkup_keyboard_clkctrl = 0x4a307878,
289         .cm_wkup_rtc_clkctrl = 0x4a307880,
290         .cm_wkup_bandgap_clkctrl = 0x4a307888,
291         .prm_vc_val_bypass = 0x4a307ba0,
292         .prm_vc_cfg_channel = 0x4a307ba4,
293         .prm_vc_cfg_i2c_mode = 0x4a307ba8,
294         .prm_vc_cfg_i2c_clk = 0x4a307bac,
295 };
297 struct omap_sys_ctrl_regs const omap4_ctrl = {
298         .control_id_code                        = 0x4A002204,
299         .control_std_fuse_opp_bgap              = 0x4a002260,
300         .control_status                         = 0x4a0022c4,
301         .control_ldosram_iva_voltage_ctrl       = 0x4A002320,
302         .control_ldosram_mpu_voltage_ctrl       = 0x4A002324,
303         .control_ldosram_core_voltage_ctrl      = 0x4A002328,
304         .control_pbiaslite                      = 0x4A100600,
305         .control_lpddr2io1_0                    = 0x4A100638,
306         .control_lpddr2io1_1                    = 0x4A10063C,
307         .control_lpddr2io1_2                    = 0x4A100640,
308         .control_lpddr2io1_3                    = 0x4A100644,
309         .control_lpddr2io2_0                    = 0x4A100648,
310         .control_lpddr2io2_1                    = 0x4A10064C,
311         .control_lpddr2io2_2                    = 0x4A100650,
312         .control_lpddr2io2_3                    = 0x4A100654,
313         .control_efuse_1                        = 0x4A100700,
314         .control_efuse_2                        = 0x4A100704,
315 };