1f3369268da12510ce2c6eb626deb53785fe0d56
1 /*
2 *
3 * Clock initialization for OMAP5
4 *
5 * (C) Copyright 2010
6 * Texas Instruments, <www.ti.com>
7 *
8 * Aneesh V <aneesh@ti.com>
9 * Sricharan R <r.sricharan@ti.com>
10 *
11 * Based on previous work by:
12 * Santosh Shilimkar <santosh.shilimkar@ti.com>
13 * Rajendra Nayak <rnayak@ti.com>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33 #include <common.h>
34 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
39 #include <asm/emif.h>
41 #ifndef CONFIG_SPL_BUILD
42 /*
43 * printing to console doesn't work unless
44 * this code is executed from SPL
45 */
46 #define printf(fmt, args...)
47 #define puts(s)
48 #endif
50 struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
52 const u32 sys_clk_array[8] = {
53 12000000, /* 12 MHz */
54 0, /* NA */
55 16800000, /* 16.8 MHz */
56 19200000, /* 19.2 MHz */
57 26000000, /* 26 MHz */
58 0, /* NA */
59 38400000, /* 38.4 MHz */
60 };
62 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
63 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
64 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
65 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
66 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
67 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
68 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
69 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
70 };
72 static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
73 {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
74 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
75 {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
76 {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
77 {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
78 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
79 {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
80 };
82 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
83 {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
84 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
85 {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
86 {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
87 {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
88 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
89 {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
90 };
92 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
93 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
94 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
95 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
96 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
97 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
98 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
99 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
100 };
102 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
103 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
104 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
105 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
106 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
107 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
109 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
110 };
112 static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
113 {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
114 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
115 {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
116 {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
117 {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
118 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
119 {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
120 };
122 static const struct dpll_params
123 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
124 {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
125 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
126 {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
127 {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
128 {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
129 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
130 {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
131 };
133 static const struct dpll_params
134 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
135 {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
136 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
137 {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
138 {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
139 {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
140 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
141 {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
142 };
144 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
145 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
146 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
147 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
148 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
149 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
150 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
151 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
152 };
154 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
155 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
156 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
157 {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
158 {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
159 {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
160 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
161 {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
162 };
164 /* ABE M & N values with sys_clk as source */
165 static const struct dpll_params
166 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
167 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
168 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
169 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
170 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
171 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
172 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
173 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
174 };
176 /* ABE M & N values with 32K clock as source */
177 static const struct dpll_params abe_dpll_params_32k_196608khz = {
178 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
179 };
181 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
182 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
183 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
184 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
185 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
186 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
187 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
188 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
189 };
191 void setup_post_dividers(u32 *const base, const struct dpll_params *params)
192 {
193 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
195 /* Setup post-dividers */
196 if (params->m2 >= 0)
197 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
198 if (params->m3 >= 0)
199 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
200 if (params->h11 >= 0)
201 writel(params->h11, &dpll_regs->cm_div_h11_dpll);
202 if (params->h12 >= 0)
203 writel(params->h12, &dpll_regs->cm_div_h12_dpll);
204 if (params->h13 >= 0)
205 writel(params->h13, &dpll_regs->cm_div_h13_dpll);
206 if (params->h14 >= 0)
207 writel(params->h14, &dpll_regs->cm_div_h14_dpll);
208 if (params->h22 >= 0)
209 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
210 if (params->h23 >= 0)
211 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
212 }
214 const struct dpll_params *get_mpu_dpll_params(void)
215 {
216 u32 sysclk_ind = get_sys_clk_index();
217 return &mpu_dpll_params_800mhz[sysclk_ind];
218 }
220 const struct dpll_params *get_core_dpll_params(void)
221 {
222 u32 sysclk_ind = get_sys_clk_index();
224 /* Configuring the DDR to be at 532mhz */
225 return &core_dpll_params_2128mhz_ddr532[sysclk_ind];
226 }
228 const struct dpll_params *get_per_dpll_params(void)
229 {
230 u32 sysclk_ind = get_sys_clk_index();
231 return &per_dpll_params_768mhz[sysclk_ind];
232 }
234 const struct dpll_params *get_iva_dpll_params(void)
235 {
236 u32 sysclk_ind = get_sys_clk_index();
237 return &iva_dpll_params_2330mhz[sysclk_ind];
238 }
240 const struct dpll_params *get_usb_dpll_params(void)
241 {
242 u32 sysclk_ind = get_sys_clk_index();
243 return &usb_dpll_params_1920mhz[sysclk_ind];
244 }
246 const struct dpll_params *get_abe_dpll_params(void)
247 {
248 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
249 u32 sysclk_ind = get_sys_clk_index();
250 return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
251 #else
252 return &abe_dpll_params_32k_196608khz;
253 #endif
254 }
256 /*
257 * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
258 * We set the maximum voltages allowed here because Smart-Reflex is not
259 * enabled in bootloader. Voltage initialization in the kernel will set
260 * these to the nominal values after enabling Smart-Reflex
261 */
262 void scale_vcores(void)
263 {
264 u32 volt_core, volt_mpu, volt_mm;
266 omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
268 /* Palmas settings */
269 if (omap_revision() != OMAP5432_ES1_0) {
270 volt_core = VDD_CORE;
271 volt_mpu = VDD_MPU;
272 volt_mm = VDD_MM;
273 } else {
274 volt_core = VDD_CORE_5432;
275 volt_mpu = VDD_MPU_5432;
276 volt_mm = VDD_MM_5432;
277 }
279 do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
280 do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
281 do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
283 if (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3) {
284 /* Configure LDO SRAM "magic" bits */
285 writel(2, &prcm->prm_sldo_core_setup);
286 writel(2, &prcm->prm_sldo_mpu_setup);
287 writel(2, &prcm->prm_sldo_mm_setup);
288 }
289 }
291 u32 get_offset_code(u32 volt_offset)
292 {
293 u32 offset_code, step = 10000; /* 10 mV represented in uV */
295 volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
297 offset_code = (volt_offset + step - 1) / step;
299 /*
300 * Offset codes 1-6 all give the base voltage in Palmas
301 * Offset code 0 switches OFF the SMPS
302 */
303 return offset_code + 6;
304 }
306 /*
307 * Enable essential clock domains, modules and
308 * do some additional special settings needed
309 */
310 void enable_basic_clocks(void)
311 {
312 u32 *const clk_domains_essential[] = {
313 &prcm->cm_l4per_clkstctrl,
314 &prcm->cm_l3init_clkstctrl,
315 &prcm->cm_memif_clkstctrl,
316 &prcm->cm_l4cfg_clkstctrl,
317 0
318 };
320 u32 *const clk_modules_hw_auto_essential[] = {
321 &prcm->cm_l3_2_gpmc_clkctrl,
322 &prcm->cm_memif_emif_1_clkctrl,
323 &prcm->cm_memif_emif_2_clkctrl,
324 &prcm->cm_l4cfg_l4_cfg_clkctrl,
325 &prcm->cm_wkup_gpio1_clkctrl,
326 &prcm->cm_l4per_gpio2_clkctrl,
327 &prcm->cm_l4per_gpio3_clkctrl,
328 &prcm->cm_l4per_gpio4_clkctrl,
329 &prcm->cm_l4per_gpio5_clkctrl,
330 &prcm->cm_l4per_gpio6_clkctrl,
331 0
332 };
334 u32 *const clk_modules_explicit_en_essential[] = {
335 &prcm->cm_wkup_gptimer1_clkctrl,
336 &prcm->cm_l3init_hsmmc1_clkctrl,
337 &prcm->cm_l3init_hsmmc2_clkctrl,
338 &prcm->cm_l4per_gptimer2_clkctrl,
339 &prcm->cm_wkup_wdtimer2_clkctrl,
340 &prcm->cm_l4per_uart3_clkctrl,
341 &prcm->cm_l4per_i2c1_clkctrl,
342 0
343 };
345 /* Enable optional additional functional clock for GPIO4 */
346 setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
347 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
349 /* Enable 96 MHz clock for MMC1 & MMC2 */
350 setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
351 HSMMC_CLKCTRL_CLKSEL_MASK);
352 setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
353 HSMMC_CLKCTRL_CLKSEL_MASK);
355 /* Set the correct clock dividers for mmc */
356 setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
357 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
358 setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
359 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
361 /* Select 32KHz clock as the source of GPTIMER1 */
362 setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
363 GPTIMER1_CLKCTRL_CLKSEL_MASK);
365 do_enable_clocks(clk_domains_essential,
366 clk_modules_hw_auto_essential,
367 clk_modules_explicit_en_essential,
368 1);
370 /* Select 384Mhz for GPU as its the POR for ES1.0 */
371 setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
372 CLKSEL_GPU_HYD_GCLK_MASK);
373 setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
374 CLKSEL_GPU_CORE_GCLK_MASK);
376 /* Enable SCRM OPT clocks for PER and CORE dpll */
377 setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
378 OPTFCLKEN_SCRM_PER_MASK);
379 setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
380 OPTFCLKEN_SCRM_CORE_MASK);
381 }
383 void enable_basic_uboot_clocks(void)
384 {
385 u32 *const clk_domains_essential[] = {
386 0
387 };
389 u32 *const clk_modules_hw_auto_essential[] = {
390 0
391 };
393 u32 *const clk_modules_explicit_en_essential[] = {
394 &prcm->cm_l4per_mcspi1_clkctrl,
395 &prcm->cm_l4per_i2c2_clkctrl,
396 &prcm->cm_l4per_i2c3_clkctrl,
397 &prcm->cm_l4per_i2c4_clkctrl,
398 &prcm->cm_l3init_hsusbtll_clkctrl,
399 &prcm->cm_l3init_hsusbhost_clkctrl,
400 &prcm->cm_l3init_fsusb_clkctrl,
401 0
402 };
404 do_enable_clocks(clk_domains_essential,
405 clk_modules_hw_auto_essential,
406 clk_modules_explicit_en_essential,
407 1);
408 }
410 /*
411 * Enable non-essential clock domains, modules and
412 * do some additional special settings needed
413 */
414 void enable_non_essential_clocks(void)
415 {
416 u32 *const clk_domains_non_essential[] = {
417 &prcm->cm_mpu_m3_clkstctrl,
418 &prcm->cm_ivahd_clkstctrl,
419 &prcm->cm_dsp_clkstctrl,
420 &prcm->cm_dss_clkstctrl,
421 &prcm->cm_sgx_clkstctrl,
422 &prcm->cm1_abe_clkstctrl,
423 &prcm->cm_c2c_clkstctrl,
424 &prcm->cm_cam_clkstctrl,
425 &prcm->cm_dss_clkstctrl,
426 &prcm->cm_sdma_clkstctrl,
427 0
428 };
430 u32 *const clk_modules_hw_auto_non_essential[] = {
431 &prcm->cm_mpu_m3_mpu_m3_clkctrl,
432 &prcm->cm_ivahd_ivahd_clkctrl,
433 &prcm->cm_ivahd_sl2_clkctrl,
434 &prcm->cm_dsp_dsp_clkctrl,
435 &prcm->cm_l3instr_l3_3_clkctrl,
436 &prcm->cm_l3instr_l3_instr_clkctrl,
437 &prcm->cm_l3instr_intrconn_wp1_clkctrl,
438 &prcm->cm_l3init_hsi_clkctrl,
439 &prcm->cm_l4per_hdq1w_clkctrl,
440 0
441 };
443 u32 *const clk_modules_explicit_en_non_essential[] = {
444 &prcm->cm1_abe_aess_clkctrl,
445 &prcm->cm1_abe_pdm_clkctrl,
446 &prcm->cm1_abe_dmic_clkctrl,
447 &prcm->cm1_abe_mcasp_clkctrl,
448 &prcm->cm1_abe_mcbsp1_clkctrl,
449 &prcm->cm1_abe_mcbsp2_clkctrl,
450 &prcm->cm1_abe_mcbsp3_clkctrl,
451 &prcm->cm1_abe_slimbus_clkctrl,
452 &prcm->cm1_abe_timer5_clkctrl,
453 &prcm->cm1_abe_timer6_clkctrl,
454 &prcm->cm1_abe_timer7_clkctrl,
455 &prcm->cm1_abe_timer8_clkctrl,
456 &prcm->cm1_abe_wdt3_clkctrl,
457 &prcm->cm_l4per_gptimer9_clkctrl,
458 &prcm->cm_l4per_gptimer10_clkctrl,
459 &prcm->cm_l4per_gptimer11_clkctrl,
460 &prcm->cm_l4per_gptimer3_clkctrl,
461 &prcm->cm_l4per_gptimer4_clkctrl,
462 &prcm->cm_l4per_mcspi2_clkctrl,
463 &prcm->cm_l4per_mcspi3_clkctrl,
464 &prcm->cm_l4per_mcspi4_clkctrl,
465 &prcm->cm_l4per_mmcsd3_clkctrl,
466 &prcm->cm_l4per_mmcsd4_clkctrl,
467 &prcm->cm_l4per_mmcsd5_clkctrl,
468 &prcm->cm_l4per_uart1_clkctrl,
469 &prcm->cm_l4per_uart2_clkctrl,
470 &prcm->cm_l4per_uart4_clkctrl,
471 &prcm->cm_wkup_keyboard_clkctrl,
472 &prcm->cm_wkup_wdtimer2_clkctrl,
473 &prcm->cm_cam_iss_clkctrl,
474 &prcm->cm_cam_fdif_clkctrl,
475 &prcm->cm_dss_dss_clkctrl,
476 &prcm->cm_sgx_sgx_clkctrl,
477 0
478 };
480 /* Enable optional functional clock for ISS */
481 setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
483 /* Enable all optional functional clocks of DSS */
484 setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
486 do_enable_clocks(clk_domains_non_essential,
487 clk_modules_hw_auto_non_essential,
488 clk_modules_explicit_en_non_essential,
489 0);
491 /* Put camera module in no sleep mode */
492 clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
493 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
494 MODULE_CLKCTRL_MODULEMODE_SHIFT);
495 }