d5f6c1d789e952d385bf6da61c65b4615903730d
1 /*
2 *
3 * HW data initialization for OMAP5
4 *
5 * (C) Copyright 2013
6 * Texas Instruments, <www.ti.com>
7 *
8 * Sricharan R <r.sricharan@ti.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28 #include <common.h>
29 #include <palmas.h>
30 #include <asm/arch/omap.h>
31 #include <asm/arch/sys_proto.h>
32 #include <asm/omap_common.h>
33 #include <asm/arch/clocks.h>
34 #include <asm/omap_gpio.h>
35 #include <asm/io.h>
36 #include <asm/emif.h>
38 struct prcm_regs const **prcm =
39 (struct prcm_regs const **) OMAP_SRAM_SCRATCH_PRCM_PTR;
40 struct dplls const **dplls_data =
41 (struct dplls const **) OMAP_SRAM_SCRATCH_DPLLS_PTR;
42 struct vcores_data const **omap_vcores =
43 (struct vcores_data const **) OMAP_SRAM_SCRATCH_VCORES_PTR;
44 struct omap_sys_ctrl_regs const **ctrl =
45 (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
47 /* OPP HIGH FREQUENCY for ES2.0 */
48 static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
49 {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
50 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
51 {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
52 {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
53 {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
54 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
55 {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
56 };
58 /* OPP NOM FREQUENCY for ES2.0, OPP HIGH for ES1.0 */
59 static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
60 {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
61 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
62 {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
63 {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
64 {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
65 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
66 {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
67 };
69 /* OPP NOM FREQUENCY for ES1.0 */
70 static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
71 {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
72 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
73 {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
74 {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
75 {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
76 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
77 {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
78 };
80 /* OPP LOW FREQUENCY for ES1.0 */
81 static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
82 {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
83 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
84 {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
85 {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
86 {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
87 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
88 {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
89 };
91 /* OPP LOW FREQUENCY for ES2.0 */
92 static const struct dpll_params mpu_dpll_params_499mhz[NUM_SYS_CLKS] = {
93 {499, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
94 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
95 {297, 9, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
96 {493, 18, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
97 {499, 25, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
98 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
99 {493, 37, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
100 };
102 static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
103 {250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
104 {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
105 {119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
106 {625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
107 {500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
108 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
109 {625, 23, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
110 };
112 static const struct dpll_params
113 core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
114 {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */
115 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
116 {443, 6, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */
117 {277, 4, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */
118 {368, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */
119 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
120 {277, 9, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */
121 };
123 static const struct dpll_params
124 core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
125 {266, 2, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 12 MHz */
126 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
127 {443, 6, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 16.8 MHz */
128 {277, 4, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 19.2 MHz */
129 {368, 8, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6}, /* 26 MHz */
130 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
131 {277, 9, 2, 5, 8, 4, 62, 63, 6, 5, 7, 6} /* 38.4 MHz */
132 };
134 static const struct dpll_params
135 core_dpll_params_2128mhz_dra7xx[NUM_SYS_CLKS] = {
136 {266, 2, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 12 MHz */
137 {266, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 20 MHz */
138 {443, 6, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 16.8 MHz */
139 {277, 4, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 19.2 MHz */
140 {368, 8, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 26 MHz */
141 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
142 {277, 9, 2, 1, -1, 4, 62, 5, -1, 5, 4, 6}, /* 38.4 MHz */
143 };
145 static const struct dpll_params
146 core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
147 {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */
148 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
149 {443, 6, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */
150 {277, 4, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */
151 {368, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */
152 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
153 {277, 9, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */
154 };
156 static const struct dpll_params
157 core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
158 {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */
159 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
160 {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */
161 {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */
162 {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */
163 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
164 {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
165 };
167 static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
168 {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
169 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
170 {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
171 {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
172 {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
173 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
174 {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
175 };
177 static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {
178 {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */
179 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
180 {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */
181 {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */
182 {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */
183 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
184 {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */
185 };
187 static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = {
188 {32, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 12 MHz */
189 {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */
190 {160, 6, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 16.8 MHz */
191 {20, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 19.2 MHz */
192 {192, 12, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 26 MHz */
193 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
194 {10, 0, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 38.4 MHz */
195 };
197 static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
198 {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
199 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
200 {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
201 {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
202 {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
203 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
204 {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
205 };
207 static const struct dpll_params iva_dpll_params_2330mhz_dra7xx[NUM_SYS_CLKS] = {
208 {1165, 11, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
209 {233, 3, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
210 {208, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
211 {182, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
212 {224, 4, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
213 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
214 {91, 2, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
215 };
217 /* ABE M & N values with sys_clk as source */
218 static const struct dpll_params
219 abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
220 {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
221 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
222 {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
223 {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
224 {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
225 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
226 {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
227 };
229 /* ABE M & N values with 32K clock as source */
230 static const struct dpll_params abe_dpll_params_32k_196608khz = {
231 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1
232 };
234 /* ABE M & N values with sysclk2(22.5792 MHz) as input */
235 static const struct dpll_params
236 abe_dpll_params_sysclk2_361267khz[NUM_SYS_CLKS] = {
237 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
238 {16, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
239 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
240 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
241 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
242 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
243 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
244 };
246 static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
247 {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
248 {480, 9, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
249 {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
250 {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
251 {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
252 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
253 {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
254 };
256 static const struct dpll_params ddr_dpll_params_2128mhz[NUM_SYS_CLKS] = {
257 {266, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
258 {266, 4, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
259 {190, 2, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
260 {665, 11, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
261 {532, 12, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
262 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
263 {665, 23, 2, 1, 8, -1, -1, -1, -1, -1, -1, -1}, /* 38.4 MHz */
264 };
266 static const struct dpll_params gmac_dpll_params_2000mhz[NUM_SYS_CLKS] = {
267 {250, 2, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 12 MHz */
268 {250, 4, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 20 MHz */
269 {119, 1, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 16.8 MHz */
270 {625, 11, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 19.2 MHz */
271 {500, 12, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 26 MHz */
272 {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
273 {625, 23, 4, 10, 40, 8, 10, -1, -1, -1, -1, -1}, /* 38.4 MHz */
274 };
276 struct dplls omap5_dplls_es1 = {
277 .mpu = mpu_dpll_params_800mhz,
278 .core = core_dpll_params_2128mhz_ddr532,
279 .per = per_dpll_params_768mhz,
280 .iva = iva_dpll_params_2330mhz,
281 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
282 .abe = abe_dpll_params_sysclk_196608khz,
283 #else
284 .abe = &abe_dpll_params_32k_196608khz,
285 #endif
286 .usb = usb_dpll_params_1920mhz,
287 .ddr = NULL
288 };
290 struct dplls omap5_dplls_es2 = {
291 .mpu = mpu_dpll_params_1100mhz,
292 .core = core_dpll_params_2128mhz_ddr532_es2,
293 .per = per_dpll_params_768mhz_es2,
294 .iva = iva_dpll_params_2330mhz,
295 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
296 .abe = abe_dpll_params_sysclk_196608khz,
297 #else
298 .abe = &abe_dpll_params_32k_196608khz,
299 #endif
300 .usb = usb_dpll_params_1920mhz,
301 .ddr = NULL
302 };
304 struct dplls dra7xx_dplls = {
305 .mpu = mpu_dpll_params_1ghz,
306 .core = core_dpll_params_2128mhz_dra7xx,
307 .per = per_dpll_params_768mhz_dra7xx,
308 .abe = abe_dpll_params_sysclk2_361267khz,
309 .iva = iva_dpll_params_2330mhz_dra7xx,
310 .usb = usb_dpll_params_1920mhz,
311 .ddr = ddr_dpll_params_2128mhz,
312 .gmac = gmac_dpll_params_2000mhz,
313 };
315 struct pmic_data palmas = {
316 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
317 .step = 10000, /* 10 mV represented in uV */
318 /*
319 * Offset codes 1-6 all give the base voltage in Palmas
320 * Offset code 0 switches OFF the SMPS
321 */
322 .start_code = 6,
323 .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR,
324 .pmic_bus_init = sri2c_init,
325 .pmic_write = omap_vc_bypass_send_value,
326 };
328 struct pmic_data tps659038 = {
329 .base_offset = PALMAS_SMPS_BASE_VOLT_UV,
330 .step = 10000, /* 10 mV represented in uV */
331 /*
332 * Offset codes 1-6 all give the base voltage in Palmas
333 * Offset code 0 switches OFF the SMPS
334 */
335 .start_code = 6,
336 .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR,
337 .pmic_bus_init = gpi2c_init,
338 .pmic_write = palmas_i2c_write_u8,
339 };
341 struct vcores_data omap5430_volts = {
342 .mpu.value = VDD_MPU,
343 .mpu.addr = SMPS_REG_ADDR_12_MPU,
344 .mpu.pmic = &palmas,
346 .core.value = VDD_CORE,
347 .core.addr = SMPS_REG_ADDR_8_CORE,
348 .core.pmic = &palmas,
350 .mm.value = VDD_MM,
351 .mm.addr = SMPS_REG_ADDR_45_IVA,
352 .mm.pmic = &palmas,
353 };
355 struct vcores_data omap5430_volts_es2 = {
356 .mpu.value = VDD_MPU_ES2,
357 .mpu.addr = SMPS_REG_ADDR_12_MPU,
358 .mpu.pmic = &palmas,
360 .core.value = VDD_CORE_ES2,
361 .core.addr = SMPS_REG_ADDR_8_CORE,
362 .core.pmic = &palmas,
364 .mm.value = VDD_MM_ES2,
365 .mm.addr = SMPS_REG_ADDR_45_IVA,
366 .mm.pmic = &palmas,
367 };
369 struct vcores_data dra752_volts = {
370 .mpu.value = VDD_MPU_DRA752,
371 .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM,
372 .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
373 .mpu.addr = TPS659038_REG_ADDR_SMPS12_MPU,
374 .mpu.pmic = &tps659038,
376 .eve.value = VDD_EVE_DRA752,
377 .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM,
378 .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
379 .eve.addr = TPS659038_REG_ADDR_SMPS45_EVE,
380 .eve.pmic = &tps659038,
382 .gpu.value = VDD_GPU_DRA752,
383 .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM,
384 .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
385 .gpu.addr = TPS659038_REG_ADDR_SMPS6_GPU,
386 .gpu.pmic = &tps659038,
388 .core.value = VDD_CORE_DRA752,
389 .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM,
390 .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
391 .core.addr = TPS659038_REG_ADDR_SMPS7_CORE,
392 .core.pmic = &tps659038,
394 .iva.value = VDD_IVA_DRA752,
395 .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM,
396 .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
397 .iva.addr = TPS659038_REG_ADDR_SMPS8_IVA,
398 .iva.pmic = &tps659038,
399 };
401 /*
402 * Enable essential clock domains, modules and
403 * do some additional special settings needed
404 */
405 void enable_basic_clocks(void)
406 {
407 u32 const clk_domains_essential[] = {
408 (*prcm)->cm_l4per_clkstctrl,
409 (*prcm)->cm_l3init_clkstctrl,
410 (*prcm)->cm_memif_clkstctrl,
411 (*prcm)->cm_l4cfg_clkstctrl,
412 0
413 };
415 u32 const clk_modules_hw_auto_essential[] = {
416 (*prcm)->cm_l3_gpmc_clkctrl,
417 (*prcm)->cm_memif_emif_1_clkctrl,
418 (*prcm)->cm_memif_emif_2_clkctrl,
419 (*prcm)->cm_l4cfg_l4_cfg_clkctrl,
420 (*prcm)->cm_wkup_gpio1_clkctrl,
421 (*prcm)->cm_l4per_gpio2_clkctrl,
422 (*prcm)->cm_l4per_gpio3_clkctrl,
423 (*prcm)->cm_l4per_gpio4_clkctrl,
424 (*prcm)->cm_l4per_gpio5_clkctrl,
425 (*prcm)->cm_l4per_gpio6_clkctrl,
426 0
427 };
429 u32 const clk_modules_explicit_en_essential[] = {
430 (*prcm)->cm_wkup_gptimer1_clkctrl,
431 (*prcm)->cm_l3init_hsmmc1_clkctrl,
432 (*prcm)->cm_l3init_hsmmc2_clkctrl,
433 (*prcm)->cm_l4per_gptimer2_clkctrl,
434 (*prcm)->cm_wkup_wdtimer2_clkctrl,
435 (*prcm)->cm_l4per_uart3_clkctrl,
436 (*prcm)->cm_l4per_i2c1_clkctrl,
437 #ifdef CONFIG_TI_QSPI
438 (*prcm)->cm_l4per_qspi_clkctrl,
439 #endif
440 0
441 };
443 /* Enable optional additional functional clock for GPIO4 */
444 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl,
445 GPIO4_CLKCTRL_OPTFCLKEN_MASK);
447 /* Enable 96 MHz clock for MMC1 & MMC2 */
448 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
449 HSMMC_CLKCTRL_CLKSEL_MASK);
450 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
451 HSMMC_CLKCTRL_CLKSEL_MASK);
453 /* Set the correct clock dividers for mmc */
454 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
455 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
456 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
457 HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
459 /* Select 32KHz clock as the source of GPTIMER1 */
460 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl,
461 GPTIMER1_CLKCTRL_CLKSEL_MASK);
463 do_enable_clocks(clk_domains_essential,
464 clk_modules_hw_auto_essential,
465 clk_modules_explicit_en_essential,
466 1);
468 #ifdef CONFIG_TI_QSPI
469 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24));
470 #endif
472 /* Enable SCRM OPT clocks for PER and CORE dpll */
473 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
474 OPTFCLKEN_SCRM_PER_MASK);
475 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl,
476 OPTFCLKEN_SCRM_CORE_MASK);
477 }
479 void enable_basic_uboot_clocks(void)
480 {
481 u32 const clk_domains_essential[] = {
482 0
483 };
485 u32 const clk_modules_hw_auto_essential[] = {
486 (*prcm)->cm_l3init_hsusbtll_clkctrl,
487 0
488 };
490 u32 const clk_modules_explicit_en_essential[] = {
491 (*prcm)->cm_l4per_mcspi1_clkctrl,
492 (*prcm)->cm_l4per_i2c2_clkctrl,
493 (*prcm)->cm_l4per_i2c3_clkctrl,
494 (*prcm)->cm_l4per_i2c4_clkctrl,
495 (*prcm)->cm_l4per_i2c5_clkctrl,
496 (*prcm)->cm_l3init_hsusbhost_clkctrl,
497 (*prcm)->cm_l3init_fsusb_clkctrl,
498 0
499 };
501 do_enable_clocks(clk_domains_essential,
502 clk_modules_hw_auto_essential,
503 clk_modules_explicit_en_essential,
504 1);
505 }
507 /*
508 * Enable non-essential clock domains, modules and
509 * do some additional special settings needed
510 */
511 void enable_non_essential_clocks(void)
512 {
513 u32 const clk_domains_non_essential[] = {
514 (*prcm)->cm_mpu_m3_clkstctrl,
515 (*prcm)->cm_ivahd_clkstctrl,
516 (*prcm)->cm_dsp_clkstctrl,
517 (*prcm)->cm_dss_clkstctrl,
518 (*prcm)->cm_sgx_clkstctrl,
519 (*prcm)->cm1_abe_clkstctrl,
520 (*prcm)->cm_c2c_clkstctrl,
521 (*prcm)->cm_cam_clkstctrl,
522 (*prcm)->cm_dss_clkstctrl,
523 (*prcm)->cm_sdma_clkstctrl,
524 0
525 };
527 u32 const clk_modules_hw_auto_non_essential[] = {
528 (*prcm)->cm_mpu_m3_mpu_m3_clkctrl,
529 (*prcm)->cm_ivahd_ivahd_clkctrl,
530 (*prcm)->cm_ivahd_sl2_clkctrl,
531 (*prcm)->cm_dsp_dsp_clkctrl,
532 (*prcm)->cm_l3instr_l3_3_clkctrl,
533 (*prcm)->cm_l3instr_l3_instr_clkctrl,
534 (*prcm)->cm_l3instr_intrconn_wp1_clkctrl,
535 (*prcm)->cm_l3init_hsi_clkctrl,
536 (*prcm)->cm_l4per_hdq1w_clkctrl,
537 0
538 };
540 u32 const clk_modules_explicit_en_non_essential[] = {
541 (*prcm)->cm1_abe_aess_clkctrl,
542 (*prcm)->cm1_abe_pdm_clkctrl,
543 (*prcm)->cm1_abe_dmic_clkctrl,
544 (*prcm)->cm1_abe_mcasp_clkctrl,
545 (*prcm)->cm1_abe_mcbsp1_clkctrl,
546 (*prcm)->cm1_abe_mcbsp2_clkctrl,
547 (*prcm)->cm1_abe_mcbsp3_clkctrl,
548 (*prcm)->cm1_abe_slimbus_clkctrl,
549 (*prcm)->cm1_abe_timer5_clkctrl,
550 (*prcm)->cm1_abe_timer6_clkctrl,
551 (*prcm)->cm1_abe_timer7_clkctrl,
552 (*prcm)->cm1_abe_timer8_clkctrl,
553 (*prcm)->cm1_abe_wdt3_clkctrl,
554 (*prcm)->cm_l4per_gptimer9_clkctrl,
555 (*prcm)->cm_l4per_gptimer10_clkctrl,
556 (*prcm)->cm_l4per_gptimer11_clkctrl,
557 (*prcm)->cm_l4per_gptimer3_clkctrl,
558 (*prcm)->cm_l4per_gptimer4_clkctrl,
559 (*prcm)->cm_l4per_mcspi2_clkctrl,
560 (*prcm)->cm_l4per_mcspi3_clkctrl,
561 (*prcm)->cm_l4per_mcspi4_clkctrl,
562 (*prcm)->cm_l4per_mmcsd3_clkctrl,
563 (*prcm)->cm_l4per_mmcsd4_clkctrl,
564 (*prcm)->cm_l4per_mmcsd5_clkctrl,
565 (*prcm)->cm_l4per_uart1_clkctrl,
566 (*prcm)->cm_l4per_uart2_clkctrl,
567 (*prcm)->cm_l4per_uart4_clkctrl,
568 (*prcm)->cm_wkup_keyboard_clkctrl,
569 (*prcm)->cm_wkup_wdtimer2_clkctrl,
570 (*prcm)->cm_cam_iss_clkctrl,
571 (*prcm)->cm_cam_fdif_clkctrl,
572 (*prcm)->cm_dss_dss_clkctrl,
573 (*prcm)->cm_sgx_sgx_clkctrl,
574 0
575 };
577 /* Enable optional functional clock for ISS */
578 setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
580 /* Enable all optional functional clocks of DSS */
581 setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
583 do_enable_clocks(clk_domains_non_essential,
584 clk_modules_hw_auto_non_essential,
585 clk_modules_explicit_en_non_essential,
586 0);
588 /* Put camera module in no sleep mode */
589 clrsetbits_le32((*prcm)->cm_cam_clkstctrl,
590 MODULE_CLKCTRL_MODULEMODE_MASK,
591 CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
592 MODULE_CLKCTRL_MODULEMODE_SHIFT);
593 }
595 const struct ctrl_ioregs ioregs_omap5430 = {
596 .ctrl_ddrch = DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
597 .ctrl_lpddr2ch = DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
598 .ctrl_ddrio_0 = DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
599 .ctrl_ddrio_1 = DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
600 .ctrl_ddrio_2 = DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
601 };
603 const struct ctrl_ioregs ioregs_omap5432_es1 = {
604 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
605 .ctrl_lpddr2ch = 0x0,
606 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
607 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE,
608 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
609 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
610 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
611 };
613 const struct ctrl_ioregs ioregs_omap5432_es2 = {
614 .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
615 .ctrl_lpddr2ch = 0x0,
616 .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2,
617 .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2,
618 .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
619 .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
620 .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
621 };
623 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
624 .ctrl_ddrch = 0x40404040,
625 .ctrl_lpddr2ch = 0x40404040,
626 .ctrl_ddr3ch = 0x80808080,
627 .ctrl_ddrio_0 = 0xbae8c631,
628 .ctrl_ddrio_1 = 0xb46318d8,
629 .ctrl_ddrio_2 = 0x84210000,
630 .ctrl_emif_sdram_config_ext = 0xb2c00000,
631 .ctrl_ddr_ctrl_ext_0 = 0xA2000000,
632 };
634 void hw_data_init(void)
635 {
636 u32 omap_rev = omap_revision();
638 switch (omap_rev) {
640 case OMAP5430_ES1_0:
641 case OMAP5432_ES1_0:
642 *prcm = &omap5_es1_prcm;
643 *dplls_data = &omap5_dplls_es1;
644 *omap_vcores = &omap5430_volts;
645 *ctrl = &omap5_ctrl;
646 break;
648 case OMAP5430_ES2_0:
649 case OMAP5432_ES2_0:
650 *prcm = &omap5_es2_prcm;
651 *dplls_data = &omap5_dplls_es2;
652 *omap_vcores = &omap5430_volts_es2;
653 *ctrl = &omap5_ctrl;
654 break;
656 case DRA752_ES1_0:
657 *prcm = &dra7xx_prcm;
658 *dplls_data = &dra7xx_dplls;
659 *omap_vcores = &dra752_volts;
660 *ctrl = &dra7xx_ctrl;
661 break;
663 default:
664 printf("\n INVALID OMAP REVISION ");
665 }
666 }
668 void get_ioregs(const struct ctrl_ioregs **regs)
669 {
670 u32 omap_rev = omap_revision();
672 switch (omap_rev) {
673 case OMAP5430_ES1_0:
674 case OMAP5430_ES2_0:
675 *regs = &ioregs_omap5430;
676 break;
677 case OMAP5432_ES1_0:
678 *regs = &ioregs_omap5432_es1;
679 break;
680 case OMAP5432_ES2_0:
681 *regs = &ioregs_omap5432_es2;
682 break;
683 case DRA752_ES1_0:
684 *regs = &ioregs_dra7xx_es1;
685 break;
687 default:
688 printf("\n INVALID OMAP REVISION ");
689 }
690 }