ARM: OMAP4+: Make control module register structure generic
[glsdk/glsdk-u-boot.git] / arch / arm / cpu / armv7 / omap5 / hwinit.c
1 /*
2  *
3  * Functions for omap5 based boards.
4  *
5  * (C) Copyright 2011
6  * Texas Instruments, <www.ti.com>
7  *
8  * Author :
9  *      Aneesh V        <aneesh@ti.com>
10  *      Steve Sakoman   <steve@sakoman.com>
11  *      Sricharan       <r.sricharan@ti.com>
12  *
13  * See file CREDITS for list of people who contributed to this
14  * project.
15  *
16  * This program is free software; you can redistribute it and/or
17  * modify it under the terms of the GNU General Public License as
18  * published by the Free Software Foundation; either version 2 of
19  * the License, or (at your option) any later version.
20  *
21  * This program is distributed in the hope that it will be useful,
22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24  * GNU General Public License for more details.
25  *
26  * You should have received a copy of the GNU General Public License
27  * along with this program; if not, write to the Free Software
28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29  * MA 02111-1307 USA
30  */
31 #include <common.h>
32 #include <asm/armv7.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/sys_proto.h>
35 #include <asm/sizes.h>
36 #include <asm/utils.h>
37 #include <asm/arch/gpio.h>
38 #include <asm/emif.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
44 static struct gpio_bank gpio_bank_54xx[6] = {
45         { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
46         { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
47         { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
48         { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
49         { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
50         { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
51 };
53 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
55 #ifdef CONFIG_SPL_BUILD
56 /* LPDDR2 specific IO settings */
57 static void io_settings_lpddr2(void)
58 {
59         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
60                                 (*ctrl)->control_ddrch1_0);
61         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
62                                 (*ctrl)->control_ddrch1_1);
63         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
64                                 (*ctrl)->control_ddrch2_0);
65         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN,
66                                 (*ctrl)->control_ddrch2_1);
67         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
68                                 (*ctrl)->control_lpddr2ch1_0);
69         writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN,
70                                 (*ctrl)->control_lpddr2ch1_1);
71         writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL,
72                                 (*ctrl)->control_ddrio_0);
73         writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL,
74                                 (*ctrl)->control_ddrio_1);
75         writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL,
76                                 (*ctrl)->control_ddrio_2);
77 }
79 /* DDR3 specific IO settings */
80 static void io_settings_ddr3(void)
81 {
82         u32 io_settings = 0;
84         writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
85                                 (*ctrl)->control_ddr3ch1_0);
86         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
87                                 (*ctrl)->control_ddrch1_0);
88         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
89                                 (*ctrl)->control_ddrch1_1);
91         writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL,
92                                 (*ctrl)->control_ddr3ch2_0);
93         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
94                                 (*ctrl)->control_ddrch2_0);
95         writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL,
96                                 (*ctrl)->control_ddrch2_1);
98         writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE,
99                                 (*ctrl)->control_ddrio_0);
100         writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE,
101                                 (*ctrl)->control_ddrio_1);
102         writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE,
103                                 (*ctrl)->control_ddrio_2);
105         /* omap5432 does not use lpddr2 */
106         writel(0x0, (*ctrl)->control_lpddr2ch1_0);
107         writel(0x0, (*ctrl)->control_lpddr2ch1_1);
109         writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
110                         (*ctrl)->control_emif1_sdram_config_ext);
111         writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
112                         (*ctrl)->control_emif2_sdram_config_ext);
114         /* Disable DLL select */
115         io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
116                                                         & 0xFFEFFFFF);
117         writel(io_settings,
118                 (*ctrl)->control_port_emif1_sdram_config);
120         io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
121                                                         & 0xFFEFFFFF);
122         writel(io_settings,
123                 (*ctrl)->control_port_emif2_sdram_config);
126 /*
127  * Some tuning of IOs for optimal power and performance
128  */
129 void do_io_settings(void)
131         u32 io_settings = 0, mask = 0;
133         /* Impedance settings EMMC, C2C 1,2, hsi2 */
134         mask = (ds_mask << 2) | (ds_mask << 8) |
135                 (ds_mask << 16) | (ds_mask << 18);
136         io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
137                                 (~mask);
138         io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
139                         (ds_45_ohm << 18) | (ds_60_ohm << 2);
140         writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
142         /* Impedance settings Mcspi2 */
143         mask = (ds_mask << 30);
144         io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
145                         (~mask);
146         io_settings |= (ds_60_ohm << 30);
147         writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
149         /* Impedance settings C2C 3,4 */
150         mask = (ds_mask << 14) | (ds_mask << 16);
151         io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
152                         (~mask);
153         io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
154         writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
156         /* Slew rate settings EMMC, C2C 1,2 */
157         mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
158         io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
159                         (~mask);
160         io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
161         writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
163         /* Slew rate settings hsi2, Mcspi2 */
164         mask = (sc_mask << 24) | (sc_mask << 28);
165         io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
166                         (~mask);
167         io_settings |= (sc_fast << 28) | (sc_fast << 24);
168         writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
170         /* Slew rate settings C2C 3,4 */
171         mask = (sc_mask << 16) | (sc_mask << 18);
172         io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
173                         (~mask);
174         io_settings |= (sc_na << 16) | (sc_na << 18);
175         writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
177         /* impedance and slew rate settings for usb */
178         mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
179                 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
180         io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
181                         (~mask);
182         io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
183                        (ds_60_ohm << 23) | (sc_fast << 20) |
184                        (sc_fast << 17) | (sc_fast << 14);
185         writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
187         if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
188                 io_settings_lpddr2();
189         else
190                 io_settings_ddr3();
192         /* Efuse settings */
193         writel(EFUSE_1, (*ctrl)->control_efuse_1);
194         writel(EFUSE_2, (*ctrl)->control_efuse_2);
195         writel(EFUSE_3, (*ctrl)->control_efuse_3);
196         writel(EFUSE_4, (*ctrl)->control_efuse_4);
198 #endif
200 void config_data_eye_leveling_samples(u32 emif_base)
202         /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
203         if (emif_base == EMIF1_BASE)
204                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
205                         (*ctrl)->control_emif1_sdram_config_ext);
206         else if (emif_base == EMIF2_BASE)
207                 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
208                         (*ctrl)->control_emif2_sdram_config_ext);
211 void init_omap_revision(void)
213         /*
214          * For some of the ES2/ES1 boards ID_CODE is not reliable:
215          * Also, ES1 and ES2 have different ARM revisions
216          * So use ARM revision for identification
217          */
218         unsigned int rev = cortex_rev();
220         switch (rev) {
221         case MIDR_CORTEX_A15_R0P0:
222                 switch (readl(CONTROL_ID_CODE)) {
223                 case OMAP5430_CONTROL_ID_CODE_ES1_0:
224                         *omap_si_rev = OMAP5430_ES1_0;
225                         break;
226                 case OMAP5432_CONTROL_ID_CODE_ES1_0:
227                 default:
228                         *omap_si_rev = OMAP5432_ES1_0;
229                         break;
230                 }
231                 break;
232         default:
233                 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
234         }
237 void reset_cpu(ulong ignored)
239         u32 omap_rev = omap_revision();
241         /*
242          * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
243          * So use cold reset in case instead.
244          */
245         if (omap_rev == OMAP5430_ES1_0)
246                 writel(PRM_RSTCTRL_RESET << 0x1, PRM_RSTCTRL);
247         else
248                 writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);