ARM: OMAP5: clock: Add the prcm register changes required for ES2.0
[glsdk/glsdk-u-boot.git] / arch / arm / cpu / armv7 / omap5 / prcm-regs.c
1 /*
2  *
3  * HW regs data for OMAP5 Soc
4  *
5  * (C) Copyright 2013
6  * Texas Instruments, <www.ti.com>
7  *
8  * Sricharan R <r.sricharan@ti.com>
9  *
10  * See file CREDITS for list of people who contributed to this
11  * project.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License as
15  * published by the Free Software Foundation; either version 2 of
16  * the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26  * MA 02111-1307 USA
27  */
29 #include <asm/omap_common.h>
31 struct prcm_regs const omap5_es1_prcm = {
32         /* cm1.ckgen */
33         .cm_clksel_core = 0x4a004100,
34         .cm_clksel_abe = 0x4a004108,
35         .cm_dll_ctrl = 0x4a004110,
36         .cm_clkmode_dpll_core = 0x4a004120,
37         .cm_idlest_dpll_core = 0x4a004124,
38         .cm_autoidle_dpll_core = 0x4a004128,
39         .cm_clksel_dpll_core = 0x4a00412c,
40         .cm_div_m2_dpll_core = 0x4a004130,
41         .cm_div_m3_dpll_core = 0x4a004134,
42         .cm_div_h11_dpll_core = 0x4a004138,
43         .cm_div_h12_dpll_core = 0x4a00413c,
44         .cm_div_h13_dpll_core = 0x4a004140,
45         .cm_div_h14_dpll_core = 0x4a004144,
46         .cm_ssc_deltamstep_dpll_core = 0x4a004148,
47         .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
48         .cm_emu_override_dpll_core = 0x4a004150,
49         .cm_div_h22_dpllcore = 0x4a004154,
50         .cm_div_h23_dpll_core = 0x4a004158,
51         .cm_clkmode_dpll_mpu = 0x4a004160,
52         .cm_idlest_dpll_mpu = 0x4a004164,
53         .cm_autoidle_dpll_mpu = 0x4a004168,
54         .cm_clksel_dpll_mpu = 0x4a00416c,
55         .cm_div_m2_dpll_mpu = 0x4a004170,
56         .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
57         .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
58         .cm_bypclk_dpll_mpu = 0x4a00419c,
59         .cm_clkmode_dpll_iva = 0x4a0041a0,
60         .cm_idlest_dpll_iva = 0x4a0041a4,
61         .cm_autoidle_dpll_iva = 0x4a0041a8,
62         .cm_clksel_dpll_iva = 0x4a0041ac,
63         .cm_div_h11_dpll_iva = 0x4a0041b8,
64         .cm_div_h12_dpll_iva = 0x4a0041bc,
65         .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
66         .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
67         .cm_bypclk_dpll_iva = 0x4a0041dc,
68         .cm_clkmode_dpll_abe = 0x4a0041e0,
69         .cm_idlest_dpll_abe = 0x4a0041e4,
70         .cm_autoidle_dpll_abe = 0x4a0041e8,
71         .cm_clksel_dpll_abe = 0x4a0041ec,
72         .cm_div_m2_dpll_abe = 0x4a0041f0,
73         .cm_div_m3_dpll_abe = 0x4a0041f4,
74         .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
75         .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
76         .cm_clkmode_dpll_ddrphy = 0x4a004220,
77         .cm_idlest_dpll_ddrphy = 0x4a004224,
78         .cm_autoidle_dpll_ddrphy = 0x4a004228,
79         .cm_clksel_dpll_ddrphy = 0x4a00422c,
80         .cm_div_m2_dpll_ddrphy = 0x4a004230,
81         .cm_div_h11_dpll_ddrphy = 0x4a004238,
82         .cm_div_h12_dpll_ddrphy = 0x4a00423c,
83         .cm_div_h13_dpll_ddrphy = 0x4a004240,
84         .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
85         .cm_shadow_freq_config1 = 0x4a004260,
86         .cm_mpu_mpu_clkctrl = 0x4a004320,
88         /* cm1.dsp */
89         .cm_dsp_clkstctrl = 0x4a004400,
90         .cm_dsp_dsp_clkctrl = 0x4a004420,
92         /* cm1.abe */
93         .cm1_abe_clkstctrl = 0x4a004500,
94         .cm1_abe_l4abe_clkctrl = 0x4a004520,
95         .cm1_abe_aess_clkctrl = 0x4a004528,
96         .cm1_abe_pdm_clkctrl = 0x4a004530,
97         .cm1_abe_dmic_clkctrl = 0x4a004538,
98         .cm1_abe_mcasp_clkctrl = 0x4a004540,
99         .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
100         .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
101         .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
102         .cm1_abe_slimbus_clkctrl = 0x4a004560,
103         .cm1_abe_timer5_clkctrl = 0x4a004568,
104         .cm1_abe_timer6_clkctrl = 0x4a004570,
105         .cm1_abe_timer7_clkctrl = 0x4a004578,
106         .cm1_abe_timer8_clkctrl = 0x4a004580,
107         .cm1_abe_wdt3_clkctrl = 0x4a004588,
109         /* cm2.ckgen */
110         .cm_clksel_mpu_m3_iss_root = 0x4a008100,
111         .cm_clksel_usb_60mhz = 0x4a008104,
112         .cm_scale_fclk = 0x4a008108,
113         .cm_core_dvfs_perf1 = 0x4a008110,
114         .cm_core_dvfs_perf2 = 0x4a008114,
115         .cm_core_dvfs_perf3 = 0x4a008118,
116         .cm_core_dvfs_perf4 = 0x4a00811c,
117         .cm_core_dvfs_current = 0x4a008124,
118         .cm_iva_dvfs_perf_tesla = 0x4a008128,
119         .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
120         .cm_iva_dvfs_perf_abe = 0x4a008130,
121         .cm_iva_dvfs_current = 0x4a008138,
122         .cm_clkmode_dpll_per = 0x4a008140,
123         .cm_idlest_dpll_per = 0x4a008144,
124         .cm_autoidle_dpll_per = 0x4a008148,
125         .cm_clksel_dpll_per = 0x4a00814c,
126         .cm_div_m2_dpll_per = 0x4a008150,
127         .cm_div_m3_dpll_per = 0x4a008154,
128         .cm_div_h11_dpll_per = 0x4a008158,
129         .cm_div_h12_dpll_per = 0x4a00815c,
130         .cm_div_h14_dpll_per = 0x4a008164,
131         .cm_ssc_deltamstep_dpll_per = 0x4a008168,
132         .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
133         .cm_emu_override_dpll_per = 0x4a008170,
134         .cm_clkmode_dpll_usb = 0x4a008180,
135         .cm_idlest_dpll_usb = 0x4a008184,
136         .cm_autoidle_dpll_usb = 0x4a008188,
137         .cm_clksel_dpll_usb = 0x4a00818c,
138         .cm_div_m2_dpll_usb = 0x4a008190,
139         .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
140         .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
141         .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
142         .cm_clkmode_dpll_unipro = 0x4a0081c0,
143         .cm_idlest_dpll_unipro = 0x4a0081c4,
144         .cm_autoidle_dpll_unipro = 0x4a0081c8,
145         .cm_clksel_dpll_unipro = 0x4a0081cc,
146         .cm_div_m2_dpll_unipro = 0x4a0081d0,
147         .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
148         .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
150         /* cm2.core */
151         .cm_coreaon_bandgap_clkctrl = 0x4a008648,
152         .cm_l3_1_clkstctrl = 0x4a008700,
153         .cm_l3_1_dynamicdep = 0x4a008708,
154         .cm_l3_1_l3_1_clkctrl = 0x4a008720,
155         .cm_l3_2_clkstctrl = 0x4a008800,
156         .cm_l3_2_dynamicdep = 0x4a008808,
157         .cm_l3_2_l3_2_clkctrl = 0x4a008820,
158         .cm_l3_2_gpmc_clkctrl = 0x4a008828,
159         .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
160         .cm_mpu_m3_clkstctrl = 0x4a008900,
161         .cm_mpu_m3_staticdep = 0x4a008904,
162         .cm_mpu_m3_dynamicdep = 0x4a008908,
163         .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
164         .cm_sdma_clkstctrl = 0x4a008a00,
165         .cm_sdma_staticdep = 0x4a008a04,
166         .cm_sdma_dynamicdep = 0x4a008a08,
167         .cm_sdma_sdma_clkctrl = 0x4a008a20,
168         .cm_memif_clkstctrl = 0x4a008b00,
169         .cm_memif_dmm_clkctrl = 0x4a008b20,
170         .cm_memif_emif_fw_clkctrl = 0x4a008b28,
171         .cm_memif_emif_1_clkctrl = 0x4a008b30,
172         .cm_memif_emif_2_clkctrl = 0x4a008b38,
173         .cm_memif_dll_clkctrl = 0x4a008b40,
174         .cm_memif_emif_h1_clkctrl = 0x4a008b50,
175         .cm_memif_emif_h2_clkctrl = 0x4a008b58,
176         .cm_memif_dll_h_clkctrl = 0x4a008b60,
177         .cm_c2c_clkstctrl = 0x4a008c00,
178         .cm_c2c_staticdep = 0x4a008c04,
179         .cm_c2c_dynamicdep = 0x4a008c08,
180         .cm_c2c_sad2d_clkctrl = 0x4a008c20,
181         .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
182         .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
183         .cm_l4cfg_clkstctrl = 0x4a008d00,
184         .cm_l4cfg_dynamicdep = 0x4a008d08,
185         .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
186         .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
187         .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
188         .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
189         .cm_l3instr_clkstctrl = 0x4a008e00,
190         .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
191         .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
192         .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
194         /* cm2.ivahd */
195         .cm_ivahd_clkstctrl = 0x4a008f00,
196         .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
197         .cm_ivahd_sl2_clkctrl = 0x4a008f28,
199         /* cm2.cam */
200         .cm_cam_clkstctrl = 0x4a009000,
201         .cm_cam_iss_clkctrl = 0x4a009020,
202         .cm_cam_fdif_clkctrl = 0x4a009028,
204         /* cm2.dss */
205         .cm_dss_clkstctrl = 0x4a009100,
206         .cm_dss_dss_clkctrl = 0x4a009120,
208         /* cm2.sgx */
209         .cm_sgx_clkstctrl = 0x4a009200,
210         .cm_sgx_sgx_clkctrl = 0x4a009220,
212         /* cm2.l3init */
213         .cm_l3init_clkstctrl = 0x4a009300,
214         .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
215         .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
216         .cm_l3init_hsi_clkctrl = 0x4a009338,
217         .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
218         .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
219         .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
220         .cm_l3init_p1500_clkctrl = 0x4a009378,
221         .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
222         .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
224         /* cm2.l4per */
225         .cm_l4per_clkstctrl = 0x4a009400,
226         .cm_l4per_dynamicdep = 0x4a009408,
227         .cm_l4per_adc_clkctrl = 0x4a009420,
228         .cm_l4per_gptimer10_clkctrl = 0x4a009428,
229         .cm_l4per_gptimer11_clkctrl = 0x4a009430,
230         .cm_l4per_gptimer2_clkctrl = 0x4a009438,
231         .cm_l4per_gptimer3_clkctrl = 0x4a009440,
232         .cm_l4per_gptimer4_clkctrl = 0x4a009448,
233         .cm_l4per_gptimer9_clkctrl = 0x4a009450,
234         .cm_l4per_elm_clkctrl = 0x4a009458,
235         .cm_l4per_gpio2_clkctrl = 0x4a009460,
236         .cm_l4per_gpio3_clkctrl = 0x4a009468,
237         .cm_l4per_gpio4_clkctrl = 0x4a009470,
238         .cm_l4per_gpio5_clkctrl = 0x4a009478,
239         .cm_l4per_gpio6_clkctrl = 0x4a009480,
240         .cm_l4per_hdq1w_clkctrl = 0x4a009488,
241         .cm_l4per_hecc1_clkctrl = 0x4a009490,
242         .cm_l4per_hecc2_clkctrl = 0x4a009498,
243         .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
244         .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
245         .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
246         .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
247         .cm_l4per_l4per_clkctrl = 0x4a0094c0,
248         .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
249         .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
250         .cm_l4per_mgate_clkctrl = 0x4a0094e8,
251         .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
252         .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
253         .cm_l4per_mcspi3_clkctrl = 0x4a009500,
254         .cm_l4per_mcspi4_clkctrl = 0x4a009508,
255         .cm_l4per_gpio7_clkctrl = 0x4a009510,
256         .cm_l4per_gpio8_clkctrl = 0x4a009518,
257         .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
258         .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
259         .cm_l4per_msprohg_clkctrl = 0x4a009530,
260         .cm_l4per_slimbus2_clkctrl = 0x4a009538,
261         .cm_l4per_uart1_clkctrl = 0x4a009540,
262         .cm_l4per_uart2_clkctrl = 0x4a009548,
263         .cm_l4per_uart3_clkctrl = 0x4a009550,
264         .cm_l4per_uart4_clkctrl = 0x4a009558,
265         .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
266         .cm_l4per_i2c5_clkctrl = 0x4a009568,
267         .cm_l4per_uart5_clkctrl = 0x4a009570,
268         .cm_l4per_uart6_clkctrl = 0x4a009578,
269         .cm_l4sec_clkstctrl = 0x4a009580,
270         .cm_l4sec_staticdep = 0x4a009584,
271         .cm_l4sec_dynamicdep = 0x4a009588,
272         .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
273         .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
274         .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
275         .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
276         .cm_l4sec_rng_clkctrl = 0x4a0095c0,
277         .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
278         .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
280         /* l4 wkup regs */
281         .cm_abe_pll_ref_clksel = 0x4ae0610c,
282         .cm_sys_clksel = 0x4ae06110,
283         .cm_wkup_clkstctrl = 0x4ae07800,
284         .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
285         .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
286         .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
287         .cm_wkup_gpio1_clkctrl = 0x4ae07838,
288         .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
289         .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
290         .cm_wkup_synctimer_clkctrl = 0x4ae07850,
291         .cm_wkup_usim_clkctrl = 0x4ae07858,
292         .cm_wkup_sarram_clkctrl = 0x4ae07860,
293         .cm_wkup_keyboard_clkctrl = 0x4ae07878,
294         .cm_wkup_rtc_clkctrl = 0x4ae07880,
295         .cm_wkup_bandgap_clkctrl = 0x4ae07888,
296         .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
297         .prm_vc_val_bypass = 0x4ae07ba0,
298         .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
299         .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
300         .prm_sldo_core_setup = 0x4ae07bc4,
301         .prm_sldo_core_ctrl = 0x4ae07bc8,
302         .prm_sldo_mpu_setup = 0x4ae07bcc,
303         .prm_sldo_mpu_ctrl = 0x4ae07bd0,
304         .prm_sldo_mm_setup = 0x4ae07bd4,
305         .prm_sldo_mm_ctrl = 0x4ae07bd8,
306 };
308 struct omap_sys_ctrl_regs const omap5_ctrl = {
309         .control_status                         = 0x4A002134,
310         .control_paconf_global                  = 0x4A002DA0,
311         .control_paconf_mode                    = 0x4A002DA4,
312         .control_smart1io_padconf_0             = 0x4A002DA8,
313         .control_smart1io_padconf_1             = 0x4A002DAC,
314         .control_smart1io_padconf_2             = 0x4A002DB0,
315         .control_smart2io_padconf_0             = 0x4A002DB4,
316         .control_smart2io_padconf_1             = 0x4A002DB8,
317         .control_smart2io_padconf_2             = 0x4A002DBC,
318         .control_smart3io_padconf_0             = 0x4A002DC0,
319         .control_smart3io_padconf_1             = 0x4A002DC4,
320         .control_pbias                          = 0x4A002E00,
321         .control_i2c_0                          = 0x4A002E04,
322         .control_camera_rx                      = 0x4A002E08,
323         .control_hdmi_tx_phy                    = 0x4A002E0C,
324         .control_uniportm                       = 0x4A002E10,
325         .control_dsiphy                         = 0x4A002E14,
326         .control_mcbsplp                        = 0x4A002E18,
327         .control_usb2phycore                    = 0x4A002E1C,
328         .control_hdmi_1                         = 0x4A002E20,
329         .control_hsi                            = 0x4A002E24,
330         .control_ddr3ch1_0                      = 0x4A002E30,
331         .control_ddr3ch2_0                      = 0x4A002E34,
332         .control_ddrch1_0                       = 0x4A002E38,
333         .control_ddrch1_1                       = 0x4A002E3C,
334         .control_ddrch2_0                       = 0x4A002E40,
335         .control_ddrch2_1                       = 0x4A002E44,
336         .control_lpddr2ch1_0                    = 0x4A002E48,
337         .control_lpddr2ch1_1                    = 0x4A002E4C,
338         .control_ddrio_0                        = 0x4A002E50,
339         .control_ddrio_1                        = 0x4A002E54,
340         .control_ddrio_2                        = 0x4A002E58,
341         .control_hyst_1                         = 0x4A002E5C,
342         .control_usbb_hsic_control              = 0x4A002E60,
343         .control_c2c                            = 0x4A002E64,
344         .control_core_control_spare_rw          = 0x4A002E68,
345         .control_core_control_spare_r           = 0x4A002E6C,
346         .control_core_control_spare_r_c0        = 0x4A002E70,
347         .control_srcomp_north_side              = 0x4A002E74,
348         .control_srcomp_south_side              = 0x4A002E78,
349         .control_srcomp_east_side               = 0x4A002E7C,
350         .control_srcomp_west_side               = 0x4A002E80,
351         .control_srcomp_code_latch              = 0x4A002E84,
352         .control_port_emif1_sdram_config        = 0x4AE0C110,
353         .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
354         .control_port_emif2_sdram_config        = 0x4AE0C118,
355         .control_emif1_sdram_config_ext         = 0x4AE0C144,
356         .control_emif2_sdram_config_ext         = 0x4AE0C148,
357         .control_smart1nopmio_padconf_0         = 0x4AE0CDA0,
358         .control_smart1nopmio_padconf_1         = 0x4AE0CDA4,
359         .control_padconf_mode                   = 0x4AE0CDA8,
360         .control_xtal_oscillator                = 0x4AE0CDAC,
361         .control_i2c_2                          = 0x4AE0CDB0,
362         .control_ckobuffer                      = 0x4AE0CDB4,
363         .control_wkup_control_spare_rw          = 0x4AE0CDB8,
364         .control_wkup_control_spare_r           = 0x4AE0CDBC,
365         .control_wkup_control_spare_r_c0        = 0x4AE0CDC0,
366         .control_srcomp_east_side_wkup          = 0x4AE0CDC4,
367         .control_efuse_1                        = 0x4AE0CDC8,
368         .control_efuse_2                        = 0x4AE0CDCC,
369         .control_efuse_3                        = 0x4AE0CDD0,
370         .control_efuse_4                        = 0x4AE0CDD4,
371         .control_efuse_5                        = 0x4AE0CDD8,
372         .control_efuse_6                        = 0x4AE0CDDC,
373         .control_efuse_7                        = 0x4AE0CDE0,
374         .control_efuse_8                        = 0x4AE0CDE4,
375         .control_efuse_9                        = 0x4AE0CDE8,
376         .control_efuse_10                       = 0x4AE0CDEC,
377         .control_efuse_11                       = 0x4AE0CDF0,
378         .control_efuse_12                       = 0x4AE0CDF4,
379         .control_efuse_13                       = 0x4AE0CDF8,
380 };
382 struct prcm_regs const omap5_es2_prcm = {
383         /* cm1.ckgen */
384         .cm_clksel_core = 0x4a004100,
385         .cm_clksel_abe = 0x4a004108,
386         .cm_dll_ctrl = 0x4a004110,
387         .cm_clkmode_dpll_core = 0x4a004120,
388         .cm_idlest_dpll_core = 0x4a004124,
389         .cm_autoidle_dpll_core = 0x4a004128,
390         .cm_clksel_dpll_core = 0x4a00412c,
391         .cm_div_m2_dpll_core = 0x4a004130,
392         .cm_div_m3_dpll_core = 0x4a004134,
393         .cm_div_h11_dpll_core = 0x4a004138,
394         .cm_div_h12_dpll_core = 0x4a00413c,
395         .cm_div_h13_dpll_core = 0x4a004140,
396         .cm_div_h14_dpll_core = 0x4a004144,
397         .cm_ssc_deltamstep_dpll_core = 0x4a004148,
398         .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
399         .cm_div_h21_dpll_core = 0x4a004150,
400         .cm_div_h22_dpllcore = 0x4a004154,
401         .cm_div_h23_dpll_core = 0x4a004158,
402         .cm_div_h24_dpll_core = 0x4a00415c,
403         .cm_clkmode_dpll_mpu = 0x4a004160,
404         .cm_idlest_dpll_mpu = 0x4a004164,
405         .cm_autoidle_dpll_mpu = 0x4a004168,
406         .cm_clksel_dpll_mpu = 0x4a00416c,
407         .cm_div_m2_dpll_mpu = 0x4a004170,
408         .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
409         .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
410         .cm_bypclk_dpll_mpu = 0x4a00419c,
411         .cm_clkmode_dpll_iva = 0x4a0041a0,
412         .cm_idlest_dpll_iva = 0x4a0041a4,
413         .cm_autoidle_dpll_iva = 0x4a0041a8,
414         .cm_clksel_dpll_iva = 0x4a0041ac,
415         .cm_div_h11_dpll_iva = 0x4a0041b8,
416         .cm_div_h12_dpll_iva = 0x4a0041bc,
417         .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
418         .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
419         .cm_bypclk_dpll_iva = 0x4a0041dc,
420         .cm_clkmode_dpll_abe = 0x4a0041e0,
421         .cm_idlest_dpll_abe = 0x4a0041e4,
422         .cm_autoidle_dpll_abe = 0x4a0041e8,
423         .cm_clksel_dpll_abe = 0x4a0041ec,
424         .cm_div_m2_dpll_abe = 0x4a0041f0,
425         .cm_div_m3_dpll_abe = 0x4a0041f4,
426         .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
427         .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
428         .cm_clkmode_dpll_ddrphy = 0x4a004220,
429         .cm_idlest_dpll_ddrphy = 0x4a004224,
430         .cm_autoidle_dpll_ddrphy = 0x4a004228,
431         .cm_clksel_dpll_ddrphy = 0x4a00422c,
432         .cm_div_m2_dpll_ddrphy = 0x4a004230,
433         .cm_div_h11_dpll_ddrphy = 0x4a004238,
434         .cm_div_h12_dpll_ddrphy = 0x4a00423c,
435         .cm_div_h13_dpll_ddrphy = 0x4a004240,
436         .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
437         .cm_shadow_freq_config1 = 0x4a004260,
438         .cm_mpu_mpu_clkctrl = 0x4a004320,
440         /* cm1.dsp */
441         .cm_dsp_clkstctrl = 0x4a004400,
442         .cm_dsp_dsp_clkctrl = 0x4a004420,
444         /* cm1.abe */
445         .cm1_abe_clkstctrl = 0x4a004500,
446         .cm1_abe_l4abe_clkctrl = 0x4a004520,
447         .cm1_abe_aess_clkctrl = 0x4a004528,
448         .cm1_abe_pdm_clkctrl = 0x4a004530,
449         .cm1_abe_dmic_clkctrl = 0x4a004538,
450         .cm1_abe_mcasp_clkctrl = 0x4a004540,
451         .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
452         .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
453         .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
454         .cm1_abe_slimbus_clkctrl = 0x4a004560,
455         .cm1_abe_timer5_clkctrl = 0x4a004568,
456         .cm1_abe_timer6_clkctrl = 0x4a004570,
457         .cm1_abe_timer7_clkctrl = 0x4a004578,
458         .cm1_abe_timer8_clkctrl = 0x4a004580,
459         .cm1_abe_wdt3_clkctrl = 0x4a004588,
463         /* cm2.ckgen */
464         .cm_clksel_mpu_m3_iss_root = 0x4a008100,
465         .cm_clksel_usb_60mhz = 0x4a008104,
466         .cm_scale_fclk = 0x4a008108,
467         .cm_core_dvfs_perf1 = 0x4a008110,
468         .cm_core_dvfs_perf2 = 0x4a008114,
469         .cm_core_dvfs_perf3 = 0x4a008118,
470         .cm_core_dvfs_perf4 = 0x4a00811c,
471         .cm_core_dvfs_current = 0x4a008124,
472         .cm_iva_dvfs_perf_tesla = 0x4a008128,
473         .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
474         .cm_iva_dvfs_perf_abe = 0x4a008130,
475         .cm_iva_dvfs_current = 0x4a008138,
476         .cm_clkmode_dpll_per = 0x4a008140,
477         .cm_idlest_dpll_per = 0x4a008144,
478         .cm_autoidle_dpll_per = 0x4a008148,
479         .cm_clksel_dpll_per = 0x4a00814c,
480         .cm_div_m2_dpll_per = 0x4a008150,
481         .cm_div_m3_dpll_per = 0x4a008154,
482         .cm_div_h11_dpll_per = 0x4a008158,
483         .cm_div_h12_dpll_per = 0x4a00815c,
484         .cm_div_h13_dpll_per = 0x4a008160,
485         .cm_div_h14_dpll_per = 0x4a008164,
486         .cm_ssc_deltamstep_dpll_per = 0x4a008168,
487         .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
488         .cm_emu_override_dpll_per = 0x4a008170,
489         .cm_clkmode_dpll_usb = 0x4a008180,
490         .cm_idlest_dpll_usb = 0x4a008184,
491         .cm_autoidle_dpll_usb = 0x4a008188,
492         .cm_clksel_dpll_usb = 0x4a00818c,
493         .cm_div_m2_dpll_usb = 0x4a008190,
494         .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
495         .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
496         .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
497         .cm_clkmode_dpll_unipro = 0x4a0081c0,
498         .cm_idlest_dpll_unipro = 0x4a0081c4,
499         .cm_autoidle_dpll_unipro = 0x4a0081c8,
500         .cm_clksel_dpll_unipro = 0x4a0081cc,
501         .cm_div_m2_dpll_unipro = 0x4a0081d0,
502         .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
503         .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
504         .cm_coreaon_bandgap_clkctrl = 0x4a008648,
507         /* cm2.core */
508         .cm_l3_1_clkstctrl = 0x4a008700,
509         .cm_l3_1_dynamicdep = 0x4a008708,
510         .cm_l3_1_l3_1_clkctrl = 0x4a008720,
511         .cm_l3_2_clkstctrl = 0x4a008800,
512         .cm_l3_2_dynamicdep = 0x4a008808,
513         .cm_l3_2_l3_2_clkctrl = 0x4a008820,
514         .cm_l3_2_gpmc_clkctrl = 0x4a008828,
515         .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
516         .cm_mpu_m3_clkstctrl = 0x4a008900,
517         .cm_mpu_m3_staticdep = 0x4a008904,
518         .cm_mpu_m3_dynamicdep = 0x4a008908,
519         .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
520         .cm_sdma_clkstctrl = 0x4a008a00,
521         .cm_sdma_staticdep = 0x4a008a04,
522         .cm_sdma_dynamicdep = 0x4a008a08,
523         .cm_sdma_sdma_clkctrl = 0x4a008a20,
524         .cm_memif_clkstctrl = 0x4a008b00,
525         .cm_memif_dmm_clkctrl = 0x4a008b20,
526         .cm_memif_emif_fw_clkctrl = 0x4a008b28,
527         .cm_memif_emif_1_clkctrl = 0x4a008b30,
528         .cm_memif_emif_2_clkctrl = 0x4a008b38,
529         .cm_memif_dll_clkctrl = 0x4a008b40,
530         .cm_memif_emif_h1_clkctrl = 0x4a008b50,
531         .cm_memif_emif_h2_clkctrl = 0x4a008b58,
532         .cm_memif_dll_h_clkctrl = 0x4a008b60,
533         .cm_c2c_clkstctrl = 0x4a008c00,
534         .cm_c2c_staticdep = 0x4a008c04,
535         .cm_c2c_dynamicdep = 0x4a008c08,
536         .cm_c2c_sad2d_clkctrl = 0x4a008c20,
537         .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
538         .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
539         .cm_l4cfg_clkstctrl = 0x4a008d00,
540         .cm_l4cfg_dynamicdep = 0x4a008d08,
541         .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
542         .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
543         .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
544         .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
545         .cm_l3instr_clkstctrl = 0x4a008e00,
546         .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
547         .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
548         .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
549         .cm_l4per_clkstctrl = 0x4a009000,
550         .cm_l4per_dynamicdep = 0x4a009008,
551         .cm_l4per_adc_clkctrl = 0x4a009020,
552         .cm_l4per_gptimer10_clkctrl = 0x4a009028,
553         .cm_l4per_gptimer11_clkctrl = 0x4a009030,
554         .cm_l4per_gptimer2_clkctrl = 0x4a009038,
555         .cm_l4per_gptimer3_clkctrl = 0x4a009040,
556         .cm_l4per_gptimer4_clkctrl = 0x4a009048,
557         .cm_l4per_gptimer9_clkctrl = 0x4a009050,
558         .cm_l4per_elm_clkctrl = 0x4a009058,
559         .cm_l4per_gpio2_clkctrl = 0x4a009060,
560         .cm_l4per_gpio3_clkctrl = 0x4a009068,
561         .cm_l4per_gpio4_clkctrl = 0x4a009070,
562         .cm_l4per_gpio5_clkctrl = 0x4a009078,
563         .cm_l4per_gpio6_clkctrl = 0x4a009080,
564         .cm_l4per_hdq1w_clkctrl = 0x4a009088,
565         .cm_l4per_hecc1_clkctrl = 0x4a009090,
566         .cm_l4per_hecc2_clkctrl = 0x4a009098,
567         .cm_l4per_i2c1_clkctrl = 0x4a0090a0,
568         .cm_l4per_i2c2_clkctrl = 0x4a0090a8,
569         .cm_l4per_i2c3_clkctrl = 0x4a0090b0,
570         .cm_l4per_i2c4_clkctrl = 0x4a0090b8,
571         .cm_l4per_l4per_clkctrl = 0x4a0090c0,
572         .cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
573         .cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
574         .cm_l4per_mgate_clkctrl = 0x4a0090e8,
575         .cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
576         .cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
577         .cm_l4per_mcspi3_clkctrl = 0x4a009100,
578         .cm_l4per_mcspi4_clkctrl = 0x4a009108,
579         .cm_l4per_gpio7_clkctrl = 0x4a009110,
580         .cm_l4per_gpio8_clkctrl = 0x4a009118,
581         .cm_l4per_mmcsd3_clkctrl = 0x4a009120,
582         .cm_l4per_mmcsd4_clkctrl = 0x4a009128,
583         .cm_l4per_msprohg_clkctrl = 0x4a009130,
584         .cm_l4per_slimbus2_clkctrl = 0x4a009138,
585         .cm_l4per_uart1_clkctrl = 0x4a009140,
586         .cm_l4per_uart2_clkctrl = 0x4a009148,
587         .cm_l4per_uart3_clkctrl = 0x4a009150,
588         .cm_l4per_uart4_clkctrl = 0x4a009158,
589         .cm_l4per_mmcsd5_clkctrl = 0x4a009160,
590         .cm_l4per_i2c5_clkctrl = 0x4a009168,
591         .cm_l4per_uart5_clkctrl = 0x4a009170,
592         .cm_l4per_uart6_clkctrl = 0x4a009178,
593         .cm_l4sec_clkstctrl = 0x4a009180,
594         .cm_l4sec_staticdep = 0x4a009184,
595         .cm_l4sec_dynamicdep = 0x4a009188,
596         .cm_l4sec_aes1_clkctrl = 0x4a0091a0,
597         .cm_l4sec_aes2_clkctrl = 0x4a0091a8,
598         .cm_l4sec_des3des_clkctrl = 0x4a0091b0,
599         .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
600         .cm_l4sec_rng_clkctrl = 0x4a0091c0,
601         .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
602         .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
604         /* cm2.ivahd */
605         .cm_ivahd_clkstctrl = 0x4a009200,
606         .cm_ivahd_ivahd_clkctrl = 0x4a009220,
607         .cm_ivahd_sl2_clkctrl = 0x4a009228,
609         /* cm2.cam */
610         .cm_cam_clkstctrl = 0x4a009300,
611         .cm_cam_iss_clkctrl = 0x4a009320,
612         .cm_cam_fdif_clkctrl = 0x4a009328,
614         /* cm2.dss */
615         .cm_dss_clkstctrl = 0x4a009400,
616         .cm_dss_dss_clkctrl = 0x4a009420,
618         /* cm2.sgx */
619         .cm_sgx_clkstctrl = 0x4a009500,
620         .cm_sgx_sgx_clkctrl = 0x4a009520,
622         /* cm2.l3init */
623         .cm_l3init_clkstctrl = 0x4a009600,
625         /* cm2.l3init */
626         .cm_l3init_hsmmc1_clkctrl = 0x4a009628,
627         .cm_l3init_hsmmc2_clkctrl = 0x4a009630,
628         .cm_l3init_hsi_clkctrl = 0x4a009638,
629         .cm_l3init_hsusbhost_clkctrl = 0x4a009658,
630         .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
631         .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
632         .cm_l3init_p1500_clkctrl = 0x4a009678,
633         .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
634         .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
636         /* l4 wkup regs */
637         .cm_abe_pll_ref_clksel = 0x4ae0610c,
638         .cm_sys_clksel = 0x4ae06110,
639         .cm_wkup_clkstctrl = 0x4ae07900,
640         .cm_wkup_l4wkup_clkctrl = 0x4ae07920,
641         .cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
642         .cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
643         .cm_wkup_gpio1_clkctrl = 0x4ae07938,
644         .cm_wkup_gptimer1_clkctrl = 0x4ae07940,
645         .cm_wkup_gptimer12_clkctrl = 0x4ae07948,
646         .cm_wkup_synctimer_clkctrl = 0x4ae07950,
647         .cm_wkup_usim_clkctrl = 0x4ae07958,
648         .cm_wkup_sarram_clkctrl = 0x4ae07960,
649         .cm_wkup_keyboard_clkctrl = 0x4ae07978,
650         .cm_wkup_rtc_clkctrl = 0x4ae07980,
651         .cm_wkup_bandgap_clkctrl = 0x4ae07988,
652         .cm_wkupaon_scrm_clkctrl = 0x4ae07990,
653         .prm_vc_val_bypass = 0x4ae07ca0,
654         .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
655         .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
657         .prm_sldo_core_setup = 0x4ae07cc4,
658         .prm_sldo_core_ctrl = 0x4ae07cc8,
659         .prm_sldo_mpu_setup = 0x4ae07ccc,
660         .prm_sldo_mpu_ctrl = 0x4ae07cd0,
661         .prm_sldo_mm_setup = 0x4ae07cd4,
662         .prm_sldo_mm_ctrl = 0x4ae07cd8,
663 };