arm: dra7xx: clock: Add the dplls data
[glsdk/glsdk-u-boot.git] / arch / arm / cpu / armv7 / omap5 / prcm-regs.c
1 /*
2  *
3  * HW regs data for OMAP5 Soc
4  *
5  * (C) Copyright 2013
6  * Texas Instruments, <www.ti.com>
7  *
8  * Sricharan R <r.sricharan@ti.com>
9  *
10  * See file CREDITS for list of people who contributed to this
11  * project.
12  *
13  * This program is free software; you can redistribute it and/or
14  * modify it under the terms of the GNU General Public License as
15  * published by the Free Software Foundation; either version 2 of
16  * the License, or (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26  * MA 02111-1307 USA
27  */
29 #include <asm/omap_common.h>
31 struct prcm_regs const omap5_es1_prcm = {
32         /* cm1.ckgen */
33         .cm_clksel_core = 0x4a004100,
34         .cm_clksel_abe = 0x4a004108,
35         .cm_dll_ctrl = 0x4a004110,
36         .cm_clkmode_dpll_core = 0x4a004120,
37         .cm_idlest_dpll_core = 0x4a004124,
38         .cm_autoidle_dpll_core = 0x4a004128,
39         .cm_clksel_dpll_core = 0x4a00412c,
40         .cm_div_m2_dpll_core = 0x4a004130,
41         .cm_div_m3_dpll_core = 0x4a004134,
42         .cm_div_h11_dpll_core = 0x4a004138,
43         .cm_div_h12_dpll_core = 0x4a00413c,
44         .cm_div_h13_dpll_core = 0x4a004140,
45         .cm_div_h14_dpll_core = 0x4a004144,
46         .cm_ssc_deltamstep_dpll_core = 0x4a004148,
47         .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
48         .cm_emu_override_dpll_core = 0x4a004150,
49         .cm_div_h22_dpllcore = 0x4a004154,
50         .cm_div_h23_dpll_core = 0x4a004158,
51         .cm_clkmode_dpll_mpu = 0x4a004160,
52         .cm_idlest_dpll_mpu = 0x4a004164,
53         .cm_autoidle_dpll_mpu = 0x4a004168,
54         .cm_clksel_dpll_mpu = 0x4a00416c,
55         .cm_div_m2_dpll_mpu = 0x4a004170,
56         .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
57         .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
58         .cm_bypclk_dpll_mpu = 0x4a00419c,
59         .cm_clkmode_dpll_iva = 0x4a0041a0,
60         .cm_idlest_dpll_iva = 0x4a0041a4,
61         .cm_autoidle_dpll_iva = 0x4a0041a8,
62         .cm_clksel_dpll_iva = 0x4a0041ac,
63         .cm_div_h11_dpll_iva = 0x4a0041b8,
64         .cm_div_h12_dpll_iva = 0x4a0041bc,
65         .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
66         .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
67         .cm_bypclk_dpll_iva = 0x4a0041dc,
68         .cm_clkmode_dpll_abe = 0x4a0041e0,
69         .cm_idlest_dpll_abe = 0x4a0041e4,
70         .cm_autoidle_dpll_abe = 0x4a0041e8,
71         .cm_clksel_dpll_abe = 0x4a0041ec,
72         .cm_div_m2_dpll_abe = 0x4a0041f0,
73         .cm_div_m3_dpll_abe = 0x4a0041f4,
74         .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
75         .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
76         .cm_clkmode_dpll_ddrphy = 0x4a004220,
77         .cm_idlest_dpll_ddrphy = 0x4a004224,
78         .cm_autoidle_dpll_ddrphy = 0x4a004228,
79         .cm_clksel_dpll_ddrphy = 0x4a00422c,
80         .cm_div_m2_dpll_ddrphy = 0x4a004230,
81         .cm_div_h11_dpll_ddrphy = 0x4a004238,
82         .cm_div_h12_dpll_ddrphy = 0x4a00423c,
83         .cm_div_h13_dpll_ddrphy = 0x4a004240,
84         .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
85         .cm_shadow_freq_config1 = 0x4a004260,
86         .cm_mpu_mpu_clkctrl = 0x4a004320,
88         /* cm1.dsp */
89         .cm_dsp_clkstctrl = 0x4a004400,
90         .cm_dsp_dsp_clkctrl = 0x4a004420,
92         /* cm1.abe */
93         .cm1_abe_clkstctrl = 0x4a004500,
94         .cm1_abe_l4abe_clkctrl = 0x4a004520,
95         .cm1_abe_aess_clkctrl = 0x4a004528,
96         .cm1_abe_pdm_clkctrl = 0x4a004530,
97         .cm1_abe_dmic_clkctrl = 0x4a004538,
98         .cm1_abe_mcasp_clkctrl = 0x4a004540,
99         .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
100         .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
101         .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
102         .cm1_abe_slimbus_clkctrl = 0x4a004560,
103         .cm1_abe_timer5_clkctrl = 0x4a004568,
104         .cm1_abe_timer6_clkctrl = 0x4a004570,
105         .cm1_abe_timer7_clkctrl = 0x4a004578,
106         .cm1_abe_timer8_clkctrl = 0x4a004580,
107         .cm1_abe_wdt3_clkctrl = 0x4a004588,
109         /* cm2.ckgen */
110         .cm_clksel_mpu_m3_iss_root = 0x4a008100,
111         .cm_clksel_usb_60mhz = 0x4a008104,
112         .cm_scale_fclk = 0x4a008108,
113         .cm_core_dvfs_perf1 = 0x4a008110,
114         .cm_core_dvfs_perf2 = 0x4a008114,
115         .cm_core_dvfs_perf3 = 0x4a008118,
116         .cm_core_dvfs_perf4 = 0x4a00811c,
117         .cm_core_dvfs_current = 0x4a008124,
118         .cm_iva_dvfs_perf_tesla = 0x4a008128,
119         .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
120         .cm_iva_dvfs_perf_abe = 0x4a008130,
121         .cm_iva_dvfs_current = 0x4a008138,
122         .cm_clkmode_dpll_per = 0x4a008140,
123         .cm_idlest_dpll_per = 0x4a008144,
124         .cm_autoidle_dpll_per = 0x4a008148,
125         .cm_clksel_dpll_per = 0x4a00814c,
126         .cm_div_m2_dpll_per = 0x4a008150,
127         .cm_div_m3_dpll_per = 0x4a008154,
128         .cm_div_h11_dpll_per = 0x4a008158,
129         .cm_div_h12_dpll_per = 0x4a00815c,
130         .cm_div_h14_dpll_per = 0x4a008164,
131         .cm_ssc_deltamstep_dpll_per = 0x4a008168,
132         .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
133         .cm_emu_override_dpll_per = 0x4a008170,
134         .cm_clkmode_dpll_usb = 0x4a008180,
135         .cm_idlest_dpll_usb = 0x4a008184,
136         .cm_autoidle_dpll_usb = 0x4a008188,
137         .cm_clksel_dpll_usb = 0x4a00818c,
138         .cm_div_m2_dpll_usb = 0x4a008190,
139         .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
140         .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
141         .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
142         .cm_clkmode_dpll_unipro = 0x4a0081c0,
143         .cm_idlest_dpll_unipro = 0x4a0081c4,
144         .cm_autoidle_dpll_unipro = 0x4a0081c8,
145         .cm_clksel_dpll_unipro = 0x4a0081cc,
146         .cm_div_m2_dpll_unipro = 0x4a0081d0,
147         .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
148         .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
150         /* cm2.core */
151         .cm_coreaon_bandgap_clkctrl = 0x4a008648,
152         .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
153         .cm_l3_1_clkstctrl = 0x4a008700,
154         .cm_l3_1_dynamicdep = 0x4a008708,
155         .cm_l3_1_l3_1_clkctrl = 0x4a008720,
156         .cm_l3_2_clkstctrl = 0x4a008800,
157         .cm_l3_2_dynamicdep = 0x4a008808,
158         .cm_l3_2_l3_2_clkctrl = 0x4a008820,
159         .cm_l3_gpmc_clkctrl = 0x4a008828,
160         .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
161         .cm_mpu_m3_clkstctrl = 0x4a008900,
162         .cm_mpu_m3_staticdep = 0x4a008904,
163         .cm_mpu_m3_dynamicdep = 0x4a008908,
164         .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
165         .cm_sdma_clkstctrl = 0x4a008a00,
166         .cm_sdma_staticdep = 0x4a008a04,
167         .cm_sdma_dynamicdep = 0x4a008a08,
168         .cm_sdma_sdma_clkctrl = 0x4a008a20,
169         .cm_memif_clkstctrl = 0x4a008b00,
170         .cm_memif_dmm_clkctrl = 0x4a008b20,
171         .cm_memif_emif_fw_clkctrl = 0x4a008b28,
172         .cm_memif_emif_1_clkctrl = 0x4a008b30,
173         .cm_memif_emif_2_clkctrl = 0x4a008b38,
174         .cm_memif_dll_clkctrl = 0x4a008b40,
175         .cm_memif_emif_h1_clkctrl = 0x4a008b50,
176         .cm_memif_emif_h2_clkctrl = 0x4a008b58,
177         .cm_memif_dll_h_clkctrl = 0x4a008b60,
178         .cm_c2c_clkstctrl = 0x4a008c00,
179         .cm_c2c_staticdep = 0x4a008c04,
180         .cm_c2c_dynamicdep = 0x4a008c08,
181         .cm_c2c_sad2d_clkctrl = 0x4a008c20,
182         .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
183         .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
184         .cm_l4cfg_clkstctrl = 0x4a008d00,
185         .cm_l4cfg_dynamicdep = 0x4a008d08,
186         .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
187         .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
188         .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
189         .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
190         .cm_l3instr_clkstctrl = 0x4a008e00,
191         .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
192         .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
193         .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
195         /* cm2.ivahd */
196         .cm_ivahd_clkstctrl = 0x4a008f00,
197         .cm_ivahd_ivahd_clkctrl = 0x4a008f20,
198         .cm_ivahd_sl2_clkctrl = 0x4a008f28,
200         /* cm2.cam */
201         .cm_cam_clkstctrl = 0x4a009000,
202         .cm_cam_iss_clkctrl = 0x4a009020,
203         .cm_cam_fdif_clkctrl = 0x4a009028,
205         /* cm2.dss */
206         .cm_dss_clkstctrl = 0x4a009100,
207         .cm_dss_dss_clkctrl = 0x4a009120,
209         /* cm2.sgx */
210         .cm_sgx_clkstctrl = 0x4a009200,
211         .cm_sgx_sgx_clkctrl = 0x4a009220,
213         /* cm2.l3init */
214         .cm_l3init_clkstctrl = 0x4a009300,
215         .cm_l3init_hsmmc1_clkctrl = 0x4a009328,
216         .cm_l3init_hsmmc2_clkctrl = 0x4a009330,
217         .cm_l3init_hsi_clkctrl = 0x4a009338,
218         .cm_l3init_hsusbhost_clkctrl = 0x4a009358,
219         .cm_l3init_hsusbotg_clkctrl = 0x4a009360,
220         .cm_l3init_hsusbtll_clkctrl = 0x4a009368,
221         .cm_l3init_p1500_clkctrl = 0x4a009378,
222         .cm_l3init_fsusb_clkctrl = 0x4a0093d0,
223         .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
225         /* cm2.l4per */
226         .cm_l4per_clkstctrl = 0x4a009400,
227         .cm_l4per_dynamicdep = 0x4a009408,
228         .cm_l4per_adc_clkctrl = 0x4a009420,
229         .cm_l4per_gptimer10_clkctrl = 0x4a009428,
230         .cm_l4per_gptimer11_clkctrl = 0x4a009430,
231         .cm_l4per_gptimer2_clkctrl = 0x4a009438,
232         .cm_l4per_gptimer3_clkctrl = 0x4a009440,
233         .cm_l4per_gptimer4_clkctrl = 0x4a009448,
234         .cm_l4per_gptimer9_clkctrl = 0x4a009450,
235         .cm_l4per_elm_clkctrl = 0x4a009458,
236         .cm_l4per_gpio2_clkctrl = 0x4a009460,
237         .cm_l4per_gpio3_clkctrl = 0x4a009468,
238         .cm_l4per_gpio4_clkctrl = 0x4a009470,
239         .cm_l4per_gpio5_clkctrl = 0x4a009478,
240         .cm_l4per_gpio6_clkctrl = 0x4a009480,
241         .cm_l4per_hdq1w_clkctrl = 0x4a009488,
242         .cm_l4per_hecc1_clkctrl = 0x4a009490,
243         .cm_l4per_hecc2_clkctrl = 0x4a009498,
244         .cm_l4per_i2c1_clkctrl = 0x4a0094a0,
245         .cm_l4per_i2c2_clkctrl = 0x4a0094a8,
246         .cm_l4per_i2c3_clkctrl = 0x4a0094b0,
247         .cm_l4per_i2c4_clkctrl = 0x4a0094b8,
248         .cm_l4per_l4per_clkctrl = 0x4a0094c0,
249         .cm_l4per_mcasp2_clkctrl = 0x4a0094d0,
250         .cm_l4per_mcasp3_clkctrl = 0x4a0094d8,
251         .cm_l4per_mgate_clkctrl = 0x4a0094e8,
252         .cm_l4per_mcspi1_clkctrl = 0x4a0094f0,
253         .cm_l4per_mcspi2_clkctrl = 0x4a0094f8,
254         .cm_l4per_mcspi3_clkctrl = 0x4a009500,
255         .cm_l4per_mcspi4_clkctrl = 0x4a009508,
256         .cm_l4per_gpio7_clkctrl = 0x4a009510,
257         .cm_l4per_gpio8_clkctrl = 0x4a009518,
258         .cm_l4per_mmcsd3_clkctrl = 0x4a009520,
259         .cm_l4per_mmcsd4_clkctrl = 0x4a009528,
260         .cm_l4per_msprohg_clkctrl = 0x4a009530,
261         .cm_l4per_slimbus2_clkctrl = 0x4a009538,
262         .cm_l4per_uart1_clkctrl = 0x4a009540,
263         .cm_l4per_uart2_clkctrl = 0x4a009548,
264         .cm_l4per_uart3_clkctrl = 0x4a009550,
265         .cm_l4per_uart4_clkctrl = 0x4a009558,
266         .cm_l4per_mmcsd5_clkctrl = 0x4a009560,
267         .cm_l4per_i2c5_clkctrl = 0x4a009568,
268         .cm_l4per_uart5_clkctrl = 0x4a009570,
269         .cm_l4per_uart6_clkctrl = 0x4a009578,
270         .cm_l4sec_clkstctrl = 0x4a009580,
271         .cm_l4sec_staticdep = 0x4a009584,
272         .cm_l4sec_dynamicdep = 0x4a009588,
273         .cm_l4sec_aes1_clkctrl = 0x4a0095a0,
274         .cm_l4sec_aes2_clkctrl = 0x4a0095a8,
275         .cm_l4sec_des3des_clkctrl = 0x4a0095b0,
276         .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8,
277         .cm_l4sec_rng_clkctrl = 0x4a0095c0,
278         .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8,
279         .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8,
281         /* l4 wkup regs */
282         .cm_abe_pll_ref_clksel = 0x4ae0610c,
283         .cm_sys_clksel = 0x4ae06110,
284         .cm_wkup_clkstctrl = 0x4ae07800,
285         .cm_wkup_l4wkup_clkctrl = 0x4ae07820,
286         .cm_wkup_wdtimer1_clkctrl = 0x4ae07828,
287         .cm_wkup_wdtimer2_clkctrl = 0x4ae07830,
288         .cm_wkup_gpio1_clkctrl = 0x4ae07838,
289         .cm_wkup_gptimer1_clkctrl = 0x4ae07840,
290         .cm_wkup_gptimer12_clkctrl = 0x4ae07848,
291         .cm_wkup_synctimer_clkctrl = 0x4ae07850,
292         .cm_wkup_usim_clkctrl = 0x4ae07858,
293         .cm_wkup_sarram_clkctrl = 0x4ae07860,
294         .cm_wkup_keyboard_clkctrl = 0x4ae07878,
295         .cm_wkup_rtc_clkctrl = 0x4ae07880,
296         .cm_wkup_bandgap_clkctrl = 0x4ae07888,
297         .cm_wkupaon_scrm_clkctrl = 0x4ae07890,
298         .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898,
299         .prm_rstctrl = 0x4ae07b00,
300         .prm_rstst = 0x4ae07b04,
301         .prm_vc_val_bypass = 0x4ae07ba0,
302         .prm_vc_cfg_i2c_mode = 0x4ae07bb4,
303         .prm_vc_cfg_i2c_clk = 0x4ae07bb8,
304         .prm_sldo_core_setup = 0x4ae07bc4,
305         .prm_sldo_core_ctrl = 0x4ae07bc8,
306         .prm_sldo_mpu_setup = 0x4ae07bcc,
307         .prm_sldo_mpu_ctrl = 0x4ae07bd0,
308         .prm_sldo_mm_setup = 0x4ae07bd4,
309         .prm_sldo_mm_ctrl = 0x4ae07bd8,
310 };
312 struct omap_sys_ctrl_regs const omap5_ctrl = {
313         .control_status                         = 0x4A002134,
314         .control_paconf_global                  = 0x4A002DA0,
315         .control_paconf_mode                    = 0x4A002DA4,
316         .control_smart1io_padconf_0             = 0x4A002DA8,
317         .control_smart1io_padconf_1             = 0x4A002DAC,
318         .control_smart1io_padconf_2             = 0x4A002DB0,
319         .control_smart2io_padconf_0             = 0x4A002DB4,
320         .control_smart2io_padconf_1             = 0x4A002DB8,
321         .control_smart2io_padconf_2             = 0x4A002DBC,
322         .control_smart3io_padconf_0             = 0x4A002DC0,
323         .control_smart3io_padconf_1             = 0x4A002DC4,
324         .control_pbias                          = 0x4A002E00,
325         .control_i2c_0                          = 0x4A002E04,
326         .control_camera_rx                      = 0x4A002E08,
327         .control_hdmi_tx_phy                    = 0x4A002E0C,
328         .control_uniportm                       = 0x4A002E10,
329         .control_dsiphy                         = 0x4A002E14,
330         .control_mcbsplp                        = 0x4A002E18,
331         .control_usb2phycore                    = 0x4A002E1C,
332         .control_hdmi_1                         = 0x4A002E20,
333         .control_hsi                            = 0x4A002E24,
334         .control_ddr3ch1_0                      = 0x4A002E30,
335         .control_ddr3ch2_0                      = 0x4A002E34,
336         .control_ddrch1_0                       = 0x4A002E38,
337         .control_ddrch1_1                       = 0x4A002E3C,
338         .control_ddrch2_0                       = 0x4A002E40,
339         .control_ddrch2_1                       = 0x4A002E44,
340         .control_lpddr2ch1_0                    = 0x4A002E48,
341         .control_lpddr2ch1_1                    = 0x4A002E4C,
342         .control_ddrio_0                        = 0x4A002E50,
343         .control_ddrio_1                        = 0x4A002E54,
344         .control_ddrio_2                        = 0x4A002E58,
345         .control_hyst_1                         = 0x4A002E5C,
346         .control_usbb_hsic_control              = 0x4A002E60,
347         .control_c2c                            = 0x4A002E64,
348         .control_core_control_spare_rw          = 0x4A002E68,
349         .control_core_control_spare_r           = 0x4A002E6C,
350         .control_core_control_spare_r_c0        = 0x4A002E70,
351         .control_srcomp_north_side              = 0x4A002E74,
352         .control_srcomp_south_side              = 0x4A002E78,
353         .control_srcomp_east_side               = 0x4A002E7C,
354         .control_srcomp_west_side               = 0x4A002E80,
355         .control_srcomp_code_latch              = 0x4A002E84,
356         .control_port_emif1_sdram_config        = 0x4AE0C110,
357         .control_port_emif1_lpddr2_nvm_config   = 0x4AE0C114,
358         .control_port_emif2_sdram_config        = 0x4AE0C118,
359         .control_emif1_sdram_config_ext         = 0x4AE0C144,
360         .control_emif2_sdram_config_ext         = 0x4AE0C148,
361         .control_smart1nopmio_padconf_0         = 0x4AE0CDA0,
362         .control_smart1nopmio_padconf_1         = 0x4AE0CDA4,
363         .control_padconf_mode                   = 0x4AE0CDA8,
364         .control_xtal_oscillator                = 0x4AE0CDAC,
365         .control_i2c_2                          = 0x4AE0CDB0,
366         .control_ckobuffer                      = 0x4AE0CDB4,
367         .control_wkup_control_spare_rw          = 0x4AE0CDB8,
368         .control_wkup_control_spare_r           = 0x4AE0CDBC,
369         .control_wkup_control_spare_r_c0        = 0x4AE0CDC0,
370         .control_srcomp_east_side_wkup          = 0x4AE0CDC4,
371         .control_efuse_1                        = 0x4AE0CDC8,
372         .control_efuse_2                        = 0x4AE0CDCC,
373         .control_efuse_3                        = 0x4AE0CDD0,
374         .control_efuse_4                        = 0x4AE0CDD4,
375         .control_efuse_5                        = 0x4AE0CDD8,
376         .control_efuse_6                        = 0x4AE0CDDC,
377         .control_efuse_7                        = 0x4AE0CDE0,
378         .control_efuse_8                        = 0x4AE0CDE4,
379         .control_efuse_9                        = 0x4AE0CDE8,
380         .control_efuse_10                       = 0x4AE0CDEC,
381         .control_efuse_11                       = 0x4AE0CDF0,
382         .control_efuse_12                       = 0x4AE0CDF4,
383         .control_efuse_13                       = 0x4AE0CDF8,
384 };
386 struct prcm_regs const omap5_es2_prcm = {
387         /* cm1.ckgen */
388         .cm_clksel_core = 0x4a004100,
389         .cm_clksel_abe = 0x4a004108,
390         .cm_dll_ctrl = 0x4a004110,
391         .cm_clkmode_dpll_core = 0x4a004120,
392         .cm_idlest_dpll_core = 0x4a004124,
393         .cm_autoidle_dpll_core = 0x4a004128,
394         .cm_clksel_dpll_core = 0x4a00412c,
395         .cm_div_m2_dpll_core = 0x4a004130,
396         .cm_div_m3_dpll_core = 0x4a004134,
397         .cm_div_h11_dpll_core = 0x4a004138,
398         .cm_div_h12_dpll_core = 0x4a00413c,
399         .cm_div_h13_dpll_core = 0x4a004140,
400         .cm_div_h14_dpll_core = 0x4a004144,
401         .cm_ssc_deltamstep_dpll_core = 0x4a004148,
402         .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c,
403         .cm_div_h21_dpll_core = 0x4a004150,
404         .cm_div_h22_dpllcore = 0x4a004154,
405         .cm_div_h23_dpll_core = 0x4a004158,
406         .cm_div_h24_dpll_core = 0x4a00415c,
407         .cm_clkmode_dpll_mpu = 0x4a004160,
408         .cm_idlest_dpll_mpu = 0x4a004164,
409         .cm_autoidle_dpll_mpu = 0x4a004168,
410         .cm_clksel_dpll_mpu = 0x4a00416c,
411         .cm_div_m2_dpll_mpu = 0x4a004170,
412         .cm_ssc_deltamstep_dpll_mpu = 0x4a004188,
413         .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c,
414         .cm_bypclk_dpll_mpu = 0x4a00419c,
415         .cm_clkmode_dpll_iva = 0x4a0041a0,
416         .cm_idlest_dpll_iva = 0x4a0041a4,
417         .cm_autoidle_dpll_iva = 0x4a0041a8,
418         .cm_clksel_dpll_iva = 0x4a0041ac,
419         .cm_div_h11_dpll_iva = 0x4a0041b8,
420         .cm_div_h12_dpll_iva = 0x4a0041bc,
421         .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8,
422         .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc,
423         .cm_bypclk_dpll_iva = 0x4a0041dc,
424         .cm_clkmode_dpll_abe = 0x4a0041e0,
425         .cm_idlest_dpll_abe = 0x4a0041e4,
426         .cm_autoidle_dpll_abe = 0x4a0041e8,
427         .cm_clksel_dpll_abe = 0x4a0041ec,
428         .cm_div_m2_dpll_abe = 0x4a0041f0,
429         .cm_div_m3_dpll_abe = 0x4a0041f4,
430         .cm_ssc_deltamstep_dpll_abe = 0x4a004208,
431         .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c,
432         .cm_clkmode_dpll_ddrphy = 0x4a004220,
433         .cm_idlest_dpll_ddrphy = 0x4a004224,
434         .cm_autoidle_dpll_ddrphy = 0x4a004228,
435         .cm_clksel_dpll_ddrphy = 0x4a00422c,
436         .cm_div_m2_dpll_ddrphy = 0x4a004230,
437         .cm_div_h11_dpll_ddrphy = 0x4a004238,
438         .cm_div_h12_dpll_ddrphy = 0x4a00423c,
439         .cm_div_h13_dpll_ddrphy = 0x4a004240,
440         .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248,
441         .cm_shadow_freq_config1 = 0x4a004260,
442         .cm_mpu_mpu_clkctrl = 0x4a004320,
444         /* cm1.dsp */
445         .cm_dsp_clkstctrl = 0x4a004400,
446         .cm_dsp_dsp_clkctrl = 0x4a004420,
448         /* cm1.abe */
449         .cm1_abe_clkstctrl = 0x4a004500,
450         .cm1_abe_l4abe_clkctrl = 0x4a004520,
451         .cm1_abe_aess_clkctrl = 0x4a004528,
452         .cm1_abe_pdm_clkctrl = 0x4a004530,
453         .cm1_abe_dmic_clkctrl = 0x4a004538,
454         .cm1_abe_mcasp_clkctrl = 0x4a004540,
455         .cm1_abe_mcbsp1_clkctrl = 0x4a004548,
456         .cm1_abe_mcbsp2_clkctrl = 0x4a004550,
457         .cm1_abe_mcbsp3_clkctrl = 0x4a004558,
458         .cm1_abe_slimbus_clkctrl = 0x4a004560,
459         .cm1_abe_timer5_clkctrl = 0x4a004568,
460         .cm1_abe_timer6_clkctrl = 0x4a004570,
461         .cm1_abe_timer7_clkctrl = 0x4a004578,
462         .cm1_abe_timer8_clkctrl = 0x4a004580,
463         .cm1_abe_wdt3_clkctrl = 0x4a004588,
467         /* cm2.ckgen */
468         .cm_clksel_mpu_m3_iss_root = 0x4a008100,
469         .cm_clksel_usb_60mhz = 0x4a008104,
470         .cm_scale_fclk = 0x4a008108,
471         .cm_core_dvfs_perf1 = 0x4a008110,
472         .cm_core_dvfs_perf2 = 0x4a008114,
473         .cm_core_dvfs_perf3 = 0x4a008118,
474         .cm_core_dvfs_perf4 = 0x4a00811c,
475         .cm_core_dvfs_current = 0x4a008124,
476         .cm_iva_dvfs_perf_tesla = 0x4a008128,
477         .cm_iva_dvfs_perf_ivahd = 0x4a00812c,
478         .cm_iva_dvfs_perf_abe = 0x4a008130,
479         .cm_iva_dvfs_current = 0x4a008138,
480         .cm_clkmode_dpll_per = 0x4a008140,
481         .cm_idlest_dpll_per = 0x4a008144,
482         .cm_autoidle_dpll_per = 0x4a008148,
483         .cm_clksel_dpll_per = 0x4a00814c,
484         .cm_div_m2_dpll_per = 0x4a008150,
485         .cm_div_m3_dpll_per = 0x4a008154,
486         .cm_div_h11_dpll_per = 0x4a008158,
487         .cm_div_h12_dpll_per = 0x4a00815c,
488         .cm_div_h13_dpll_per = 0x4a008160,
489         .cm_div_h14_dpll_per = 0x4a008164,
490         .cm_ssc_deltamstep_dpll_per = 0x4a008168,
491         .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c,
492         .cm_emu_override_dpll_per = 0x4a008170,
493         .cm_clkmode_dpll_usb = 0x4a008180,
494         .cm_idlest_dpll_usb = 0x4a008184,
495         .cm_autoidle_dpll_usb = 0x4a008188,
496         .cm_clksel_dpll_usb = 0x4a00818c,
497         .cm_div_m2_dpll_usb = 0x4a008190,
498         .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8,
499         .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac,
500         .cm_clkdcoldo_dpll_usb = 0x4a0081b4,
501         .cm_clkmode_dpll_unipro = 0x4a0081c0,
502         .cm_idlest_dpll_unipro = 0x4a0081c4,
503         .cm_autoidle_dpll_unipro = 0x4a0081c8,
504         .cm_clksel_dpll_unipro = 0x4a0081cc,
505         .cm_div_m2_dpll_unipro = 0x4a0081d0,
506         .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8,
507         .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec,
508         .cm_coreaon_bandgap_clkctrl = 0x4a008648,
509         .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,
511         /* cm2.core */
512         .cm_l3_1_clkstctrl = 0x4a008700,
513         .cm_l3_1_dynamicdep = 0x4a008708,
514         .cm_l3_1_l3_1_clkctrl = 0x4a008720,
515         .cm_l3_2_clkstctrl = 0x4a008800,
516         .cm_l3_2_dynamicdep = 0x4a008808,
517         .cm_l3_2_l3_2_clkctrl = 0x4a008820,
518         .cm_l3_gpmc_clkctrl = 0x4a008828,
519         .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830,
520         .cm_mpu_m3_clkstctrl = 0x4a008900,
521         .cm_mpu_m3_staticdep = 0x4a008904,
522         .cm_mpu_m3_dynamicdep = 0x4a008908,
523         .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920,
524         .cm_sdma_clkstctrl = 0x4a008a00,
525         .cm_sdma_staticdep = 0x4a008a04,
526         .cm_sdma_dynamicdep = 0x4a008a08,
527         .cm_sdma_sdma_clkctrl = 0x4a008a20,
528         .cm_memif_clkstctrl = 0x4a008b00,
529         .cm_memif_dmm_clkctrl = 0x4a008b20,
530         .cm_memif_emif_fw_clkctrl = 0x4a008b28,
531         .cm_memif_emif_1_clkctrl = 0x4a008b30,
532         .cm_memif_emif_2_clkctrl = 0x4a008b38,
533         .cm_memif_dll_clkctrl = 0x4a008b40,
534         .cm_memif_emif_h1_clkctrl = 0x4a008b50,
535         .cm_memif_emif_h2_clkctrl = 0x4a008b58,
536         .cm_memif_dll_h_clkctrl = 0x4a008b60,
537         .cm_c2c_clkstctrl = 0x4a008c00,
538         .cm_c2c_staticdep = 0x4a008c04,
539         .cm_c2c_dynamicdep = 0x4a008c08,
540         .cm_c2c_sad2d_clkctrl = 0x4a008c20,
541         .cm_c2c_modem_icr_clkctrl = 0x4a008c28,
542         .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30,
543         .cm_l4cfg_clkstctrl = 0x4a008d00,
544         .cm_l4cfg_dynamicdep = 0x4a008d08,
545         .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20,
546         .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28,
547         .cm_l4cfg_mailbox_clkctrl = 0x4a008d30,
548         .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38,
549         .cm_l3instr_clkstctrl = 0x4a008e00,
550         .cm_l3instr_l3_3_clkctrl = 0x4a008e20,
551         .cm_l3instr_l3_instr_clkctrl = 0x4a008e28,
552         .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40,
553         .cm_l4per_clkstctrl = 0x4a009000,
554         .cm_l4per_dynamicdep = 0x4a009008,
555         .cm_l4per_adc_clkctrl = 0x4a009020,
556         .cm_l4per_gptimer10_clkctrl = 0x4a009028,
557         .cm_l4per_gptimer11_clkctrl = 0x4a009030,
558         .cm_l4per_gptimer2_clkctrl = 0x4a009038,
559         .cm_l4per_gptimer3_clkctrl = 0x4a009040,
560         .cm_l4per_gptimer4_clkctrl = 0x4a009048,
561         .cm_l4per_gptimer9_clkctrl = 0x4a009050,
562         .cm_l4per_elm_clkctrl = 0x4a009058,
563         .cm_l4per_gpio2_clkctrl = 0x4a009060,
564         .cm_l4per_gpio3_clkctrl = 0x4a009068,
565         .cm_l4per_gpio4_clkctrl = 0x4a009070,
566         .cm_l4per_gpio5_clkctrl = 0x4a009078,
567         .cm_l4per_gpio6_clkctrl = 0x4a009080,
568         .cm_l4per_hdq1w_clkctrl = 0x4a009088,
569         .cm_l4per_hecc1_clkctrl = 0x4a009090,
570         .cm_l4per_hecc2_clkctrl = 0x4a009098,
571         .cm_l4per_i2c1_clkctrl = 0x4a0090a0,
572         .cm_l4per_i2c2_clkctrl = 0x4a0090a8,
573         .cm_l4per_i2c3_clkctrl = 0x4a0090b0,
574         .cm_l4per_i2c4_clkctrl = 0x4a0090b8,
575         .cm_l4per_l4per_clkctrl = 0x4a0090c0,
576         .cm_l4per_mcasp2_clkctrl = 0x4a0090d0,
577         .cm_l4per_mcasp3_clkctrl = 0x4a0090d8,
578         .cm_l4per_mgate_clkctrl = 0x4a0090e8,
579         .cm_l4per_mcspi1_clkctrl = 0x4a0090f0,
580         .cm_l4per_mcspi2_clkctrl = 0x4a0090f8,
581         .cm_l4per_mcspi3_clkctrl = 0x4a009100,
582         .cm_l4per_mcspi4_clkctrl = 0x4a009108,
583         .cm_l4per_gpio7_clkctrl = 0x4a009110,
584         .cm_l4per_gpio8_clkctrl = 0x4a009118,
585         .cm_l4per_mmcsd3_clkctrl = 0x4a009120,
586         .cm_l4per_mmcsd4_clkctrl = 0x4a009128,
587         .cm_l4per_msprohg_clkctrl = 0x4a009130,
588         .cm_l4per_slimbus2_clkctrl = 0x4a009138,
589         .cm_l4per_uart1_clkctrl = 0x4a009140,
590         .cm_l4per_uart2_clkctrl = 0x4a009148,
591         .cm_l4per_uart3_clkctrl = 0x4a009150,
592         .cm_l4per_uart4_clkctrl = 0x4a009158,
593         .cm_l4per_mmcsd5_clkctrl = 0x4a009160,
594         .cm_l4per_i2c5_clkctrl = 0x4a009168,
595         .cm_l4per_uart5_clkctrl = 0x4a009170,
596         .cm_l4per_uart6_clkctrl = 0x4a009178,
597         .cm_l4sec_clkstctrl = 0x4a009180,
598         .cm_l4sec_staticdep = 0x4a009184,
599         .cm_l4sec_dynamicdep = 0x4a009188,
600         .cm_l4sec_aes1_clkctrl = 0x4a0091a0,
601         .cm_l4sec_aes2_clkctrl = 0x4a0091a8,
602         .cm_l4sec_des3des_clkctrl = 0x4a0091b0,
603         .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8,
604         .cm_l4sec_rng_clkctrl = 0x4a0091c0,
605         .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8,
606         .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8,
608         /* cm2.ivahd */
609         .cm_ivahd_clkstctrl = 0x4a009200,
610         .cm_ivahd_ivahd_clkctrl = 0x4a009220,
611         .cm_ivahd_sl2_clkctrl = 0x4a009228,
613         /* cm2.cam */
614         .cm_cam_clkstctrl = 0x4a009300,
615         .cm_cam_iss_clkctrl = 0x4a009320,
616         .cm_cam_fdif_clkctrl = 0x4a009328,
618         /* cm2.dss */
619         .cm_dss_clkstctrl = 0x4a009400,
620         .cm_dss_dss_clkctrl = 0x4a009420,
622         /* cm2.sgx */
623         .cm_sgx_clkstctrl = 0x4a009500,
624         .cm_sgx_sgx_clkctrl = 0x4a009520,
626         /* cm2.l3init */
627         .cm_l3init_clkstctrl = 0x4a009600,
629         /* cm2.l3init */
630         .cm_l3init_hsmmc1_clkctrl = 0x4a009628,
631         .cm_l3init_hsmmc2_clkctrl = 0x4a009630,
632         .cm_l3init_hsi_clkctrl = 0x4a009638,
633         .cm_l3init_hsusbhost_clkctrl = 0x4a009658,
634         .cm_l3init_hsusbotg_clkctrl = 0x4a009660,
635         .cm_l3init_hsusbtll_clkctrl = 0x4a009668,
636         .cm_l3init_p1500_clkctrl = 0x4a009678,
637         .cm_l3init_fsusb_clkctrl = 0x4a0096d0,
638         .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
640         /* l4 wkup regs */
641         .cm_abe_pll_ref_clksel = 0x4ae0610c,
642         .cm_sys_clksel = 0x4ae06110,
643         .cm_wkup_clkstctrl = 0x4ae07900,
644         .cm_wkup_l4wkup_clkctrl = 0x4ae07920,
645         .cm_wkup_wdtimer1_clkctrl = 0x4ae07928,
646         .cm_wkup_wdtimer2_clkctrl = 0x4ae07930,
647         .cm_wkup_gpio1_clkctrl = 0x4ae07938,
648         .cm_wkup_gptimer1_clkctrl = 0x4ae07940,
649         .cm_wkup_gptimer12_clkctrl = 0x4ae07948,
650         .cm_wkup_synctimer_clkctrl = 0x4ae07950,
651         .cm_wkup_usim_clkctrl = 0x4ae07958,
652         .cm_wkup_sarram_clkctrl = 0x4ae07960,
653         .cm_wkup_keyboard_clkctrl = 0x4ae07978,
654         .cm_wkup_rtc_clkctrl = 0x4ae07980,
655         .cm_wkup_bandgap_clkctrl = 0x4ae07988,
656         .cm_wkupaon_scrm_clkctrl = 0x4ae07990,
657         .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998,
658         .prm_rstctrl = 0x4ae07c00,
659         .prm_rstst = 0x4ae07c04,
660         .prm_vc_val_bypass = 0x4ae07ca0,
661         .prm_vc_cfg_i2c_mode = 0x4ae07cb4,
662         .prm_vc_cfg_i2c_clk = 0x4ae07cb8,
664         .prm_sldo_core_setup = 0x4ae07cc4,
665         .prm_sldo_core_ctrl = 0x4ae07cc8,
666         .prm_sldo_mpu_setup = 0x4ae07ccc,
667         .prm_sldo_mpu_ctrl = 0x4ae07cd0,
668         .prm_sldo_mm_setup = 0x4ae07cd4,
669         .prm_sldo_mm_ctrl = 0x4ae07cd8,
670 };
672 struct prcm_regs const dra7xx_prcm = {
673         /* cm1.ckgen */
674         .cm_clksel_core                         = 0x4a005100,
675         .cm_clksel_abe                          = 0x4a005108,
676         .cm_dll_ctrl                            = 0x4a005110,
677         .cm_clkmode_dpll_core                   = 0x4a005120,
678         .cm_idlest_dpll_core                    = 0x4a005124,
679         .cm_autoidle_dpll_core                  = 0x4a005128,
680         .cm_clksel_dpll_core                    = 0x4a00512c,
681         .cm_div_m2_dpll_core                    = 0x4a005130,
682         .cm_div_m3_dpll_core                    = 0x4a005134,
683         .cm_div_h11_dpll_core                   = 0x4a005138,
684         .cm_div_h12_dpll_core                   = 0x4a00513c,
685         .cm_div_h13_dpll_core                   = 0x4a005140,
686         .cm_div_h14_dpll_core                   = 0x4a005144,
687         .cm_ssc_deltamstep_dpll_core            = 0x4a005148,
688         .cm_ssc_modfreqdiv_dpll_core            = 0x4a00514c,
689         .cm_div_h21_dpll_core                   = 0x4a005150,
690         .cm_div_h22_dpllcore                    = 0x4a005154,
691         .cm_div_h23_dpll_core                   = 0x4a005158,
692         .cm_div_h24_dpll_core                   = 0x4a00515c,
693         .cm_clkmode_dpll_mpu                    = 0x4a005160,
694         .cm_idlest_dpll_mpu                     = 0x4a005164,
695         .cm_autoidle_dpll_mpu                   = 0x4a005168,
696         .cm_clksel_dpll_mpu                     = 0x4a00516c,
697         .cm_div_m2_dpll_mpu                     = 0x4a005170,
698         .cm_ssc_deltamstep_dpll_mpu             = 0x4a005188,
699         .cm_ssc_modfreqdiv_dpll_mpu             = 0x4a00518c,
700         .cm_bypclk_dpll_mpu                     = 0x4a00519c,
701         .cm_clkmode_dpll_iva                    = 0x4a0051a0,
702         .cm_idlest_dpll_iva                     = 0x4a0051a4,
703         .cm_autoidle_dpll_iva                   = 0x4a0051a8,
704         .cm_clksel_dpll_iva                     = 0x4a0051ac,
705         .cm_ssc_deltamstep_dpll_iva             = 0x4a0051c8,
706         .cm_ssc_modfreqdiv_dpll_iva             = 0x4a0051cc,
707         .cm_bypclk_dpll_iva                     = 0x4a0051dc,
708         .cm_clkmode_dpll_abe                    = 0x4a0051e0,
709         .cm_idlest_dpll_abe                     = 0x4a0051e4,
710         .cm_autoidle_dpll_abe                   = 0x4a0051e8,
711         .cm_clksel_dpll_abe                     = 0x4a0051ec,
712         .cm_div_m2_dpll_abe                     = 0x4a0051f0,
713         .cm_div_m3_dpll_abe                     = 0x4a0051f4,
714         .cm_ssc_deltamstep_dpll_abe             = 0x4a005208,
715         .cm_ssc_modfreqdiv_dpll_abe             = 0x4a00520c,
716         .cm_clkmode_dpll_ddrphy                 = 0x4a005210,
717         .cm_idlest_dpll_ddrphy                  = 0x4a005214,
718         .cm_autoidle_dpll_ddrphy                = 0x4a005218,
719         .cm_clksel_dpll_ddrphy                  = 0x4a00521c,
720         .cm_div_m2_dpll_ddrphy                  = 0x4a005220,
721         .cm_div_h11_dpll_ddrphy                 = 0x4a005228,
722         .cm_ssc_deltamstep_dpll_ddrphy          = 0x4a00522c,
723         .cm_clkmode_dpll_dsp                    = 0x4a005234,
724         .cm_shadow_freq_config1                 = 0x4a005260,
726         /* cm1.mpu */
727         .cm_mpu_mpu_clkctrl                     = 0x4a005320,
729         /* cm1.dsp */
730         .cm_dsp_clkstctrl                       = 0x4a005400,
731         .cm_dsp_dsp_clkctrl                     = 0x4a005420,
733         /* cm2.ckgen */
734         .cm_clksel_usb_60mhz                    = 0x4a008104,
735         .cm_clkmode_dpll_per                    = 0x4a008140,
736         .cm_idlest_dpll_per                     = 0x4a008144,
737         .cm_autoidle_dpll_per                   = 0x4a008148,
738         .cm_clksel_dpll_per                     = 0x4a00814c,
739         .cm_div_m2_dpll_per                     = 0x4a008150,
740         .cm_div_m3_dpll_per                     = 0x4a008154,
741         .cm_div_h11_dpll_per                    = 0x4a008158,
742         .cm_div_h12_dpll_per                    = 0x4a00815c,
743         .cm_div_h13_dpll_per                    = 0x4a008160,
744         .cm_div_h14_dpll_per                    = 0x4a008164,
745         .cm_ssc_deltamstep_dpll_per             = 0x4a008168,
746         .cm_ssc_modfreqdiv_dpll_per             = 0x4a00816c,
747         .cm_clkmode_dpll_usb                    = 0x4a008180,
748         .cm_idlest_dpll_usb                     = 0x4a008184,
749         .cm_autoidle_dpll_usb                   = 0x4a008188,
750         .cm_clksel_dpll_usb                     = 0x4a00818c,
751         .cm_div_m2_dpll_usb                     = 0x4a008190,
752         .cm_ssc_deltamstep_dpll_usb             = 0x4a0081a8,
753         .cm_ssc_modfreqdiv_dpll_usb             = 0x4a0081ac,
754         .cm_clkdcoldo_dpll_usb                  = 0x4a0081b4,
755         .cm_clkmode_dpll_pcie_ref               = 0x4a008200,
756         .cm_clkmode_apll_pcie                   = 0x4a00821c,
757         .cm_idlest_apll_pcie                    = 0x4a008220,
758         .cm_div_m2_apll_pcie                    = 0x4a008224,
759         .cm_clkvcoldo_apll_pcie                 = 0x4a008228,
761         /* cm2.core */
762         .cm_l3_1_clkstctrl                      = 0x4a008700,
763         .cm_l3_1_dynamicdep                     = 0x4a008708,
764         .cm_l3_1_l3_1_clkctrl                   = 0x4a008720,
765         .cm_l3_gpmc_clkctrl                     = 0x4a008728,
766         .cm_mpu_m3_clkstctrl                    = 0x4a008900,
767         .cm_mpu_m3_staticdep                    = 0x4a008904,
768         .cm_mpu_m3_dynamicdep                   = 0x4a008908,
769         .cm_mpu_m3_mpu_m3_clkctrl               = 0x4a008920,
770         .cm_sdma_clkstctrl                      = 0x4a008a00,
771         .cm_sdma_staticdep                      = 0x4a008a04,
772         .cm_sdma_dynamicdep                     = 0x4a008a08,
773         .cm_sdma_sdma_clkctrl                   = 0x4a008a20,
774         .cm_memif_clkstctrl                     = 0x4a008b00,
775         .cm_memif_dmm_clkctrl                   = 0x4a008b20,
776         .cm_memif_emif_fw_clkctrl               = 0x4a008b28,
777         .cm_memif_emif_1_clkctrl                = 0x4a008b30,
778         .cm_memif_emif_2_clkctrl                = 0x4a008b38,
779         .cm_memif_dll_clkctrl                   = 0x4a008b40,
780         .cm_l4cfg_clkstctrl                     = 0x4a008d00,
781         .cm_l4cfg_dynamicdep                    = 0x4a008d08,
782         .cm_l4cfg_l4_cfg_clkctrl                = 0x4a008d20,
783         .cm_l4cfg_hw_sem_clkctrl                = 0x4a008d28,
784         .cm_l4cfg_mailbox_clkctrl               = 0x4a008d30,
785         .cm_l4cfg_sar_rom_clkctrl               = 0x4a008d38,
786         .cm_l3instr_clkstctrl                   = 0x4a008e00,
787         .cm_l3instr_l3_3_clkctrl                = 0x4a008e20,
788         .cm_l3instr_l3_instr_clkctrl            = 0x4a008e28,
789         .cm_l3instr_intrconn_wp1_clkctrl        = 0x4a008e40,
791         /* cm2.ivahd */
792         .cm_ivahd_clkstctrl                     = 0x4a008f00,
793         .cm_ivahd_ivahd_clkctrl                 = 0x4a008f20,
794         .cm_ivahd_sl2_clkctrl                   = 0x4a008f28,
796         /* cm2.cam */
797         .cm_cam_clkstctrl                       = 0x4a009000,
798         .cm_cam_vip1_clkctrl                    = 0x4a009020,
799         .cm_cam_vip2_clkctrl                    = 0x4a009028,
800         .cm_cam_vip3_clkctrl                    = 0x4a009030,
801         .cm_cam_lvdsrx_clkctrl                  = 0x4a009038,
802         .cm_cam_csi1_clkctrl                    = 0x4a009040,
803         .cm_cam_csi2_clkctrl                    = 0x4a009048,
805         /* cm2.dss */
806         .cm_dss_clkstctrl                       = 0x4a009100,
807         .cm_dss_dss_clkctrl                     = 0x4a009120,
809         /* cm2.sgx */
810         .cm_sgx_clkstctrl                       = 0x4a009200,
811         .cm_sgx_sgx_clkctrl                     = 0x4a009220,
813         /* cm2.l3init */
814         .cm_l3init_clkstctrl                    = 0x4a009300,
816         /* cm2.l3init */
817         .cm_l3init_hsmmc1_clkctrl               = 0x4a009328,
818         .cm_l3init_hsmmc2_clkctrl               = 0x4a009330,
819         .cm_l3init_hsusbhost_clkctrl            = 0x4a009340,
820         .cm_l3init_hsusbotg_clkctrl             = 0x4a009348,
821         .cm_l3init_hsusbtll_clkctrl             = 0x4a009350,
822         .cm_l3init_ocp2scp1_clkctrl             = 0x4a0093e0,
824         /* cm2.l4per */
825         .cm_l4per_clkstctrl                     = 0x4a009700,
826         .cm_l4per_dynamicdep                    = 0x4a009708,
827         .cm_l4per_gptimer10_clkctrl             = 0x4a009728,
828         .cm_l4per_gptimer11_clkctrl             = 0x4a009730,
829         .cm_l4per_gptimer2_clkctrl              = 0x4a009738,
830         .cm_l4per_gptimer3_clkctrl              = 0x4a009740,
831         .cm_l4per_gptimer4_clkctrl              = 0x4a009748,
832         .cm_l4per_gptimer9_clkctrl              = 0x4a009750,
833         .cm_l4per_elm_clkctrl                   = 0x4a009758,
834         .cm_l4per_gpio2_clkctrl                 = 0x4a009760,
835         .cm_l4per_gpio3_clkctrl                 = 0x4a009768,
836         .cm_l4per_gpio4_clkctrl                 = 0x4a009770,
837         .cm_l4per_gpio5_clkctrl                 = 0x4a009778,
838         .cm_l4per_gpio6_clkctrl                 = 0x4a009780,
839         .cm_l4per_hdq1w_clkctrl                 = 0x4a009788,
840         .cm_l4per_i2c1_clkctrl                  = 0x4a0097a0,
841         .cm_l4per_i2c2_clkctrl                  = 0x4a0097a8,
842         .cm_l4per_i2c3_clkctrl                  = 0x4a0097b0,
843         .cm_l4per_i2c4_clkctrl                  = 0x4a0097b8,
844         .cm_l4per_l4per_clkctrl                 = 0x4a0097c0,
845         .cm_l4per_mcspi1_clkctrl                = 0x4a0097f0,
846         .cm_l4per_mcspi2_clkctrl                = 0x4a0097f8,
847         .cm_l4per_mcspi3_clkctrl                = 0x4a009800,
848         .cm_l4per_mcspi4_clkctrl                = 0x4a009808,
849         .cm_l4per_gpio7_clkctrl                 = 0x4a009810,
850         .cm_l4per_gpio8_clkctrl                 = 0x4a009818,
851         .cm_l4per_mmcsd3_clkctrl                = 0x4a009820,
852         .cm_l4per_mmcsd4_clkctrl                = 0x4a009828,
853         .cm_l4per_uart1_clkctrl                 = 0x4a009840,
854         .cm_l4per_uart2_clkctrl                 = 0x4a009848,
855         .cm_l4per_uart3_clkctrl                 = 0x4a009850,
856         .cm_l4per_uart4_clkctrl                 = 0x4a009858,
857         .cm_l4per_uart5_clkctrl                 = 0x4a009870,
858         .cm_l4sec_clkstctrl                     = 0x4a009880,
859         .cm_l4sec_staticdep                     = 0x4a009884,
860         .cm_l4sec_dynamicdep                    = 0x4a009888,
861         .cm_l4sec_aes1_clkctrl                  = 0x4a0098a0,
862         .cm_l4sec_aes2_clkctrl                  = 0x4a0098a8,
863         .cm_l4sec_des3des_clkctrl               = 0x4a0098b0,
864         .cm_l4sec_rng_clkctrl                   = 0x4a0098c0,
865         .cm_l4sec_sha2md51_clkctrl              = 0x4a0098c8,
866         .cm_l4sec_cryptodma_clkctrl             = 0x4a0098d8,
868         /* l4 wkup regs */
869         .cm_abe_pll_ref_clksel                  = 0x4ae0610c,
870         .cm_sys_clksel                          = 0x4ae06110,
871         .cm_wkup_clkstctrl                      = 0x4ae07800,
872         .cm_wkup_l4wkup_clkctrl                 = 0x4ae07820,
873         .cm_wkup_wdtimer1_clkctrl               = 0x4ae07828,
874         .cm_wkup_wdtimer2_clkctrl               = 0x4ae07830,
875         .cm_wkup_gpio1_clkctrl                  = 0x4ae07838,
876         .cm_wkup_gptimer1_clkctrl               = 0x4ae07840,
877         .cm_wkup_gptimer12_clkctrl              = 0x4ae07848,
878         .cm_wkup_sarram_clkctrl                 = 0x4ae07860,
879         .cm_wkup_keyboard_clkctrl               = 0x4ae07878,
880         .cm_wkupaon_scrm_clkctrl                = 0x4ae07890,
881         .prm_rstctrl                            = 0x4ae07d00,
882         .prm_rstst                              = 0x4ae07d04,
883         .prm_vc_val_bypass                      = 0x4ae07da0,
884         .prm_vc_cfg_i2c_mode                    = 0x4ae07db4,
885         .prm_vc_cfg_i2c_clk                     = 0x4ae07db8,
886 };